2 * Copyright (c) 2006 Olivier Houchard
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
36 #define _ARM32_BUS_DMA_PRIVATE
37 #include <machine/armreg.h>
38 #include <machine/bus.h>
39 #include <machine/intr.h>
41 #include <arm/xscale/i8134x/i81342reg.h>
42 #include <arm/xscale/i8134x/i81342var.h>
44 #define WDTCR_ENABLE1 0x1e1e1e1e
45 #define WDTCR_ENABLE2 0xe1e1e1e1
47 static volatile int intr_enabled0;
48 static volatile int intr_enabled1;
49 static volatile int intr_enabled2;
50 static volatile int intr_enabled3;
52 struct bus_space i81342_bs_tag;
54 /* Read the interrupt pending register */
57 uint32_t intpnd0_read(void)
61 __asm __volatile("mrc p6, 0, %0, c0, c3, 0"
67 uint32_t intpnd1_read(void)
71 __asm __volatile("mrc p6, 0, %0, c1, c3, 0"
77 uint32_t intpnd2_read(void)
81 __asm __volatile("mrc p6, 0, %0, c2, c3, 0"
87 uint32_t intpnd3_read(void)
91 __asm __volatile("mrc p6, 0, %0, c3, c3, 0"
96 /* Read the interrupt control register */
97 /* 0 masked, 1 unmasked */
99 uint32_t intctl0_read(void)
103 __asm __volatile("mrc p6, 0, %0, c0, c4, 0"
109 uint32_t intctl1_read(void)
113 __asm __volatile("mrc p6, 0, %0, c1, c4, 0"
119 uint32_t intctl2_read(void)
123 __asm __volatile("mrc p6, 0, %0, c2, c4, 0"
129 uint32_t intctl3_read(void)
133 __asm __volatile("mrc p6, 0, %0, c3, c4, 0"
138 /* Write the interrupt control register */
141 void intctl0_write(uint32_t val)
144 __asm __volatile("mcr p6, 0, %0, c0, c4, 0"
149 void intctl1_write(uint32_t val)
152 __asm __volatile("mcr p6, 0, %0, c1, c4, 0"
157 void intctl2_write(uint32_t val)
160 __asm __volatile("mcr p6, 0, %0, c2, c4, 0"
165 void intctl3_write(uint32_t val)
168 __asm __volatile("mcr p6, 0, %0, c3, c4, 0"
172 /* Read the interrupt steering register */
175 uint32_t intstr0_read(void)
179 __asm __volatile("mrc p6, 0, %0, c0, c5, 0"
185 uint32_t intstr1_read(void)
189 __asm __volatile("mrc p6, 0, %0, c1, c5, 0"
195 uint32_t intstr2_read(void)
199 __asm __volatile("mrc p6, 0, %0, c2, c5, 0"
205 uint32_t intstr3_read(void)
209 __asm __volatile("mrc p6, 0, %0, c3, c5, 0"
214 /* Write the interrupt steering register */
217 void intstr0_write(uint32_t val)
220 __asm __volatile("mcr p6, 0, %0, c0, c5, 0"
225 void intstr1_write(uint32_t val)
228 __asm __volatile("mcr p6, 0, %0, c1, c5, 0"
233 void intstr2_write(uint32_t val)
236 __asm __volatile("mcr p6, 0, %0, c2, c5, 0"
241 void intstr3_write(uint32_t val)
244 __asm __volatile("mcr p6, 0, %0, c3, c5, 0"
252 disable_interrupts(PSR_I);
253 /* XXX: Use the watchdog to reset for now */
254 __asm __volatile("mcr p6, 0, %0, c8, c9, 0\n"
255 "mcr p6, 0, %1, c7, c9, 0\n"
256 "mcr p6, 0, %2, c7, c9, 0\n"
257 : : "r" (1), "r" (WDTCR_ENABLE1), "r" (WDTCR_ENABLE2));
262 arm_mask_irq(uintptr_t nb)
266 intr_enabled0 &= ~(1 << nb);
267 intctl0_write(intr_enabled0);
268 } else if (nb < 64) {
269 intr_enabled1 &= ~(1 << (nb - 32));
270 intctl1_write(intr_enabled1);
271 } else if (nb < 96) {
272 intr_enabled2 &= ~(1 << (nb - 64));
273 intctl2_write(intr_enabled2);
275 intr_enabled3 &= ~(1 << (nb - 96));
276 intctl3_write(intr_enabled3);
281 arm_unmask_irq(uintptr_t nb)
284 intr_enabled0 |= (1 << nb);
285 intctl0_write(intr_enabled0);
286 } else if (nb < 64) {
287 intr_enabled1 |= (1 << (nb - 32));
288 intctl1_write(intr_enabled1);
289 } else if (nb < 96) {
290 intr_enabled2 |= (1 << (nb - 64));
291 intctl2_write(intr_enabled2);
293 intr_enabled3 |= (1 << (nb - 96));
294 intctl3_write(intr_enabled3);
299 arm_get_next_irq(int last __unused)
302 val = intpnd0_read() & intr_enabled0;
304 return (ffs(val) - 1);
305 val = intpnd1_read() & intr_enabled1;
307 return (32 + ffs(val) - 1);
308 val = intpnd2_read() & intr_enabled2;
310 return (64 + ffs(val) - 1);
311 val = intpnd3_read() & intr_enabled3;
313 return (96 + ffs(val) - 1);
318 bus_dma_get_range_nb(void)
323 struct arm32_dma_range *
324 bus_dma_get_range(void)
330 i81342_probe(device_t dev)
334 freq = *(volatile unsigned int *)(IOP34X_VADDR + IOP34X_PFR);
336 switch (freq & IOP34X_FREQ_MASK) {
337 case IOP34X_FREQ_600:
338 device_set_desc(dev, "Intel 81342 600MHz");
340 case IOP34X_FREQ_667:
341 device_set_desc(dev, "Intel 81342 667MHz");
343 case IOP34X_FREQ_800:
344 device_set_desc(dev, "Intel 81342 800MHz");
346 case IOP34X_FREQ_833:
347 device_set_desc(dev, "Intel 81342 833MHz");
349 case IOP34X_FREQ_1000:
350 device_set_desc(dev, "Intel 81342 1000MHz");
352 case IOP34X_FREQ_1200:
353 device_set_desc(dev, "Intel 81342 1200MHz");
356 device_set_desc(dev, "Intel 81342 unknown frequency");
363 i81342_identify(driver_t *driver, device_t parent)
366 BUS_ADD_CHILD(parent, 0, "iq", 0);
370 i81342_attach(device_t dev)
372 struct i81342_softc *sc = device_get_softc(dev);
375 i81342_bs_init(&i81342_bs_tag, sc);
376 sc->sc_st = &i81342_bs_tag;
377 sc->sc_sh = IOP34X_VADDR;
378 esstrsr = bus_space_read_4(sc->sc_st, sc->sc_sh, IOP34X_ESSTSR0);
379 sc->sc_atux_sh = IOP34X_ATUX_ADDR(esstrsr) - IOP34X_HWADDR +
381 sc->sc_atue_sh = IOP34X_ATUE_ADDR(esstrsr) - IOP34X_HWADDR +
383 /* Disable all interrupts. */
388 /* Defaults to IRQ */
393 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
394 sc->sc_irq_rman.rm_descr = "i81342 IRQs";
395 if (rman_init(&sc->sc_irq_rman) != 0 ||
396 rman_manage_region(&sc->sc_irq_rman, 0, 127) != 0)
397 panic("i81342_attach: failed to set up IRQ rman");
399 device_add_child(dev, "obio", 0);
400 device_add_child(dev, "itimer", 0);
401 device_add_child(dev, "iopwdog", 0);
402 device_add_child(dev, "pcib", 0);
403 device_add_child(dev, "pcib", 1);
404 device_add_child(dev, "iqseg", 0);
405 bus_generic_probe(dev);
406 bus_generic_attach(dev);
410 static struct resource *
411 i81342_alloc_resource(device_t dev, device_t child, int type, int *rid,
412 u_long start, u_long end, u_long count, u_int flags)
414 struct i81342_softc *sc = device_get_softc(dev);
417 if (type == SYS_RES_IRQ) {
418 rv = rman_reserve_resource(&sc->sc_irq_rman,
419 start, end, count, flags, child);
421 rman_set_rid(rv, *rid);
429 i81342_setup_intr(device_t dev, device_t child, struct resource *ires,
430 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
435 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
436 filt, intr, arg, cookiep);
443 i81342_teardown_intr(device_t dev, device_t child, struct resource *res,
446 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
449 static device_method_t i81342_methods[] = {
450 DEVMETHOD(device_probe, i81342_probe),
451 DEVMETHOD(device_attach, i81342_attach),
452 DEVMETHOD(device_identify, i81342_identify),
453 DEVMETHOD(bus_alloc_resource, i81342_alloc_resource),
454 DEVMETHOD(bus_setup_intr, i81342_setup_intr),
455 DEVMETHOD(bus_teardown_intr, i81342_teardown_intr),
459 static driver_t i81342_driver = {
462 sizeof(struct i81342_softc),
464 static devclass_t i81342_devclass;
466 DRIVER_MODULE(iq, nexus, i81342_driver, i81342_devclass, 0, 0);