2 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 compatible = "samsung,exynos5";
33 interrupt-parent = <&GIC>;
49 compatible = "simple-bus";
53 GIC: interrupt-controller@10481000 {
54 compatible = "arm,gic";
55 reg = < 0x10481000 0x1000 >, /* Distributor Registers */
56 < 0x10482000 0x2000 >; /* CPU Interface Registers */
59 #interrupt-cells = <1>;
62 combiner: interrupt-controller@10440000 {
63 compatible = "exynos,combiner";
64 reg = <0x10440000 0x1000>;
65 interrupts = < 32 33 34 35 36 37 38 39
66 40 41 42 43 44 45 46 47
67 48 49 50 51 52 53 54 55
68 56 57 58 59 60 61 62 63 >;
69 interrupt-parent = <&GIC>;
73 compatible = "exynos,clk";
74 reg = < 0x10020000 0x20000 >;
78 compatible = "exynos,mct";
79 reg = < 0x101C0000 0x1000 >;
80 clock-frequency = <24000000>;
84 compatible = "arm,armv7-timer";
85 clock-frequency = <24000000>;
86 interrupts = < 29 30 27 26 >;
87 interrupt-parent = <&GIC>;
91 compatible = "samsung,s3c24x0-timer";
92 reg = <0x12DD0000 0x1000>;
94 interrupt-parent = <&GIC>;
95 clock-frequency = <24000000>;
99 compatible = "exynos,pad";
101 reg = <0x11400000 0x1000>, /* gpio left */
102 <0x13400000 0x1000>, /* gpio right */
103 <0x10D10000 0x1000>, /* gpio c2c */
105 interrupts = < 78 77 82 79 >;
106 interrupt-parent = <&GIC>;
110 compatible = "exynos,usb-ehci", "usb-ehci";
111 reg = <0x12110000 0x1000>, /* EHCI */
112 <0x12130000 0x1000>, /* EHCI host ctrl */
113 <0x10040000 0x1000>, /* Power */
114 <0x10050230 0x10>; /* Sysreg */
115 interrupts = < 103 >;
116 interrupt-parent = <&GIC>;
120 compatible = "exynos,usb-ohci", "usb-ohci";
122 reg = <0x12120000 0x10000>;
123 interrupts = < 103 >;
124 interrupt-parent = <&GIC>;
128 compatible = "sdhci_generic";
130 reg = <0x12200000 0x1000>;
132 interrupt-parent = <&GIC>;
133 max-frequency = <24000000>; /* TODO: verify freq */
137 compatible = "sdhci_generic";
139 reg = <0x12210000 0x1000>;
141 interrupt-parent = <&GIC>;
142 max-frequency = <24000000>;
146 compatible = "sdhci_generic";
148 reg = <0x12220000 0x1000>;
150 interrupt-parent = <&GIC>;
151 max-frequency = <24000000>;
155 compatible = "sdhci_generic";
157 reg = <0x12230000 0x1000>;
159 interrupt-parent = <&GIC>;
160 max-frequency = <24000000>;
163 serial0: serial@12C00000 {
164 compatible = "exynos";
166 reg = <0x12C00000 0x100>;
168 interrupt-parent = <&GIC>;
169 clock-frequency = < 100000000 >;
170 current-speed = <115200>;
173 serial1: serial@12C10000 {
174 compatible = "exynos";
176 reg = <0x12C10000 0x100>;
178 interrupt-parent = <&GIC>;
179 clock-frequency = < 100000000 >;
180 current-speed = <115200>;
183 serial2: serial@12C20000 {
184 compatible = "exynos";
186 reg = <0x12C20000 0x100>;
188 interrupt-parent = <&GIC>;
189 clock-frequency = < 100000000 >;
190 current-speed = <115200>;
193 serial3: serial@12C30000 {
194 compatible = "exynos";
196 reg = <0x12C30000 0x100>;
198 interrupt-parent = <&GIC>;
199 clock-frequency = < 100000000 >;
200 current-speed = <115200>;
204 compatible = "exynos,i2c";
206 reg = <0x12C60000 0x10000>;
208 interrupt-parent = <&GIC>;
212 compatible = "exynos,i2c";
214 reg = <0x12C70000 0x10000>;
216 interrupt-parent = <&GIC>;
220 compatible = "exynos,i2c";
222 reg = <0x12C80000 0x10000>;
224 interrupt-parent = <&GIC>;
228 compatible = "exynos,i2c";
230 reg = <0x12C90000 0x10000>;
232 interrupt-parent = <&GIC>;
236 compatible = "exynos,i2c";
238 reg = <0x12CA0000 0x10000>;
240 interrupt-parent = <&GIC>;
244 compatible = "exynos,i2c";
246 reg = <0x12CB0000 0x10000>;
248 interrupt-parent = <&GIC>;
252 compatible = "exynos,i2c";
254 reg = <0x12CC0000 0x10000>;
256 interrupt-parent = <&GIC>;
260 compatible = "exynos,i2c";
262 reg = <0x12CD0000 0x10000>;
264 interrupt-parent = <&GIC>;
267 fimd0: fimd@14400000 {
268 compatible = "exynos,fimd";
270 reg = < 0x14400000 0x10000 >, /* fimd */
271 < 0x14420000 0x10000 >, /* disp */
272 < 0x10050000 0x220 >; /* sysreg */
273 interrupt-parent = <&GIC>;
277 compatible = "exynos,dp";
279 reg = < 0x145B0000 0x10000 >,
280 < 0x10040720 0x10 >; /* PHY */
281 interrupt-parent = <&GIC>;