sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  13 **
  14 ** Redistribution and use in source and binary forms, with or without
  15 ** modification, are permitted provided that the following conditions
  16 ** are met:
  17 ** 1. Redistributions of source code must retain the above copyright
  18 **    notice, this list of conditions and the following disclaimer.
  19 ** 2. Redistributions in binary form must reproduce the above copyright
  20 **    notice, this list of conditions and the following disclaimer in the
  21 **    documentation and/or other materials provided with the distribution.
  22 ** 3. The name of the author may not be used to endorse or promote products
  23 **    derived from this software without specific prior written permission.
  24 **
  25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 ********************************************************************************
  36 ** History
  37 **
  38 **    REV#         DATE         NAME        DESCRIPTION
  39 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  40 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  41 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  42 **                                          clean unused function
  43 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  44 **                                          firmware version check
  45 **                                          and firmware update notify for hardware bug fix
  46 **                                          handling if none zero high part physical address
  47 **                                          of srb resource
  48 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  49 **                                          add iop message xfer
  50 **                                          with scsi pass-through command
  51 **                                          add new device id of sas raid adapters
  52 **                                          code fit for SPARC64 & PPC
  53 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  54 **                                          and cause g_vfs_done() read write error
  55 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  56 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  57 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  58 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  59 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  60 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  61 **                                          for any one LUN device failed
  62 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  63 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  64 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  65 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  66 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  67 **              02/14/2011  Ching Huang     Modified pktRequestCount
  68 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  69 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  70 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  71 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  72 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  73 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  74 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  75 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  76 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  77 ** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
  78 ** 1.20.00.29   12/18/2013  Ching Huang     Change simq allocation number, support ARC1883
  79 ** 1.30.00.00   11/30/2015  Ching Huang     Added support ARC1203
  80 ******************************************************************************************
  81 */
  82
  83 #include <sys/cdefs.h>
  84 __FBSDID("$FreeBSD$");
  85
  86 #if 0
  87 #define ARCMSR_DEBUG1                   1
  88 #endif
  89 #include <sys/param.h>
  90 #include <sys/systm.h>
  91 #include <sys/malloc.h>
  92 #include <sys/kernel.h>
  93 #include <sys/bus.h>
  94 #include <sys/queue.h>
  95 #include <sys/stat.h>
  96 #include <sys/devicestat.h>
  97 #include <sys/kthread.h>
  98 #include <sys/module.h>
  99 #include <sys/proc.h>
 100 #include <sys/lock.h>
 101 #include <sys/sysctl.h>
 102 #include <sys/poll.h>
 103 #include <sys/ioccom.h>
 104 #include <vm/vm.h>
 105 #include <vm/vm_param.h>
 106 #include <vm/pmap.h>
 107
 108 #include <isa/rtc.h>
 109
 110 #include <machine/bus.h>
 111 #include <machine/resource.h>
 112 #include <machine/atomic.h>
 113 #include <sys/conf.h>
 114 #include <sys/rman.h>
 115
 116 #include <cam/cam.h>
 117 #include <cam/cam_ccb.h>
 118 #include <cam/cam_sim.h>
 119 #include <cam/cam_periph.h>
 120 #include <cam/cam_xpt_periph.h>
 121 #include <cam/cam_xpt_sim.h>
 122 #include <cam/cam_debug.h>
 123 #include <cam/scsi/scsi_all.h>
 124 #include <cam/scsi/scsi_message.h>
 125 /*
 126 **************************************************************************
 127 **************************************************************************
 128 */
 129 #if __FreeBSD_version >= 500005
 130         #include <sys/selinfo.h>
 131         #include <sys/mutex.h>
 132         #include <sys/endian.h>
 133         #include <dev/pci/pcivar.h>
 134         #include <dev/pci/pcireg.h>
 135 #else
 136         #include <sys/select.h>
 137         #include <pci/pcivar.h>
 138         #include <pci/pcireg.h>
 139 #endif
 140
 141 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
 142 #define CAM_NEW_TRAN_CODE       1
 143 #endif
 144
 145 #if __FreeBSD_version > 500000
 146 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 147 #else
 148 #define arcmsr_callout_init(a)  callout_init(a);
 149 #endif
 150
 151 #define ARCMSR_DRIVER_VERSION   "arcmsr version 1.30.00.00 2015-11-30"
 152 #include <dev/arcmsr/arcmsr.h>
 153 /*
 154 **************************************************************************
 155 **************************************************************************
 156 */
 157 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 158 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 159 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 160 static int arcmsr_probe(device_t dev);
 161 static int arcmsr_attach(device_t dev);
 162 static int arcmsr_detach(device_t dev);
 163 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 164 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 165 static int arcmsr_shutdown(device_t dev);
 166 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 167 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 168 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 169 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 170 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 171 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 172 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 173 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 174 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 175 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 176 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 177 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 178 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 179 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 180 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 181 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 182 static int arcmsr_resume(device_t dev);
 183 static int arcmsr_suspend(device_t dev);
 184 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 185 static void arcmsr_polling_devmap(void *arg);
 186 static void arcmsr_srb_timeout(void *arg);
 187 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 188 #ifdef ARCMSR_DEBUG1
 189 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 190 #endif
 191 /*
 192 **************************************************************************
 193 **************************************************************************
 194 */
 195 static void UDELAY(u_int32_t us) { DELAY(us); }
 196 /*
 197 **************************************************************************
 198 **************************************************************************
 199 */
 200 static bus_dmamap_callback_t arcmsr_map_free_srb;
 201 static bus_dmamap_callback_t arcmsr_execute_srb;
 202 /*
 203 **************************************************************************
 204 **************************************************************************
 205 */
 206 static d_open_t arcmsr_open;
 207 static d_close_t arcmsr_close;
 208 static d_ioctl_t arcmsr_ioctl;
 209
 210 static device_method_t arcmsr_methods[]={
 211         DEVMETHOD(device_probe,         arcmsr_probe),
 212         DEVMETHOD(device_attach,        arcmsr_attach),
 213         DEVMETHOD(device_detach,        arcmsr_detach),
 214         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 215         DEVMETHOD(device_suspend,       arcmsr_suspend),
 216         DEVMETHOD(device_resume,        arcmsr_resume),
 217
 218 #if __FreeBSD_version >= 803000
 219         DEVMETHOD_END
 220 #else
 221         { 0, 0 }
 222 #endif
 223 };
 224
 225 static driver_t arcmsr_driver={
 226         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 227 };
 228
 229 static devclass_t arcmsr_devclass;
 230 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 231 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 232 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 233 #ifndef BUS_DMA_COHERENT
 234         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 235 #endif
 236 #if __FreeBSD_version >= 501000
 237 static struct cdevsw arcmsr_cdevsw={
 238         #if __FreeBSD_version >= 503000
 239                 .d_version = D_VERSION,
 240         #endif
 241         #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
 242                 .d_flags   = D_NEEDGIANT,
 243         #endif
 244                 .d_open    = arcmsr_open,       /* open     */
 245                 .d_close   = arcmsr_close,      /* close    */
 246                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 247                 .d_name    = "arcmsr",          /* name     */
 248         };
 249 #else
 250         #define ARCMSR_CDEV_MAJOR       180
 251
 252 static struct cdevsw arcmsr_cdevsw = {
 253                 arcmsr_open,                    /* open     */
 254                 arcmsr_close,                   /* close    */
 255                 noread,                         /* read     */
 256                 nowrite,                        /* write    */
 257                 arcmsr_ioctl,                   /* ioctl    */
 258                 nopoll,                         /* poll     */
 259                 nommap,                         /* mmap     */
 260                 nostrategy,                     /* strategy */
 261                 "arcmsr",                       /* name     */
 262                 ARCMSR_CDEV_MAJOR,              /* major    */
 263                 nodump,                         /* dump     */
 264                 nopsize,                        /* psize    */
 265                 0                               /* flags    */
 266         };
 267 #endif
 268 /*
 269 **************************************************************************
 270 **************************************************************************
 271 */
 272 #if     __FreeBSD_version < 500005
 273         static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
 274 #else
 275         #if     __FreeBSD_version < 503000
 276         static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
 277         #else
 278         static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 279         #endif
 280 #endif
 281 {
 282         #if     __FreeBSD_version < 503000
 283                 struct AdapterControlBlock *acb = dev->si_drv1;
 284         #else
 285                 int     unit = dev2unit(dev);
 286                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 287         #endif
 288         if(acb == NULL) {
 289                 return ENXIO;
 290         }
 291         return (0);
 292 }
 293 /*
 294 **************************************************************************
 295 **************************************************************************
 296 */
 297 #if     __FreeBSD_version < 500005
 298         static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
 299 #else
 300         #if     __FreeBSD_version < 503000
 301         static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
 302         #else
 303         static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 304         #endif
 305 #endif
 306 {
 307         #if     __FreeBSD_version < 503000
 308                 struct AdapterControlBlock *acb = dev->si_drv1;
 309         #else
 310                 int     unit = dev2unit(dev);
 311                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 312         #endif
 313         if(acb == NULL) {
 314                 return ENXIO;
 315         }
 316         return 0;
 317 }
 318 /*
 319 **************************************************************************
 320 **************************************************************************
 321 */
 322 #if     __FreeBSD_version < 500005
 323         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
 324 #else
 325         #if     __FreeBSD_version < 503000
 326         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 327         #else
 328         static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 329         #endif
 330 #endif
 331 {
 332         #if     __FreeBSD_version < 503000
 333                 struct AdapterControlBlock *acb = dev->si_drv1;
 334         #else
 335                 int     unit = dev2unit(dev);
 336                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 337         #endif
 338
 339         if(acb == NULL) {
 340                 return ENXIO;
 341         }
 342         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 343 }
 344 /*
 345 **********************************************************************
 346 **********************************************************************
 347 */
 348 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 349 {
 350         u_int32_t intmask_org = 0;
 351
 352         switch (acb->adapter_type) {
 353         case ACB_ADAPTER_TYPE_A: {
 354                         /* disable all outbound interrupt */
 355                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 356                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 357                 }
 358                 break;
 359         case ACB_ADAPTER_TYPE_B: {
 360                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 361                         /* disable all outbound interrupt */
 362                         intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
 363                                                 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 364                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
 365                 }
 366                 break;
 367         case ACB_ADAPTER_TYPE_C: {
 368                         /* disable all outbound interrupt */
 369                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 370                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 371                 }
 372                 break;
 373         case ACB_ADAPTER_TYPE_D: {
 374                         /* disable all outbound interrupt */
 375                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
 376                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 377                 }
 378                 break;
 379         }
 380         return (intmask_org);
 381 }
 382 /*
 383 **********************************************************************
 384 **********************************************************************
 385 */
 386 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 387 {
 388         u_int32_t mask;
 389
 390         switch (acb->adapter_type) {
 391         case ACB_ADAPTER_TYPE_A: {
 392                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 393                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 394                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 395                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 396                 }
 397                 break;
 398         case ACB_ADAPTER_TYPE_B: {
 399                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 400                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 401                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 402                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 403                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 404                 }
 405                 break;
 406         case ACB_ADAPTER_TYPE_C: {
 407                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 408                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 409                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 410                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 411                 }
 412                 break;
 413         case ACB_ADAPTER_TYPE_D: {
 414                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 415                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 416                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 417                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 418                         acb->outbound_int_enable = mask;
 419                 }
 420                 break;
 421         }
 422 }
 423 /*
 424 **********************************************************************
 425 **********************************************************************
 426 */
 427 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 428 {
 429         u_int32_t Index;
 430         u_int8_t Retries = 0x00;
 431
 432         do {
 433                 for(Index=0; Index < 100; Index++) {
 434                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 435                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 436                                 return TRUE;
 437                         }
 438                         UDELAY(10000);
 439                 }/*max 1 seconds*/
 440         }while(Retries++ < 20);/*max 20 sec*/
 441         return (FALSE);
 442 }
 443 /*
 444 **********************************************************************
 445 **********************************************************************
 446 */
 447 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 448 {
 449         u_int32_t Index;
 450         u_int8_t Retries = 0x00;
 451         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 452
 453         do {
 454                 for(Index=0; Index < 100; Index++) {
 455                         if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 456                                 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 457                                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 458                                 return TRUE;
 459                         }
 460                         UDELAY(10000);
 461                 }/*max 1 seconds*/
 462         }while(Retries++ < 20);/*max 20 sec*/
 463         return (FALSE);
 464 }
 465 /*
 466 **********************************************************************
 467 **********************************************************************
 468 */
 469 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 470 {
 471         u_int32_t Index;
 472         u_int8_t Retries = 0x00;
 473
 474         do {
 475                 for(Index=0; Index < 100; Index++) {
 476                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 477                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 478                                 return TRUE;
 479                         }
 480                         UDELAY(10000);
 481                 }/*max 1 seconds*/
 482         }while(Retries++ < 20);/*max 20 sec*/
 483         return (FALSE);
 484 }
 485 /*
 486 **********************************************************************
 487 **********************************************************************
 488 */
 489 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 490 {
 491         u_int32_t Index;
 492         u_int8_t Retries = 0x00;
 493
 494         do {
 495                 for(Index=0; Index < 100; Index++) {
 496                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 497                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 498                                 return TRUE;
 499                         }
 500                         UDELAY(10000);
 501                 }/*max 1 seconds*/
 502         }while(Retries++ < 20);/*max 20 sec*/
 503         return (FALSE);
 504 }
 505 /*
 506 ************************************************************************
 507 ************************************************************************
 508 */
 509 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 510 {
 511         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 512
 513         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 514         do {
 515                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 516                         break;
 517                 } else {
 518                         retry_count--;
 519                 }
 520         }while(retry_count != 0);
 521 }
 522 /*
 523 ************************************************************************
 524 ************************************************************************
 525 */
 526 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 527 {
 528         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 529         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 530
 531         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 532         do {
 533                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 534                         break;
 535                 } else {
 536                         retry_count--;
 537                 }
 538         }while(retry_count != 0);
 539 }
 540 /*
 541 ************************************************************************
 542 ************************************************************************
 543 */
 544 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 545 {
 546         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 547
 548         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 549         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 550         do {
 551                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 552                         break;
 553                 } else {
 554                         retry_count--;
 555                 }
 556         }while(retry_count != 0);
 557 }
 558 /*
 559 ************************************************************************
 560 ************************************************************************
 561 */
 562 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 563 {
 564         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 565
 566         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 567         do {
 568                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 569                         break;
 570                 } else {
 571                         retry_count--;
 572                 }
 573         }while(retry_count != 0);
 574 }
 575 /*
 576 ************************************************************************
 577 ************************************************************************
 578 */
 579 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 580 {
 581         switch (acb->adapter_type) {
 582         case ACB_ADAPTER_TYPE_A: {
 583                         arcmsr_flush_hba_cache(acb);
 584                 }
 585                 break;
 586         case ACB_ADAPTER_TYPE_B: {
 587                         arcmsr_flush_hbb_cache(acb);
 588                 }
 589                 break;
 590         case ACB_ADAPTER_TYPE_C: {
 591                         arcmsr_flush_hbc_cache(acb);
 592                 }
 593                 break;
 594         case ACB_ADAPTER_TYPE_D: {
 595                         arcmsr_flush_hbd_cache(acb);
 596                 }
 597                 break;
 598         }
 599 }
 600 /*
 601 *******************************************************************************
 602 *******************************************************************************
 603 */
 604 static int arcmsr_suspend(device_t dev)
 605 {
 606         struct AdapterControlBlock      *acb = device_get_softc(dev);
 607
 608         /* flush controller */
 609         arcmsr_iop_parking(acb);
 610         /* disable all outbound interrupt */
 611         arcmsr_disable_allintr(acb);
 612         return(0);
 613 }
 614 /*
 615 *******************************************************************************
 616 *******************************************************************************
 617 */
 618 static int arcmsr_resume(device_t dev)
 619 {
 620         struct AdapterControlBlock      *acb = device_get_softc(dev);
 621
 622         arcmsr_iop_init(acb);
 623         return(0);
 624 }
 625 /*
 626 *********************************************************************************
 627 *********************************************************************************
 628 */
 629 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 630 {
 631         struct AdapterControlBlock *acb;
 632         u_int8_t target_id, target_lun;
 633         struct cam_sim *sim;
 634
 635         sim = (struct cam_sim *) cb_arg;
 636         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 637         switch (code) {
 638         case AC_LOST_DEVICE:
 639                 target_id = xpt_path_target_id(path);
 640                 target_lun = xpt_path_lun_id(path);
 641                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 642                         break;
 643                 }
 644         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 645                 break;
 646         default:
 647                 break;
 648         }
 649 }
 650 /*
 651 **********************************************************************
 652 **********************************************************************
 653 */
 654 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 655 {
 656         union ccb *pccb = srb->pccb;
 657
 658         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 659         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 660         if(pccb->csio.sense_len) {
 661                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 662                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 663                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 664                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 665                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 666         }
 667 }
 668 /*
 669 *********************************************************************
 670 *********************************************************************
 671 */
 672 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 673 {
 674         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 675         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 676                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 677         }
 678 }
 679 /*
 680 *********************************************************************
 681 *********************************************************************
 682 */
 683 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 684 {
 685         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 686         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 687         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 688                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 689         }
 690 }
 691 /*
 692 *********************************************************************
 693 *********************************************************************
 694 */
 695 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 696 {
 697         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 698         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 699         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 700                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 701         }
 702 }
 703 /*
 704 *********************************************************************
 705 *********************************************************************
 706 */
 707 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 708 {
 709         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 710         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 711                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 712         }
 713 }
 714 /*
 715 *********************************************************************
 716 *********************************************************************
 717 */
 718 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 719 {
 720         switch (acb->adapter_type) {
 721         case ACB_ADAPTER_TYPE_A: {
 722                         arcmsr_abort_hba_allcmd(acb);
 723                 }
 724                 break;
 725         case ACB_ADAPTER_TYPE_B: {
 726                         arcmsr_abort_hbb_allcmd(acb);
 727                 }
 728                 break;
 729         case ACB_ADAPTER_TYPE_C: {
 730                         arcmsr_abort_hbc_allcmd(acb);
 731                 }
 732                 break;
 733         case ACB_ADAPTER_TYPE_D: {
 734                         arcmsr_abort_hbd_allcmd(acb);
 735                 }
 736                 break;
 737         }
 738 }
 739 /*
 740 **********************************************************************
 741 **********************************************************************
 742 */
 743 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 744 {
 745         struct AdapterControlBlock *acb = srb->acb;
 746         union ccb *pccb = srb->pccb;
 747
 748         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 749                 callout_stop(&srb->ccb_callout);
 750         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 751                 bus_dmasync_op_t op;
 752
 753                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 754                         op = BUS_DMASYNC_POSTREAD;
 755                 } else {
 756                         op = BUS_DMASYNC_POSTWRITE;
 757                 }
 758                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 759                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 760         }
 761         if(stand_flag == 1) {
 762                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 763                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 764                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 765                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 766                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 767                 }
 768         }
 769         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 770                 arcmsr_free_srb(srb);
 771         acb->pktReturnCount++;
 772         xpt_done(pccb);
 773 }
 774 /*
 775 **************************************************************************
 776 **************************************************************************
 777 */
 778 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 779 {
 780         int target, lun;
 781
 782         target = srb->pccb->ccb_h.target_id;
 783         lun = srb->pccb->ccb_h.target_lun;
 784         if(error == FALSE) {
 785                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 786                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 787                 }
 788                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 789                 arcmsr_srb_complete(srb, 1);
 790         } else {
 791                 switch(srb->arcmsr_cdb.DeviceStatus) {
 792                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 793                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 794                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 795                                 }
 796                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 797                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 798                                 arcmsr_srb_complete(srb, 1);
 799                         }
 800                         break;
 801                 case ARCMSR_DEV_ABORTED:
 802                 case ARCMSR_DEV_INIT_FAIL: {
 803                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 804                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 805                                 arcmsr_srb_complete(srb, 1);
 806                         }
 807                         break;
 808                 case SCSISTAT_CHECK_CONDITION: {
 809                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 810                                 arcmsr_report_sense_info(srb);
 811                                 arcmsr_srb_complete(srb, 1);
 812                         }
 813                         break;
 814                 default:
 815                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 816                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 817                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 818                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 819                         /*unknown error or crc error just for retry*/
 820                         arcmsr_srb_complete(srb, 1);
 821                         break;
 822                 }
 823         }
 824 }
 825 /*
 826 **************************************************************************
 827 **************************************************************************
 828 */
 829 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 830 {
 831         struct CommandControlBlock *srb;
 832
 833         /* check if command done with no error*/
 834         switch (acb->adapter_type) {
 835         case ACB_ADAPTER_TYPE_C:
 836         case ACB_ADAPTER_TYPE_D:
 837                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 838                 break;
 839         case ACB_ADAPTER_TYPE_A:
 840         case ACB_ADAPTER_TYPE_B:
 841         default:
 842                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 843                 break;
 844         }
 845         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 846                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 847                         arcmsr_free_srb(srb);
 848                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 849                         return;
 850                 }
 851                 printf("arcmsr%d: return srb has been completed\n"
 852                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 853                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 854                 return;
 855         }
 856         arcmsr_report_srb_state(acb, srb, error);
 857 }
 858 /*
 859 **************************************************************************
 860 **************************************************************************
 861 */
 862 static void     arcmsr_srb_timeout(void *arg)
 863 {
 864         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 865         struct AdapterControlBlock *acb;
 866         int target, lun;
 867         u_int8_t cmd;
 868
 869         target = srb->pccb->ccb_h.target_id;
 870         lun = srb->pccb->ccb_h.target_lun;
 871         acb = srb->acb;
 872         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 873         if(srb->srb_state == ARCMSR_SRB_START)
 874         {
 875                 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
 876                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 877                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 878                 arcmsr_srb_complete(srb, 1);
 879                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 880                                  acb->pci_unit, target, lun, cmd, srb);
 881         }
 882         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 883 #ifdef ARCMSR_DEBUG1
 884         arcmsr_dump_data(acb);
 885 #endif
 886 }
 887
 888 /*
 889 **********************************************************************
 890 **********************************************************************
 891 */
 892 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 893 {
 894         int i=0;
 895         u_int32_t flag_srb;
 896         u_int16_t error;
 897
 898         switch (acb->adapter_type) {
 899         case ACB_ADAPTER_TYPE_A: {
 900                         u_int32_t outbound_intstatus;
 901
 902                         /*clear and abort all outbound posted Q*/
 903                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 904                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 905                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 906                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 907                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 908                         }
 909                 }
 910                 break;
 911         case ACB_ADAPTER_TYPE_B: {
 912                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 913
 914                         /*clear all outbound posted Q*/
 915                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 916                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 917                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
 918                                         phbbmu->done_qbuffer[i] = 0;
 919                                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 920                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 921                                 }
 922                                 phbbmu->post_qbuffer[i] = 0;
 923                         }/*drain reply FIFO*/
 924                         phbbmu->doneq_index = 0;
 925                         phbbmu->postq_index = 0;
 926                 }
 927                 break;
 928         case ACB_ADAPTER_TYPE_C: {
 929
 930                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 931                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 932                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 933                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 934                         }
 935                 }
 936                 break;
 937         case ACB_ADAPTER_TYPE_D: {
 938                         arcmsr_hbd_postqueue_isr(acb);
 939                 }
 940                 break;
 941         }
 942 }
 943 /*
 944 ****************************************************************************
 945 ****************************************************************************
 946 */
 947 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 948 {
 949         struct CommandControlBlock *srb;
 950         u_int32_t intmask_org;
 951         u_int32_t i=0;
 952
 953         if(acb->srboutstandingcount>0) {
 954                 /* disable all outbound interrupt */
 955                 intmask_org = arcmsr_disable_allintr(acb);
 956                 /*clear and abort all outbound posted Q*/
 957                 arcmsr_done4abort_postqueue(acb);
 958                 /* talk to iop 331 outstanding command aborted*/
 959                 arcmsr_abort_allcmd(acb);
 960                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 961                         srb = acb->psrb_pool[i];
 962                         if(srb->srb_state == ARCMSR_SRB_START) {
 963                                 srb->srb_state = ARCMSR_SRB_ABORTED;
 964                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 965                                 arcmsr_srb_complete(srb, 1);
 966                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n"
 967                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
 968                                                 , srb->pccb->ccb_h.target_lun, srb);
 969                         }
 970                 }
 971                 /* enable all outbound interrupt */
 972                 arcmsr_enable_allintr(acb, intmask_org);
 973         }
 974         acb->srboutstandingcount = 0;
 975         acb->workingsrb_doneindex = 0;
 976         acb->workingsrb_startindex = 0;
 977         acb->pktRequestCount = 0;
 978         acb->pktReturnCount = 0;
 979 }
 980 /*
 981 **********************************************************************
 982 **********************************************************************
 983 */
 984 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 985                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
 986 {
 987         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
 988         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
 989         u_int32_t address_lo, address_hi;
 990         union ccb *pccb = srb->pccb;
 991         struct ccb_scsiio *pcsio = &pccb->csio;
 992         u_int32_t arccdbsize = 0x30;
 993
 994         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
 995         arcmsr_cdb->Bus = 0;
 996         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
 997         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
 998         arcmsr_cdb->Function = 1;
 999         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1000         bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
1001         if(nseg != 0) {
1002                 struct AdapterControlBlock *acb = srb->acb;
1003                 bus_dmasync_op_t op;
1004                 u_int32_t length, i, cdb_sgcount = 0;
1005
1006                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1007                         op = BUS_DMASYNC_PREREAD;
1008                 } else {
1009                         op = BUS_DMASYNC_PREWRITE;
1010                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1011                         srb->srb_flags |= SRB_FLAG_WRITE;
1012                 }
1013                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1014                 for(i=0; i < nseg; i++) {
1015                         /* Get the physical address of the current data pointer */
1016                         length = arcmsr_htole32(dm_segs[i].ds_len);
1017                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1018                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1019                         if(address_hi == 0) {
1020                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1021                                 pdma_sg->address = address_lo;
1022                                 pdma_sg->length = length;
1023                                 psge += sizeof(struct SG32ENTRY);
1024                                 arccdbsize += sizeof(struct SG32ENTRY);
1025                         } else {
1026                                 u_int32_t sg64s_size = 0, tmplength = length;
1027
1028                                 while(1) {
1029                                         u_int64_t span4G, length0;
1030                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1031
1032                                         span4G = (u_int64_t)address_lo + tmplength;
1033                                         pdma_sg->addresshigh = address_hi;
1034                                         pdma_sg->address = address_lo;
1035                                         if(span4G > 0x100000000) {
1036                                                 /*see if cross 4G boundary*/
1037                                                 length0 = 0x100000000-address_lo;
1038                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1039                                                 address_hi = address_hi+1;
1040                                                 address_lo = 0;
1041                                                 tmplength = tmplength - (u_int32_t)length0;
1042                                                 sg64s_size += sizeof(struct SG64ENTRY);
1043                                                 psge += sizeof(struct SG64ENTRY);
1044                                                 cdb_sgcount++;
1045                                         } else {
1046                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1047                                                 sg64s_size += sizeof(struct SG64ENTRY);
1048                                                 psge += sizeof(struct SG64ENTRY);
1049                                                 break;
1050                                         }
1051                                 }
1052                                 arccdbsize += sg64s_size;
1053                         }
1054                         cdb_sgcount++;
1055                 }
1056                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1057                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1058                 if( arccdbsize > 256) {
1059                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1060                 }
1061         } else {
1062                 arcmsr_cdb->DataLength = 0;
1063         }
1064         srb->arc_cdb_size = arccdbsize;
1065         arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1066 }
1067 /*
1068 **************************************************************************
1069 **************************************************************************
1070 */
1071 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1072 {
1073         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1074         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1075
1076         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1077         atomic_add_int(&acb->srboutstandingcount, 1);
1078         srb->srb_state = ARCMSR_SRB_START;
1079
1080         switch (acb->adapter_type) {
1081         case ACB_ADAPTER_TYPE_A: {
1082                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1083                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1084                         } else {
1085                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1086                         }
1087                 }
1088                 break;
1089         case ACB_ADAPTER_TYPE_B: {
1090                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1091                         int ending_index, index;
1092
1093                         index = phbbmu->postq_index;
1094                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1095                         phbbmu->post_qbuffer[ending_index] = 0;
1096                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1097                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1098                         } else {
1099                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1100                         }
1101                         index++;
1102                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1103                         phbbmu->postq_index = index;
1104                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1105                 }
1106                 break;
1107         case ACB_ADAPTER_TYPE_C: {
1108                         u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1109
1110                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1111                         ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1112                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1113                         if(cdb_phyaddr_hi32)
1114                         {
1115                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1116                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1117                         }
1118                         else
1119                         {
1120                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1121                         }
1122                 }
1123                 break;
1124         case ACB_ADAPTER_TYPE_D: {
1125                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1126                         u_int16_t index_stripped;
1127                         u_int16_t postq_index;
1128                         struct InBound_SRB *pinbound_srb;
1129
1130                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1131                         postq_index = phbdmu->postq_index;
1132                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1133                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1134                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1135                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1136                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1137                         if (postq_index & 0x4000) {
1138                                 index_stripped = postq_index & 0xFF;
1139                                 index_stripped += 1;
1140                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1141                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1142                         } else {
1143                                 index_stripped = postq_index;
1144                                 index_stripped += 1;
1145                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1146                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1147                         }
1148                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1149                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1150                 }
1151                 break;
1152         }
1153 }
1154 /*
1155 ************************************************************************
1156 ************************************************************************
1157 */
1158 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1159 {
1160         struct QBUFFER *qbuffer=NULL;
1161
1162         switch (acb->adapter_type) {
1163         case ACB_ADAPTER_TYPE_A: {
1164                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1165
1166                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1167                 }
1168                 break;
1169         case ACB_ADAPTER_TYPE_B: {
1170                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1171
1172                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1173                 }
1174                 break;
1175         case ACB_ADAPTER_TYPE_C: {
1176                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1177
1178                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1179                 }
1180                 break;
1181         case ACB_ADAPTER_TYPE_D: {
1182                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1183
1184                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1185                 }
1186                 break;
1187         }
1188         return(qbuffer);
1189 }
1190 /*
1191 ************************************************************************
1192 ************************************************************************
1193 */
1194 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1195 {
1196         struct QBUFFER *qbuffer = NULL;
1197
1198         switch (acb->adapter_type) {
1199         case ACB_ADAPTER_TYPE_A: {
1200                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1201
1202                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1203                 }
1204                 break;
1205         case ACB_ADAPTER_TYPE_B: {
1206                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1207
1208                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1209                 }
1210                 break;
1211         case ACB_ADAPTER_TYPE_C: {
1212                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1213
1214                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1215                 }
1216                 break;
1217         case ACB_ADAPTER_TYPE_D: {
1218                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1219
1220                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1221                 }
1222                 break;
1223         }
1224         return(qbuffer);
1225 }
1226 /*
1227 **************************************************************************
1228 **************************************************************************
1229 */
1230 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1231 {
1232         switch (acb->adapter_type) {
1233         case ACB_ADAPTER_TYPE_A: {
1234                         /* let IOP know data has been read */
1235                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1236                 }
1237                 break;
1238         case ACB_ADAPTER_TYPE_B: {
1239                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1240                         /* let IOP know data has been read */
1241                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1242                 }
1243                 break;
1244         case ACB_ADAPTER_TYPE_C: {
1245                         /* let IOP know data has been read */
1246                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1247                 }
1248                 break;
1249         case ACB_ADAPTER_TYPE_D: {
1250                         /* let IOP know data has been read */
1251                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1252                 }
1253                 break;
1254         }
1255 }
1256 /*
1257 **************************************************************************
1258 **************************************************************************
1259 */
1260 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1261 {
1262         switch (acb->adapter_type) {
1263         case ACB_ADAPTER_TYPE_A: {
1264                         /*
1265                         ** push inbound doorbell tell iop, driver data write ok
1266                         ** and wait reply on next hwinterrupt for next Qbuffer post
1267                         */
1268                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1269                 }
1270                 break;
1271         case ACB_ADAPTER_TYPE_B: {
1272                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1273                         /*
1274                         ** push inbound doorbell tell iop, driver data write ok
1275                         ** and wait reply on next hwinterrupt for next Qbuffer post
1276                         */
1277                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1278                 }
1279                 break;
1280         case ACB_ADAPTER_TYPE_C: {
1281                         /*
1282                         ** push inbound doorbell tell iop, driver data write ok
1283                         ** and wait reply on next hwinterrupt for next Qbuffer post
1284                         */
1285                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1286                 }
1287                 break;
1288         case ACB_ADAPTER_TYPE_D: {
1289                         /*
1290                         ** push inbound doorbell tell iop, driver data write ok
1291                         ** and wait reply on next hwinterrupt for next Qbuffer post
1292                         */
1293                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1294                 }
1295                 break;
1296         }
1297 }
1298 /*
1299 ************************************************************************
1300 ************************************************************************
1301 */
1302 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1303 {
1304         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1305         CHIP_REG_WRITE32(HBA_MessageUnit,
1306                 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1307         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1308                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1309                         , acb->pci_unit);
1310         }
1311 }
1312 /*
1313 ************************************************************************
1314 ************************************************************************
1315 */
1316 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1317 {
1318         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1319         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1320         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1321         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1322                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1323                         , acb->pci_unit);
1324         }
1325 }
1326 /*
1327 ************************************************************************
1328 ************************************************************************
1329 */
1330 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1331 {
1332         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1333         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1334         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1335         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1336                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1337         }
1338 }
1339 /*
1340 ************************************************************************
1341 ************************************************************************
1342 */
1343 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1344 {
1345         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1346         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1347         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1348                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1349         }
1350 }
1351 /*
1352 ************************************************************************
1353 ************************************************************************
1354 */
1355 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1356 {
1357         switch (acb->adapter_type) {
1358         case ACB_ADAPTER_TYPE_A: {
1359                         arcmsr_stop_hba_bgrb(acb);
1360                 }
1361                 break;
1362         case ACB_ADAPTER_TYPE_B: {
1363                         arcmsr_stop_hbb_bgrb(acb);
1364                 }
1365                 break;
1366         case ACB_ADAPTER_TYPE_C: {
1367                         arcmsr_stop_hbc_bgrb(acb);
1368                 }
1369                 break;
1370         case ACB_ADAPTER_TYPE_D: {
1371                         arcmsr_stop_hbd_bgrb(acb);
1372                 }
1373                 break;
1374         }
1375 }
1376 /*
1377 ************************************************************************
1378 ************************************************************************
1379 */
1380 static void arcmsr_poll(struct cam_sim *psim)
1381 {
1382         struct AdapterControlBlock *acb;
1383         int     mutex;
1384
1385         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1386         mutex = mtx_owned(&acb->isr_lock);
1387         if( mutex == 0 )
1388                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1389         arcmsr_interrupt(acb);
1390         if( mutex == 0 )
1391                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1392 }
1393 /*
1394 **************************************************************************
1395 **************************************************************************
1396 */
1397 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1398         struct QBUFFER *prbuffer) {
1399
1400         u_int8_t *pQbuffer;
1401         u_int8_t *buf1 = 0;
1402         u_int32_t *iop_data, *buf2 = 0;
1403         u_int32_t iop_len, data_len;
1404
1405         iop_data = (u_int32_t *)prbuffer->data;
1406         iop_len = (u_int32_t)prbuffer->data_len;
1407         if ( iop_len > 0 )
1408         {
1409                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1410                 buf2 = (u_int32_t *)buf1;
1411                 if( buf1 == NULL)
1412                         return (0);
1413                 data_len = iop_len;
1414                 while(data_len >= 4)
1415                 {
1416                         *buf2++ = *iop_data++;
1417                         data_len -= 4;
1418                 }
1419                 if(data_len)
1420                         *buf2 = *iop_data;
1421                 buf2 = (u_int32_t *)buf1;
1422         }
1423         while (iop_len > 0) {
1424                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1425                 *pQbuffer = *buf1;
1426                 acb->rqbuf_lastindex++;
1427                 /* if last, index number set it to 0 */
1428                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1429                 buf1++;
1430                 iop_len--;
1431         }
1432         if(buf2)
1433                 free( (u_int8_t *)buf2, M_DEVBUF);
1434         /* let IOP know data has been read */
1435         arcmsr_iop_message_read(acb);
1436         return (1);
1437 }
1438 /*
1439 **************************************************************************
1440 **************************************************************************
1441 */
1442 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1443         struct QBUFFER *prbuffer) {
1444
1445         u_int8_t *pQbuffer;
1446         u_int8_t *iop_data;
1447         u_int32_t iop_len;
1448
1449         if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1450                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1451         }
1452         iop_data = (u_int8_t *)prbuffer->data;
1453         iop_len = (u_int32_t)prbuffer->data_len;
1454         while (iop_len > 0) {
1455                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1456                 *pQbuffer = *iop_data;
1457                 acb->rqbuf_lastindex++;
1458                 /* if last, index number set it to 0 */
1459                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1460                 iop_data++;
1461                 iop_len--;
1462         }
1463         /* let IOP know data has been read */
1464         arcmsr_iop_message_read(acb);
1465         return (1);
1466 }
1467 /*
1468 **************************************************************************
1469 **************************************************************************
1470 */
1471 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1472 {
1473         struct QBUFFER *prbuffer;
1474         int my_empty_len;
1475
1476         /*check this iop data if overflow my rqbuffer*/
1477         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1478         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1479         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1480                 (ARCMSR_MAX_QBUFFER-1);
1481         if(my_empty_len >= prbuffer->data_len) {
1482                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1483                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1484         } else {
1485                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1486         }
1487         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1488 }
1489 /*
1490 **********************************************************************
1491 **********************************************************************
1492 */
1493 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1494 {
1495         u_int8_t *pQbuffer;
1496         struct QBUFFER *pwbuffer;
1497         u_int8_t *buf1 = 0;
1498         u_int32_t *iop_data, *buf2 = 0;
1499         u_int32_t allxfer_len = 0, data_len;
1500
1501         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1502                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1503                 buf2 = (u_int32_t *)buf1;
1504                 if( buf1 == NULL)
1505                         return;
1506
1507                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1508                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1509                 iop_data = (u_int32_t *)pwbuffer->data;
1510                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1511                         && (allxfer_len < 124)) {
1512                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1513                         *buf1 = *pQbuffer;
1514                         acb->wqbuf_firstindex++;
1515                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1516                         buf1++;
1517                         allxfer_len++;
1518                 }
1519                 pwbuffer->data_len = allxfer_len;
1520                 data_len = allxfer_len;
1521                 buf1 = (u_int8_t *)buf2;
1522                 while(data_len >= 4)
1523                 {
1524                         *iop_data++ = *buf2++;
1525                         data_len -= 4;
1526                 }
1527                 if(data_len)
1528                         *iop_data = *buf2;
1529                 free( buf1, M_DEVBUF);
1530                 arcmsr_iop_message_wrote(acb);
1531         }
1532 }
1533 /*
1534 **********************************************************************
1535 **********************************************************************
1536 */
1537 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1538 {
1539         u_int8_t *pQbuffer;
1540         struct QBUFFER *pwbuffer;
1541         u_int8_t *iop_data;
1542         int32_t allxfer_len=0;
1543
1544         if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1545                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1546                 return;
1547         }
1548         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1549                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1550                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1551                 iop_data = (u_int8_t *)pwbuffer->data;
1552                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1553                         && (allxfer_len < 124)) {
1554                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1555                         *iop_data = *pQbuffer;
1556                         acb->wqbuf_firstindex++;
1557                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1558                         iop_data++;
1559                         allxfer_len++;
1560                 }
1561                 pwbuffer->data_len = allxfer_len;
1562                 arcmsr_iop_message_wrote(acb);
1563         }
1564 }
1565 /*
1566 **************************************************************************
1567 **************************************************************************
1568 */
1569 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1570 {
1571         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1572         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1573         /*
1574         *****************************************************************
1575         **   check if there are any mail packages from user space program
1576         **   in my post bag, now is the time to send them into Areca's firmware
1577         *****************************************************************
1578         */
1579         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1580                 arcmsr_Write_data_2iop_wqbuffer(acb);
1581         }
1582         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1583                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1584         }
1585         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1586 }
1587 /*
1588 **************************************************************************
1589 **************************************************************************
1590 */
1591 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1592 {
1593 /*
1594         if (ccb->ccb_h.status != CAM_REQ_CMP)
1595                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1596                         "failure status=%x\n", ccb->ccb_h.target_id,
1597                         ccb->ccb_h.target_lun, ccb->ccb_h.status);
1598         else
1599                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1600 */
1601         xpt_free_path(ccb->ccb_h.path);
1602         xpt_free_ccb(ccb);
1603 }
1604
1605 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1606 {
1607         struct cam_path     *path;
1608         union ccb           *ccb;
1609
1610         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1611                         return;
1612         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1613         {
1614                 xpt_free_ccb(ccb);
1615                 return;
1616         }
1617 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1618         bzero(ccb, sizeof(union ccb));
1619         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1620         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1621         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1622         ccb->crcn.flags = CAM_FLAG_NONE;
1623         xpt_action(ccb);
1624 }
1625
1626
1627 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1628 {
1629         struct CommandControlBlock *srb;
1630         u_int32_t intmask_org;
1631         int i;
1632
1633         /* disable all outbound interrupts */
1634         intmask_org = arcmsr_disable_allintr(acb);
1635         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1636         {
1637                 srb = acb->psrb_pool[i];
1638                 if (srb->srb_state == ARCMSR_SRB_START)
1639                 {
1640                         if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1641                         {
1642                                 srb->srb_state = ARCMSR_SRB_ABORTED;
1643                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1644                                 arcmsr_srb_complete(srb, 1);
1645                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1646                         }
1647                 }
1648         }
1649         /* enable outbound Post Queue, outbound doorbell Interrupt */
1650         arcmsr_enable_allintr(acb, intmask_org);
1651 }
1652 /*
1653 **************************************************************************
1654 **************************************************************************
1655 */
1656 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1657         u_int32_t       devicemap;
1658         u_int32_t       target, lun;
1659         u_int32_t       deviceMapCurrent[4]={0};
1660         u_int8_t        *pDevMap;
1661
1662         switch (acb->adapter_type) {
1663         case ACB_ADAPTER_TYPE_A:
1664                 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1665                 for (target = 0; target < 4; target++)
1666                 {
1667                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1668                         devicemap += 4;
1669                 }
1670                 break;
1671
1672         case ACB_ADAPTER_TYPE_B:
1673                 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1674                 for (target = 0; target < 4; target++)
1675                 {
1676                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1677                         devicemap += 4;
1678                 }
1679                 break;
1680
1681         case ACB_ADAPTER_TYPE_C:
1682                 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1683                 for (target = 0; target < 4; target++)
1684                 {
1685                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1686                         devicemap += 4;
1687                 }
1688                 break;
1689         case ACB_ADAPTER_TYPE_D:
1690                 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1691                 for (target = 0; target < 4; target++)
1692                 {
1693                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1694                         devicemap += 4;
1695                 }
1696                 break;
1697         }
1698
1699         if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1700         {
1701                 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1702         }
1703         /*
1704         ** adapter posted CONFIG message
1705         ** copy the new map, note if there are differences with the current map
1706         */
1707         pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1708         for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1709         {
1710                 if (*pDevMap != acb->device_map[target])
1711                 {
1712                         u_int8_t difference, bit_check;
1713
1714                         difference = *pDevMap ^ acb->device_map[target];
1715                         for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1716                         {
1717                                 bit_check = (1 << lun);         /*check bit from 0....31*/
1718                                 if(difference & bit_check)
1719                                 {
1720                                         if(acb->device_map[target] & bit_check)
1721                                         {/* unit departed */
1722                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1723                                                 arcmsr_abort_dr_ccbs(acb, target, lun);
1724                                                 arcmsr_rescan_lun(acb, target, lun);
1725                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1726                                         }
1727                                         else
1728                                         {/* unit arrived */
1729                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1730                                                 arcmsr_rescan_lun(acb, target, lun);
1731                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1732                                         }
1733                                 }
1734                         }
1735 /*                      printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1736                         acb->device_map[target] = *pDevMap;
1737                 }
1738                 pDevMap++;
1739         }
1740 }
1741 /*
1742 **************************************************************************
1743 **************************************************************************
1744 */
1745 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1746         u_int32_t outbound_message;
1747
1748         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1749         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1750         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1751                 arcmsr_dr_handle( acb );
1752 }
1753 /*
1754 **************************************************************************
1755 **************************************************************************
1756 */
1757 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1758         u_int32_t outbound_message;
1759         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1760
1761         /* clear interrupts */
1762         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1763         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1764         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1765                 arcmsr_dr_handle( acb );
1766 }
1767 /*
1768 **************************************************************************
1769 **************************************************************************
1770 */
1771 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1772         u_int32_t outbound_message;
1773
1774         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1775         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1776         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1777                 arcmsr_dr_handle( acb );
1778 }
1779 /*
1780 **************************************************************************
1781 **************************************************************************
1782 */
1783 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1784         u_int32_t outbound_message;
1785
1786         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1787         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1788         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1789                 arcmsr_dr_handle( acb );
1790 }
1791 /*
1792 **************************************************************************
1793 **************************************************************************
1794 */
1795 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1796 {
1797         u_int32_t doorbell_status;
1798
1799         /*
1800         *******************************************************************
1801         **  Maybe here we need to check wrqbuffer_lock is lock or not
1802         **  DOORBELL: din! don!
1803         **  check if there are any mail need to pack from firmware
1804         *******************************************************************
1805         */
1806         doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1807         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1808         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1809                 arcmsr_iop2drv_data_wrote_handle(acb);
1810         }
1811         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1812                 arcmsr_iop2drv_data_read_handle(acb);
1813         }
1814 }
1815 /*
1816 **************************************************************************
1817 **************************************************************************
1818 */
1819 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1820 {
1821         u_int32_t doorbell_status;
1822
1823         /*
1824         *******************************************************************
1825         **  Maybe here we need to check wrqbuffer_lock is lock or not
1826         **  DOORBELL: din! don!
1827         **  check if there are any mail need to pack from firmware
1828         *******************************************************************
1829         */
1830         doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1831         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1832         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1833                 arcmsr_iop2drv_data_wrote_handle(acb);
1834         }
1835         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1836                 arcmsr_iop2drv_data_read_handle(acb);
1837         }
1838         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1839                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1840         }
1841 }
1842 /*
1843 **************************************************************************
1844 **************************************************************************
1845 */
1846 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1847 {
1848         u_int32_t doorbell_status;
1849
1850         /*
1851         *******************************************************************
1852         **  Maybe here we need to check wrqbuffer_lock is lock or not
1853         **  DOORBELL: din! don!
1854         **  check if there are any mail need to pack from firmware
1855         *******************************************************************
1856         */
1857         doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1858         if(doorbell_status)
1859                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1860         while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1861                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1862                         arcmsr_iop2drv_data_wrote_handle(acb);
1863                 }
1864                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1865                         arcmsr_iop2drv_data_read_handle(acb);
1866                 }
1867                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1868                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1869                 }
1870                 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1871                 if(doorbell_status)
1872                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1873         }
1874 }
1875 /*
1876 **************************************************************************
1877 **************************************************************************
1878 */
1879 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1880 {
1881         u_int32_t flag_srb;
1882         u_int16_t error;
1883
1884         /*
1885         *****************************************************************************
1886         **               areca cdb command done
1887         *****************************************************************************
1888         */
1889         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1890                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1891         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
1892                 0, outbound_queueport)) != 0xFFFFFFFF) {
1893                 /* check if command done with no error*/
1894         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
1895                 arcmsr_drain_donequeue(acb, flag_srb, error);
1896         }       /*drain reply FIFO*/
1897 }
1898 /*
1899 **************************************************************************
1900 **************************************************************************
1901 */
1902 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1903 {
1904         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1905         u_int32_t flag_srb;
1906         int index;
1907         u_int16_t error;
1908
1909         /*
1910         *****************************************************************************
1911         **               areca cdb command done
1912         *****************************************************************************
1913         */
1914         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1915                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1916         index = phbbmu->doneq_index;
1917         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
1918                 phbbmu->done_qbuffer[index] = 0;
1919                 index++;
1920                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1921                 phbbmu->doneq_index = index;
1922                 /* check if command done with no error*/
1923         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1924                 arcmsr_drain_donequeue(acb, flag_srb, error);
1925         }       /*drain reply FIFO*/
1926 }
1927 /*
1928 **************************************************************************
1929 **************************************************************************
1930 */
1931 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1932 {
1933         u_int32_t flag_srb,throttling = 0;
1934         u_int16_t error;
1935
1936         /*
1937         *****************************************************************************
1938         **               areca cdb command done
1939         *****************************************************************************
1940         */
1941         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1942         do {
1943                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1944                 if (flag_srb == 0xFFFFFFFF)
1945                         break;
1946                 /* check if command done with no error*/
1947                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1948                 arcmsr_drain_donequeue(acb, flag_srb, error);
1949                 throttling++;
1950                 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1951                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1952                         throttling = 0;
1953                 }
1954         } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
1955 }
1956 /*
1957 **********************************************************************
1958 **
1959 **********************************************************************
1960 */
1961 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1962 {
1963         uint16_t doneq_index, index_stripped;
1964
1965         doneq_index = phbdmu->doneq_index;
1966         if (doneq_index & 0x4000) {
1967                 index_stripped = doneq_index & 0xFF;
1968                 index_stripped += 1;
1969                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1970                 phbdmu->doneq_index = index_stripped ?
1971                     (index_stripped | 0x4000) : index_stripped;
1972         } else {
1973                 index_stripped = doneq_index;
1974                 index_stripped += 1;
1975                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1976                 phbdmu->doneq_index = index_stripped ?
1977                     index_stripped : (index_stripped | 0x4000);
1978         }
1979         return (phbdmu->doneq_index);
1980 }
1981 /*
1982 **************************************************************************
1983 **************************************************************************
1984 */
1985 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
1986 {
1987         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1988         u_int32_t outbound_write_pointer;
1989         u_int32_t addressLow;
1990         uint16_t doneq_index;
1991         u_int16_t error;
1992         /*
1993         *****************************************************************************
1994         **               areca cdb command done
1995         *****************************************************************************
1996         */
1997         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
1998                 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
1999                 return;
2000         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2001                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2002         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2003         doneq_index = phbdmu->doneq_index;
2004         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2005                 doneq_index = arcmsr_get_doneq_index(phbdmu);
2006                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2007                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2008                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2009                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2010                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2011         }
2012         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2013         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2014 }
2015 /*
2016 **********************************************************************
2017 **********************************************************************
2018 */
2019 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2020 {
2021         u_int32_t outbound_intStatus;
2022         /*
2023         *********************************************
2024         **   check outbound intstatus
2025         *********************************************
2026         */
2027         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2028         if(!outbound_intStatus) {
2029                 /*it must be share irq*/
2030                 return;
2031         }
2032         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2033         /* MU doorbell interrupts*/
2034         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2035                 arcmsr_hba_doorbell_isr(acb);
2036         }
2037         /* MU post queue interrupts*/
2038         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2039                 arcmsr_hba_postqueue_isr(acb);
2040         }
2041         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2042                 arcmsr_hba_message_isr(acb);
2043         }
2044 }
2045 /*
2046 **********************************************************************
2047 **********************************************************************
2048 */
2049 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2050 {
2051         u_int32_t outbound_doorbell;
2052         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2053         /*
2054         *********************************************
2055         **   check outbound intstatus
2056         *********************************************
2057         */
2058         outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2059         if(!outbound_doorbell) {
2060                 /*it must be share irq*/
2061                 return;
2062         }
2063         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2064         READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2065         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2066         /* MU ioctl transfer doorbell interrupts*/
2067         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2068                 arcmsr_iop2drv_data_wrote_handle(acb);
2069         }
2070         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2071                 arcmsr_iop2drv_data_read_handle(acb);
2072         }
2073         /* MU post queue interrupts*/
2074         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2075                 arcmsr_hbb_postqueue_isr(acb);
2076         }
2077         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2078                 arcmsr_hbb_message_isr(acb);
2079         }
2080 }
2081 /*
2082 **********************************************************************
2083 **********************************************************************
2084 */
2085 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2086 {
2087         u_int32_t host_interrupt_status;
2088         /*
2089         *********************************************
2090         **   check outbound intstatus
2091         *********************************************
2092         */
2093         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2094                 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2095                 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2096         if(!host_interrupt_status) {
2097                 /*it must be share irq*/
2098                 return;
2099         }
2100         do {
2101                 /* MU doorbell interrupts*/
2102                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2103                         arcmsr_hbc_doorbell_isr(acb);
2104                 }
2105                 /* MU post queue interrupts*/
2106                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2107                         arcmsr_hbc_postqueue_isr(acb);
2108                 }
2109                 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2110         } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2111 }
2112 /*
2113 **********************************************************************
2114 **********************************************************************
2115 */
2116 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2117 {
2118         u_int32_t host_interrupt_status;
2119         u_int32_t intmask_org;
2120         /*
2121         *********************************************
2122         **   check outbound intstatus
2123         *********************************************
2124         */
2125         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2126         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2127                 /*it must be share irq*/
2128                 return;
2129         }
2130         /* disable outbound interrupt */
2131         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2132         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2133         /* MU doorbell interrupts*/
2134         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2135                 arcmsr_hbd_doorbell_isr(acb);
2136         }
2137         /* MU post queue interrupts*/
2138         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2139                 arcmsr_hbd_postqueue_isr(acb);
2140         }
2141         /* enable all outbound interrupt */
2142         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2143 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2144 }
2145 /*
2146 ******************************************************************************
2147 ******************************************************************************
2148 */
2149 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2150 {
2151         switch (acb->adapter_type) {
2152         case ACB_ADAPTER_TYPE_A:
2153                 arcmsr_handle_hba_isr(acb);
2154                 break;
2155         case ACB_ADAPTER_TYPE_B:
2156                 arcmsr_handle_hbb_isr(acb);
2157                 break;
2158         case ACB_ADAPTER_TYPE_C:
2159                 arcmsr_handle_hbc_isr(acb);
2160                 break;
2161         case ACB_ADAPTER_TYPE_D:
2162                 arcmsr_handle_hbd_isr(acb);
2163                 break;
2164         default:
2165                 printf("arcmsr%d: interrupt service,"
2166                 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2167                 break;
2168         }
2169 }
2170 /*
2171 **********************************************************************
2172 **********************************************************************
2173 */
2174 static void arcmsr_intr_handler(void *arg)
2175 {
2176         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2177
2178         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2179         arcmsr_interrupt(acb);
2180         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2181 }
2182 /*
2183 ******************************************************************************
2184 ******************************************************************************
2185 */
2186 static void     arcmsr_polling_devmap(void *arg)
2187 {
2188         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2189         switch (acb->adapter_type) {
2190         case ACB_ADAPTER_TYPE_A:
2191                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2192                 break;
2193
2194         case ACB_ADAPTER_TYPE_B: {
2195                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2196                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2197                 }
2198                 break;
2199
2200         case ACB_ADAPTER_TYPE_C:
2201                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2202                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2203                 break;
2204
2205         case ACB_ADAPTER_TYPE_D:
2206                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2207                 break;
2208         }
2209
2210         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2211         {
2212                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2213         }
2214 }
2215
2216 /*
2217 *******************************************************************************
2218 **
2219 *******************************************************************************
2220 */
2221 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2222 {
2223         u_int32_t intmask_org;
2224
2225         if(acb != NULL) {
2226                 /* stop adapter background rebuild */
2227                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2228                         intmask_org = arcmsr_disable_allintr(acb);
2229                         arcmsr_stop_adapter_bgrb(acb);
2230                         arcmsr_flush_adapter_cache(acb);
2231                         arcmsr_enable_allintr(acb, intmask_org);
2232                 }
2233         }
2234 }
2235 /*
2236 ***********************************************************************
2237 **
2238 ************************************************************************
2239 */
2240 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2241 {
2242         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2243         u_int32_t retvalue = EINVAL;
2244
2245         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2246         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2247                 return retvalue;
2248         }
2249         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2250         switch(ioctl_cmd) {
2251         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2252                         u_int8_t *pQbuffer;
2253                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2254                         u_int32_t allxfer_len=0;
2255
2256                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2257                                 && (allxfer_len < 1031)) {
2258                                 /*copy READ QBUFFER to srb*/
2259                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2260                                 *ptmpQbuffer = *pQbuffer;
2261                                 acb->rqbuf_firstindex++;
2262                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2263                                 /*if last index number set it to 0 */
2264                                 ptmpQbuffer++;
2265                                 allxfer_len++;
2266                         }
2267                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2268                                 struct QBUFFER *prbuffer;
2269
2270                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2271                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2272                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2273                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2274                         }
2275                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2276                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2277                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2278                 }
2279                 break;
2280         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2281                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2282                         u_int8_t *pQbuffer;
2283                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2284
2285                         user_len = pcmdmessagefld->cmdmessage.Length;
2286                         /*check if data xfer length of this request will overflow my array qbuffer */
2287                         wqbuf_lastindex = acb->wqbuf_lastindex;
2288                         wqbuf_firstindex = acb->wqbuf_firstindex;
2289                         if(wqbuf_lastindex != wqbuf_firstindex) {
2290                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2291                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2292                         } else {
2293                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2294                                         (ARCMSR_MAX_QBUFFER - 1);
2295                                 if(my_empty_len >= user_len) {
2296                                         while(user_len > 0) {
2297                                                 /*copy srb data to wqbuffer*/
2298                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2299                                                 *pQbuffer = *ptmpuserbuffer;
2300                                                 acb->wqbuf_lastindex++;
2301                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2302                                                 /*if last index number set it to 0 */
2303                                                 ptmpuserbuffer++;
2304                                                 user_len--;
2305                                         }
2306                                         /*post fist Qbuffer*/
2307                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2308                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2309                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2310                                         }
2311                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2312                                 } else {
2313                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2314                                 }
2315                         }
2316                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2317                 }
2318                 break;
2319         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2320                         u_int8_t *pQbuffer = acb->rqbuffer;
2321
2322                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2323                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2324                                 arcmsr_iop_message_read(acb);
2325                                 /*signature, let IOP know data has been readed */
2326                         }
2327                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2328                         acb->rqbuf_firstindex = 0;
2329                         acb->rqbuf_lastindex = 0;
2330                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2331                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2332                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2333                 }
2334                 break;
2335         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2336                 {
2337                         u_int8_t *pQbuffer = acb->wqbuffer;
2338
2339                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2340                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2341                                 arcmsr_iop_message_read(acb);
2342                                 /*signature, let IOP know data has been readed */
2343                         }
2344                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2345                         acb->wqbuf_firstindex = 0;
2346                         acb->wqbuf_lastindex = 0;
2347                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2348                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2349                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2350                 }
2351                 break;
2352         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2353                         u_int8_t *pQbuffer;
2354
2355                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2356                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2357                                 arcmsr_iop_message_read(acb);
2358                                 /*signature, let IOP know data has been readed */
2359                         }
2360                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2361                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2362                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2363                         acb->rqbuf_firstindex = 0;
2364                         acb->rqbuf_lastindex = 0;
2365                         acb->wqbuf_firstindex = 0;
2366                         acb->wqbuf_lastindex = 0;
2367                         pQbuffer = acb->rqbuffer;
2368                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2369                         pQbuffer = acb->wqbuffer;
2370                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2371                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2372                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2373                 }
2374                 break;
2375         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2376                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2377                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2378                 }
2379                 break;
2380         case ARCMSR_MESSAGE_SAY_HELLO: {
2381                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2382                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2383
2384                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2385                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2386                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2387                                 return ENOIOCTL;
2388                         }
2389                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2390                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2391                 }
2392                 break;
2393         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2394                         arcmsr_iop_parking(acb);
2395                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2396                 }
2397                 break;
2398         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2399                         arcmsr_flush_adapter_cache(acb);
2400                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2401                 }
2402                 break;
2403         }
2404         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2405         return (retvalue);
2406 }
2407 /*
2408 **************************************************************************
2409 **************************************************************************
2410 */
2411 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2412 {
2413         struct AdapterControlBlock      *acb;
2414
2415         acb = srb->acb;
2416         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2417         srb->srb_state = ARCMSR_SRB_DONE;
2418         srb->srb_flags = 0;
2419         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2420         acb->workingsrb_doneindex++;
2421         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2422         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2423 }
2424 /*
2425 **************************************************************************
2426 **************************************************************************
2427 */
2428 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2429 {
2430         struct CommandControlBlock *srb = NULL;
2431         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2432
2433         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2434         workingsrb_doneindex = acb->workingsrb_doneindex;
2435         workingsrb_startindex = acb->workingsrb_startindex;
2436         srb = acb->srbworkingQ[workingsrb_startindex];
2437         workingsrb_startindex++;
2438         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2439         if(workingsrb_doneindex != workingsrb_startindex) {
2440                 acb->workingsrb_startindex = workingsrb_startindex;
2441         } else {
2442                 srb = NULL;
2443         }
2444         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2445         return(srb);
2446 }
2447 /*
2448 **************************************************************************
2449 **************************************************************************
2450 */
2451 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2452 {
2453         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2454         int retvalue = 0, transfer_len = 0;
2455         char *buffer;
2456         u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
2457                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
2458                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8  |
2459                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
2460                                         /* 4 bytes: Areca io control code */
2461         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2462                 buffer = pccb->csio.data_ptr;
2463                 transfer_len = pccb->csio.dxfer_len;
2464         } else {
2465                 retvalue = ARCMSR_MESSAGE_FAIL;
2466                 goto message_out;
2467         }
2468         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2469                 retvalue = ARCMSR_MESSAGE_FAIL;
2470                 goto message_out;
2471         }
2472         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2473         switch(controlcode) {
2474         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2475                         u_int8_t *pQbuffer;
2476                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2477                         int32_t allxfer_len = 0;
2478
2479                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2480                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2481                                 && (allxfer_len < 1031)) {
2482                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2483                                 *ptmpQbuffer = *pQbuffer;
2484                                 acb->rqbuf_firstindex++;
2485                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2486                                 ptmpQbuffer++;
2487                                 allxfer_len++;
2488                         }
2489                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2490                                 struct QBUFFER  *prbuffer;
2491
2492                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2493                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2494                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2495                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2496                         }
2497                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2498                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2499                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2500                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2501                 }
2502                 break;
2503         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2504                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2505                         u_int8_t *pQbuffer;
2506                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2507
2508                         user_len = pcmdmessagefld->cmdmessage.Length;
2509                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2510                         wqbuf_lastindex = acb->wqbuf_lastindex;
2511                         wqbuf_firstindex = acb->wqbuf_firstindex;
2512                         if (wqbuf_lastindex != wqbuf_firstindex) {
2513                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2514                                 /* has error report sensedata */
2515                                 if(pccb->csio.sense_len) {
2516                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2517                                 /* Valid,ErrorCode */
2518                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2519                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2520                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2521                                 /* AdditionalSenseLength */
2522                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2523                                 /* AdditionalSenseCode */
2524                                 }
2525                                 retvalue = ARCMSR_MESSAGE_FAIL;
2526                         } else {
2527                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2528                                                 &(ARCMSR_MAX_QBUFFER - 1);
2529                                 if (my_empty_len >= user_len) {
2530                                         while (user_len > 0) {
2531                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2532                                                 *pQbuffer = *ptmpuserbuffer;
2533                                                 acb->wqbuf_lastindex++;
2534                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2535                                                 ptmpuserbuffer++;
2536                                                 user_len--;
2537                                         }
2538                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2539                                                 acb->acb_flags &=
2540                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2541                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2542                                         }
2543                                 } else {
2544                                         /* has error report sensedata */
2545                                         if(pccb->csio.sense_len) {
2546                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2547                                         /* Valid,ErrorCode */
2548                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2549                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2550                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2551                                         /* AdditionalSenseLength */
2552                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2553                                         /* AdditionalSenseCode */
2554                                         }
2555                                         retvalue = ARCMSR_MESSAGE_FAIL;
2556                                 }
2557                         }
2558                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2559                 }
2560                 break;
2561         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2562                         u_int8_t *pQbuffer = acb->rqbuffer;
2563
2564                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2565                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2566                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2567                                 arcmsr_iop_message_read(acb);
2568                         }
2569                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2570                         acb->rqbuf_firstindex = 0;
2571                         acb->rqbuf_lastindex = 0;
2572                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2573                         pcmdmessagefld->cmdmessage.ReturnCode =
2574                             ARCMSR_MESSAGE_RETURNCODE_OK;
2575                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2576                 }
2577                 break;
2578         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2579                         u_int8_t *pQbuffer = acb->wqbuffer;
2580
2581                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2582                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2583                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2584                                 arcmsr_iop_message_read(acb);
2585                         }
2586                         acb->acb_flags |=
2587                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2588                                         ACB_F_MESSAGE_WQBUFFER_READ);
2589                         acb->wqbuf_firstindex = 0;
2590                         acb->wqbuf_lastindex = 0;
2591                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2592                         pcmdmessagefld->cmdmessage.ReturnCode =
2593                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2594                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2595                 }
2596                 break;
2597         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2598                         u_int8_t *pQbuffer;
2599
2600                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2601                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2602                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2603                                 arcmsr_iop_message_read(acb);
2604                         }
2605                         acb->acb_flags |=
2606                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2607                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2608                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2609                         acb->rqbuf_firstindex = 0;
2610                         acb->rqbuf_lastindex = 0;
2611                         acb->wqbuf_firstindex = 0;
2612                         acb->wqbuf_lastindex = 0;
2613                         pQbuffer = acb->rqbuffer;
2614                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2615                         pQbuffer = acb->wqbuffer;
2616                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2617                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2618                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2619                 }
2620                 break;
2621         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2622                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2623                 }
2624                 break;
2625         case ARCMSR_MESSAGE_SAY_HELLO: {
2626                         int8_t *hello_string = "Hello! I am ARCMSR";
2627
2628                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2629                                 , (int16_t)strlen(hello_string));
2630                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2631                 }
2632                 break;
2633         case ARCMSR_MESSAGE_SAY_GOODBYE:
2634                 arcmsr_iop_parking(acb);
2635                 break;
2636         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2637                 arcmsr_flush_adapter_cache(acb);
2638                 break;
2639         default:
2640                 retvalue = ARCMSR_MESSAGE_FAIL;
2641         }
2642 message_out:
2643         return (retvalue);
2644 }
2645 /*
2646 *********************************************************************
2647 *********************************************************************
2648 */
2649 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2650 {
2651         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2652         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2653         union ccb *pccb;
2654         int target, lun;
2655
2656         pccb = srb->pccb;
2657         target = pccb->ccb_h.target_id;
2658         lun = pccb->ccb_h.target_lun;
2659         acb->pktRequestCount++;
2660         if(error != 0) {
2661                 if(error != EFBIG) {
2662                         printf("arcmsr%d: unexpected error %x"
2663                                 " returned from 'bus_dmamap_load' \n"
2664                                 , acb->pci_unit, error);
2665                 }
2666                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2667                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2668                 }
2669                 arcmsr_srb_complete(srb, 0);
2670                 return;
2671         }
2672         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2673                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2674                 arcmsr_srb_complete(srb, 0);
2675                 return;
2676         }
2677         if(acb->acb_flags & ACB_F_BUS_RESET) {
2678                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2679                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2680                 arcmsr_srb_complete(srb, 0);
2681                 return;
2682         }
2683         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2684                 u_int8_t block_cmd, cmd;
2685
2686                 cmd = pccb->csio.cdb_io.cdb_bytes[0];
2687                 block_cmd = cmd & 0x0f;
2688                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2689                         printf("arcmsr%d:block 'read/write' command "
2690                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2691                                 , acb->pci_unit, cmd, target, lun);
2692                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2693                         arcmsr_srb_complete(srb, 0);
2694                         return;
2695                 }
2696         }
2697         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2698                 if(nseg != 0) {
2699                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2700                 }
2701                 arcmsr_srb_complete(srb, 0);
2702                 return;
2703         }
2704         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2705                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2706                 {
2707                         xpt_freeze_simq(acb->psim, 1);
2708                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2709                 }
2710                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2711                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2712                 arcmsr_srb_complete(srb, 0);
2713                 return;
2714         }
2715         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2716         arcmsr_build_srb(srb, dm_segs, nseg);
2717         arcmsr_post_srb(acb, srb);
2718         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2719         {
2720                 arcmsr_callout_init(&srb->ccb_callout);
2721                 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
2722                     (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
2723                     arcmsr_srb_timeout, srb, 0);
2724                 srb->srb_flags |= SRB_FLAG_TIMER_START;
2725         }
2726 }
2727 /*
2728 *****************************************************************************************
2729 *****************************************************************************************
2730 */
2731 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2732 {
2733         struct CommandControlBlock *srb;
2734         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2735         u_int32_t intmask_org;
2736         int i = 0;
2737
2738         acb->num_aborts++;
2739         /*
2740         ***************************************************************************
2741         ** It is the upper layer do abort command this lock just prior to calling us.
2742         ** First determine if we currently own this command.
2743         ** Start by searching the device queue. If not found
2744         ** at all, and the system wanted us to just abort the
2745         ** command return success.
2746         ***************************************************************************
2747         */
2748         if(acb->srboutstandingcount != 0) {
2749                 /* disable all outbound interrupt */
2750                 intmask_org = arcmsr_disable_allintr(acb);
2751                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2752                         srb = acb->psrb_pool[i];
2753                         if(srb->srb_state == ARCMSR_SRB_START) {
2754                                 if(srb->pccb == abortccb) {
2755                                         srb->srb_state = ARCMSR_SRB_ABORTED;
2756                                         printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
2757                                                 "outstanding command \n"
2758                                                 , acb->pci_unit, abortccb->ccb_h.target_id
2759                                                 , abortccb->ccb_h.target_lun, srb);
2760                                         arcmsr_polling_srbdone(acb, srb);
2761                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
2762                                         arcmsr_enable_allintr(acb, intmask_org);
2763                                         return (TRUE);
2764                                 }
2765                         }
2766                 }
2767                 /* enable outbound Post Queue, outbound doorbell Interrupt */
2768                 arcmsr_enable_allintr(acb, intmask_org);
2769         }
2770         return(FALSE);
2771 }
2772 /*
2773 ****************************************************************************
2774 ****************************************************************************
2775 */
2776 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2777 {
2778         int retry = 0;
2779
2780         acb->num_resets++;
2781         acb->acb_flags |= ACB_F_BUS_RESET;
2782         while(acb->srboutstandingcount != 0 && retry < 400) {
2783                 arcmsr_interrupt(acb);
2784                 UDELAY(25000);
2785                 retry++;
2786         }
2787         arcmsr_iop_reset(acb);
2788         acb->acb_flags &= ~ACB_F_BUS_RESET;
2789 }
2790 /*
2791 **************************************************************************
2792 **************************************************************************
2793 */
2794 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2795                 union ccb *pccb)
2796 {
2797         if (pccb->ccb_h.target_lun) {
2798                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2799                 xpt_done(pccb);
2800                 return;
2801         }
2802         pccb->ccb_h.status |= CAM_REQ_CMP;
2803         switch (pccb->csio.cdb_io.cdb_bytes[0]) {
2804         case INQUIRY: {
2805                 unsigned char inqdata[36];
2806                 char *buffer = pccb->csio.data_ptr;
2807
2808                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
2809                 inqdata[1] = 0;                 /* rem media bit & Dev Type Modifier */
2810                 inqdata[2] = 0;                 /* ISO, ECMA, & ANSI versions */
2811                 inqdata[3] = 0;
2812                 inqdata[4] = 31;                /* length of additional data */
2813                 inqdata[5] = 0;
2814                 inqdata[6] = 0;
2815                 inqdata[7] = 0;
2816                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
2817                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
2818                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2819                 memcpy(buffer, inqdata, sizeof(inqdata));
2820                 xpt_done(pccb);
2821         }
2822         break;
2823         case WRITE_BUFFER:
2824         case READ_BUFFER: {
2825                 if (arcmsr_iop_message_xfer(acb, pccb)) {
2826                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2827                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2828                 }
2829                 xpt_done(pccb);
2830         }
2831         break;
2832         default:
2833                 xpt_done(pccb);
2834         }
2835 }
2836 /*
2837 *********************************************************************
2838 *********************************************************************
2839 */
2840 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
2841 {
2842         struct AdapterControlBlock *acb;
2843
2844         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
2845         if(acb == NULL) {
2846                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2847                 xpt_done(pccb);
2848                 return;
2849         }
2850         switch (pccb->ccb_h.func_code) {
2851         case XPT_SCSI_IO: {
2852                         struct CommandControlBlock *srb;
2853                         int target = pccb->ccb_h.target_id;
2854                         int error;
2855
2856                         if(target == 16) {
2857                                 /* virtual device for iop message transfer */
2858                                 arcmsr_handle_virtual_command(acb, pccb);
2859                                 return;
2860                         }
2861                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
2862                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2863                                 xpt_done(pccb);
2864                                 return;
2865                         }
2866                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
2867                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
2868                         srb->pccb = pccb;
2869                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
2870                                 , srb->dm_segs_dmamap
2871                                 , pccb
2872                                 , arcmsr_execute_srb, srb, /*flags*/0);
2873                         if(error == EINPROGRESS) {
2874                                 xpt_freeze_simq(acb->psim, 1);
2875                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2876                         }
2877                         break;
2878                 }
2879         case XPT_TARGET_IO: {
2880                         /* target mode not yet support vendor specific commands. */
2881                         pccb->ccb_h.status |= CAM_REQ_CMP;
2882                         xpt_done(pccb);
2883                         break;
2884                 }
2885         case XPT_PATH_INQ: {
2886                         struct ccb_pathinq *cpi = &pccb->cpi;
2887
2888                         cpi->version_num = 1;
2889                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
2890                         cpi->target_sprt = 0;
2891                         cpi->hba_misc = 0;
2892                         cpi->hba_eng_cnt = 0;
2893                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
2894                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
2895                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2896                         cpi->bus_id = cam_sim_bus(psim);
2897                         strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2898                         strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2899                         strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2900                         cpi->unit_number = cam_sim_unit(psim);
2901                 #ifdef  CAM_NEW_TRAN_CODE
2902                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
2903                                 cpi->base_transfer_speed = 1200000;
2904                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2905                                 cpi->base_transfer_speed = 600000;
2906                         else
2907                                 cpi->base_transfer_speed = 300000;
2908                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2909                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2910                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2911                         {
2912                                 cpi->transport = XPORT_SAS;
2913                                 cpi->transport_version = 0;
2914                                 cpi->protocol_version = SCSI_REV_SPC2;
2915                         }
2916                         else
2917                         {
2918                                 cpi->transport = XPORT_SPI;
2919                                 cpi->transport_version = 2;
2920                                 cpi->protocol_version = SCSI_REV_2;
2921                         }
2922                         cpi->protocol = PROTO_SCSI;
2923                 #endif
2924                         cpi->ccb_h.status |= CAM_REQ_CMP;
2925                         xpt_done(pccb);
2926                         break;
2927                 }
2928         case XPT_ABORT: {
2929                         union ccb *pabort_ccb;
2930
2931                         pabort_ccb = pccb->cab.abort_ccb;
2932                         switch (pabort_ccb->ccb_h.func_code) {
2933                         case XPT_ACCEPT_TARGET_IO:
2934                         case XPT_IMMED_NOTIFY:
2935                         case XPT_CONT_TARGET_IO:
2936                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2937                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2938                                         xpt_done(pabort_ccb);
2939                                         pccb->ccb_h.status |= CAM_REQ_CMP;
2940                                 } else {
2941                                         xpt_print_path(pabort_ccb->ccb_h.path);
2942                                         printf("Not found\n");
2943                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
2944                                 }
2945                                 break;
2946                         case XPT_SCSI_IO:
2947                                 pccb->ccb_h.status |= CAM_UA_ABORT;
2948                                 break;
2949                         default:
2950                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2951                                 break;
2952                         }
2953                         xpt_done(pccb);
2954                         break;
2955                 }
2956         case XPT_RESET_BUS:
2957         case XPT_RESET_DEV: {
2958                         u_int32_t       i;
2959
2960                         arcmsr_bus_reset(acb);
2961                         for (i=0; i < 500; i++) {
2962                                 DELAY(1000);
2963                         }
2964                         pccb->ccb_h.status |= CAM_REQ_CMP;
2965                         xpt_done(pccb);
2966                         break;
2967                 }
2968         case XPT_TERM_IO: {
2969                         pccb->ccb_h.status |= CAM_REQ_INVALID;
2970                         xpt_done(pccb);
2971                         break;
2972                 }
2973         case XPT_GET_TRAN_SETTINGS: {
2974                         struct ccb_trans_settings *cts;
2975
2976                         if(pccb->ccb_h.target_id == 16) {
2977                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2978                                 xpt_done(pccb);
2979                                 break;
2980                         }
2981                         cts = &pccb->cts;
2982                 #ifdef  CAM_NEW_TRAN_CODE
2983                         {
2984                                 struct ccb_trans_settings_scsi *scsi;
2985                                 struct ccb_trans_settings_spi *spi;
2986                                 struct ccb_trans_settings_sas *sas;
2987
2988                                 scsi = &cts->proto_specific.scsi;
2989                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2990                                 scsi->valid = CTS_SCSI_VALID_TQ;
2991                                 cts->protocol = PROTO_SCSI;
2992
2993                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2994                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2995                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
2996                                 {
2997                                         cts->protocol_version = SCSI_REV_SPC2;
2998                                         cts->transport_version = 0;
2999                                         cts->transport = XPORT_SAS;
3000                                         sas = &cts->xport_specific.sas;
3001                                         sas->valid = CTS_SAS_VALID_SPEED;
3002                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3003                                                 sas->bitrate = 1200000;
3004                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3005                                                 sas->bitrate = 600000;
3006                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3007                                                 sas->bitrate = 300000;
3008                                 }
3009                                 else
3010                                 {
3011                                         cts->protocol_version = SCSI_REV_2;
3012                                         cts->transport_version = 2;
3013                                         cts->transport = XPORT_SPI;
3014                                         spi = &cts->xport_specific.spi;
3015                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3016                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3017                                                 spi->sync_period = 1;
3018                                         else
3019                                                 spi->sync_period = 2;
3020                                         spi->sync_offset = 32;
3021                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3022                                         spi->valid = CTS_SPI_VALID_DISC
3023                                                 | CTS_SPI_VALID_SYNC_RATE
3024                                                 | CTS_SPI_VALID_SYNC_OFFSET
3025                                                 | CTS_SPI_VALID_BUS_WIDTH;
3026                                 }
3027                         }
3028                 #else
3029                         {
3030                                 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3031                                 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3032                                         cts->sync_period = 1;
3033                                 else
3034                                         cts->sync_period = 2;
3035                                 cts->sync_offset = 32;
3036                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3037                                 cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3038                                 CCB_TRANS_SYNC_OFFSET_VALID |
3039                                 CCB_TRANS_BUS_WIDTH_VALID |
3040                                 CCB_TRANS_DISC_VALID |
3041                                 CCB_TRANS_TQ_VALID;
3042                         }
3043                 #endif
3044                         pccb->ccb_h.status |= CAM_REQ_CMP;
3045                         xpt_done(pccb);
3046                         break;
3047                 }
3048         case XPT_SET_TRAN_SETTINGS: {
3049                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3050                         xpt_done(pccb);
3051                         break;
3052                 }
3053         case XPT_CALC_GEOMETRY:
3054                         if(pccb->ccb_h.target_id == 16) {
3055                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3056                                 xpt_done(pccb);
3057                                 break;
3058                         }
3059 #if __FreeBSD_version >= 500000
3060                         cam_calc_geometry(&pccb->ccg, 1);
3061 #else
3062                         {
3063                         struct ccb_calc_geometry *ccg;
3064                         u_int32_t size_mb;
3065                         u_int32_t secs_per_cylinder;
3066
3067                         ccg = &pccb->ccg;
3068                         if (ccg->block_size == 0) {
3069                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3070                                 xpt_done(pccb);
3071                                 break;
3072                         }
3073                         if(((1024L * 1024L)/ccg->block_size) < 0) {
3074                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3075                                 xpt_done(pccb);
3076                                 break;
3077                         }
3078                         size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3079                         if(size_mb > 1024 ) {
3080                                 ccg->heads = 255;
3081                                 ccg->secs_per_track = 63;
3082                         } else {
3083                                 ccg->heads = 64;
3084                                 ccg->secs_per_track = 32;
3085                         }
3086                         secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3087                         ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3088                         pccb->ccb_h.status |= CAM_REQ_CMP;
3089                         }
3090 #endif
3091                         xpt_done(pccb);
3092                         break;
3093         default:
3094                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3095                 xpt_done(pccb);
3096                 break;
3097         }
3098 }
3099 /*
3100 **********************************************************************
3101 **********************************************************************
3102 */
3103 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3104 {
3105         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3106         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3107         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3108                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3109         }
3110 }
3111 /*
3112 **********************************************************************
3113 **********************************************************************
3114 */
3115 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3116 {
3117         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3118         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3119         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3120         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3121                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3122         }
3123 }
3124 /*
3125 **********************************************************************
3126 **********************************************************************
3127 */
3128 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3129 {
3130         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3131         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3132         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3133         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3134                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3135         }
3136 }
3137 /*
3138 **********************************************************************
3139 **********************************************************************
3140 */
3141 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3142 {
3143         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3144         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3145         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3146                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3147         }
3148 }
3149 /*
3150 **********************************************************************
3151 **********************************************************************
3152 */
3153 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3154 {
3155         switch (acb->adapter_type) {
3156         case ACB_ADAPTER_TYPE_A:
3157                 arcmsr_start_hba_bgrb(acb);
3158                 break;
3159         case ACB_ADAPTER_TYPE_B:
3160                 arcmsr_start_hbb_bgrb(acb);
3161                 break;
3162         case ACB_ADAPTER_TYPE_C:
3163                 arcmsr_start_hbc_bgrb(acb);
3164                 break;
3165         case ACB_ADAPTER_TYPE_D:
3166                 arcmsr_start_hbd_bgrb(acb);
3167                 break;
3168         }
3169 }
3170 /*
3171 **********************************************************************
3172 **
3173 **********************************************************************
3174 */
3175 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3176 {
3177         struct CommandControlBlock *srb;
3178         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3179         u_int16_t       error;
3180
3181 polling_ccb_retry:
3182         poll_count++;
3183         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3184         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3185         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3186         while(1) {
3187                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3188                         0, outbound_queueport)) == 0xFFFFFFFF) {
3189                         if(poll_srb_done) {
3190                                 break;/*chip FIFO no ccb for completion already*/
3191                         } else {
3192                                 UDELAY(25000);
3193                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3194                                         break;
3195                                 }
3196                                 goto polling_ccb_retry;
3197                         }
3198                 }
3199                 /* check if command done with no error*/
3200                 srb = (struct CommandControlBlock *)
3201                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3202                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3203                 poll_srb_done = (srb == poll_srb) ? 1:0;
3204                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3205                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3206                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3207                                         "poll command abort successfully \n"
3208                                         , acb->pci_unit
3209                                         , srb->pccb->ccb_h.target_id
3210                                         , srb->pccb->ccb_h.target_lun, srb);
3211                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3212                                 arcmsr_srb_complete(srb, 1);
3213                                 continue;
3214                         }
3215                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3216                                 "srboutstandingcount=%d \n"
3217                                 , acb->pci_unit
3218                                 , srb, acb->srboutstandingcount);
3219                         continue;
3220                 }
3221                 arcmsr_report_srb_state(acb, srb, error);
3222         }       /*drain reply FIFO*/
3223 }
3224 /*
3225 **********************************************************************
3226 **
3227 **********************************************************************
3228 */
3229 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3230 {
3231         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3232         struct CommandControlBlock *srb;
3233         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3234         int index;
3235         u_int16_t       error;
3236
3237 polling_ccb_retry:
3238         poll_count++;
3239         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3240         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3241         while(1) {
3242                 index = phbbmu->doneq_index;
3243                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3244                         if(poll_srb_done) {
3245                                 break;/*chip FIFO no ccb for completion already*/
3246                         } else {
3247                                 UDELAY(25000);
3248                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3249                                         break;
3250                                 }
3251                                 goto polling_ccb_retry;
3252                         }
3253                 }
3254                 phbbmu->done_qbuffer[index] = 0;
3255                 index++;
3256                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3257                 phbbmu->doneq_index = index;
3258                 /* check if command done with no error*/
3259                 srb = (struct CommandControlBlock *)
3260                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3261                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3262                 poll_srb_done = (srb == poll_srb) ? 1:0;
3263                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3264                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3265                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3266                                         "poll command abort successfully \n"
3267                                         , acb->pci_unit
3268                                         , srb->pccb->ccb_h.target_id
3269                                         , srb->pccb->ccb_h.target_lun, srb);
3270                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3271                                 arcmsr_srb_complete(srb, 1);
3272                                 continue;
3273                         }
3274                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3275                                 "srboutstandingcount=%d \n"
3276                                 , acb->pci_unit
3277                                 , srb, acb->srboutstandingcount);
3278                         continue;
3279                 }
3280                 arcmsr_report_srb_state(acb, srb, error);
3281         }       /*drain reply FIFO*/
3282 }
3283 /*
3284 **********************************************************************
3285 **
3286 **********************************************************************
3287 */
3288 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3289 {
3290         struct CommandControlBlock *srb;
3291         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3292         u_int16_t       error;
3293
3294 polling_ccb_retry:
3295         poll_count++;
3296         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3297         while(1) {
3298                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3299                         if(poll_srb_done) {
3300                                 break;/*chip FIFO no ccb for completion already*/
3301                         } else {
3302                                 UDELAY(25000);
3303                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3304                                         break;
3305                                 }
3306                                 if (acb->srboutstandingcount == 0) {
3307                                     break;
3308                                 }
3309                                 goto polling_ccb_retry;
3310                         }
3311                 }
3312                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3313                 /* check if command done with no error*/
3314                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3315                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3316                 if (poll_srb != NULL)
3317                         poll_srb_done = (srb == poll_srb) ? 1:0;
3318                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3319                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3320                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3321                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3322                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3323                                 arcmsr_srb_complete(srb, 1);
3324                                 continue;
3325                         }
3326                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3327                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3328                         continue;
3329                 }
3330                 arcmsr_report_srb_state(acb, srb, error);
3331         }       /*drain reply FIFO*/
3332 }
3333 /*
3334 **********************************************************************
3335 **
3336 **********************************************************************
3337 */
3338 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3339 {
3340         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3341         struct CommandControlBlock *srb;
3342         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3343         u_int32_t outbound_write_pointer;
3344         u_int16_t       error, doneq_index;
3345
3346 polling_ccb_retry:
3347         poll_count++;
3348         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3349         while(1) {
3350                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3351                 doneq_index = phbdmu->doneq_index;
3352                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3353                         if(poll_srb_done) {
3354                                 break;/*chip FIFO no ccb for completion already*/
3355                         } else {
3356                                 UDELAY(25000);
3357                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3358                                         break;
3359                                 }
3360                                 if (acb->srboutstandingcount == 0) {
3361                                         break;
3362                                 }
3363                                 goto polling_ccb_retry;
3364                         }
3365                 }
3366                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3367                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3368                 /* check if command done with no error*/
3369                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3370                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3371                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3372                 if (poll_srb != NULL)
3373                         poll_srb_done = (srb == poll_srb) ? 1:0;
3374                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3375                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3376                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3377                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3378                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3379                                 arcmsr_srb_complete(srb, 1);
3380                                 continue;
3381                         }
3382                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3383                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3384                         continue;
3385                 }
3386                 arcmsr_report_srb_state(acb, srb, error);
3387         }       /*drain reply FIFO*/
3388 }
3389 /*
3390 **********************************************************************
3391 **********************************************************************
3392 */
3393 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3394 {
3395         switch (acb->adapter_type) {
3396         case ACB_ADAPTER_TYPE_A: {
3397                         arcmsr_polling_hba_srbdone(acb, poll_srb);
3398                 }
3399                 break;
3400         case ACB_ADAPTER_TYPE_B: {
3401                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
3402                 }
3403                 break;
3404         case ACB_ADAPTER_TYPE_C: {
3405                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
3406                 }
3407                 break;
3408         case ACB_ADAPTER_TYPE_D: {
3409                         arcmsr_polling_hbd_srbdone(acb, poll_srb);
3410                 }
3411                 break;
3412         }
3413 }
3414 /*
3415 **********************************************************************
3416 **********************************************************************
3417 */
3418 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3419 {
3420         char *acb_firm_model = acb->firm_model;
3421         char *acb_firm_version = acb->firm_version;
3422         char *acb_device_map = acb->device_map;
3423         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3424         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3425         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3426         int i;
3427
3428         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3429         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3430                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3431         }
3432         i = 0;
3433         while(i < 8) {
3434                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3435                 /* 8 bytes firm_model, 15, 60-67*/
3436                 acb_firm_model++;
3437                 i++;
3438         }
3439         i=0;
3440         while(i < 16) {
3441                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3442                 /* 16 bytes firm_version, 17, 68-83*/
3443                 acb_firm_version++;
3444                 i++;
3445         }
3446         i=0;
3447         while(i < 16) {
3448                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3449                 acb_device_map++;
3450                 i++;
3451         }
3452         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3453         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3454         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3455         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3456         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3457         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3458         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3459                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3460         else
3461                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3462 }
3463 /*
3464 **********************************************************************
3465 **********************************************************************
3466 */
3467 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3468 {
3469         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3470         char *acb_firm_model = acb->firm_model;
3471         char *acb_firm_version = acb->firm_version;
3472         char *acb_device_map = acb->device_map;
3473         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3474         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3475         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3476         int i;
3477
3478         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3479         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3480                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3481         }
3482         i = 0;
3483         while(i < 8) {
3484                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3485                 /* 8 bytes firm_model, 15, 60-67*/
3486                 acb_firm_model++;
3487                 i++;
3488         }
3489         i = 0;
3490         while(i < 16) {
3491                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3492                 /* 16 bytes firm_version, 17, 68-83*/
3493                 acb_firm_version++;
3494                 i++;
3495         }
3496         i = 0;
3497         while(i < 16) {
3498                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3499                 acb_device_map++;
3500                 i++;
3501         }
3502         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3503         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3504         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3505         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3506         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3507         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3508         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3509                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3510         else
3511                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3512 }
3513 /*
3514 **********************************************************************
3515 **********************************************************************
3516 */
3517 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3518 {
3519         char *acb_firm_model = acb->firm_model;
3520         char *acb_firm_version = acb->firm_version;
3521         char *acb_device_map = acb->device_map;
3522         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3523         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3524         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3525         int i;
3526
3527         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3528         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3529         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3530                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3531         }
3532         i = 0;
3533         while(i < 8) {
3534                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3535                 /* 8 bytes firm_model, 15, 60-67*/
3536                 acb_firm_model++;
3537                 i++;
3538         }
3539         i = 0;
3540         while(i < 16) {
3541                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3542                 /* 16 bytes firm_version, 17, 68-83*/
3543                 acb_firm_version++;
3544                 i++;
3545         }
3546         i = 0;
3547         while(i < 16) {
3548                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3549                 acb_device_map++;
3550                 i++;
3551         }
3552         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3553         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3554         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3555         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3556         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3557         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3558         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3559                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3560         else
3561                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3562 }
3563 /*
3564 **********************************************************************
3565 **********************************************************************
3566 */
3567 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3568 {
3569         char *acb_firm_model = acb->firm_model;
3570         char *acb_firm_version = acb->firm_version;
3571         char *acb_device_map = acb->device_map;
3572         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3573         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3574         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3575         int i;
3576
3577         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3578                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3579         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3580         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3581                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3582         }
3583         i = 0;
3584         while(i < 8) {
3585                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3586                 /* 8 bytes firm_model, 15, 60-67*/
3587                 acb_firm_model++;
3588                 i++;
3589         }
3590         i = 0;
3591         while(i < 16) {
3592                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3593                 /* 16 bytes firm_version, 17, 68-83*/
3594                 acb_firm_version++;
3595                 i++;
3596         }
3597         i = 0;
3598         while(i < 16) {
3599                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3600                 acb_device_map++;
3601                 i++;
3602         }
3603         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3604         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3605         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3606         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3607         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3608         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3609         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3610                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3611         else
3612                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3613 }
3614 /*
3615 **********************************************************************
3616 **********************************************************************
3617 */
3618 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3619 {
3620         switch (acb->adapter_type) {
3621         case ACB_ADAPTER_TYPE_A: {
3622                         arcmsr_get_hba_config(acb);
3623                 }
3624                 break;
3625         case ACB_ADAPTER_TYPE_B: {
3626                         arcmsr_get_hbb_config(acb);
3627                 }
3628                 break;
3629         case ACB_ADAPTER_TYPE_C: {
3630                         arcmsr_get_hbc_config(acb);
3631                 }
3632                 break;
3633         case ACB_ADAPTER_TYPE_D: {
3634                         arcmsr_get_hbd_config(acb);
3635                 }
3636                 break;
3637         }
3638 }
3639 /*
3640 **********************************************************************
3641 **********************************************************************
3642 */
3643 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3644 {
3645         int     timeout=0;
3646
3647         switch (acb->adapter_type) {
3648         case ACB_ADAPTER_TYPE_A: {
3649                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3650                         {
3651                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3652                                 {
3653                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3654                                         return;
3655                                 }
3656                                 UDELAY(15000); /* wait 15 milli-seconds */
3657                         }
3658                 }
3659                 break;
3660         case ACB_ADAPTER_TYPE_B: {
3661                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3662                         while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3663                         {
3664                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3665                                 {
3666                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3667                                         return;
3668                                 }
3669                                 UDELAY(15000); /* wait 15 milli-seconds */
3670                         }
3671                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3672                 }
3673                 break;
3674         case ACB_ADAPTER_TYPE_C: {
3675                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3676                         {
3677                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3678                                 {
3679                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3680                                         return;
3681                                 }
3682                                 UDELAY(15000); /* wait 15 milli-seconds */
3683                         }
3684                 }
3685                 break;
3686         case ACB_ADAPTER_TYPE_D: {
3687                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3688                         {
3689                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3690                                 {
3691                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3692                                         return;
3693                                 }
3694                                 UDELAY(15000); /* wait 15 milli-seconds */
3695                         }
3696                 }
3697                 break;
3698         }
3699 }
3700 /*
3701 **********************************************************************
3702 **********************************************************************
3703 */
3704 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3705 {
3706         u_int32_t outbound_doorbell;
3707
3708         switch (acb->adapter_type) {
3709         case ACB_ADAPTER_TYPE_A: {
3710                         /* empty doorbell Qbuffer if door bell ringed */
3711                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3712                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3713                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3714
3715                 }
3716                 break;
3717         case ACB_ADAPTER_TYPE_B: {
3718                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3719                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3720                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3721                         /* let IOP know data has been read */
3722                 }
3723                 break;
3724         case ACB_ADAPTER_TYPE_C: {
3725                         /* empty doorbell Qbuffer if door bell ringed */
3726                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3727                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
3728                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3729                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
3730                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
3731                 }
3732                 break;
3733         case ACB_ADAPTER_TYPE_D: {
3734                         /* empty doorbell Qbuffer if door bell ringed */
3735                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
3736                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3737                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
3738
3739                 }
3740                 break;
3741         }
3742 }
3743 /*
3744 ************************************************************************
3745 ************************************************************************
3746 */
3747 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3748 {
3749         unsigned long srb_phyaddr;
3750         u_int32_t srb_phyaddr_hi32;
3751         u_int32_t srb_phyaddr_lo32;
3752
3753         /*
3754         ********************************************************************
3755         ** here we need to tell iop 331 our freesrb.HighPart
3756         ** if freesrb.HighPart is not zero
3757         ********************************************************************
3758         */
3759         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
3760         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
3761         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
3762         switch (acb->adapter_type) {
3763         case ACB_ADAPTER_TYPE_A: {
3764                         if(srb_phyaddr_hi32 != 0) {
3765                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3766                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3767                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3768                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3769                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3770                                         return FALSE;
3771                                 }
3772                         }
3773                 }
3774                 break;
3775                 /*
3776                 ***********************************************************************
3777                 **    if adapter type B, set window of "post command Q"
3778                 ***********************************************************************
3779                 */
3780         case ACB_ADAPTER_TYPE_B: {
3781                         u_int32_t post_queue_phyaddr;
3782                         struct HBB_MessageUnit *phbbmu;
3783
3784                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3785                         phbbmu->postq_index = 0;
3786                         phbbmu->doneq_index = 0;
3787                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3788                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3789                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3790                                 return FALSE;
3791                         }
3792                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
3793                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
3794                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3795                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3796                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3797                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3798                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3799                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3800                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3801                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3802                                 return FALSE;
3803                         }
3804                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3805                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3806                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3807                                 return FALSE;
3808                         }
3809                 }
3810                 break;
3811         case ACB_ADAPTER_TYPE_C: {
3812                         if(srb_phyaddr_hi32 != 0) {
3813                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3814                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3815                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3816                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3817                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3818                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3819                                         return FALSE;
3820                                 }
3821                         }
3822                 }
3823                 break;
3824         case ACB_ADAPTER_TYPE_D: {
3825                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
3826                         struct HBD_MessageUnit0 *phbdmu;
3827
3828                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3829                         phbdmu->postq_index = 0;
3830                         phbdmu->doneq_index = 0x40FF;
3831                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3832                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
3833                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3834                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
3835                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3836                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3837                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
3838                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
3839                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
3840                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3841                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3842                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3843                                 return FALSE;
3844                         }
3845                 }
3846                 break;
3847         }
3848         return (TRUE);
3849 }
3850 /*
3851 ************************************************************************
3852 ************************************************************************
3853 */
3854 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3855 {
3856         switch (acb->adapter_type)
3857         {
3858         case ACB_ADAPTER_TYPE_A:
3859         case ACB_ADAPTER_TYPE_C:
3860         case ACB_ADAPTER_TYPE_D:
3861                 break;
3862         case ACB_ADAPTER_TYPE_B: {
3863                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3864                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3865                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3866                                 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3867                                 return;
3868                         }
3869                 }
3870                 break;
3871         }
3872 }
3873 /*
3874 **********************************************************************
3875 **********************************************************************
3876 */
3877 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3878 {
3879         u_int32_t intmask_org;
3880
3881         /* disable all outbound interrupt */
3882         intmask_org = arcmsr_disable_allintr(acb);
3883         arcmsr_wait_firmware_ready(acb);
3884         arcmsr_iop_confirm(acb);
3885         arcmsr_get_firmware_spec(acb);
3886         /*start background rebuild*/
3887         arcmsr_start_adapter_bgrb(acb);
3888         /* empty doorbell Qbuffer if door bell ringed */
3889         arcmsr_clear_doorbell_queue_buffer(acb);
3890         arcmsr_enable_eoi_mode(acb);
3891         /* enable outbound Post Queue, outbound doorbell Interrupt */
3892         arcmsr_enable_allintr(acb, intmask_org);
3893         acb->acb_flags |= ACB_F_IOP_INITED;
3894 }
3895 /*
3896 **********************************************************************
3897 **********************************************************************
3898 */
3899 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3900 {
3901         struct AdapterControlBlock *acb = arg;
3902         struct CommandControlBlock *srb_tmp;
3903         u_int32_t i;
3904         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
3905
3906         acb->srb_phyaddr.phyaddr = srb_phyaddr;
3907         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
3908         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3909                 if(bus_dmamap_create(acb->dm_segs_dmat,
3910                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
3911                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3912                         printf("arcmsr%d:"
3913                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3914                         return;
3915                 }
3916                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
3917                 {
3918                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
3919                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
3920                 }
3921                 else
3922                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
3923                 srb_tmp->acb = acb;
3924                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
3925                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
3926                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
3927         }
3928         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
3929 }
3930 /*
3931 ************************************************************************
3932 ************************************************************************
3933 */
3934 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3935 {
3936         /* remove the control device */
3937         if(acb->ioctl_dev != NULL) {
3938                 destroy_dev(acb->ioctl_dev);
3939         }
3940         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3941         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3942         bus_dma_tag_destroy(acb->srb_dmat);
3943         bus_dma_tag_destroy(acb->dm_segs_dmat);
3944         bus_dma_tag_destroy(acb->parent_dmat);
3945 }
3946 /*
3947 ************************************************************************
3948 ************************************************************************
3949 */
3950 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
3951 {
3952         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
3953         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
3954         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
3955         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
3956 }
3957 /*
3958 ************************************************************************
3959 ************************************************************************
3960 */
3961 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
3962 {
3963         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3964         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
3965         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
3966         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
3967 }
3968 /*
3969 ************************************************************************
3970 ************************************************************************
3971 */
3972 static u_int32_t arcmsr_initialize(device_t dev)
3973 {
3974         struct AdapterControlBlock *acb = device_get_softc(dev);
3975         u_int16_t pci_command;
3976         int i, j,max_coherent_size;
3977         u_int32_t vendor_dev_id;
3978
3979         vendor_dev_id = pci_get_devid(dev);
3980         acb->vendor_device_id = vendor_dev_id;
3981         acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3982         switch (vendor_dev_id) {
3983         case PCIDevVenIDARC1880:
3984         case PCIDevVenIDARC1882:
3985         case PCIDevVenIDARC1213:
3986         case PCIDevVenIDARC1223: {
3987                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
3988                         if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
3989                                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
3990                         else
3991                                 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3992                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3993                 }
3994                 break;
3995         case PCIDevVenIDARC1214: {
3996                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
3997                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3998                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
3999                 }
4000                 break;
4001         case PCIDevVenIDARC1200:
4002         case PCIDevVenIDARC1201: {
4003                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4004                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4005                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4006                 }
4007                 break;
4008         case PCIDevVenIDARC1203: {
4009                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4010                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4011                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4012                 }
4013                 break;
4014         case PCIDevVenIDARC1110:
4015         case PCIDevVenIDARC1120:
4016         case PCIDevVenIDARC1130:
4017         case PCIDevVenIDARC1160:
4018         case PCIDevVenIDARC1170:
4019         case PCIDevVenIDARC1210:
4020         case PCIDevVenIDARC1220:
4021         case PCIDevVenIDARC1230:
4022         case PCIDevVenIDARC1231:
4023         case PCIDevVenIDARC1260:
4024         case PCIDevVenIDARC1261:
4025         case PCIDevVenIDARC1270:
4026         case PCIDevVenIDARC1280:
4027         case PCIDevVenIDARC1212:
4028         case PCIDevVenIDARC1222:
4029         case PCIDevVenIDARC1380:
4030         case PCIDevVenIDARC1381:
4031         case PCIDevVenIDARC1680:
4032         case PCIDevVenIDARC1681: {
4033                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
4034                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4035                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4036                 }
4037                 break;
4038         default: {
4039                         printf("arcmsr%d:"
4040                         " unknown RAID adapter type \n", device_get_unit(dev));
4041                         return ENOMEM;
4042                 }
4043         }
4044 #if __FreeBSD_version >= 700000
4045         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4046 #else
4047         if(bus_dma_tag_create(  /*PCI parent*/          NULL,
4048 #endif
4049                                 /*alignemnt*/           1,
4050                                 /*boundary*/            0,
4051                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4052                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4053                                 /*filter*/              NULL,
4054                                 /*filterarg*/           NULL,
4055                                 /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4056                                 /*nsegments*/           BUS_SPACE_UNRESTRICTED,
4057                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4058                                 /*flags*/               0,
4059 #if __FreeBSD_version >= 501102
4060                                 /*lockfunc*/            NULL,
4061                                 /*lockarg*/             NULL,
4062 #endif
4063                                                         &acb->parent_dmat) != 0)
4064         {
4065                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4066                 return ENOMEM;
4067         }
4068
4069         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4070         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4071                                 /*alignment*/           1,
4072                                 /*boundary*/            0,
4073 #ifdef PAE
4074                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4075 #else
4076                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4077 #endif
4078                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4079                                 /*filter*/              NULL,
4080                                 /*filterarg*/           NULL,
4081                                 /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4082                                 /*nsegments*/           ARCMSR_MAX_SG_ENTRIES,
4083                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4084                                 /*flags*/               0,
4085 #if __FreeBSD_version >= 501102
4086                                 /*lockfunc*/            busdma_lock_mutex,
4087                                 /*lockarg*/             &acb->isr_lock,
4088 #endif
4089                                                         &acb->dm_segs_dmat) != 0)
4090         {
4091                 bus_dma_tag_destroy(acb->parent_dmat);
4092                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4093                 return ENOMEM;
4094         }
4095
4096         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4097         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4098                                 /*alignment*/           0x20,
4099                                 /*boundary*/            0,
4100                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4101                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4102                                 /*filter*/              NULL,
4103                                 /*filterarg*/           NULL,
4104                                 /*maxsize*/             max_coherent_size,
4105                                 /*nsegments*/           1,
4106                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4107                                 /*flags*/               0,
4108 #if __FreeBSD_version >= 501102
4109                                 /*lockfunc*/            NULL,
4110                                 /*lockarg*/             NULL,
4111 #endif
4112                                                         &acb->srb_dmat) != 0)
4113         {
4114                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4115                 bus_dma_tag_destroy(acb->parent_dmat);
4116                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4117                 return ENXIO;
4118         }
4119         /* Allocation for our srbs */
4120         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4121                 bus_dma_tag_destroy(acb->srb_dmat);
4122                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4123                 bus_dma_tag_destroy(acb->parent_dmat);
4124                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4125                 return ENXIO;
4126         }
4127         /* And permanently map them */
4128         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4129                 bus_dma_tag_destroy(acb->srb_dmat);
4130                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4131                 bus_dma_tag_destroy(acb->parent_dmat);
4132                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4133                 return ENXIO;
4134         }
4135         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4136         pci_command |= PCIM_CMD_BUSMASTEREN;
4137         pci_command |= PCIM_CMD_PERRESPEN;
4138         pci_command |= PCIM_CMD_MWRICEN;
4139         /* Enable Busmaster */
4140         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4141         switch(acb->adapter_type) {
4142         case ACB_ADAPTER_TYPE_A: {
4143                         u_int32_t rid0 = PCIR_BAR(0);
4144                         vm_offset_t     mem_base0;
4145
4146                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
4147                         if(acb->sys_res_arcmsr[0] == NULL) {
4148                                 arcmsr_free_resource(acb);
4149                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4150                                 return ENOMEM;
4151                         }
4152                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4153                                 arcmsr_free_resource(acb);
4154                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4155                                 return ENXIO;
4156                         }
4157                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4158                         if(mem_base0 == 0) {
4159                                 arcmsr_free_resource(acb);
4160                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4161                                 return ENXIO;
4162                         }
4163                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4164                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4165                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4166                 }
4167                 break;
4168         case ACB_ADAPTER_TYPE_B: {
4169                         struct HBB_MessageUnit *phbbmu;
4170                         struct CommandControlBlock *freesrb;
4171                         u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4172                         vm_offset_t     mem_base[]={0,0};
4173                         u_long  size;
4174                         if (vendor_dev_id == PCIDevVenIDARC1203)
4175                                 size = sizeof(struct HBB_DOORBELL_1203);
4176                         else
4177                                 size = sizeof(struct HBB_DOORBELL);
4178                         for(i=0; i < 2; i++) {
4179                                 if(i == 0) {
4180                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
4181                                                                                         0ul, ~0ul, size, RF_ACTIVE);
4182                                 } else {
4183                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
4184                                                                                         0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
4185                                 }
4186                                 if(acb->sys_res_arcmsr[i] == NULL) {
4187                                         arcmsr_free_resource(acb);
4188                                         printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4189                                         return ENOMEM;
4190                                 }
4191                                 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4192                                         arcmsr_free_resource(acb);
4193                                         printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4194                                         return ENXIO;
4195                                 }
4196                                 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4197                                 if(mem_base[i] == 0) {
4198                                         arcmsr_free_resource(acb);
4199                                         printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4200                                         return ENXIO;
4201                                 }
4202                                 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4203                                 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4204                         }
4205                         freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4206                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4207                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4208                         phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4209                         phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4210                         if (vendor_dev_id == PCIDevVenIDARC1203) {
4211                                 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4212                                 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4213                                 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4214                                 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4215                         } else {
4216                                 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4217                                 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4218                                 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4219                                 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4220                         }
4221                 }
4222                 break;
4223         case ACB_ADAPTER_TYPE_C: {
4224                         u_int32_t rid0 = PCIR_BAR(1);
4225                         vm_offset_t     mem_base0;
4226
4227                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
4228                         if(acb->sys_res_arcmsr[0] == NULL) {
4229                                 arcmsr_free_resource(acb);
4230                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4231                                 return ENOMEM;
4232                         }
4233                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4234                                 arcmsr_free_resource(acb);
4235                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4236                                 return ENXIO;
4237                         }
4238                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4239                         if(mem_base0 == 0) {
4240                                 arcmsr_free_resource(acb);
4241                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4242                                 return ENXIO;
4243                         }
4244                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4245                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4246                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4247                 }
4248                 break;
4249         case ACB_ADAPTER_TYPE_D: {
4250                         struct HBD_MessageUnit0 *phbdmu;
4251                         u_int32_t rid0 = PCIR_BAR(0);
4252                         vm_offset_t     mem_base0;
4253
4254                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
4255                         if(acb->sys_res_arcmsr[0] == NULL) {
4256                                 arcmsr_free_resource(acb);
4257                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4258                                 return ENOMEM;
4259                         }
4260                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4261                                 arcmsr_free_resource(acb);
4262                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4263                                 return ENXIO;
4264                         }
4265                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4266                         if(mem_base0 == 0) {
4267                                 arcmsr_free_resource(acb);
4268                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4269                                 return ENXIO;
4270                         }
4271                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4272                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4273                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4274                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4275                         phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4276                 }
4277                 break;
4278         }
4279         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4280                 arcmsr_free_resource(acb);
4281                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4282                 return ENXIO;
4283         }
4284         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4285         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4286         /*
4287         ********************************************************************
4288         ** init raid volume state
4289         ********************************************************************
4290         */
4291         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4292                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4293                         acb->devstate[i][j] = ARECA_RAID_GONE;
4294                 }
4295         }
4296         arcmsr_iop_init(acb);
4297         return(0);
4298 }
4299 /*
4300 ************************************************************************
4301 ************************************************************************
4302 */
4303 static int arcmsr_attach(device_t dev)
4304 {
4305         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4306         u_int32_t unit=device_get_unit(dev);
4307         struct ccb_setasync csa;
4308         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4309         struct resource *irqres;
4310         int     rid;
4311
4312         if(acb == NULL) {
4313                 printf("arcmsr%d: cannot allocate softc\n", unit);
4314                 return (ENOMEM);
4315         }
4316         arcmsr_mutex_init(acb);
4317         acb->pci_dev = dev;
4318         acb->pci_unit = unit;
4319         if(arcmsr_initialize(dev)) {
4320                 printf("arcmsr%d: initialize failure!\n", unit);
4321                 arcmsr_mutex_destroy(acb);
4322                 return ENXIO;
4323         }
4324         /* After setting up the adapter, map our interrupt */
4325         rid = 0;
4326         irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE);
4327         if(irqres == NULL ||
4328 #if __FreeBSD_version >= 700025
4329                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
4330 #else
4331                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
4332 #endif
4333                 arcmsr_free_resource(acb);
4334                 arcmsr_mutex_destroy(acb);
4335                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4336                 return ENXIO;
4337         }
4338         acb->irqres = irqres;
4339         /*
4340          * Now let the CAM generic SCSI layer find the SCSI devices on
4341          * the bus *  start queue to reset to the idle loop. *
4342          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4343          * max_sim_transactions
4344         */
4345         devq = cam_simq_alloc(acb->maxOutstanding);
4346         if(devq == NULL) {
4347                 arcmsr_free_resource(acb);
4348                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4349                 arcmsr_mutex_destroy(acb);
4350                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4351                 return ENXIO;
4352         }
4353 #if __FreeBSD_version >= 700025
4354         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4355 #else
4356         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4357 #endif
4358         if(acb->psim == NULL) {
4359                 arcmsr_free_resource(acb);
4360                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4361                 cam_simq_free(devq);
4362                 arcmsr_mutex_destroy(acb);
4363                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4364                 return ENXIO;
4365         }
4366         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4367 #if __FreeBSD_version >= 700044
4368         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4369 #else
4370         if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4371 #endif
4372                 arcmsr_free_resource(acb);
4373                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4374                 cam_sim_free(acb->psim, /*free_devq*/TRUE);
4375                 arcmsr_mutex_destroy(acb);
4376                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4377                 return ENXIO;
4378         }
4379         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4380                 arcmsr_free_resource(acb);
4381                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4382                 xpt_bus_deregister(cam_sim_path(acb->psim));
4383                 cam_sim_free(acb->psim, /* free_simq */ TRUE);
4384                 arcmsr_mutex_destroy(acb);
4385                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4386                 return ENXIO;
4387         }
4388         /*
4389         ****************************************************
4390         */
4391         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4392         csa.ccb_h.func_code = XPT_SASYNC_CB;
4393         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4394         csa.callback = arcmsr_async;
4395         csa.callback_arg = acb->psim;
4396         xpt_action((union ccb *)&csa);
4397         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4398         /* Create the control device.  */
4399         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4400
4401 #if __FreeBSD_version < 503000
4402         acb->ioctl_dev->si_drv1 = acb;
4403 #endif
4404 #if __FreeBSD_version > 500005
4405         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4406 #endif
4407         arcmsr_callout_init(&acb->devmap_callout);
4408         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4409         return (0);
4410 }
4411
4412 /*
4413 ************************************************************************
4414 ************************************************************************
4415 */
4416 static int arcmsr_probe(device_t dev)
4417 {
4418         u_int32_t id;
4419         u_int16_t sub_device_id;
4420         static char buf[256];
4421         char x_type[]={"unknown"};
4422         char *type;
4423         int raid6 = 1;
4424
4425         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4426                 return (ENXIO);
4427         }
4428         sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4429         switch(id = pci_get_devid(dev)) {
4430         case PCIDevVenIDARC1110:
4431         case PCIDevVenIDARC1200:
4432         case PCIDevVenIDARC1201:
4433         case PCIDevVenIDARC1210:
4434                 raid6 = 0;
4435                 /*FALLTHRU*/
4436         case PCIDevVenIDARC1120:
4437         case PCIDevVenIDARC1130:
4438         case PCIDevVenIDARC1160:
4439         case PCIDevVenIDARC1170:
4440         case PCIDevVenIDARC1220:
4441         case PCIDevVenIDARC1230:
4442         case PCIDevVenIDARC1231:
4443         case PCIDevVenIDARC1260:
4444         case PCIDevVenIDARC1261:
4445         case PCIDevVenIDARC1270:
4446         case PCIDevVenIDARC1280:
4447                 type = "SATA 3G";
4448                 break;
4449         case PCIDevVenIDARC1212:
4450         case PCIDevVenIDARC1222:
4451         case PCIDevVenIDARC1380:
4452         case PCIDevVenIDARC1381:
4453         case PCIDevVenIDARC1680:
4454         case PCIDevVenIDARC1681:
4455                 type = "SAS 3G";
4456                 break;
4457         case PCIDevVenIDARC1880:
4458         case PCIDevVenIDARC1882:
4459         case PCIDevVenIDARC1213:
4460         case PCIDevVenIDARC1223:
4461                 if (sub_device_id == ARECA_SUB_DEV_ID_1883)
4462                         type = "SAS 12G";
4463                 else
4464                         type = "SAS 6G";
4465                 break;
4466         case PCIDevVenIDARC1214:
4467         case PCIDevVenIDARC1203:
4468                 type = "SATA 6G";
4469                 break;
4470         default:
4471                 type = x_type;
4472                 raid6 = 0;
4473                 break;
4474         }
4475         if(type == x_type)
4476                 return(ENXIO);
4477         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
4478                 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4479         device_set_desc_copy(dev, buf);
4480         return (BUS_PROBE_DEFAULT);
4481 }
4482 /*
4483 ************************************************************************
4484 ************************************************************************
4485 */
4486 static int arcmsr_shutdown(device_t dev)
4487 {
4488         u_int32_t  i;
4489         u_int32_t intmask_org;
4490         struct CommandControlBlock *srb;
4491         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4492
4493         /* stop adapter background rebuild */
4494         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4495         /* disable all outbound interrupt */
4496         intmask_org = arcmsr_disable_allintr(acb);
4497         arcmsr_stop_adapter_bgrb(acb);
4498         arcmsr_flush_adapter_cache(acb);
4499         /* abort all outstanding command */
4500         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4501         acb->acb_flags &= ~ACB_F_IOP_INITED;
4502         if(acb->srboutstandingcount != 0) {
4503                 /*clear and abort all outbound posted Q*/
4504                 arcmsr_done4abort_postqueue(acb);
4505                 /* talk to iop 331 outstanding command aborted*/
4506                 arcmsr_abort_allcmd(acb);
4507                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4508                         srb = acb->psrb_pool[i];
4509                         if(srb->srb_state == ARCMSR_SRB_START) {
4510                                 srb->srb_state = ARCMSR_SRB_ABORTED;
4511                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4512                                 arcmsr_srb_complete(srb, 1);
4513                         }
4514                 }
4515         }
4516         acb->srboutstandingcount = 0;
4517         acb->workingsrb_doneindex = 0;
4518         acb->workingsrb_startindex = 0;
4519         acb->pktRequestCount = 0;
4520         acb->pktReturnCount = 0;
4521         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4522         return (0);
4523 }
4524 /*
4525 ************************************************************************
4526 ************************************************************************
4527 */
4528 static int arcmsr_detach(device_t dev)
4529 {
4530         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4531         int i;
4532
4533         callout_stop(&acb->devmap_callout);
4534         bus_teardown_intr(dev, acb->irqres, acb->ih);
4535         arcmsr_shutdown(dev);
4536         arcmsr_free_resource(acb);
4537         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4538                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
4539         }
4540         bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4541         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4542         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4543         xpt_free_path(acb->ppath);
4544         xpt_bus_deregister(cam_sim_path(acb->psim));
4545         cam_sim_free(acb->psim, TRUE);
4546         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4547         arcmsr_mutex_destroy(acb);
4548         return (0);
4549 }
4550
4551 #ifdef ARCMSR_DEBUG1
4552 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4553 {
4554         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4555                 return;
4556         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
4557         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
4558         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4559         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
4560 }
4561 #endif
4562