2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
53 /* local prototypes */
54 static int ata_serverworks_chipinit(device_t dev);
55 static int ata_serverworks_ch_attach(device_t dev);
56 static int ata_serverworks_ch_detach(device_t dev);
57 static void ata_serverworks_tf_read(struct ata_request *request);
58 static void ata_serverworks_tf_write(struct ata_request *request);
59 static int ata_serverworks_setmode(device_t dev, int target, int mode);
60 static void ata_serverworks_sata_reset(device_t dev);
61 static int ata_serverworks_status(device_t dev);
71 * ServerWorks chipset support functions
74 ata_serverworks_probe(device_t dev)
76 struct ata_pci_controller *ctlr = device_get_softc(dev);
77 static const struct ata_chip_id ids[] =
78 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" },
79 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
80 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
81 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
82 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
83 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
84 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
85 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
86 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
87 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
88 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
91 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
94 if (!(ctlr->chip = ata_match_chip(dev, ids)))
98 ctlr->chipinit = ata_serverworks_chipinit;
99 return (BUS_PROBE_LOW_PRIORITY);
103 ata_serverworks_status(device_t dev)
105 struct ata_channel *ch = device_get_softc(dev);
106 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
109 * Check if this interrupt belongs to our channel.
111 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
115 * We need to do a 4-byte read on the status reg before the values
116 * will report correctly
119 ATA_IDX_INL(ch,ATA_STATUS);
121 return ata_pci_status(dev);
125 ata_serverworks_chipinit(device_t dev)
127 struct ata_pci_controller *ctlr = device_get_softc(dev);
129 if (ata_setup_interrupt(dev, ata_generic_intr))
132 if (ctlr->chip->cfg1 == SWKS_MIO) {
133 ctlr->r_type2 = SYS_RES_MEMORY;
134 ctlr->r_rid2 = PCIR_BAR(5);
135 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
136 &ctlr->r_rid2, RF_ACTIVE)))
139 ctlr->channels = ctlr->chip->cfg2;
140 ctlr->ch_attach = ata_serverworks_ch_attach;
141 ctlr->ch_detach = ata_serverworks_ch_detach;
142 ctlr->setmode = ata_sata_setmode;
143 ctlr->getrev = ata_sata_getrev;
144 ctlr->reset = ata_serverworks_sata_reset;
147 else if (ctlr->chip->cfg1 == SWKS_33) {
151 /* locate the ISA part in the southbridge and enable UDMA33 */
152 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
153 for (i = 0; i < nchildren; i++) {
154 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
155 pci_write_config(children[i], 0x64,
156 (pci_read_config(children[i], 0x64, 4) &
157 ~0x00002000) | 0x00004000, 4);
161 free(children, M_TEMP);
165 pci_write_config(dev, 0x5a,
166 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
167 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1);
169 ctlr->setmode = ata_serverworks_setmode;
174 ata_serverworks_ch_attach(device_t dev)
176 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
177 struct ata_channel *ch = device_get_softc(dev);
181 ch_offset = ch->unit * 0x100;
183 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
184 ch->r_io[i].res = ctlr->r_res2;
186 /* setup ATA registers */
187 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
188 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
189 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
190 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
191 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
192 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
193 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
194 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
195 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
196 ata_default_registers(dev);
198 /* setup DMA registers */
199 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
200 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
201 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
203 /* setup SATA registers */
204 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
205 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
206 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
208 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE;
210 ch->hw.tf_read = ata_serverworks_tf_read;
211 ch->hw.tf_write = ata_serverworks_tf_write;
213 if (ctlr->chip->chipid == ATA_K2) {
215 * Set SICR registers to turn off waiting for a status message
216 * before sending FIS. Values obtained from the Darwin driver.
219 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
220 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
221 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
224 * Some controllers have a bug where they will send the command
225 * to the drive before seeing a DMA start, and then can begin
226 * receiving data before the DMA start arrives. The controller
227 * will then become confused and either corrupt the data or crash.
228 * Remedy this by starting DMA before sending the drive command.
231 ch->flags |= ATA_DMA_BEFORE_CMD;
234 * The status register must be read as a long to fill the other
238 ch->hw.status = ata_serverworks_status;
239 ch->flags |= ATA_STATUS_IS_LONG;
242 /* chip does not reliably do 64K DMA transfers */
243 ch->dma.max_iosize = 64 * DEV_BSIZE;
245 ata_pci_dmainit(dev);
251 ata_serverworks_ch_detach(device_t dev)
254 ata_pci_dmafini(dev);
259 ata_serverworks_tf_read(struct ata_request *request)
261 struct ata_channel *ch = device_get_softc(request->parent);
263 if (request->flags & ATA_R_48BIT) {
266 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
267 temp = ATA_IDX_INW(ch, ATA_SECTOR);
268 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
269 ((u_int64_t)(temp & 0xff00) << 24);
270 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
271 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
272 ((u_int64_t)(temp & 0xff00) << 32);
273 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
274 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
275 ((u_int64_t)(temp & 0xff00) << 40);
278 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
279 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
280 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
281 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
282 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
287 ata_serverworks_tf_write(struct ata_request *request)
289 struct ata_channel *ch = device_get_softc(request->parent);
291 if (request->flags & ATA_R_48BIT) {
292 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
293 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
294 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
295 (request->u.ata.lba & 0x00ff));
296 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
297 ((request->u.ata.lba >> 8) & 0x00ff));
298 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
299 ((request->u.ata.lba >> 16) & 0x00ff));
300 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
303 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
304 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
305 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
306 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
307 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
308 ATA_IDX_OUTW(ch, ATA_DRIVE,
309 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
310 ((request->u.ata.lba >> 24) & 0x0f));
315 ata_serverworks_setmode(device_t dev, int target, int mode)
317 device_t parent = device_get_parent(dev);
318 struct ata_pci_controller *ctlr = device_get_softc(parent);
319 struct ata_channel *ch = device_get_softc(dev);
320 int devno = (ch->unit << 1) + target;
321 int offset = (devno ^ 0x01) << 3;
323 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
324 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
326 mode = min(mode, ctlr->chip->max_dma);
327 if (mode >= ATA_UDMA0) {
328 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
329 pci_write_config(parent, 0x56,
330 (pci_read_config(parent, 0x56, 2) &
331 ~(0xf << (devno << 2))) |
332 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
333 pci_write_config(parent, 0x54,
334 pci_read_config(parent, 0x54, 1) |
336 pci_write_config(parent, 0x44,
337 (pci_read_config(parent, 0x44, 4) &
339 (dmatimings[2] << offset), 4);
341 } else if (mode >= ATA_WDMA0) {
342 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
343 pci_write_config(parent, 0x54,
344 pci_read_config(parent, 0x54, 1) &
345 ~(0x01 << devno), 1);
346 pci_write_config(parent, 0x44,
347 (pci_read_config(parent, 0x44, 4) &
349 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
350 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
351 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
353 /* Disable UDMA, set requested PIO. */
354 pci_write_config(parent, 0x54,
355 pci_read_config(parent, 0x54, 1) &
356 ~(0x01 << devno), 1);
359 /* Set PIO mode and timings, calculated above. */
360 if (ctlr->chip->cfg1 != SWKS_33) {
361 pci_write_config(parent, 0x4a,
362 (pci_read_config(parent, 0x4a, 2) &
363 ~(0xf << (devno << 2))) |
364 ((piomode - ATA_PIO0) << (devno<<2)),2);
366 pci_write_config(parent, 0x40,
367 (pci_read_config(parent, 0x40, 4) &
369 (piotimings[ata_mode2idx(piomode)] << offset), 4);
374 ata_serverworks_sata_reset(device_t dev)
376 struct ata_channel *ch = device_get_softc(dev);
378 if (ata_sata_phy_reset(dev, -1, 0))
379 ata_generic_reset(dev);
384 ATA_DECLARE_DRIVER(ata_serverworks);