2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
53 /* local prototypes */
54 static int ata_via_chipinit(device_t dev);
55 static int ata_via_ch_attach(device_t dev);
56 static int ata_via_ch_detach(device_t dev);
57 static void ata_via_reset(device_t dev);
58 static int ata_via_status(device_t dev);
59 static int ata_via_old_setmode(device_t dev, int target, int mode);
60 static void ata_via_southbridge_fixup(device_t dev);
61 static int ata_via_new_setmode(device_t dev, int target, int mode);
62 static int ata_via_sata_ch_attach(device_t dev);
63 static int ata_via_sata_getrev(device_t dev, int target);
64 static int ata_via_sata_setmode(device_t dev, int target, int mode);
65 static void ata_via_sata_reset(device_t dev);
66 static int ata_via_sata_scr_read(device_t dev, int port, int reg,
68 static int ata_via_sata_scr_write(device_t dev, int port, int reg,
70 static int ata_via_sata_status(device_t dev);
84 * VIA Technologies Inc. chipset support functions
87 ata_via_probe(device_t dev)
89 struct ata_pci_controller *ctlr = device_get_softc(dev);
90 static const struct ata_chip_id ids[] =
91 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
92 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
93 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
94 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
95 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
96 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
97 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
98 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
99 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
100 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
101 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
102 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
103 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
104 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
105 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
106 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
107 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
108 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
109 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" },
110 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" },
111 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" },
112 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" },
113 { 0, 0, 0, 0, 0, 0 }};
114 static const struct ata_chip_id new_ids[] =
115 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
116 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
117 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
118 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
119 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
120 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
121 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
122 { 0, 0, 0, 0, 0, 0 }};
124 if (pci_get_vendor(dev) != ATA_VIA_ID)
127 if (pci_get_devid(dev) == ATA_VIA82C571 ||
128 pci_get_devid(dev) == ATA_VIACX700IDE ||
129 pci_get_devid(dev) == ATA_VIASATAIDE ||
130 pci_get_devid(dev) == ATA_VIASATAIDE2 ||
131 pci_get_devid(dev) == ATA_VIASATAIDE3) {
132 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
136 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
141 ctlr->chipinit = ata_via_chipinit;
142 return (BUS_PROBE_LOW_PRIORITY);
146 ata_via_chipinit(device_t dev)
148 struct ata_pci_controller *ctlr = device_get_softc(dev);
150 if (ata_setup_interrupt(dev, ata_generic_intr))
153 /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
154 if (ctlr->chip->cfg2 & VIASATA) {
155 ctlr->ch_attach = ata_via_sata_ch_attach;
156 ctlr->setmode = ata_via_sata_setmode;
157 ctlr->getrev = ata_via_sata_getrev;
158 ctlr->reset = ata_via_sata_reset;
161 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */
162 if (ctlr->chip->max_dma >= ATA_SA150) {
163 ctlr->r_type2 = SYS_RES_IOPORT;
164 ctlr->r_rid2 = PCIR_BAR(5);
165 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
166 &ctlr->r_rid2, RF_ACTIVE))) {
167 ctlr->ch_attach = ata_via_ch_attach;
168 ctlr->ch_detach = ata_via_ch_detach;
169 ctlr->reset = ata_via_reset;
171 if (ctlr->chip->cfg2 & VIABAR) {
173 ctlr->setmode = ata_via_new_setmode;
175 ctlr->setmode = ata_sata_setmode;
176 ctlr->getrev = ata_sata_getrev;
180 /* prepare for ATA-66 on the 82C686a and 82C596b */
181 if (ctlr->chip->cfg2 & VIACLK)
182 pci_write_config(dev, 0x50, 0x030b030b, 4);
184 /* the southbridge might need the data corruption fix */
185 if (ctlr->chip->cfg2 & VIABUG)
186 ata_via_southbridge_fixup(dev);
188 /* set fifo configuration half'n'half */
189 pci_write_config(dev, 0x43,
190 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
192 /* set status register read retry */
193 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
195 /* set DMA read & end-of-sector fifo flush */
196 pci_write_config(dev, 0x46,
197 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
199 /* set sector size */
200 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
201 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
203 ctlr->setmode = ata_via_old_setmode;
208 ata_via_ch_attach(device_t dev)
210 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
211 struct ata_channel *ch = device_get_softc(dev);
213 /* newer SATA chips has resources in one BAR for each channel */
214 if (ctlr->chip->cfg2 & VIABAR) {
215 struct resource *r_io;
218 ata_pci_dmainit(dev);
220 rid = PCIR_BAR(ch->unit);
221 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
226 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
227 ch->r_io[i].res = r_io;
228 ch->r_io[i].offset = i;
230 ch->r_io[ATA_CONTROL].res = r_io;
231 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
232 ch->r_io[ATA_IDX_ADDR].res = r_io;
233 ata_default_registers(dev);
234 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
235 ch->r_io[i].res = ctlr->r_res1;
236 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
243 /* setup the usual register normal pci style */
244 if (ata_pci_ch_attach(dev))
248 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
249 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
250 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
251 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
252 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
253 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
254 ch->hw.status = ata_via_status;
255 ch->flags |= ATA_NO_SLAVE;
256 ch->flags |= ATA_SATA;
257 ch->flags |= ATA_PERIODIC_POLL;
259 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff);
265 ata_via_ch_detach(device_t dev)
267 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
268 struct ata_channel *ch = device_get_softc(dev);
270 /* newer SATA chips has resources in one BAR for each channel */
271 if (ctlr->chip->cfg2 & VIABAR) {
274 rid = PCIR_BAR(ch->unit);
275 bus_release_resource(device_get_parent(dev),
276 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res);
278 ata_pci_dmafini(dev);
281 /* setup the usual register normal pci style */
282 if (ata_pci_ch_detach(dev))
290 ata_via_reset(device_t dev)
292 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
293 struct ata_channel *ch = device_get_softc(dev);
295 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
296 ata_generic_reset(dev);
298 if (ata_sata_phy_reset(dev, -1, 1))
299 ata_generic_reset(dev);
306 ata_via_status(device_t dev)
309 ata_sata_phy_check_events(dev, -1);
310 return (ata_pci_status(dev));
314 ata_via_new_setmode(device_t dev, int target, int mode)
316 device_t parent = device_get_parent(dev);
317 struct ata_pci_controller *ctlr = device_get_softc(parent);
318 struct ata_channel *ch = device_get_softc(dev);
320 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
322 static const uint8_t pio_timings[] =
323 { 0xa8, 0x65, 0x65, 0x32, 0x20 };
324 static const uint8_t dma_timings[] =
325 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
327 /* This chip can't do WDMA. */
328 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0)
330 if (mode >= ATA_UDMA0) {
331 pci_write_config(parent, 0xb3,
332 dma_timings[mode & ATA_MODE_MASK], 1);
336 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1);
338 mode = ata_sata_setmode(dev, target, mode);
343 ata_via_old_setmode(device_t dev, int target, int mode)
345 device_t parent = device_get_parent(dev);
346 struct ata_pci_controller *ctlr = device_get_softc(parent);
347 struct ata_channel *ch = device_get_softc(dev);
348 int devno = (ch->unit << 1) + target;
349 int reg = 0x53 - devno;
351 static const uint8_t timings[] =
352 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
353 static const uint8_t modes[][7] = {
354 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
355 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
356 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
357 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
359 mode = min(mode, ctlr->chip->max_dma);
360 /* Set UDMA timings */
361 if (mode >= ATA_UDMA0) {
362 pci_write_config(parent, reg,
363 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
366 pci_write_config(parent, reg, 0x8b, 1);
369 /* Set WDMA/PIO timings */
370 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);
375 ata_via_southbridge_fixup(device_t dev)
380 if (device_get_children(device_get_parent(dev), &children, &nchildren))
383 for (i = 0; i < nchildren; i++) {
384 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
385 pci_get_devid(children[i]) == ATA_VIA8371 ||
386 pci_get_devid(children[i]) == ATA_VIA8662 ||
387 pci_get_devid(children[i]) == ATA_VIA8361) {
388 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
390 if ((reg76 & 0xf0) != 0xd0) {
392 "Correcting VIA config for southbridge data corruption bug\n");
393 pci_write_config(children[i], 0x75, 0x80, 1);
394 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
399 free(children, M_TEMP);
403 ata_via_sata_ch_attach(device_t dev)
405 struct ata_channel *ch = device_get_softc(dev);
407 if (ata_pci_ch_attach(dev))
410 ch->hw.status = ata_via_sata_status;
411 ch->hw.pm_read = ata_via_sata_scr_read;
412 ch->hw.pm_write = ata_via_sata_scr_write;
413 ch->flags |= ATA_PERIODIC_POLL;
414 ch->flags |= ATA_SATA;
415 ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff);
416 ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff);
422 ata_via_sata_getrev(device_t dev, int target)
424 device_t parent = device_get_parent(dev);
425 struct ata_channel *ch = device_get_softc(dev);
428 if (pci_read_config(parent, 0xa0 + target, 1) & 0x10)
437 ata_via_sata_setmode(device_t dev, int target, int mode)
439 struct ata_channel *ch = device_get_softc(dev);
443 return (ata_via_old_setmode(dev, target, mode));
447 ata_via_sata_reset(device_t dev)
449 struct ata_channel *ch = device_get_softc(dev);
453 devs = ata_sata_phy_reset(dev, 0, 0);
455 devs += ata_sata_phy_reset(dev, 1, 0);
459 ata_generic_reset(dev);
465 ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result)
470 parent = device_get_parent(dev);
471 port = (port == 1) ? 1 : 0;
474 val = pci_read_config(parent, 0xa0 + port, 1);
475 *result = val & 0x03;
476 if (*result != ATA_SS_DET_NO_DEVICE) {
478 *result |= ATA_SS_IPM_PARTIAL;
480 *result |= ATA_SS_IPM_SLUMBER;
482 *result |= ATA_SS_IPM_ACTIVE;
484 *result |= ATA_SS_SPD_GEN2;
486 *result |= ATA_SS_SPD_GEN1;
490 *result = pci_read_config(parent, 0xa8 + port * 4, 4);
493 val = pci_read_config(parent, 0xa4 + port, 1);
496 *result |= ATA_SC_DET_RESET;
498 *result |= ATA_SC_DET_DISABLE;
500 *result |= ATA_SC_IPM_DIS_PARTIAL;
502 *result |= ATA_SC_IPM_DIS_SLUMBER;
511 ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value)
516 parent = device_get_parent(dev);
517 port = (port == 1) ? 1 : 0;
520 pci_write_config(parent, 0xa8 + port * 4, value, 4);
524 if (value & ATA_SC_DET_RESET)
526 if (value & ATA_SC_DET_DISABLE)
528 if (value & ATA_SC_IPM_DIS_PARTIAL)
530 if (value & ATA_SC_IPM_DIS_SLUMBER)
532 pci_write_config(parent, 0xa4 + port, val, 1);
541 ata_via_sata_status(device_t dev)
544 ata_sata_phy_check_events(dev, 0);
545 ata_sata_phy_check_events(dev, 1);
546 return (ata_pci_status(dev));
549 ATA_DECLARE_DRIVER(ata_via);