2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
83 #include <net80211/ieee80211_var.h>
84 #include <net80211/ieee80211_regdomain.h>
85 #ifdef IEEE80211_SUPPORT_SUPERG
86 #include <net80211/ieee80211_superg.h>
92 #include <netinet/in.h>
93 #include <netinet/if_ether.h>
96 #include <dev/ath/if_athvar.h>
98 #include <dev/ath/if_ath_debug.h>
99 #include <dev/ath/if_ath_misc.h>
100 #include <dev/ath/if_ath_tx.h>
101 #include <dev/ath/if_ath_beacon.h>
104 #include <dev/ath/ath_tx99/ath_tx99.h>
108 * Setup a h/w transmit queue for beacons.
111 ath_beaconq_setup(struct ath_softc *sc)
113 struct ath_hal *ah = sc->sc_ah;
116 memset(&qi, 0, sizeof(qi));
117 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
118 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
119 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
120 /* NB: for dynamic turbo, don't enable any other interrupts */
121 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
123 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE |
124 HAL_TXQ_TXERRINT_ENABLE;
126 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
130 * Setup the transmit queue parameters for the beacon queue.
133 ath_beaconq_config(struct ath_softc *sc)
135 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
136 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
137 struct ath_hal *ah = sc->sc_ah;
140 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
141 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
142 ic->ic_opmode == IEEE80211_M_MBSS) {
144 * Always burst out beacon and CAB traffic.
146 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
147 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
148 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
150 struct wmeParams *wmep =
151 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
153 * Adhoc mode; important thing is to use 2x cwmin.
155 qi.tqi_aifs = wmep->wmep_aifsn;
156 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
157 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
160 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
161 device_printf(sc->sc_dev, "unable to update parameters for "
162 "beacon hardware queue!\n");
165 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
168 #undef ATH_EXPONENT_TO_VALUE
172 * Allocate and setup an initial beacon frame.
175 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
177 struct ieee80211vap *vap = ni->ni_vap;
178 struct ath_vap *avp = ATH_VAP(vap);
184 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n",
185 __func__, bf->bf_m, bf->bf_node);
186 if (bf->bf_m != NULL) {
187 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
191 if (bf->bf_node != NULL) {
192 ieee80211_free_node(bf->bf_node);
197 * NB: the beacon data buffer must be 32-bit aligned;
198 * we assume the mbuf routines will return us something
199 * with this alignment (perhaps should assert).
201 m = ieee80211_beacon_alloc(ni, &avp->av_boff);
203 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
204 sc->sc_stats.ast_be_nombuf++;
207 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
208 bf->bf_segs, &bf->bf_nseg,
211 device_printf(sc->sc_dev,
212 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
219 * Calculate a TSF adjustment factor required for staggered
220 * beacons. Note that we assume the format of the beacon
221 * frame leaves the tstamp field immediately following the
224 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
226 struct ieee80211_frame *wh;
229 * The beacon interval is in TU's; the TSF is in usecs.
230 * We figure out how many TU's to add to align the timestamp
231 * then convert to TSF units and handle byte swapping before
232 * inserting it in the frame. The hardware will then add this
233 * each time a beacon frame is sent. Note that we align vap's
234 * 1..N and leave vap 0 untouched. This means vap 0 has a
235 * timestamp in one beacon interval while the others get a
236 * timstamp aligned to the next interval.
238 tsfadjust = ni->ni_intval *
239 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
240 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
242 DPRINTF(sc, ATH_DEBUG_BEACON,
243 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
244 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
245 avp->av_bslot, ni->ni_intval,
246 (long long unsigned) le64toh(tsfadjust));
248 wh = mtod(m, struct ieee80211_frame *);
249 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
252 bf->bf_node = ieee80211_ref_node(ni);
258 * Setup the beacon frame for transmit.
261 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
263 #define USE_SHPREAMBLE(_ic) \
264 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
265 == IEEE80211_F_SHPREAMBLE)
266 struct ieee80211_node *ni = bf->bf_node;
267 struct ieee80211com *ic = ni->ni_ic;
268 struct mbuf *m = bf->bf_m;
269 struct ath_hal *ah = sc->sc_ah;
272 const HAL_RATE_TABLE *rt;
274 HAL_DMA_ADDR bufAddrList[4];
275 uint32_t segLenList[4];
276 HAL_11N_RATE_SERIES rc[4];
278 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
279 __func__, m, m->m_len);
281 /* setup descriptors */
286 flags = HAL_TXDESC_NOACK;
287 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
288 /* self-linked descriptor */
289 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr);
290 flags |= HAL_TXDESC_VEOL;
292 * Let hardware handle antenna switching.
294 antenna = sc->sc_txantenna;
296 ath_hal_settxdesclink(sc->sc_ah, ds, 0);
298 * Switch antenna every 4 beacons.
299 * XXX assumes two antenna
301 if (sc->sc_txantenna != 0)
302 antenna = sc->sc_txantenna;
303 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
304 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
306 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
309 KASSERT(bf->bf_nseg == 1,
310 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
313 * Calculate rate code.
314 * XXX everything at min xmit rate
317 rt = sc->sc_currates;
318 rate = rt->info[rix].rateCode;
319 if (USE_SHPREAMBLE(ic))
320 rate |= rt->info[rix].shortPreamble;
321 ath_hal_setuptxdesc(ah, ds
322 , m->m_len + IEEE80211_CRC_LEN /* frame length */
323 , sizeof(struct ieee80211_frame)/* header length */
324 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
325 , ieee80211_get_node_txpower(ni) /* txpower XXX */
326 , rate, 1 /* series 0 rate/tries */
327 , HAL_TXKEYIX_INVALID /* no encryption */
328 , antenna /* antenna mode */
329 , flags /* no ack, veol for beacons */
330 , 0 /* rts/cts rate */
331 , 0 /* rts/cts duration */
335 * The EDMA HAL currently assumes that _all_ rate control
336 * settings are done in ath_hal_set11nratescenario(), rather
337 * than in ath_hal_setuptxdesc().
340 memset(&rc, 0, sizeof(rc));
342 rc[0].ChSel = sc->sc_txchainmask;
344 rc[0].Rate = rt->info[rix].rateCode;
345 rc[0].RateIndex = rix;
346 rc[0].tx_power_cap = 0x3f;
348 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4),
350 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags);
353 /* NB: beacon's BufLen must be a multiple of 4 bytes */
354 segLenList[0] = roundup(m->m_len, 4);
355 segLenList[1] = segLenList[2] = segLenList[3] = 0;
356 bufAddrList[0] = bf->bf_segs[0].ds_addr;
357 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0;
358 ath_hal_filltxdesc(ah, ds
361 , 0 /* XXX desc id */
362 , sc->sc_bhalq /* hardware TXQ */
363 , AH_TRUE /* first segment */
364 , AH_TRUE /* last segment */
365 , ds /* first descriptor */
370 #undef USE_SHPREAMBLE
374 ath_beacon_update(struct ieee80211vap *vap, int item)
376 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
378 setbit(bo->bo_flags, item);
382 * Handle a beacon miss.
385 ath_beacon_miss(struct ath_softc *sc)
387 HAL_SURVEY_SAMPLE hs;
391 bzero(&hs, sizeof(hs));
393 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs);
395 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) {
396 DPRINTF(sc, ATH_DEBUG_BEACON,
403 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON))
404 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL);
407 DPRINTF(sc, ATH_DEBUG_BEACON,
408 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, "
409 "extchanbusy=%u, cyclecount=%u\n",
420 * Transmit a beacon frame at SWBA. Dynamic updates to the
421 * frame contents are done as needed and the slot time is
422 * also adjusted based on current state.
425 ath_beacon_proc(void *arg, int pending)
427 struct ath_softc *sc = arg;
428 struct ath_hal *ah = sc->sc_ah;
429 struct ieee80211vap *vap;
434 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
437 * Check if the previous beacon has gone out. If
438 * not don't try to post another, skip this period
439 * and wait for the next. Missed beacons indicate
440 * a problem and should not occur. If we miss too
441 * many consecutive beacons reset the device.
443 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
445 sc->sc_stats.ast_be_missed++;
447 DPRINTF(sc, ATH_DEBUG_BEACON,
448 "%s: missed %u consecutive beacons\n",
449 __func__, sc->sc_bmisscount);
450 if (sc->sc_bmisscount >= ath_bstuck_threshold)
451 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
454 if (sc->sc_bmisscount != 0) {
455 DPRINTF(sc, ATH_DEBUG_BEACON,
456 "%s: resume beacon xmit after %u misses\n",
457 __func__, sc->sc_bmisscount);
458 sc->sc_bmisscount = 0;
460 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON))
461 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL);
465 if (sc->sc_stagbeacons) { /* staggered beacons */
466 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
469 tsftu = ath_hal_gettsf32(ah) >> 10;
471 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
472 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
474 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
475 bf = ath_beacon_generate(sc, vap);
477 bfaddr = bf->bf_daddr;
479 } else { /* burst'd beacons */
480 uint32_t *bflink = &bfaddr;
482 for (slot = 0; slot < ATH_BCBUF; slot++) {
483 vap = sc->sc_bslot[slot];
484 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
485 bf = ath_beacon_generate(sc, vap);
487 * XXX TODO: this should use settxdesclinkptr()
488 * otherwise it won't work for EDMA chipsets!
491 /* XXX should do this using the ds */
492 *bflink = bf->bf_daddr;
493 ath_hal_gettxdesclinkptr(sc->sc_ah,
494 bf->bf_desc, &bflink);
499 * XXX TODO: this should use settxdesclinkptr()
500 * otherwise it won't work for EDMA chipsets!
502 *bflink = 0; /* terminate list */
506 * Handle slot time change when a non-ERP station joins/leaves
507 * an 11g network. The 802.11 layer notifies us via callback,
508 * we mark updateslot, then wait one beacon before effecting
509 * the change. This gives associated stations at least one
510 * beacon interval to note the state change.
513 if (sc->sc_updateslot == UPDATE) {
514 sc->sc_updateslot = COMMIT; /* commit next beacon */
515 sc->sc_slotupdate = slot;
516 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
517 ath_setslottime(sc); /* commit change to h/w */
520 * Check recent per-antenna transmit statistics and flip
521 * the default antenna if noticeably more frames went out
522 * on the non-default antenna.
523 * XXX assumes 2 anntenae
525 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
526 otherant = sc->sc_defant & 1 ? 2 : 1;
527 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
528 ath_setdefantenna(sc, otherant);
529 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
532 /* Program the CABQ with the contents of the CABQ txq and start it */
533 ATH_TXQ_LOCK(sc->sc_cabq);
534 ath_beacon_cabq_start(sc);
535 ATH_TXQ_UNLOCK(sc->sc_cabq);
537 /* Program the new beacon frame if we have one for this interval */
540 * Stop any current dma and put the new frame on the queue.
541 * This should never fail since we check above that no frames
542 * are still pending on the queue.
544 if (! sc->sc_isedma) {
545 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
546 DPRINTF(sc, ATH_DEBUG_ANY,
547 "%s: beacon queue %u did not stop?\n",
548 __func__, sc->sc_bhalq);
551 /* NB: cabq traffic should already be queued and primed */
553 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
554 ath_hal_txstart(ah, sc->sc_bhalq);
556 sc->sc_stats.ast_be_xmit++;
561 ath_beacon_cabq_start_edma(struct ath_softc *sc)
563 struct ath_buf *bf, *bf_last;
564 struct ath_txq *cabq = sc->sc_cabq;
570 ATH_TXQ_LOCK_ASSERT(cabq);
572 if (TAILQ_EMPTY(&cabq->axq_q))
574 bf = TAILQ_FIRST(&cabq->axq_q);
575 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s);
578 * This is a dirty, dirty hack to push the contents of
579 * the cabq staging queue into the FIFO.
581 * This ideally should live in the EDMA code file
582 * and only push things into the CABQ if there's a FIFO
585 * We can't treat this like a normal TX queue because
586 * in the case of multi-VAP traffic, we may have to flush
587 * the CABQ each new (staggered) beacon that goes out.
588 * But for non-staggered beacons, we could in theory
589 * handle multicast traffic for all VAPs in one FIFO
590 * push. Just keep all of this in mind if you're wondering
591 * how to correctly/better handle multi-VAP CABQ traffic
596 * Is the CABQ FIFO free? If not, complain loudly and
597 * don't queue anything. Maybe we'll flush the CABQ
598 * traffic, maybe we won't. But that'll happen next
601 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) {
602 device_printf(sc->sc_dev,
603 "%s: Q%d: CAB FIFO queue=%d?\n",
606 cabq->axq_fifo_depth);
611 * Ok, so here's the gymnastics reqiured to make this
616 * Tag the first/last buffer appropriately.
618 bf->bf_flags |= ATH_BUF_FIFOPTR;
619 bf_last->bf_flags |= ATH_BUF_FIFOEND;
623 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) {
624 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0);
630 * We now need to push this set of frames onto the tail
631 * of the FIFO queue. We don't adjust the aggregate
632 * count, only the queue depth counter(s).
633 * We also need to blank the link pointer now.
635 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list);
636 cabq->axq_link = NULL;
637 cabq->fifo.axq_depth += cabq->axq_depth;
640 /* Bump FIFO queue */
641 cabq->axq_fifo_depth++;
643 /* Push the first entry into the hardware */
644 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
645 cabq->axq_flags |= ATH_TXQ_PUTRUNNING;
647 /* NB: gated by beacon so safe to start here */
648 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
653 ath_beacon_cabq_start_legacy(struct ath_softc *sc)
656 struct ath_txq *cabq = sc->sc_cabq;
658 ATH_TXQ_LOCK_ASSERT(cabq);
659 if (TAILQ_EMPTY(&cabq->axq_q))
661 bf = TAILQ_FIRST(&cabq->axq_q);
663 /* Push the first entry into the hardware */
664 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
665 cabq->axq_flags |= ATH_TXQ_PUTRUNNING;
667 /* NB: gated by beacon so safe to start here */
668 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
672 * Start CABQ transmission - this assumes that all frames are prepped
673 * and ready in the CABQ.
676 ath_beacon_cabq_start(struct ath_softc *sc)
678 struct ath_txq *cabq = sc->sc_cabq;
680 ATH_TXQ_LOCK_ASSERT(cabq);
682 if (TAILQ_EMPTY(&cabq->axq_q))
686 ath_beacon_cabq_start_edma(sc);
688 ath_beacon_cabq_start_legacy(sc);
692 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
694 struct ath_vap *avp = ATH_VAP(vap);
695 struct ath_txq *cabq = sc->sc_cabq;
700 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
701 ("not running, state %d", vap->iv_state));
702 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
705 * Update dynamic beacon contents. If this returns
706 * non-zero then we need to remap the memory because
707 * the beacon frame changed size (probably because
708 * of the TIM bitmap).
712 /* XXX lock mcastq? */
713 nmcastq = avp->av_mcastq.axq_depth;
715 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
716 /* XXX too conservative? */
717 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
718 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
719 bf->bf_segs, &bf->bf_nseg,
722 if_printf(vap->iv_ifp,
723 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
728 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
729 DPRINTF(sc, ATH_DEBUG_BEACON,
730 "%s: cabq did not drain, mcastq %u cabq %u\n",
731 __func__, nmcastq, cabq->axq_depth);
732 sc->sc_stats.ast_cabq_busy++;
733 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
735 * CABQ traffic from a previous vap is still pending.
736 * We must drain the q before this beacon frame goes
737 * out as otherwise this vap's stations will get cab
738 * frames from a different vap.
739 * XXX could be slow causing us to miss DBA
742 * XXX TODO: this doesn't stop CABQ DMA - it assumes
743 * that since we're about to transmit a beacon, we've
744 * already stopped transmitting on the CABQ. But this
745 * doesn't at all mean that the CABQ DMA QCU will
746 * accept a new TXDP! So what, should we do a DMA
747 * stop? What if it fails?
749 * More thought is required here.
751 ath_tx_draintxq(sc, cabq);
754 ath_beacon_setup(sc, bf);
755 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
758 * Enable the CAB queue before the beacon queue to
759 * insure cab frames are triggered by this beacon.
761 if (avp->av_boff.bo_tim[4] & 1) {
763 /* NB: only at DTIM */
764 ATH_TXQ_LOCK(&avp->av_mcastq);
766 struct ath_buf *bfm, *bfc_last;
769 * Move frames from the s/w mcast q to the h/w cab q.
771 * XXX TODO: if we chain together multiple VAPs
772 * worth of CABQ traffic, should we keep the
773 * MORE data bit set on the last frame of each
774 * intermediary VAP (ie, only clear the MORE
775 * bit of the last frame on the last vap?)
777 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q);
781 * If there's already a frame on the CABQ, we
782 * need to link to the end of the last frame.
783 * We can't use axq_link here because
784 * EDMA descriptors require some recalculation
785 * (checksum) to occur.
787 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s);
788 if (bfc_last != NULL) {
789 ath_hal_settxdesclink(sc->sc_ah,
793 ath_txqmove(cabq, &avp->av_mcastq);
794 ATH_TXQ_UNLOCK(cabq);
796 * XXX not entirely accurate, in case a mcast
797 * queue frame arrived before we grabbed the TX
800 sc->sc_stats.ast_cabq_xmit += nmcastq;
802 ATH_TXQ_UNLOCK(&avp->av_mcastq);
808 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
810 struct ath_vap *avp = ATH_VAP(vap);
811 struct ath_hal *ah = sc->sc_ah;
816 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
819 * Update dynamic beacon contents. If this returns
820 * non-zero then we need to remap the memory because
821 * the beacon frame changed size (probably because
822 * of the TIM bitmap).
826 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
827 /* XXX too conservative? */
828 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
829 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
830 bf->bf_segs, &bf->bf_nseg,
833 if_printf(vap->iv_ifp,
834 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
839 ath_beacon_setup(sc, bf);
840 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
842 /* NB: caller is known to have already stopped tx dma */
843 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
844 ath_hal_txstart(ah, sc->sc_bhalq);
848 * Reclaim beacon resources and return buffer to the pool.
851 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
854 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
855 __func__, bf, bf->bf_m, bf->bf_node);
856 if (bf->bf_m != NULL) {
857 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
861 if (bf->bf_node != NULL) {
862 ieee80211_free_node(bf->bf_node);
865 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
869 * Reclaim beacon resources.
872 ath_beacon_free(struct ath_softc *sc)
876 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
877 DPRINTF(sc, ATH_DEBUG_NODE,
878 "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
879 __func__, bf, bf->bf_m, bf->bf_node);
880 if (bf->bf_m != NULL) {
881 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
885 if (bf->bf_node != NULL) {
886 ieee80211_free_node(bf->bf_node);
893 * Configure the beacon and sleep timers.
895 * When operating as an AP this resets the TSF and sets
896 * up the hardware to notify us when we need to issue beacons.
898 * When operating in station mode this sets up the beacon
899 * timers according to the timestamp of the last received
900 * beacon and the current TSF, configures PCF and DTIM
901 * handling, programs the sleep registers so the hardware
902 * will wakeup in time to receive beacons, and configures
903 * the beacon miss handling so we'll receive a BMISS
904 * interrupt when we stop seeing beacons from the AP
905 * we've associated with.
908 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
910 #define TSF_TO_TU(_h,_l) \
911 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
913 struct ath_hal *ah = sc->sc_ah;
914 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
915 struct ieee80211_node *ni;
916 u_int32_t nexttbtt, intval, tsftu;
917 u_int32_t nexttbtt_u8, intval_u8;
921 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
923 * Just ensure that we aren't being called when the last
927 device_printf(sc->sc_dev, "%s: called with no VAPs\n",
932 ni = ieee80211_ref_node(vap->iv_bss);
934 /* extract tstamp from last beacon and convert to TU */
935 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
936 LE_READ_4(ni->ni_tstamp.data));
937 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
938 ic->ic_opmode == IEEE80211_M_MBSS) {
940 * For multi-bss ap/mesh support beacons are either staggered
941 * evenly over N slots or burst together. For the former
942 * arrange for the SWBA to be delivered for each slot.
943 * Slots that are not occupied will generate nothing.
945 /* NB: the beacon interval is kept internally in TU's */
946 intval = ni->ni_intval & HAL_BEACON_PERIOD;
947 if (sc->sc_stagbeacons)
950 /* NB: the beacon interval is kept internally in TU's */
951 intval = ni->ni_intval & HAL_BEACON_PERIOD;
953 if (nexttbtt == 0) /* e.g. for ap mode */
955 else if (intval) /* NB: can be 0 for monitor mode */
956 nexttbtt = roundup(nexttbtt, intval);
957 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
958 __func__, nexttbtt, intval, ni->ni_intval);
959 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
961 int dtimperiod, dtimcount;
962 int cfpperiod, cfpcount;
965 * Setup dtim and cfp parameters according to
966 * last beacon we received (which may be none).
968 dtimperiod = ni->ni_dtim_period;
969 if (dtimperiod <= 0) /* NB: 0 if not known */
971 dtimcount = ni->ni_dtim_count;
972 if (dtimcount >= dtimperiod) /* NB: sanity check */
973 dtimcount = 0; /* XXX? */
974 cfpperiod = 1; /* NB: no PCF support yet */
977 * Pull nexttbtt forward to reflect the current
978 * TSF and calculate dtim+cfp state for the result.
980 tsf = ath_hal_gettsf64(ah);
981 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
984 if (--dtimcount < 0) {
985 dtimcount = dtimperiod - 1;
987 cfpcount = cfpperiod - 1;
989 } while (nexttbtt < tsftu);
990 memset(&bs, 0, sizeof(bs));
991 bs.bs_intval = intval;
992 bs.bs_nexttbtt = nexttbtt;
993 bs.bs_dtimperiod = dtimperiod*intval;
994 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
995 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
996 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
997 bs.bs_cfpmaxduration = 0;
1000 * The 802.11 layer records the offset to the DTIM
1001 * bitmap while receiving beacons; use it here to
1002 * enable h/w detection of our AID being marked in
1003 * the bitmap vector (to indicate frames for us are
1004 * pending at the AP).
1005 * XXX do DTIM handling in s/w to WAR old h/w bugs
1006 * XXX enable based on h/w rev for newer chips
1008 bs.bs_timoffset = ni->ni_timoff;
1011 * Calculate the number of consecutive beacons to miss
1012 * before taking a BMISS interrupt.
1013 * Note that we clamp the result to at most 10 beacons.
1015 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
1016 if (bs.bs_bmissthreshold > 10)
1017 bs.bs_bmissthreshold = 10;
1018 else if (bs.bs_bmissthreshold <= 0)
1019 bs.bs_bmissthreshold = 1;
1022 * Calculate sleep duration. The configuration is
1023 * given in ms. We insure a multiple of the beacon
1024 * period is used. Also, if the sleep duration is
1025 * greater than the DTIM period then it makes senses
1026 * to make it a multiple of that.
1028 * XXX fixed at 100ms
1030 bs.bs_sleepduration =
1031 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
1032 if (bs.bs_sleepduration > bs.bs_dtimperiod)
1033 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
1035 DPRINTF(sc, ATH_DEBUG_BEACON,
1036 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
1043 , bs.bs_bmissthreshold
1044 , bs.bs_sleepduration
1046 , bs.bs_cfpmaxduration
1050 ath_hal_intrset(ah, 0);
1051 ath_hal_beacontimers(ah, &bs);
1052 sc->sc_imask |= HAL_INT_BMISS;
1053 ath_hal_intrset(ah, sc->sc_imask);
1055 ath_hal_intrset(ah, 0);
1056 if (nexttbtt == intval)
1057 intval |= HAL_BEACON_RESET_TSF;
1058 if (ic->ic_opmode == IEEE80211_M_IBSS) {
1060 * In IBSS mode enable the beacon timers but only
1061 * enable SWBA interrupts if we need to manually
1062 * prepare beacon frames. Otherwise we use a
1063 * self-linked tx descriptor and let the hardware
1066 intval |= HAL_BEACON_ENA;
1067 if (!sc->sc_hasveol)
1068 sc->sc_imask |= HAL_INT_SWBA;
1069 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
1071 * Pull nexttbtt forward to reflect
1074 tsf = ath_hal_gettsf64(ah);
1075 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
1078 } while (nexttbtt < tsftu);
1080 ath_beaconq_config(sc);
1081 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
1082 ic->ic_opmode == IEEE80211_M_MBSS) {
1084 * In AP/mesh mode we enable the beacon timers
1085 * and SWBA interrupts to prepare beacon frames.
1087 intval |= HAL_BEACON_ENA;
1088 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
1089 ath_beaconq_config(sc);
1093 * Now dirty things because for now, the EDMA HAL has
1094 * nexttbtt and intval is TU/8.
1096 if (sc->sc_isedma) {
1097 nexttbtt_u8 = (nexttbtt << 3);
1098 intval_u8 = (intval << 3);
1099 if (intval & HAL_BEACON_ENA)
1100 intval_u8 |= HAL_BEACON_ENA;
1101 if (intval & HAL_BEACON_RESET_TSF)
1102 intval_u8 |= HAL_BEACON_RESET_TSF;
1103 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8);
1105 ath_hal_beaconinit(ah, nexttbtt, intval);
1106 sc->sc_bmisscount = 0;
1107 ath_hal_intrset(ah, sc->sc_imask);
1109 * When using a self-linked beacon descriptor in
1110 * ibss mode load it once here.
1112 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
1113 ath_beacon_start_adhoc(sc, vap);
1115 sc->sc_syncbeacon = 0;
1116 ieee80211_free_node(ni);