2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/eventhandler.h>
38 #include <sys/types.h>
40 #include <sys/selinfo.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <machine/bus.h>
44 #include <net/ethernet.h>
46 #include <net/if_media.h>
47 #include <net/if_var.h>
48 #include <net/if_clone.h>
49 #include <net/if_types.h>
50 #include <net/netmap.h>
51 #include <dev/netmap/netmap_kern.h>
53 #include "common/common.h"
54 #include "common/t4_regs.h"
55 #include "common/t4_regs_values.h"
57 extern int fl_pad; /* XXXNM */
58 extern int spg_len; /* XXXNM */
59 extern int fl_pktshift; /* XXXNM */
61 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters");
64 * 0 = normal netmap rx
66 * 2 = supermassive black hole (buffer packing enabled)
69 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0,
70 "Sink incoming packets.");
73 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
74 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
76 int holdoff_tmr_idx = 2;
77 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
78 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
82 * -1: no congestion feedback (not recommended).
83 * 0: backpressure the channel instead of dropping packets right away.
84 * 1: no backpressure, drop packets for the congested queue immediately.
86 static int nm_cong_drop = 1;
87 TUNABLE_INT("hw.cxgbe.nm_cong_drop", &nm_cong_drop);
89 /* netmap ifnet routines */
90 static void cxgbe_nm_init(void *);
91 static int cxgbe_nm_ioctl(struct ifnet *, unsigned long, caddr_t);
92 static int cxgbe_nm_transmit(struct ifnet *, struct mbuf *);
93 static void cxgbe_nm_qflush(struct ifnet *);
95 static int cxgbe_nm_init_synchronized(struct port_info *);
96 static int cxgbe_nm_uninit_synchronized(struct port_info *);
99 cxgbe_nm_init(void *arg)
101 struct port_info *pi = arg;
102 struct adapter *sc = pi->adapter;
104 if (begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nminit") != 0)
106 cxgbe_nm_init_synchronized(pi);
107 end_synchronized_op(sc, 0);
113 cxgbe_nm_init_synchronized(struct port_info *pi)
115 struct adapter *sc = pi->adapter;
116 struct ifnet *ifp = pi->nm_ifp;
119 ASSERT_SYNCHRONIZED_OP(sc);
121 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
122 return (0); /* already running */
124 if (!(sc->flags & FULL_INIT_DONE) &&
125 ((rc = adapter_full_init(sc)) != 0))
126 return (rc); /* error message displayed already */
128 if (!(pi->flags & PORT_INIT_DONE) &&
129 ((rc = port_full_init(pi)) != 0))
130 return (rc); /* error message displayed already */
132 rc = update_mac_settings(ifp, XGMAC_ALL);
134 return (rc); /* error message displayed already */
136 ifp->if_drv_flags |= IFF_DRV_RUNNING;
142 cxgbe_nm_uninit_synchronized(struct port_info *pi)
145 struct adapter *sc = pi->adapter;
147 struct ifnet *ifp = pi->nm_ifp;
149 ASSERT_SYNCHRONIZED_OP(sc);
151 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
157 cxgbe_nm_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
159 int rc = 0, mtu, flags;
160 struct port_info *pi = ifp->if_softc;
161 struct adapter *sc = pi->adapter;
162 struct ifreq *ifr = (struct ifreq *)data;
165 MPASS(pi->nm_ifp == ifp);
170 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
173 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nmtu");
177 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
178 rc = update_mac_settings(ifp, XGMAC_MTU);
179 end_synchronized_op(sc, 0);
183 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nflg");
187 if (ifp->if_flags & IFF_UP) {
188 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
189 flags = pi->nmif_flags;
190 if ((ifp->if_flags ^ flags) &
191 (IFF_PROMISC | IFF_ALLMULTI)) {
192 rc = update_mac_settings(ifp,
193 XGMAC_PROMISC | XGMAC_ALLMULTI);
196 rc = cxgbe_nm_init_synchronized(pi);
197 pi->nmif_flags = ifp->if_flags;
198 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
199 rc = cxgbe_nm_uninit_synchronized(pi);
200 end_synchronized_op(sc, 0);
204 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
205 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4nmulti");
208 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
209 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
210 end_synchronized_op(sc, LOCK_HELD);
214 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
215 if (mask & IFCAP_TXCSUM) {
216 ifp->if_capenable ^= IFCAP_TXCSUM;
217 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
219 if (mask & IFCAP_TXCSUM_IPV6) {
220 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
221 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
223 if (mask & IFCAP_RXCSUM)
224 ifp->if_capenable ^= IFCAP_RXCSUM;
225 if (mask & IFCAP_RXCSUM_IPV6)
226 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
231 ifmedia_ioctl(ifp, ifr, &pi->nm_media, cmd);
235 rc = ether_ioctl(ifp, cmd, data);
242 cxgbe_nm_transmit(struct ifnet *ifp, struct mbuf *m)
250 cxgbe_nm_qflush(struct ifnet *ifp)
257 alloc_nm_rxq_hwq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int cong)
261 struct adapter *sc = pi->adapter;
262 struct netmap_adapter *na = NA(pi->nm_ifp);
266 MPASS(nm_rxq->iq_desc != NULL);
267 MPASS(nm_rxq->fl_desc != NULL);
269 bzero(nm_rxq->iq_desc, pi->qsize_rxq * IQ_ESIZE);
270 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + spg_len);
272 bzero(&c, sizeof(c));
273 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
274 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
276 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
278 if (pi->flags & INTR_NM_RXQ) {
279 KASSERT(nm_rxq->intr_idx < sc->intr_count,
280 ("%s: invalid direct intr_idx %d", __func__,
282 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
284 CXGBE_UNIMPLEMENTED(__func__); /* XXXNM: needs review */
285 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx) |
288 c.type_to_iqandstindex = htobe32(v |
289 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
290 V_FW_IQ_CMD_VIID(pi->nm_viid) |
291 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
292 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
293 F_FW_IQ_CMD_IQGTSMODE |
294 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
295 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
296 c.iqsize = htobe16(pi->qsize_rxq);
297 c.iqaddr = htobe64(nm_rxq->iq_ba);
299 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
300 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
301 F_FW_IQ_CMD_FL0CONGEN);
303 c.iqns_to_fl0congen |=
304 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
305 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
306 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
307 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
308 c.fl0dcaen_to_fl0cidxfthresh =
309 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
310 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
311 c.fl0size = htobe16(na->num_rx_desc / 8 + spg_len / EQ_ESIZE);
312 c.fl0addr = htobe64(nm_rxq->fl_ba);
314 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
316 device_printf(sc->dev,
317 "failed to create netmap ingress queue: %d\n", rc);
322 MPASS(nm_rxq->iq_sidx == pi->qsize_rxq - spg_len / IQ_ESIZE);
323 nm_rxq->iq_gen = F_RSPD_GEN;
324 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
325 nm_rxq->iq_abs_id = be16toh(c.physiqid);
326 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
327 if (cntxt_id >= sc->sge.niq) {
328 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
329 __func__, cntxt_id, sc->sge.niq - 1);
331 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
333 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
334 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
335 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
336 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
337 if (cntxt_id >= sc->sge.neq) {
338 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
339 __func__, cntxt_id, sc->sge.neq - 1);
341 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
343 nm_rxq->fl_db_val = F_DBPRIO | V_QID(nm_rxq->fl_cntxt_id) | V_PIDX(0);
345 nm_rxq->fl_db_val |= F_DBTYPE;
347 if (is_t5(sc) && cong >= 0) {
350 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
351 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
352 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
353 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
354 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
355 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
360 for (i = 0; i < 4; i++) {
362 val |= 1 << (i << 2);
366 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
368 /* report error but carry on */
369 device_printf(sc->dev,
370 "failed to set congestion manager context for "
371 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
375 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
376 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
377 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
383 free_nm_rxq_hwq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
385 struct adapter *sc = pi->adapter;
388 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
389 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
391 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
392 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
397 alloc_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
401 struct adapter *sc = pi->adapter;
402 struct netmap_adapter *na = NA(pi->nm_ifp);
403 struct fw_eq_eth_cmd c;
406 MPASS(nm_txq->desc != NULL);
408 len = na->num_tx_desc * EQ_ESIZE + spg_len;
409 bzero(nm_txq->desc, len);
411 bzero(&c, sizeof(c));
412 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
413 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
414 V_FW_EQ_ETH_CMD_VFN(0));
415 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
416 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
417 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
418 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(pi->nm_viid));
420 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
421 V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
422 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
423 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
424 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
425 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
426 c.eqaddr = htobe64(nm_txq->ba);
428 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
430 device_printf(pi->dev,
431 "failed to create netmap egress queue: %d\n", rc);
435 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
436 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
437 if (cntxt_id >= sc->sge.neq)
438 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
439 cntxt_id, sc->sge.neq - 1);
440 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
442 nm_txq->pidx = nm_txq->cidx = 0;
443 MPASS(nm_txq->sidx == na->num_tx_desc);
444 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
446 nm_txq->doorbells = sc->doorbells;
447 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
448 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
449 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
450 uint32_t s_qpp = sc->sge.eq_s_qpp;
451 uint32_t mask = (1 << s_qpp) - 1;
452 volatile uint8_t *udb;
454 udb = sc->udbs_base + UDBS_DB_OFFSET;
455 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
456 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
457 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
458 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
460 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
463 nm_txq->udb = (volatile void *)udb;
470 free_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
472 struct adapter *sc = pi->adapter;
475 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
477 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
478 nm_txq->cntxt_id, rc);
483 cxgbe_netmap_on(struct adapter *sc, struct port_info *pi, struct ifnet *ifp,
484 struct netmap_adapter *na)
486 struct netmap_slot *slot;
487 struct sge_nm_rxq *nm_rxq;
488 struct sge_nm_txq *nm_txq;
490 struct hw_buf_info *hwb;
493 ASSERT_SYNCHRONIZED_OP(sc);
495 if ((pi->flags & PORT_INIT_DONE) == 0 ||
496 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
499 hwb = &sc->sge.hw_buf_info[0];
500 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
501 if (hwb->size == NETMAP_BUF_SIZE(na))
504 if (i >= SGE_FLBUF_SIZES) {
505 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
506 NETMAP_BUF_SIZE(na));
511 /* Must set caps before calling netmap_reset */
512 nm_set_native_flags(na);
514 for_each_nm_rxq(pi, i, nm_rxq) {
515 alloc_nm_rxq_hwq(pi, nm_rxq, tnl_cong(pi, nm_cong_drop));
516 nm_rxq->fl_hwidx = hwidx;
517 slot = netmap_reset(na, NR_RX, i, 0);
518 MPASS(slot != NULL); /* XXXNM: error check, not assert */
520 /* We deal with 8 bufs at a time */
521 MPASS((na->num_rx_desc & 7) == 0);
522 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
523 for (j = 0; j < nm_rxq->fl_sidx; j++) {
526 PNMB(na, &slot[j], &ba);
528 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
530 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
532 j /= 8; /* driver pidx to hardware pidx */
534 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
535 nm_rxq->fl_db_val | V_PIDX(j));
538 for_each_nm_txq(pi, i, nm_txq) {
539 alloc_nm_txq_hwq(pi, nm_txq);
540 slot = netmap_reset(na, NR_TX, i, 0);
541 MPASS(slot != NULL); /* XXXNM: error check, not assert */
544 rss = malloc(pi->nm_rss_size * sizeof (*rss), M_CXGBE, M_ZERO |
546 for (i = 0; i < pi->nm_rss_size;) {
547 for_each_nm_rxq(pi, j, nm_rxq) {
548 rss[i++] = nm_rxq->iq_abs_id;
549 if (i == pi->nm_rss_size)
553 rc = -t4_config_rss_range(sc, sc->mbox, pi->nm_viid, 0, pi->nm_rss_size,
554 rss, pi->nm_rss_size);
556 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
559 rc = -t4_enable_vi(sc, sc->mbox, pi->nm_viid, true, true);
561 if_printf(ifp, "netmap enable_vi failed: %d\n", rc);
567 cxgbe_netmap_off(struct adapter *sc, struct port_info *pi, struct ifnet *ifp,
568 struct netmap_adapter *na)
571 struct sge_nm_txq *nm_txq;
572 struct sge_nm_rxq *nm_rxq;
574 ASSERT_SYNCHRONIZED_OP(sc);
576 rc = -t4_enable_vi(sc, sc->mbox, pi->nm_viid, false, false);
578 if_printf(ifp, "netmap disable_vi failed: %d\n", rc);
579 nm_clear_native_flags(na);
581 for_each_nm_txq(pi, i, nm_txq) {
582 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
584 /* Wait for hw pidx to catch up ... */
585 while (be16toh(nm_txq->pidx) != spg->pidx)
588 /* ... and then for the cidx. */
589 while (spg->pidx != spg->cidx)
592 free_nm_txq_hwq(pi, nm_txq);
594 for_each_nm_rxq(pi, i, nm_rxq) {
595 free_nm_rxq_hwq(pi, nm_rxq);
602 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
604 struct ifnet *ifp = na->ifp;
605 struct port_info *pi = ifp->if_softc;
606 struct adapter *sc = pi->adapter;
609 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nmreg");
613 rc = cxgbe_netmap_on(sc, pi, ifp, na);
615 rc = cxgbe_netmap_off(sc, pi, ifp, na);
616 end_synchronized_op(sc, 0);
621 /* How many packets can a single type1 WR carry in n descriptors */
623 ndesc_to_npkt(const int n)
626 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
630 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
632 /* Space (in descriptors) needed for a type1 WR that carries n packets */
634 npkt_to_ndesc(const int n)
637 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
639 return ((n + 2) / 2);
642 /* Space (in 16B units) needed for a type1 WR that carries n packets */
644 npkt_to_len16(const int n)
647 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
652 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
655 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
658 u_int db = nm_txq->doorbells;
660 MPASS(nm_txq->pidx != nm_txq->dbidx);
662 n = NMIDXDIFF(nm_txq, dbidx);
664 clrbit(&db, DOORBELL_WCWR);
667 switch (ffs(db) - 1) {
669 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
672 case DOORBELL_WCWR: {
673 volatile uint64_t *dst, *src;
676 * Queues whose 128B doorbell segment fits in the page do not
677 * use relative qid (udb_qid is always 0). Only queues with
678 * doorbell segments can do WCWR.
680 KASSERT(nm_txq->udb_qid == 0 && n == 1,
681 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
682 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
684 dst = (volatile void *)((uintptr_t)nm_txq->udb +
685 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
686 src = (void *)&nm_txq->desc[nm_txq->dbidx];
687 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
694 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
699 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
700 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
703 nm_txq->dbidx = nm_txq->pidx;
706 int lazy_tx_credit_flush = 1;
709 * Write work requests to send 'npkt' frames and ring the doorbell to send them
710 * on their way. No need to check for wraparound.
713 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
714 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum)
716 struct netmap_ring *ring = kring->ring;
717 struct netmap_slot *slot;
718 const u_int lim = kring->nkr_num_slots - 1;
719 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
722 struct cpl_tx_pkt_core *cpl;
723 struct ulptx_sgl *usgl;
727 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
730 wr = (void *)&nm_txq->desc[nm_txq->pidx];
731 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
732 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
736 cpl = (void *)(wr + 1);
738 for (i = 0; i < n; i++) {
739 slot = &ring->slot[kring->nr_hwcur];
740 PNMB(kring->na, slot, &ba);
743 cpl->ctrl0 = nm_txq->cpl_ctrl0;
745 cpl->len = htobe16(slot->len);
747 * netmap(4) says "netmap does not use features such as
748 * checksum offloading, TCP segmentation offloading,
749 * encryption, VLAN encapsulation/decapsulation, etc."
751 * So the ncxl interfaces have tx hardware checksumming
752 * disabled by default. But you can override netmap by
753 * enabling IFCAP_TXCSUM on the interface manully.
755 cpl->ctrl1 = txcsum ? 0 :
756 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
758 usgl = (void *)(cpl + 1);
759 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
761 usgl->len0 = htobe32(slot->len);
762 usgl->addr0 = htobe64(ba);
764 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
765 cpl = (void *)(usgl + 1);
766 MPASS(slot->len + len <= UINT16_MAX);
768 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
770 wr->plen = htobe16(len);
773 nm_txq->pidx += npkt_to_ndesc(n);
774 MPASS(nm_txq->pidx <= nm_txq->sidx);
775 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
777 * This routine doesn't know how to write WRs that wrap
778 * around. Make sure it wasn't asked to.
784 if (npkt == 0 && npkt_remaining == 0) {
786 if (lazy_tx_credit_flush == 0) {
787 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
789 nm_txq->equeqidx = nm_txq->pidx;
790 nm_txq->equiqidx = nm_txq->pidx;
792 ring_nm_txq_db(sc, nm_txq);
796 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
797 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
799 nm_txq->equeqidx = nm_txq->pidx;
800 nm_txq->equiqidx = nm_txq->pidx;
801 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
802 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
803 nm_txq->equeqidx = nm_txq->pidx;
805 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
806 ring_nm_txq_db(sc, nm_txq);
809 /* Will get called again. */
810 MPASS(npkt_remaining);
813 /* How many contiguous free descriptors starting at pidx */
815 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
818 if (nm_txq->cidx > nm_txq->pidx)
819 return (nm_txq->cidx - nm_txq->pidx - 1);
820 else if (nm_txq->cidx > 0)
821 return (nm_txq->sidx - nm_txq->pidx);
823 return (nm_txq->sidx - nm_txq->pidx - 1);
827 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
829 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
830 uint16_t hw_cidx = spg->cidx; /* snapshot */
831 struct fw_eth_tx_pkts_wr *wr;
834 hw_cidx = be16toh(hw_cidx);
836 while (nm_txq->cidx != hw_cidx) {
837 wr = (void *)&nm_txq->desc[nm_txq->cidx];
839 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)));
840 MPASS(wr->type == 1);
841 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
844 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
847 * We never sent a WR that wrapped around so the credits coming
848 * back, WR by WR, should never cause the cidx to wrap around
851 MPASS(nm_txq->cidx <= nm_txq->sidx);
852 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
860 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
862 struct netmap_adapter *na = kring->na;
863 struct ifnet *ifp = na->ifp;
864 struct port_info *pi = ifp->if_softc;
865 struct adapter *sc = pi->adapter;
866 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[pi->first_nm_txq + kring->ring_id];
867 const u_int head = kring->rhead;
869 int n, d, npkt_remaining, ndesc_remaining, txcsum;
872 * Tx was at kring->nr_hwcur last time around and now we need to advance
873 * to kring->rhead. Note that the driver's pidx moves independent of
874 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
875 * between descriptors and frames isn't 1:1).
878 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
879 kring->nkr_num_slots - kring->nr_hwcur + head;
880 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6);
881 while (npkt_remaining) {
882 reclaimed += reclaim_nm_tx_desc(nm_txq);
883 ndesc_remaining = contiguous_ndesc_available(nm_txq);
884 /* Can't run out of descriptors with packets still remaining */
885 MPASS(ndesc_remaining > 0);
887 /* # of desc needed to tx all remaining packets */
888 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
889 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
890 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
892 if (d <= ndesc_remaining)
895 /* Can't send all, calculate how many can be sent */
896 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
897 MAX_NPKT_IN_TYPE1_WR;
898 if (ndesc_remaining % SGE_MAX_WR_NDESC)
899 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
902 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
904 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum);
906 MPASS(npkt_remaining == 0);
907 MPASS(kring->nr_hwcur == head);
908 MPASS(nm_txq->dbidx == nm_txq->pidx);
911 * Second part: reclaim buffers for completed transmissions.
913 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
914 reclaimed += reclaim_nm_tx_desc(nm_txq);
915 kring->nr_hwtail += reclaimed;
916 if (kring->nr_hwtail >= kring->nkr_num_slots)
917 kring->nr_hwtail -= kring->nkr_num_slots;
920 nm_txsync_finalize(kring);
926 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
928 struct netmap_adapter *na = kring->na;
929 struct netmap_ring *ring = kring->ring;
930 struct ifnet *ifp = na->ifp;
931 struct port_info *pi = ifp->if_softc;
932 struct adapter *sc = pi->adapter;
933 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[pi->first_nm_rxq + kring->ring_id];
934 u_int const head = nm_rxsync_prologue(kring);
936 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
939 return (0); /* No updates ever. */
941 if (netmap_no_pendintr || force_update) {
942 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
943 kring->nr_kflags &= ~NKR_PENDINTR;
946 /* Userspace done with buffers from kring->nr_hwcur to head */
947 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
948 kring->nkr_num_slots - kring->nr_hwcur + head;
951 u_int fl_pidx = nm_rxq->fl_pidx;
952 struct netmap_slot *slot = &ring->slot[fl_pidx];
954 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
957 * We always deal with 8 buffers at a time. We must have
958 * stopped at an 8B boundary (fl_pidx) last time around and we
959 * must have a multiple of 8B buffers to give to the freelist.
961 MPASS((fl_pidx & 7) == 0);
964 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
965 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
968 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
971 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
972 slot->flags &= ~NS_BUF_CHANGED;
973 MPASS(fl_pidx <= nm_rxq->fl_sidx);
976 if (fl_pidx == nm_rxq->fl_sidx) {
978 slot = &ring->slot[0];
980 if (++dbinc == 8 && n >= 32) {
982 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
983 nm_rxq->fl_db_val | V_PIDX(dbinc));
987 MPASS(nm_rxq->fl_pidx == fl_pidx);
991 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
992 nm_rxq->fl_db_val | V_PIDX(dbinc));
996 nm_rxsync_finalize(kring);
1002 * Create an ifnet solely for netmap use and register it with the kernel.
1005 create_netmap_ifnet(struct port_info *pi)
1007 struct adapter *sc = pi->adapter;
1008 struct netmap_adapter na;
1010 device_t dev = pi->dev;
1011 uint8_t mac[ETHER_ADDR_LEN];
1014 if (pi->nnmtxq <= 0 || pi->nnmrxq <= 0)
1016 MPASS(pi->nm_ifp == NULL);
1019 * Allocate a virtual interface exclusively for netmap use. Give it the
1020 * MAC address normally reserved for use by a TOE interface. (The TOE
1021 * driver on FreeBSD doesn't use it).
1023 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, &mac[0],
1024 &pi->nm_rss_size, FW_VI_FUNC_OFLD, 0);
1026 device_printf(dev, "unable to allocate netmap virtual "
1027 "interface for port %d: %d\n", pi->port_id, -rc);
1031 pi->nm_xact_addr_filt = -1;
1033 ifp = if_alloc(IFT_ETHER);
1035 device_printf(dev, "Cannot allocate netmap ifnet\n");
1041 if_initname(ifp, is_t4(pi->adapter) ? "ncxgbe" : "ncxl",
1042 device_get_unit(dev));
1043 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1045 ifp->if_init = cxgbe_nm_init;
1046 ifp->if_ioctl = cxgbe_nm_ioctl;
1047 ifp->if_transmit = cxgbe_nm_transmit;
1048 ifp->if_qflush = cxgbe_nm_qflush;
1051 * netmap(4) says "netmap does not use features such as checksum
1052 * offloading, TCP segmentation offloading, encryption, VLAN
1053 * encapsulation/decapsulation, etc."
1055 * By default we comply with the statement above. But we do declare the
1056 * ifnet capable of L3/L4 checksumming so that a user can override
1057 * netmap and have the hardware do the L3/L4 checksums.
1059 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_JUMBO_MTU |
1061 ifp->if_capenable = 0;
1062 ifp->if_hwassist = 0;
1064 /* nm_media has already been setup by the caller */
1066 ether_ifattach(ifp, mac);
1069 * Register with netmap in the kernel.
1071 bzero(&na, sizeof(na));
1073 na.ifp = pi->nm_ifp;
1074 na.na_flags = NAF_BDG_MAYSLEEP;
1076 /* Netmap doesn't know about the space reserved for the status page. */
1077 na.num_tx_desc = pi->qsize_txq - spg_len / EQ_ESIZE;
1080 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
1081 * num_rx_desc is based on the number of buffers that can be held in the
1082 * freelist, and not the number of entries in the iq. (These two are
1083 * not exactly the same due to the space taken up by the status page).
1085 na.num_rx_desc = (pi->qsize_rxq / 8) * 8;
1086 na.nm_txsync = cxgbe_netmap_txsync;
1087 na.nm_rxsync = cxgbe_netmap_rxsync;
1088 na.nm_register = cxgbe_netmap_reg;
1089 na.num_tx_rings = pi->nnmtxq;
1090 na.num_rx_rings = pi->nnmrxq;
1091 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */
1097 destroy_netmap_ifnet(struct port_info *pi)
1099 struct adapter *sc = pi->adapter;
1101 if (pi->nm_ifp == NULL)
1104 netmap_detach(pi->nm_ifp);
1105 ifmedia_removeall(&pi->nm_media);
1106 ether_ifdetach(pi->nm_ifp);
1107 if_free(pi->nm_ifp);
1108 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->nm_viid);
1114 handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp,
1115 const struct cpl_fw6_msg *cpl)
1117 const struct cpl_sge_egr_update *egr;
1119 struct sge_nm_txq *nm_txq;
1121 if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL)
1122 panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type);
1124 /* data[0] is RSS header */
1125 egr = (const void *)&cpl->data[1];
1126 oq = be32toh(egr->opcode_qid);
1127 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1128 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1130 netmap_tx_irq(ifp, nm_txq->nid);
1134 t4_nm_intr(void *arg)
1136 struct sge_nm_rxq *nm_rxq = arg;
1137 struct port_info *pi = nm_rxq->pi;
1138 struct adapter *sc = pi->adapter;
1139 struct ifnet *ifp = pi->nm_ifp;
1140 struct netmap_adapter *na = NA(ifp);
1141 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid];
1142 struct netmap_ring *ring = kring->ring;
1143 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1145 u_int n = 0, work = 0;
1147 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1148 u_int fl_credits = fl_cidx & 7;
1150 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1154 lq = be32toh(d->rsp.pldbuflen_qid);
1155 opcode = d->rss.opcode;
1157 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1158 case X_RSPD_TYPE_FLBUF:
1159 if (black_hole != 2) {
1160 /* No buffer packing so new buf every time */
1161 MPASS(lq & F_RSPD_NEWBUF);
1166 case X_RSPD_TYPE_CPL:
1167 MPASS(opcode < NUM_CPL_CMDS);
1172 handle_nm_fw6_msg(sc, ifp,
1173 (const void *)&d->cpl[0]);
1176 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - fl_pktshift;
1177 ring->slot[fl_cidx].flags = kring->nkr_slot_flags;
1178 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0;
1179 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0;
1180 if (__predict_false(fl_cidx == nm_rxq->fl_sidx))
1184 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1185 __func__, opcode, nm_rxq);
1189 case X_RSPD_TYPE_INTR:
1190 /* Not equipped to handle forwarded interrupts. */
1191 panic("%s: netmap queue received interrupt for iq %u\n",
1195 panic("%s: illegal response type %d on nm_rxq %p",
1196 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1200 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1201 nm_rxq->iq_cidx = 0;
1202 d = &nm_rxq->iq_desc[0];
1203 nm_rxq->iq_gen ^= F_RSPD_GEN;
1206 if (__predict_false(++n == rx_ndesc)) {
1207 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1208 if (black_hole && fl_credits >= 8) {
1210 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1212 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
1213 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1214 fl_credits = fl_cidx & 7;
1215 } else if (!black_hole) {
1216 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1219 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1220 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1221 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1226 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1229 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1230 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
1231 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1233 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1235 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(n) |
1236 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1237 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));