2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/linker.h>
35 #include <sys/firmware.h>
37 #include <dev/drm2/drmP.h>
38 #include <dev/drm2/radeon/radeon_drm.h>
39 #include "radeon_drv.h"
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
49 MODULE_FIRMWARE("radeon/R600_pfp.bin");
50 MODULE_FIRMWARE("radeon/R600_me.bin");
51 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV610_me.bin");
53 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV630_me.bin");
55 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV620_me.bin");
57 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV635_me.bin");
59 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV670_me.bin");
61 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
62 MODULE_FIRMWARE("radeon/RS780_me.bin");
63 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV770_me.bin");
65 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV730_me.bin");
67 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
68 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
73 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
74 unsigned family, u32 *ib, int *l);
75 void r600_cs_legacy_init(void);
78 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
79 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
81 #define R600_PTE_VALID (1 << 0)
82 #define R600_PTE_SYSTEM (1 << 1)
83 #define R600_PTE_SNOOPED (1 << 2)
84 #define R600_PTE_READABLE (1 << 5)
85 #define R600_PTE_WRITEABLE (1 << 6)
87 /* MAX values used for gfx init */
88 #define R6XX_MAX_SH_GPRS 256
89 #define R6XX_MAX_TEMP_GPRS 16
90 #define R6XX_MAX_SH_THREADS 256
91 #define R6XX_MAX_SH_STACK_ENTRIES 4096
92 #define R6XX_MAX_BACKENDS 8
93 #define R6XX_MAX_BACKENDS_MASK 0xff
94 #define R6XX_MAX_SIMDS 8
95 #define R6XX_MAX_SIMDS_MASK 0xff
96 #define R6XX_MAX_PIPES 8
97 #define R6XX_MAX_PIPES_MASK 0xff
99 #define R7XX_MAX_SH_GPRS 256
100 #define R7XX_MAX_TEMP_GPRS 16
101 #define R7XX_MAX_SH_THREADS 256
102 #define R7XX_MAX_SH_STACK_ENTRIES 4096
103 #define R7XX_MAX_BACKENDS 8
104 #define R7XX_MAX_BACKENDS_MASK 0xff
105 #define R7XX_MAX_SIMDS 16
106 #define R7XX_MAX_SIMDS_MASK 0xffff
107 #define R7XX_MAX_PIPES 8
108 #define R7XX_MAX_PIPES_MASK 0xff
110 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
114 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
116 for (i = 0; i < dev_priv->usec_timeout; i++) {
118 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
119 slots = (RADEON_READ(R600_GRBM_STATUS)
120 & R700_CMDFIFO_AVAIL_MASK);
122 slots = (RADEON_READ(R600_GRBM_STATUS)
123 & R600_CMDFIFO_AVAIL_MASK);
124 if (slots >= entries)
128 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
129 RADEON_READ(R600_GRBM_STATUS),
130 RADEON_READ(R600_GRBM_STATUS2));
135 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
139 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
141 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
142 ret = r600_do_wait_for_fifo(dev_priv, 8);
144 ret = r600_do_wait_for_fifo(dev_priv, 16);
147 for (i = 0; i < dev_priv->usec_timeout; i++) {
148 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
152 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
153 RADEON_READ(R600_GRBM_STATUS),
154 RADEON_READ(R600_GRBM_STATUS2));
159 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
161 struct drm_sg_mem *entry = dev->sg;
171 if (gart_info->bus_addr) {
173 max_pages = (gart_info->table_size / sizeof(u64));
174 pages = (entry->pages <= max_pages)
175 ? entry->pages : max_pages;
177 for (i = 0; i < pages; i++) {
178 if (!entry->busaddr[i])
180 pci_unmap_page(dev->pdev, entry->busaddr[i],
181 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
184 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
185 gart_info->bus_addr = 0;
189 /* R600 has page table setup */
190 int r600_page_table_init(struct drm_device *dev)
192 drm_radeon_private_t *dev_priv = dev->dev_private;
193 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
194 struct drm_local_map *map = &gart_info->mapping;
195 struct drm_sg_mem *entry = dev->sg;
200 dma_addr_t entry_addr;
201 int max_ati_pages, max_real_pages, gart_idx;
203 /* okay page table is available - lets rock */
204 max_ati_pages = (gart_info->table_size / sizeof(u64));
205 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
207 pages = (entry->pages <= max_real_pages) ?
208 entry->pages : max_real_pages;
210 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
213 for (i = 0; i < pages; i++) {
215 entry->busaddr[i] = pci_map_page(dev->pdev,
216 entry->pagelist[i], 0,
218 PCI_DMA_BIDIRECTIONAL);
219 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
220 DRM_ERROR("unable to map PCIGART pages!\n");
221 r600_page_table_cleanup(dev, gart_info);
225 entry_addr = entry->busaddr[i];
226 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
227 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
228 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
229 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
231 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
236 DRM_DEBUG("page entry %d: 0x%016llx\n",
237 i, (unsigned long long)page_base);
238 entry_addr += ATI_PCIGART_PAGE_SIZE;
248 static void r600_vm_flush_gart_range(struct drm_device *dev)
250 drm_radeon_private_t *dev_priv = dev->dev_private;
251 u32 resp, countdown = 1000;
252 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
253 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
254 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
257 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
260 } while (((resp & 0xf0) == 0) && countdown);
263 static void r600_vm_init(struct drm_device *dev)
265 drm_radeon_private_t *dev_priv = dev->dev_private;
266 /* initialise the VM to use the page table we constructed up there */
269 u32 vm_l2_cntl, vm_l2_cntl3;
270 /* okay set up the PCIE aperture type thingo */
271 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
272 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
273 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
276 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
277 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
278 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
280 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
281 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
283 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
284 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
286 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
287 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
289 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
290 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
292 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
293 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
295 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
296 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
298 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
299 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
301 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
302 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
303 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
305 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
306 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
307 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
308 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
309 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
311 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
313 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
315 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
317 /* disable all other contexts */
318 for (i = 1; i < 8; i++)
319 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
321 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
322 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
323 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
325 r600_vm_flush_gart_range(dev);
328 static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
330 const char *chip_name;
331 size_t pfp_req_size, me_req_size;
335 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
336 case CHIP_R600: chip_name = "R600"; break;
337 case CHIP_RV610: chip_name = "RV610"; break;
338 case CHIP_RV630: chip_name = "RV630"; break;
339 case CHIP_RV620: chip_name = "RV620"; break;
340 case CHIP_RV635: chip_name = "RV635"; break;
341 case CHIP_RV670: chip_name = "RV670"; break;
343 case CHIP_RS880: chip_name = "RS780"; break;
344 case CHIP_RV770: chip_name = "RV770"; break;
346 case CHIP_RV740: chip_name = "RV730"; break;
347 case CHIP_RV710: chip_name = "RV710"; break;
348 default: panic("%s: Unsupported family %d", __func__, dev_priv->flags & RADEON_FAMILY_MASK);
351 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
352 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
353 me_req_size = R700_PM4_UCODE_SIZE * 4;
355 pfp_req_size = PFP_UCODE_SIZE * 4;
356 me_req_size = PM4_UCODE_SIZE * 12;
359 DRM_INFO("Loading %s CP Microcode\n", chip_name);
362 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
363 dev_priv->pfp_fw = firmware_get(fw_name);
364 if (dev_priv->pfp_fw == NULL) {
368 if (dev_priv->pfp_fw->datasize != pfp_req_size) {
370 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
371 dev_priv->pfp_fw->datasize, fw_name);
376 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
377 dev_priv->me_fw = firmware_get(fw_name);
378 if (dev_priv->me_fw == NULL) {
382 if (dev_priv->me_fw->datasize != me_req_size) {
384 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
385 dev_priv->me_fw->datasize, fw_name);
392 "r600_cp: Failed to load firmware \"%s\"\n",
394 if (dev_priv->pfp_fw != NULL) {
395 firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD);
396 dev_priv->pfp_fw = NULL;
398 if (dev_priv->me_fw != NULL) {
399 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
400 dev_priv->me_fw = NULL;
406 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
408 const __be32 *fw_data;
411 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
414 r600_do_cp_stop(dev_priv);
416 RADEON_WRITE(R600_CP_RB_CNTL,
418 R600_BUF_SWAP_32BIT |
424 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
425 RADEON_READ(R600_GRBM_SOFT_RESET);
427 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
429 fw_data = (const __be32 *)dev_priv->me_fw->data;
430 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
431 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
432 RADEON_WRITE(R600_CP_ME_RAM_DATA,
433 be32_to_cpup(fw_data++));
435 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
436 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
437 for (i = 0; i < PFP_UCODE_SIZE; i++)
438 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
439 be32_to_cpup(fw_data++));
441 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
442 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
443 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
447 static void r700_vm_init(struct drm_device *dev)
449 drm_radeon_private_t *dev_priv = dev->dev_private;
450 /* initialise the VM to use the page table we constructed up there */
453 u32 vm_l2_cntl, vm_l2_cntl3;
454 /* okay set up the PCIE aperture type thingo */
455 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
456 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
457 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
459 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
460 R700_ENABLE_L1_FRAGMENT_PROCESSING |
461 R700_SYSTEM_ACCESS_MODE_IN_SYS |
462 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
463 R700_EFFECTIVE_L1_TLB_SIZE(5) |
464 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
466 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
467 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
468 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
469 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
470 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
471 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
472 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
474 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
475 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
476 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
478 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
479 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
480 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
482 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
484 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
486 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
488 /* disable all other contexts */
489 for (i = 1; i < 8; i++)
490 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
492 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
493 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
494 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
496 r600_vm_flush_gart_range(dev);
499 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
501 const __be32 *fw_data;
504 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
507 r600_do_cp_stop(dev_priv);
509 RADEON_WRITE(R600_CP_RB_CNTL,
511 R600_BUF_SWAP_32BIT |
517 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
518 RADEON_READ(R600_GRBM_SOFT_RESET);
520 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
522 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
523 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
524 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
525 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
526 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
528 fw_data = (const __be32 *)dev_priv->me_fw->data;
529 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
530 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
531 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
532 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
534 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
535 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
536 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
540 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
544 /* Start with assuming that writeback doesn't work */
545 dev_priv->writeback_works = 0;
547 /* Writeback doesn't seem to work everywhere, test it here and possibly
548 * enable it if it appears to work
550 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
552 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
554 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
557 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
558 if (val == 0xdeadbeef)
563 if (tmp < dev_priv->usec_timeout) {
564 dev_priv->writeback_works = 1;
565 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
567 dev_priv->writeback_works = 0;
568 DRM_INFO("writeback test failed\n");
570 if (radeon_no_wb == 1) {
571 dev_priv->writeback_works = 0;
572 DRM_INFO("writeback forced off\n");
575 if (!dev_priv->writeback_works) {
576 /* Disable writeback to avoid unnecessary bus master transfer */
577 RADEON_WRITE(R600_CP_RB_CNTL,
579 R600_BUF_SWAP_32BIT |
581 RADEON_READ(R600_CP_RB_CNTL) |
583 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
587 int r600_do_engine_reset(struct drm_device *dev)
589 drm_radeon_private_t *dev_priv = dev->dev_private;
590 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
592 DRM_INFO("Resetting GPU\n");
594 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
595 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
596 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
598 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
599 RADEON_READ(R600_GRBM_SOFT_RESET);
601 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
602 RADEON_READ(R600_GRBM_SOFT_RESET);
604 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
605 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
606 RADEON_WRITE(R600_CP_RB_CNTL,
608 R600_BUF_SWAP_32BIT |
610 R600_RB_RPTR_WR_ENA);
612 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
613 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
614 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
615 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
617 /* Reset the CP ring */
618 r600_do_cp_reset(dev_priv);
620 /* The CP is no longer running after an engine reset */
621 dev_priv->cp_running = 0;
623 /* Reset any pending vertex, indirect buffers */
624 radeon_freelist_reset(dev);
630 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
632 u32 backend_disable_mask)
635 u32 enabled_backends_mask;
636 u32 enabled_backends_count;
638 u32 swizzle_pipe[R6XX_MAX_PIPES];
642 if (num_tile_pipes > R6XX_MAX_PIPES)
643 num_tile_pipes = R6XX_MAX_PIPES;
644 if (num_tile_pipes < 1)
646 if (num_backends > R6XX_MAX_BACKENDS)
647 num_backends = R6XX_MAX_BACKENDS;
648 if (num_backends < 1)
651 enabled_backends_mask = 0;
652 enabled_backends_count = 0;
653 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
654 if (((backend_disable_mask >> i) & 1) == 0) {
655 enabled_backends_mask |= (1 << i);
656 ++enabled_backends_count;
658 if (enabled_backends_count == num_backends)
662 if (enabled_backends_count == 0) {
663 enabled_backends_mask = 1;
664 enabled_backends_count = 1;
667 if (enabled_backends_count != num_backends)
668 num_backends = enabled_backends_count;
670 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
671 switch (num_tile_pipes) {
727 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
728 while (((1 << cur_backend) & enabled_backends_mask) == 0)
729 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
731 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
733 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
739 static int r600_count_pipe_bits(uint32_t val)
741 return hweight32(val);
744 static void r600_gfx_init(struct drm_device *dev,
745 drm_radeon_private_t *dev_priv)
747 int i, j, num_qd_pipes;
751 u32 num_gs_verts_per_thread;
753 u32 gs_prim_buffer_depth = 0;
754 u32 sq_ms_fifo_sizes;
756 u32 sq_gpr_resource_mgmt_1 = 0;
757 u32 sq_gpr_resource_mgmt_2 = 0;
758 u32 sq_thread_resource_mgmt = 0;
759 u32 sq_stack_resource_mgmt_1 = 0;
760 u32 sq_stack_resource_mgmt_2 = 0;
761 u32 hdp_host_path_cntl;
763 u32 gb_tiling_config = 0;
764 u32 cc_rb_backend_disable;
765 u32 cc_gc_shader_pipe_config;
768 /* setup chip specs */
769 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
771 dev_priv->r600_max_pipes = 4;
772 dev_priv->r600_max_tile_pipes = 8;
773 dev_priv->r600_max_simds = 4;
774 dev_priv->r600_max_backends = 4;
775 dev_priv->r600_max_gprs = 256;
776 dev_priv->r600_max_threads = 192;
777 dev_priv->r600_max_stack_entries = 256;
778 dev_priv->r600_max_hw_contexts = 8;
779 dev_priv->r600_max_gs_threads = 16;
780 dev_priv->r600_sx_max_export_size = 128;
781 dev_priv->r600_sx_max_export_pos_size = 16;
782 dev_priv->r600_sx_max_export_smx_size = 128;
783 dev_priv->r600_sq_num_cf_insts = 2;
787 dev_priv->r600_max_pipes = 2;
788 dev_priv->r600_max_tile_pipes = 2;
789 dev_priv->r600_max_simds = 3;
790 dev_priv->r600_max_backends = 1;
791 dev_priv->r600_max_gprs = 128;
792 dev_priv->r600_max_threads = 192;
793 dev_priv->r600_max_stack_entries = 128;
794 dev_priv->r600_max_hw_contexts = 8;
795 dev_priv->r600_max_gs_threads = 4;
796 dev_priv->r600_sx_max_export_size = 128;
797 dev_priv->r600_sx_max_export_pos_size = 16;
798 dev_priv->r600_sx_max_export_smx_size = 128;
799 dev_priv->r600_sq_num_cf_insts = 2;
805 dev_priv->r600_max_pipes = 1;
806 dev_priv->r600_max_tile_pipes = 1;
807 dev_priv->r600_max_simds = 2;
808 dev_priv->r600_max_backends = 1;
809 dev_priv->r600_max_gprs = 128;
810 dev_priv->r600_max_threads = 192;
811 dev_priv->r600_max_stack_entries = 128;
812 dev_priv->r600_max_hw_contexts = 4;
813 dev_priv->r600_max_gs_threads = 4;
814 dev_priv->r600_sx_max_export_size = 128;
815 dev_priv->r600_sx_max_export_pos_size = 16;
816 dev_priv->r600_sx_max_export_smx_size = 128;
817 dev_priv->r600_sq_num_cf_insts = 1;
820 dev_priv->r600_max_pipes = 4;
821 dev_priv->r600_max_tile_pipes = 4;
822 dev_priv->r600_max_simds = 4;
823 dev_priv->r600_max_backends = 4;
824 dev_priv->r600_max_gprs = 192;
825 dev_priv->r600_max_threads = 192;
826 dev_priv->r600_max_stack_entries = 256;
827 dev_priv->r600_max_hw_contexts = 8;
828 dev_priv->r600_max_gs_threads = 16;
829 dev_priv->r600_sx_max_export_size = 128;
830 dev_priv->r600_sx_max_export_pos_size = 16;
831 dev_priv->r600_sx_max_export_smx_size = 128;
832 dev_priv->r600_sq_num_cf_insts = 2;
840 for (i = 0; i < 32; i++) {
841 RADEON_WRITE((0x2c14 + j), 0x00000000);
842 RADEON_WRITE((0x2c18 + j), 0x00000000);
843 RADEON_WRITE((0x2c1c + j), 0x00000000);
844 RADEON_WRITE((0x2c20 + j), 0x00000000);
845 RADEON_WRITE((0x2c24 + j), 0x00000000);
849 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
851 /* setup tiling, simd, pipe config */
852 ramcfg = RADEON_READ(R600_RAMCFG);
854 switch (dev_priv->r600_max_tile_pipes) {
856 gb_tiling_config |= R600_PIPE_TILING(0);
859 gb_tiling_config |= R600_PIPE_TILING(1);
862 gb_tiling_config |= R600_PIPE_TILING(2);
865 gb_tiling_config |= R600_PIPE_TILING(3);
871 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
873 gb_tiling_config |= R600_GROUP_SIZE(0);
875 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
876 gb_tiling_config |= R600_ROW_TILING(3);
877 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
880 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
882 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
885 gb_tiling_config |= R600_BANK_SWAPS(1);
887 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
888 cc_rb_backend_disable |=
889 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
891 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
892 cc_gc_shader_pipe_config |=
893 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
894 cc_gc_shader_pipe_config |=
895 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
897 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
899 r600_count_pipe_bits((cc_rb_backend_disable &
900 R6XX_MAX_BACKENDS_MASK) >> 16)),
901 (cc_rb_backend_disable >> 16));
902 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
904 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
905 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
906 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
907 if (gb_tiling_config & 0xc0) {
908 dev_priv->r600_group_size = 512;
910 dev_priv->r600_group_size = 256;
912 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
913 if (gb_tiling_config & 0x30) {
914 dev_priv->r600_nbanks = 8;
916 dev_priv->r600_nbanks = 4;
919 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
920 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
921 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
924 R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
925 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
926 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
928 /* set HW defaults for 3D engine */
929 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
930 R600_ROQ_IB2_START(0x2b)));
932 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
933 R600_ROQ_END(0x40)));
935 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
940 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
941 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
943 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
944 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
945 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
946 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
947 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
949 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
950 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
951 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
952 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
953 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
954 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
955 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
957 RADEON_WRITE(R600_DB_DEBUG, 0);
959 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
960 R600_DEPTH_FLUSH(16) |
961 R600_DEPTH_PENDING_FREE(4) |
962 R600_DEPTH_CACHELINE_FREE(16)));
963 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
964 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
966 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
967 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
969 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
970 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
971 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
972 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
973 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
974 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
975 R600_FETCH_FIFO_HIWATER(0xa) |
976 R600_DONE_FIFO_HIWATER(0xe0) |
977 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
978 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
979 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
980 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
981 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
983 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
985 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
986 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
988 sq_config = RADEON_READ(R600_SQ_CONFIG);
989 sq_config &= ~(R600_PS_PRIO(3) |
993 sq_config |= (R600_DX9_CONSTS |
1000 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
1001 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
1002 R600_NUM_VS_GPRS(124) |
1003 R600_NUM_CLAUSE_TEMP_GPRS(4));
1004 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
1005 R600_NUM_ES_GPRS(0));
1006 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
1007 R600_NUM_VS_THREADS(48) |
1008 R600_NUM_GS_THREADS(4) |
1009 R600_NUM_ES_THREADS(4));
1010 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
1011 R600_NUM_VS_STACK_ENTRIES(128));
1012 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
1013 R600_NUM_ES_STACK_ENTRIES(0));
1014 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1015 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1016 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1017 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
1018 /* no vertex cache */
1019 sq_config &= ~R600_VC_ENABLE;
1021 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1022 R600_NUM_VS_GPRS(44) |
1023 R600_NUM_CLAUSE_TEMP_GPRS(2));
1024 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1025 R600_NUM_ES_GPRS(17));
1026 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1027 R600_NUM_VS_THREADS(78) |
1028 R600_NUM_GS_THREADS(4) |
1029 R600_NUM_ES_THREADS(31));
1030 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1031 R600_NUM_VS_STACK_ENTRIES(40));
1032 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1033 R600_NUM_ES_STACK_ENTRIES(16));
1034 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1035 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1036 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1037 R600_NUM_VS_GPRS(44) |
1038 R600_NUM_CLAUSE_TEMP_GPRS(2));
1039 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1040 R600_NUM_ES_GPRS(18));
1041 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1042 R600_NUM_VS_THREADS(78) |
1043 R600_NUM_GS_THREADS(4) |
1044 R600_NUM_ES_THREADS(31));
1045 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1046 R600_NUM_VS_STACK_ENTRIES(40));
1047 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1048 R600_NUM_ES_STACK_ENTRIES(16));
1049 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1050 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1051 R600_NUM_VS_GPRS(44) |
1052 R600_NUM_CLAUSE_TEMP_GPRS(2));
1053 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1054 R600_NUM_ES_GPRS(17));
1055 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1056 R600_NUM_VS_THREADS(78) |
1057 R600_NUM_GS_THREADS(4) |
1058 R600_NUM_ES_THREADS(31));
1059 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1060 R600_NUM_VS_STACK_ENTRIES(64));
1061 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1062 R600_NUM_ES_STACK_ENTRIES(64));
1065 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1066 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1067 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1068 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1069 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1070 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1072 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1073 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1074 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1075 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1076 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1078 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1080 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1084 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1092 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1100 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1110 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1114 gs_prim_buffer_depth = 0;
1120 gs_prim_buffer_depth = 32;
1123 gs_prim_buffer_depth = 128;
1129 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1130 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1131 /* Max value for this is 256 */
1132 if (vgt_gs_per_es > 256)
1133 vgt_gs_per_es = 256;
1135 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1136 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1137 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1138 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1140 /* more default values. 2D/3D driver should adjust as needed */
1141 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1142 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1143 RADEON_WRITE(R600_SX_MISC, 0);
1144 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1145 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1146 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1147 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1148 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1149 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1151 /* clear render buffer base addresses */
1152 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1153 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1154 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1155 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1156 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1157 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1158 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1159 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1161 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1166 tc_cntl = R600_TC_L2_SIZE(8);
1170 tc_cntl = R600_TC_L2_SIZE(4);
1173 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1176 tc_cntl = R600_TC_L2_SIZE(0);
1180 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1182 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1183 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1185 arb_pop = RADEON_READ(R600_ARB_POP);
1186 arb_pop |= R600_ENABLE_TC128;
1187 RADEON_WRITE(R600_ARB_POP, arb_pop);
1189 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1190 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1191 R600_NUM_CLIP_SEQ(3)));
1192 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1196 static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv,
1199 u32 backend_disable_mask)
1201 u32 backend_map = 0;
1202 u32 enabled_backends_mask;
1203 u32 enabled_backends_count;
1205 u32 swizzle_pipe[R7XX_MAX_PIPES];
1208 bool force_no_swizzle;
1210 if (num_tile_pipes > R7XX_MAX_PIPES)
1211 num_tile_pipes = R7XX_MAX_PIPES;
1212 if (num_tile_pipes < 1)
1214 if (num_backends > R7XX_MAX_BACKENDS)
1215 num_backends = R7XX_MAX_BACKENDS;
1216 if (num_backends < 1)
1219 enabled_backends_mask = 0;
1220 enabled_backends_count = 0;
1221 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1222 if (((backend_disable_mask >> i) & 1) == 0) {
1223 enabled_backends_mask |= (1 << i);
1224 ++enabled_backends_count;
1226 if (enabled_backends_count == num_backends)
1230 if (enabled_backends_count == 0) {
1231 enabled_backends_mask = 1;
1232 enabled_backends_count = 1;
1235 if (enabled_backends_count != num_backends)
1236 num_backends = enabled_backends_count;
1238 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1241 force_no_swizzle = false;
1246 force_no_swizzle = true;
1250 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1251 switch (num_tile_pipes) {
1253 swizzle_pipe[0] = 0;
1256 swizzle_pipe[0] = 0;
1257 swizzle_pipe[1] = 1;
1260 if (force_no_swizzle) {
1261 swizzle_pipe[0] = 0;
1262 swizzle_pipe[1] = 1;
1263 swizzle_pipe[2] = 2;
1265 swizzle_pipe[0] = 0;
1266 swizzle_pipe[1] = 2;
1267 swizzle_pipe[2] = 1;
1271 if (force_no_swizzle) {
1272 swizzle_pipe[0] = 0;
1273 swizzle_pipe[1] = 1;
1274 swizzle_pipe[2] = 2;
1275 swizzle_pipe[3] = 3;
1277 swizzle_pipe[0] = 0;
1278 swizzle_pipe[1] = 2;
1279 swizzle_pipe[2] = 3;
1280 swizzle_pipe[3] = 1;
1284 if (force_no_swizzle) {
1285 swizzle_pipe[0] = 0;
1286 swizzle_pipe[1] = 1;
1287 swizzle_pipe[2] = 2;
1288 swizzle_pipe[3] = 3;
1289 swizzle_pipe[4] = 4;
1291 swizzle_pipe[0] = 0;
1292 swizzle_pipe[1] = 2;
1293 swizzle_pipe[2] = 4;
1294 swizzle_pipe[3] = 1;
1295 swizzle_pipe[4] = 3;
1299 if (force_no_swizzle) {
1300 swizzle_pipe[0] = 0;
1301 swizzle_pipe[1] = 1;
1302 swizzle_pipe[2] = 2;
1303 swizzle_pipe[3] = 3;
1304 swizzle_pipe[4] = 4;
1305 swizzle_pipe[5] = 5;
1307 swizzle_pipe[0] = 0;
1308 swizzle_pipe[1] = 2;
1309 swizzle_pipe[2] = 4;
1310 swizzle_pipe[3] = 5;
1311 swizzle_pipe[4] = 3;
1312 swizzle_pipe[5] = 1;
1316 if (force_no_swizzle) {
1317 swizzle_pipe[0] = 0;
1318 swizzle_pipe[1] = 1;
1319 swizzle_pipe[2] = 2;
1320 swizzle_pipe[3] = 3;
1321 swizzle_pipe[4] = 4;
1322 swizzle_pipe[5] = 5;
1323 swizzle_pipe[6] = 6;
1325 swizzle_pipe[0] = 0;
1326 swizzle_pipe[1] = 2;
1327 swizzle_pipe[2] = 4;
1328 swizzle_pipe[3] = 6;
1329 swizzle_pipe[4] = 3;
1330 swizzle_pipe[5] = 1;
1331 swizzle_pipe[6] = 5;
1335 if (force_no_swizzle) {
1336 swizzle_pipe[0] = 0;
1337 swizzle_pipe[1] = 1;
1338 swizzle_pipe[2] = 2;
1339 swizzle_pipe[3] = 3;
1340 swizzle_pipe[4] = 4;
1341 swizzle_pipe[5] = 5;
1342 swizzle_pipe[6] = 6;
1343 swizzle_pipe[7] = 7;
1345 swizzle_pipe[0] = 0;
1346 swizzle_pipe[1] = 2;
1347 swizzle_pipe[2] = 4;
1348 swizzle_pipe[3] = 6;
1349 swizzle_pipe[4] = 3;
1350 swizzle_pipe[5] = 1;
1351 swizzle_pipe[6] = 7;
1352 swizzle_pipe[7] = 5;
1358 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1359 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1360 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1362 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1364 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1370 static void r700_gfx_init(struct drm_device *dev,
1371 drm_radeon_private_t *dev_priv)
1373 int i, j, num_qd_pipes;
1378 u32 num_gs_verts_per_thread;
1380 u32 gs_prim_buffer_depth = 0;
1381 u32 sq_ms_fifo_sizes;
1383 u32 sq_thread_resource_mgmt;
1384 u32 hdp_host_path_cntl;
1385 u32 sq_dyn_gpr_size_simd_ab_0;
1387 u32 gb_tiling_config = 0;
1388 u32 cc_rb_backend_disable;
1389 u32 cc_gc_shader_pipe_config;
1393 /* setup chip specs */
1394 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1396 dev_priv->r600_max_pipes = 4;
1397 dev_priv->r600_max_tile_pipes = 8;
1398 dev_priv->r600_max_simds = 10;
1399 dev_priv->r600_max_backends = 4;
1400 dev_priv->r600_max_gprs = 256;
1401 dev_priv->r600_max_threads = 248;
1402 dev_priv->r600_max_stack_entries = 512;
1403 dev_priv->r600_max_hw_contexts = 8;
1404 dev_priv->r600_max_gs_threads = 16 * 2;
1405 dev_priv->r600_sx_max_export_size = 128;
1406 dev_priv->r600_sx_max_export_pos_size = 16;
1407 dev_priv->r600_sx_max_export_smx_size = 112;
1408 dev_priv->r600_sq_num_cf_insts = 2;
1410 dev_priv->r700_sx_num_of_sets = 7;
1411 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1412 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1413 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1416 dev_priv->r600_max_pipes = 2;
1417 dev_priv->r600_max_tile_pipes = 4;
1418 dev_priv->r600_max_simds = 8;
1419 dev_priv->r600_max_backends = 2;
1420 dev_priv->r600_max_gprs = 128;
1421 dev_priv->r600_max_threads = 248;
1422 dev_priv->r600_max_stack_entries = 256;
1423 dev_priv->r600_max_hw_contexts = 8;
1424 dev_priv->r600_max_gs_threads = 16 * 2;
1425 dev_priv->r600_sx_max_export_size = 256;
1426 dev_priv->r600_sx_max_export_pos_size = 32;
1427 dev_priv->r600_sx_max_export_smx_size = 224;
1428 dev_priv->r600_sq_num_cf_insts = 2;
1430 dev_priv->r700_sx_num_of_sets = 7;
1431 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1432 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1433 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1434 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1435 dev_priv->r600_sx_max_export_pos_size -= 16;
1436 dev_priv->r600_sx_max_export_smx_size += 16;
1440 dev_priv->r600_max_pipes = 2;
1441 dev_priv->r600_max_tile_pipes = 2;
1442 dev_priv->r600_max_simds = 2;
1443 dev_priv->r600_max_backends = 1;
1444 dev_priv->r600_max_gprs = 256;
1445 dev_priv->r600_max_threads = 192;
1446 dev_priv->r600_max_stack_entries = 256;
1447 dev_priv->r600_max_hw_contexts = 4;
1448 dev_priv->r600_max_gs_threads = 8 * 2;
1449 dev_priv->r600_sx_max_export_size = 128;
1450 dev_priv->r600_sx_max_export_pos_size = 16;
1451 dev_priv->r600_sx_max_export_smx_size = 112;
1452 dev_priv->r600_sq_num_cf_insts = 1;
1454 dev_priv->r700_sx_num_of_sets = 7;
1455 dev_priv->r700_sc_prim_fifo_size = 0x40;
1456 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1457 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1460 dev_priv->r600_max_pipes = 4;
1461 dev_priv->r600_max_tile_pipes = 4;
1462 dev_priv->r600_max_simds = 8;
1463 dev_priv->r600_max_backends = 4;
1464 dev_priv->r600_max_gprs = 256;
1465 dev_priv->r600_max_threads = 248;
1466 dev_priv->r600_max_stack_entries = 512;
1467 dev_priv->r600_max_hw_contexts = 8;
1468 dev_priv->r600_max_gs_threads = 16 * 2;
1469 dev_priv->r600_sx_max_export_size = 256;
1470 dev_priv->r600_sx_max_export_pos_size = 32;
1471 dev_priv->r600_sx_max_export_smx_size = 224;
1472 dev_priv->r600_sq_num_cf_insts = 2;
1474 dev_priv->r700_sx_num_of_sets = 7;
1475 dev_priv->r700_sc_prim_fifo_size = 0x100;
1476 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1477 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1479 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1480 dev_priv->r600_sx_max_export_pos_size -= 16;
1481 dev_priv->r600_sx_max_export_smx_size += 16;
1488 /* Initialize HDP */
1490 for (i = 0; i < 32; i++) {
1491 RADEON_WRITE((0x2c14 + j), 0x00000000);
1492 RADEON_WRITE((0x2c18 + j), 0x00000000);
1493 RADEON_WRITE((0x2c1c + j), 0x00000000);
1494 RADEON_WRITE((0x2c20 + j), 0x00000000);
1495 RADEON_WRITE((0x2c24 + j), 0x00000000);
1499 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1501 /* setup tiling, simd, pipe config */
1502 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1504 switch (dev_priv->r600_max_tile_pipes) {
1506 gb_tiling_config |= R600_PIPE_TILING(0);
1509 gb_tiling_config |= R600_PIPE_TILING(1);
1512 gb_tiling_config |= R600_PIPE_TILING(2);
1515 gb_tiling_config |= R600_PIPE_TILING(3);
1521 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1522 gb_tiling_config |= R600_BANK_TILING(1);
1524 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1526 gb_tiling_config |= R600_GROUP_SIZE(0);
1528 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1529 gb_tiling_config |= R600_ROW_TILING(3);
1530 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1533 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1535 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1538 gb_tiling_config |= R600_BANK_SWAPS(1);
1540 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1541 cc_rb_backend_disable |=
1542 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1544 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1545 cc_gc_shader_pipe_config |=
1546 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1547 cc_gc_shader_pipe_config |=
1548 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1550 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1553 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv,
1554 dev_priv->r600_max_tile_pipes,
1555 (R7XX_MAX_BACKENDS -
1556 r600_count_pipe_bits((cc_rb_backend_disable &
1557 R7XX_MAX_BACKENDS_MASK) >> 16)),
1558 (cc_rb_backend_disable >> 16));
1559 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1561 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1562 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1563 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1564 if (gb_tiling_config & 0xc0) {
1565 dev_priv->r600_group_size = 512;
1567 dev_priv->r600_group_size = 256;
1569 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1570 if (gb_tiling_config & 0x30) {
1571 dev_priv->r600_nbanks = 8;
1573 dev_priv->r600_nbanks = 4;
1576 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1577 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1578 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1580 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1581 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1582 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1583 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1584 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1587 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
1588 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1589 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1591 /* set HW defaults for 3D engine */
1592 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1593 R600_ROQ_IB2_START(0x2b)));
1595 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1597 ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX);
1598 RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO);
1600 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1601 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1602 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1604 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1605 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1606 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1607 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1609 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740)
1610 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1611 R700_GS_FLUSH_CTL(4) |
1612 R700_ACK_FLUSH_CTL(3) |
1613 R700_SYNC_FLUSH_CTL));
1615 db_debug3 = RADEON_READ(R700_DB_DEBUG3);
1616 db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f);
1617 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1620 db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f);
1625 db_debug3 |= R700_DB_CLK_OFF_DELAY(2);
1628 RADEON_WRITE(R700_DB_DEBUG3, db_debug3);
1630 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) {
1631 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1632 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1633 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1636 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1637 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1638 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1640 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1641 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1642 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1644 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1646 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1648 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1650 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1652 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1654 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1655 R600_DONE_FIFO_HIWATER(0xe0) |
1656 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1657 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1661 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1665 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1668 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1670 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1671 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1673 sq_config = RADEON_READ(R600_SQ_CONFIG);
1674 sq_config &= ~(R600_PS_PRIO(3) |
1678 sq_config |= (R600_DX9_CONSTS |
1685 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1686 /* no vertex cache */
1687 sq_config &= ~R600_VC_ENABLE;
1689 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1691 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1692 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1693 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1695 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1696 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1698 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1699 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1700 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1701 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1702 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1704 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1705 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1707 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1708 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1710 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1711 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1713 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1714 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1715 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1716 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1718 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1719 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1720 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1721 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1722 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1723 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1724 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1725 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1727 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1728 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1730 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1731 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1732 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1734 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1735 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1737 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1741 gs_prim_buffer_depth = 384;
1744 gs_prim_buffer_depth = 128;
1750 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1751 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1752 /* Max value for this is 256 */
1753 if (vgt_gs_per_es > 256)
1754 vgt_gs_per_es = 256;
1756 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1757 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1758 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1760 /* more default values. 2D/3D driver should adjust as needed */
1761 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1762 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1763 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1764 RADEON_WRITE(R600_SX_MISC, 0);
1765 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1766 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1767 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1768 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1769 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1770 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1771 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1772 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1774 /* clear render buffer base addresses */
1775 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1776 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1777 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1778 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1779 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1780 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1781 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1782 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1784 RADEON_WRITE(R700_TCP_CNTL, 0);
1786 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1787 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1789 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1791 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1792 R600_NUM_CLIP_SEQ(3)));
1796 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1797 drm_radeon_private_t *dev_priv,
1798 struct drm_file *file_priv)
1800 struct drm_radeon_master_private *master_priv;
1804 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1805 r700_gfx_init(dev, dev_priv);
1807 r600_gfx_init(dev, dev_priv);
1809 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1810 RADEON_READ(R600_GRBM_SOFT_RESET);
1812 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1815 /* Set ring buffer size */
1817 RADEON_WRITE(R600_CP_RB_CNTL,
1818 R600_BUF_SWAP_32BIT |
1820 (dev_priv->ring.rptr_update_l2qw << 8) |
1821 dev_priv->ring.size_l2qw);
1823 RADEON_WRITE(R600_CP_RB_CNTL,
1824 RADEON_RB_NO_UPDATE |
1825 (dev_priv->ring.rptr_update_l2qw << 8) |
1826 dev_priv->ring.size_l2qw);
1829 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0);
1831 /* Set the write pointer delay */
1832 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1835 RADEON_WRITE(R600_CP_RB_CNTL,
1836 R600_BUF_SWAP_32BIT |
1838 R600_RB_RPTR_WR_ENA |
1839 (dev_priv->ring.rptr_update_l2qw << 8) |
1840 dev_priv->ring.size_l2qw);
1842 RADEON_WRITE(R600_CP_RB_CNTL,
1844 R600_RB_RPTR_WR_ENA |
1845 (dev_priv->ring.rptr_update_l2qw << 8) |
1846 dev_priv->ring.size_l2qw);
1849 /* Initialize the ring buffer's read and write pointers */
1850 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1851 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1852 SET_RING_HEAD(dev_priv, 0);
1853 dev_priv->ring.tail = 0;
1856 if (dev_priv->flags & RADEON_IS_AGP) {
1857 rptr_addr = dev_priv->ring_rptr->offset
1859 dev_priv->gart_vm_start;
1863 rptr_addr = dev_priv->ring_rptr->offset
1864 - ((unsigned long) dev->sg->vaddr)
1865 + dev_priv->gart_vm_start;
1867 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc));
1868 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr));
1871 RADEON_WRITE(R600_CP_RB_CNTL,
1872 RADEON_BUF_SWAP_32BIT |
1873 (dev_priv->ring.rptr_update_l2qw << 8) |
1874 dev_priv->ring.size_l2qw);
1876 RADEON_WRITE(R600_CP_RB_CNTL,
1877 (dev_priv->ring.rptr_update_l2qw << 8) |
1878 dev_priv->ring.size_l2qw);
1882 if (dev_priv->flags & RADEON_IS_AGP) {
1884 radeon_write_agp_base(dev_priv, dev->agp->base);
1887 radeon_write_agp_location(dev_priv,
1888 (((dev_priv->gart_vm_start - 1 +
1889 dev_priv->gart_size) & 0xffff0000) |
1890 (dev_priv->gart_vm_start >> 16)));
1892 ring_start = (dev_priv->cp_ring->offset
1894 + dev_priv->gart_vm_start);
1897 ring_start = (dev_priv->cp_ring->offset
1898 - (unsigned long)dev->sg->vaddr>
1899 + dev_priv->gart_vm_start);
1901 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1903 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1905 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1907 /* Initialize the scratch register pointer. This will cause
1908 * the scratch register values to be written out to memory
1909 * whenever they are updated.
1911 * We simply put this behind the ring read pointer, this works
1912 * with PCI GART as well as (whatever kind of) AGP GART
1917 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
1918 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1919 scratch_addr += R600_SCRATCH_REG_OFFSET;
1921 scratch_addr &= 0xffffffff;
1923 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1926 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1928 /* Turn on bus mastering */
1929 radeon_enable_bm(dev_priv);
1931 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1932 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1934 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1935 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1937 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1938 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1940 /* reset sarea copies of these */
1941 master_priv = file_priv->master->driver_priv;
1942 if (master_priv->sarea_priv) {
1943 master_priv->sarea_priv->last_frame = 0;
1944 master_priv->sarea_priv->last_dispatch = 0;
1945 master_priv->sarea_priv->last_clear = 0;
1948 r600_do_wait_for_idle(dev_priv);
1952 int r600_do_cleanup_cp(struct drm_device *dev)
1954 drm_radeon_private_t *dev_priv = dev->dev_private;
1957 /* Make sure interrupts are disabled here because the uninstall ioctl
1958 * may not have been called from userspace and after dev_private
1959 * is freed, it's too late.
1961 if (dev->irq_enabled)
1962 drm_irq_uninstall(dev);
1965 if (dev_priv->flags & RADEON_IS_AGP) {
1966 if (dev_priv->cp_ring != NULL) {
1967 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1968 dev_priv->cp_ring = NULL;
1970 if (dev_priv->ring_rptr != NULL) {
1971 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1972 dev_priv->ring_rptr = NULL;
1974 if (dev->agp_buffer_map != NULL) {
1975 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1976 dev->agp_buffer_map = NULL;
1982 if (dev_priv->gart_info.bus_addr)
1983 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1985 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1986 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1987 dev_priv->gart_info.addr = NULL;
1990 /* only clear to the start of flags */
1991 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1996 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1997 struct drm_file *file_priv)
1999 drm_radeon_private_t *dev_priv = dev->dev_private;
2000 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2004 sx_init(&dev_priv->cs_mutex, "drm__radeon_private__cs_mutex");
2005 r600_cs_legacy_init();
2006 /* if we require new memory map but we don't have it fail */
2007 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
2008 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
2009 r600_do_cleanup_cp(dev);
2013 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
2014 DRM_DEBUG("Forcing AGP card to PCI mode\n");
2015 dev_priv->flags &= ~RADEON_IS_AGP;
2016 /* The writeback test succeeds, but when writeback is enabled,
2017 * the ring buffer read ptr update fails after first 128 bytes.
2020 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
2022 DRM_DEBUG("Restoring AGP flag\n");
2023 dev_priv->flags |= RADEON_IS_AGP;
2026 dev_priv->usec_timeout = init->usec_timeout;
2027 if (dev_priv->usec_timeout < 1 ||
2028 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
2029 DRM_DEBUG("TIMEOUT problem!\n");
2030 r600_do_cleanup_cp(dev);
2034 /* Enable vblank on CRTC1 for older X servers
2036 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
2037 dev_priv->do_boxes = 0;
2038 dev_priv->cp_mode = init->cp_mode;
2040 /* We don't support anything other than bus-mastering ring mode,
2041 * but the ring can be in either AGP or PCI space for the ring
2044 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
2045 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
2046 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
2047 r600_do_cleanup_cp(dev);
2051 switch (init->fb_bpp) {
2053 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
2057 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
2060 dev_priv->front_offset = init->front_offset;
2061 dev_priv->front_pitch = init->front_pitch;
2062 dev_priv->back_offset = init->back_offset;
2063 dev_priv->back_pitch = init->back_pitch;
2065 dev_priv->ring_offset = init->ring_offset;
2066 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
2067 dev_priv->buffers_offset = init->buffers_offset;
2068 dev_priv->gart_textures_offset = init->gart_textures_offset;
2070 master_priv->sarea = drm_getsarea(dev);
2071 if (!master_priv->sarea) {
2072 DRM_ERROR("could not find sarea!\n");
2073 r600_do_cleanup_cp(dev);
2077 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
2078 if (!dev_priv->cp_ring) {
2079 DRM_ERROR("could not find cp ring region!\n");
2080 r600_do_cleanup_cp(dev);
2083 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
2084 if (!dev_priv->ring_rptr) {
2085 DRM_ERROR("could not find ring read pointer!\n");
2086 r600_do_cleanup_cp(dev);
2089 dev->agp_buffer_token = init->buffers_offset;
2090 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
2091 if (!dev->agp_buffer_map) {
2092 DRM_ERROR("could not find dma buffer region!\n");
2093 r600_do_cleanup_cp(dev);
2097 if (init->gart_textures_offset) {
2098 dev_priv->gart_textures =
2099 drm_core_findmap(dev, init->gart_textures_offset);
2100 if (!dev_priv->gart_textures) {
2101 DRM_ERROR("could not find GART texture region!\n");
2102 r600_do_cleanup_cp(dev);
2109 if (dev_priv->flags & RADEON_IS_AGP) {
2110 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
2111 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
2112 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
2113 if (!dev_priv->cp_ring->handle ||
2114 !dev_priv->ring_rptr->handle ||
2115 !dev->agp_buffer_map->handle) {
2116 DRM_ERROR("could not find ioremap agp regions!\n");
2117 r600_do_cleanup_cp(dev);
2123 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
2124 dev_priv->ring_rptr->handle =
2125 (void *)(unsigned long)dev_priv->ring_rptr->offset;
2126 dev->agp_buffer_map->handle =
2127 (void *)(unsigned long)dev->agp_buffer_map->offset;
2129 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2130 dev_priv->cp_ring->handle);
2131 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2132 dev_priv->ring_rptr->handle);
2133 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2134 dev->agp_buffer_map->handle);
2137 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2139 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2140 - dev_priv->fb_location;
2142 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2143 ((dev_priv->front_offset
2144 + dev_priv->fb_location) >> 10));
2146 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2147 ((dev_priv->back_offset
2148 + dev_priv->fb_location) >> 10));
2150 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2151 ((dev_priv->depth_offset
2152 + dev_priv->fb_location) >> 10));
2154 dev_priv->gart_size = init->gart_size;
2156 /* New let's set the memory map ... */
2157 if (dev_priv->new_memmap) {
2160 DRM_INFO("Setting GART location based on new memory map\n");
2162 /* If using AGP, try to locate the AGP aperture at the same
2163 * location in the card and on the bus, though we have to
2168 if (dev_priv->flags & RADEON_IS_AGP) {
2169 base = dev->agp->base;
2170 /* Check if valid */
2171 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2172 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2173 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2179 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2181 base = dev_priv->fb_location + dev_priv->fb_size;
2182 if (base < dev_priv->fb_location ||
2183 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2184 base = dev_priv->fb_location
2185 - dev_priv->gart_size;
2187 dev_priv->gart_vm_start = base & 0xffc00000u;
2188 if (dev_priv->gart_vm_start != base)
2189 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2190 base, dev_priv->gart_vm_start);
2195 if (dev_priv->flags & RADEON_IS_AGP)
2196 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2198 + dev_priv->gart_vm_start);
2201 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2202 - (unsigned long)dev->sg->vaddr
2203 + dev_priv->gart_vm_start);
2205 DRM_DEBUG("fb 0x%08x size %d\n",
2206 (unsigned int) dev_priv->fb_location,
2207 (unsigned int) dev_priv->fb_size);
2208 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2209 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2210 (unsigned int) dev_priv->gart_vm_start);
2211 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2212 dev_priv->gart_buffers_offset);
2214 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2215 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2216 + init->ring_size / sizeof(u32));
2217 dev_priv->ring.size = init->ring_size;
2218 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2220 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2221 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2223 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2224 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2226 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2228 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2231 if (dev_priv->flags & RADEON_IS_AGP) {
2232 /* XXX turn off pcie gart */
2236 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2237 /* if we have an offset set from userspace */
2238 if (!dev_priv->pcigart_offset_set) {
2239 DRM_ERROR("Need gart offset from userspace\n");
2240 r600_do_cleanup_cp(dev);
2244 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2246 dev_priv->gart_info.bus_addr =
2247 dev_priv->pcigart_offset + dev_priv->fb_location;
2248 dev_priv->gart_info.mapping.offset =
2249 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2250 dev_priv->gart_info.mapping.size =
2251 dev_priv->gart_info.table_size;
2253 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2254 if (!dev_priv->gart_info.mapping.handle) {
2255 DRM_ERROR("ioremap failed.\n");
2256 r600_do_cleanup_cp(dev);
2260 dev_priv->gart_info.addr =
2261 dev_priv->gart_info.mapping.handle;
2263 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2264 dev_priv->gart_info.addr,
2265 dev_priv->pcigart_offset);
2267 if (!r600_page_table_init(dev)) {
2268 DRM_ERROR("Failed to init GART table\n");
2269 r600_do_cleanup_cp(dev);
2273 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2279 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2280 int err = r600_cp_init_microcode(dev_priv);
2282 DRM_ERROR("Failed to load firmware!\n");
2283 r600_do_cleanup_cp(dev);
2287 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2288 r700_cp_load_microcode(dev_priv);
2290 r600_cp_load_microcode(dev_priv);
2292 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2294 dev_priv->last_buf = 0;
2296 r600_do_engine_reset(dev);
2297 r600_test_writeback(dev_priv);
2302 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2304 drm_radeon_private_t *dev_priv = dev->dev_private;
2307 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2309 r700_cp_load_microcode(dev_priv);
2312 r600_cp_load_microcode(dev_priv);
2314 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2315 r600_do_engine_reset(dev);
2320 /* Wait for the CP to go idle.
2322 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2328 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2329 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2330 /* wait for 3D idle clean */
2331 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2332 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2333 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2338 return r600_do_wait_for_idle(dev_priv);
2341 /* Start the Command Processor.
2343 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2350 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2351 OUT_RING(0x00000001);
2352 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2353 OUT_RING(0x00000003);
2355 OUT_RING(0x00000000);
2356 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2357 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2358 OUT_RING(0x00000000);
2359 OUT_RING(0x00000000);
2363 /* set the mux and reset the halt bit */
2365 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2367 dev_priv->cp_running = 1;
2371 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2376 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2377 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2378 SET_RING_HEAD(dev_priv, cur_read_ptr);
2379 dev_priv->ring.tail = cur_read_ptr;
2382 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2388 cp_me = 0xff | R600_CP_ME_HALT;
2390 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2392 dev_priv->cp_running = 0;
2395 int r600_cp_dispatch_indirect(struct drm_device *dev,
2396 struct drm_buf *buf, int start, int end)
2398 drm_radeon_private_t *dev_priv = dev->dev_private;
2402 unsigned long offset = (dev_priv->gart_buffers_offset
2403 + buf->offset + start);
2404 int dwords = (end - start + 3) / sizeof(u32);
2406 DRM_DEBUG("dwords:%d\n", dwords);
2407 DRM_DEBUG("offset 0x%lx\n", offset);
2410 /* Indirect buffer data must be a multiple of 16 dwords.
2411 * pad the data with a Type-2 CP packet.
2413 while (dwords & 0xf) {
2415 ((char *)dev->agp_buffer_map->handle
2416 + buf->offset + start);
2417 data[dwords++] = RADEON_CP_PACKET2;
2420 /* Fire off the indirect buffer */
2422 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2423 OUT_RING((offset & 0xfffffffc));
2424 OUT_RING((upper_32_bits(offset) & 0xff));
2432 void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2434 drm_radeon_private_t *dev_priv = dev->dev_private;
2435 struct drm_master *master = file_priv->master;
2436 struct drm_radeon_master_private *master_priv = master->driver_priv;
2437 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2438 int nbox = sarea_priv->nbox;
2439 struct drm_clip_rect *pbox = sarea_priv->boxes;
2440 int i, cpp, src_pitch, dst_pitch;
2445 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2450 if (sarea_priv->pfCurrentPage == 0) {
2451 src_pitch = dev_priv->back_pitch;
2452 dst_pitch = dev_priv->front_pitch;
2453 src = dev_priv->back_offset + dev_priv->fb_location;
2454 dst = dev_priv->front_offset + dev_priv->fb_location;
2456 src_pitch = dev_priv->front_pitch;
2457 dst_pitch = dev_priv->back_pitch;
2458 src = dev_priv->front_offset + dev_priv->fb_location;
2459 dst = dev_priv->back_offset + dev_priv->fb_location;
2462 if (r600_prepare_blit_copy(dev, file_priv)) {
2463 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2466 for (i = 0; i < nbox; i++) {
2469 int w = pbox[i].x2 - x;
2470 int h = pbox[i].y2 - y;
2472 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2477 src_pitch, dst_pitch, cpp);
2479 r600_done_blit_copy(dev);
2481 /* Increment the frame counter. The client-side 3D driver must
2482 * throttle the framerate by waiting for this value before
2483 * performing the swapbuffer ioctl.
2485 sarea_priv->last_frame++;
2488 R600_FRAME_AGE(sarea_priv->last_frame);
2492 int r600_cp_dispatch_texture(struct drm_device *dev,
2493 struct drm_file *file_priv,
2494 drm_radeon_texture_t *tex,
2495 drm_radeon_tex_image_t *image)
2497 drm_radeon_private_t *dev_priv = dev->dev_private;
2498 struct drm_buf *buf;
2500 const u8 __user *data;
2501 int size, pass_size;
2502 u64 src_offset, dst_offset;
2504 if (!radeon_check_offset(dev_priv, tex->offset)) {
2505 DRM_ERROR("Invalid destination offset\n");
2509 /* this might fail for zero-sized uploads - are those illegal? */
2510 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2511 DRM_ERROR("Invalid final destination offset\n");
2515 size = tex->height * tex->pitch;
2520 dst_offset = tex->offset;
2522 if (r600_prepare_blit_copy(dev, file_priv)) {
2523 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2527 data = (const u8 __user *)image->data;
2530 buf = radeon_freelist_get(dev);
2532 DRM_DEBUG("EAGAIN\n");
2533 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2538 if (pass_size > buf->total)
2539 pass_size = buf->total;
2541 /* Dispatch the indirect buffer.
2544 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2546 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2547 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2551 buf->file_priv = file_priv;
2552 buf->used = pass_size;
2553 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2555 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2557 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2559 /* Update the input parameters for next time */
2560 image->data = (const u8 __user *)image->data + pass_size;
2561 dst_offset += pass_size;
2564 r600_done_blit_copy(dev);
2572 static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2574 /* FIXME: check if wrap affect last reported wrap & sequence */
2575 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2576 if (!radeon->cs_id_scnt) {
2577 /* increment wrap counter */
2578 radeon->cs_id_wcnt += 0x01000000;
2579 /* valid sequence counter start at 1 */
2580 radeon->cs_id_scnt = 1;
2582 return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2585 static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2589 *id = radeon_cs_id_get(dev_priv);
2593 R600_CLEAR_AGE(*id);
2598 static int r600_ib_get(struct drm_device *dev,
2599 struct drm_file *fpriv,
2600 struct drm_buf **buffer)
2602 struct drm_buf *buf;
2605 buf = radeon_freelist_get(dev);
2609 buf->file_priv = fpriv;
2614 static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2615 struct drm_file *fpriv, int l, int r)
2617 drm_radeon_private_t *dev_priv = dev->dev_private;
2621 r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2622 radeon_cp_discard_buffer(dev, fpriv->master, buf);
2627 int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2629 struct drm_radeon_private *dev_priv = dev->dev_private;
2630 struct drm_radeon_cs *cs = data;
2631 struct drm_buf *buf;
2636 if (dev_priv == NULL) {
2637 DRM_ERROR("called with no initialization\n");
2640 family = dev_priv->flags & RADEON_FAMILY_MASK;
2641 if (family < CHIP_R600) {
2642 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2645 sx_xlock(&dev_priv->cs_mutex);
2648 r = r600_ib_get(dev, fpriv, &buf);
2650 DRM_ERROR("ib_get failed\n");
2653 ib = (u32 *)((uintptr_t)dev->agp_buffer_map->handle + buf->offset);
2654 /* now parse command stream */
2655 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
2661 r600_ib_free(dev, buf, fpriv, l, r);
2662 /* emit cs id sequence */
2663 r600_cs_id_emit(dev_priv, &cs_id);
2665 sx_xunlock(&dev_priv->cs_mutex);
2669 void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2671 struct drm_radeon_private *dev_priv = dev->dev_private;
2673 *npipes = dev_priv->r600_npipes;
2674 *nbanks = dev_priv->r600_nbanks;
2675 *group_size = dev_priv->r600_group_size;