sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                      0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  50 #define E1000_DEV_ID_82544GC_LOM                0x100D
  51 #define E1000_DEV_ID_82540EM                    0x100E
  52 #define E1000_DEV_ID_82540EM_LOM                0x1015
  53 #define E1000_DEV_ID_82540EP_LOM                0x1016
  54 #define E1000_DEV_ID_82540EP                    0x1017
  55 #define E1000_DEV_ID_82540EP_LP                 0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  70 #define E1000_DEV_ID_82541EI                    0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  72 #define E1000_DEV_ID_82541ER_LOM                0x1014
  73 #define E1000_DEV_ID_82541ER                    0x1078
  74 #define E1000_DEV_ID_82541GI                    0x1076
  75 #define E1000_DEV_ID_82541GI_LF                 0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  77 #define E1000_DEV_ID_82547EI                    0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  79 #define E1000_DEV_ID_82547GI                    0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  92 #define E1000_DEV_ID_82572EI                    0x10B9
  93 #define E1000_DEV_ID_82573E                     0x108B
  94 #define E1000_DEV_ID_82573E_IAMT                0x108C
  95 #define E1000_DEV_ID_82573L                     0x109A
  96 #define E1000_DEV_ID_82574L                     0x10D3
  97 #define E1000_DEV_ID_82574LA                    0x10F6
  98 #define E1000_DEV_ID_82583V                     0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 123 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 124 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 125 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 126 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 127 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 128 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 129 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 130 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 131 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 132 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 133 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 136 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 137 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 138 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 139 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 140 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 143 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 145 #define E1000_DEV_ID_82576                      0x10C9
 146 #define E1000_DEV_ID_82576_FIBER                0x10E6
 147 #define E1000_DEV_ID_82576_SERDES               0x10E7
 148 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 149 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 150 #define E1000_DEV_ID_82576_NS                   0x150A
 151 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 152 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 153 #define E1000_DEV_ID_82576_VF                   0x10CA
 154 #define E1000_DEV_ID_82576_VF_HV                0x152D
 155 #define E1000_DEV_ID_I350_VF                    0x1520
 156 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 157 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 158 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 159 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 160 #define E1000_DEV_ID_82580_COPPER               0x150E
 161 #define E1000_DEV_ID_82580_FIBER                0x150F
 162 #define E1000_DEV_ID_82580_SERDES               0x1510
 163 #define E1000_DEV_ID_82580_SGMII                0x1511
 164 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 165 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 166 #define E1000_DEV_ID_I350_COPPER                0x1521
 167 #define E1000_DEV_ID_I350_FIBER                 0x1522
 168 #define E1000_DEV_ID_I350_SERDES                0x1523
 169 #define E1000_DEV_ID_I350_SGMII                 0x1524
 170 #define E1000_DEV_ID_I350_DA4                   0x1546
 171 #define E1000_DEV_ID_I210_COPPER                0x1533
 172 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 173 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 174 #define E1000_DEV_ID_I210_FIBER                 0x1536
 175 #define E1000_DEV_ID_I210_SERDES                0x1537
 176 #define E1000_DEV_ID_I210_SGMII                 0x1538
 177 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 178 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 179 #define E1000_DEV_ID_I211_COPPER                0x1539
 180 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 181 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 182 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 183 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 184 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 185 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 186 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 187
 188 #define E1000_REVISION_0        0
 189 #define E1000_REVISION_1        1
 190 #define E1000_REVISION_2        2
 191 #define E1000_REVISION_3        3
 192 #define E1000_REVISION_4        4
 193
 194 #define E1000_FUNC_0            0
 195 #define E1000_FUNC_1            1
 196 #define E1000_FUNC_2            2
 197 #define E1000_FUNC_3            3
 198
 199 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 200 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 201 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 202 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 203
 204 enum e1000_mac_type {
 205         e1000_undefined = 0,
 206         e1000_82542,
 207         e1000_82543,
 208         e1000_82544,
 209         e1000_82540,
 210         e1000_82545,
 211         e1000_82545_rev_3,
 212         e1000_82546,
 213         e1000_82546_rev_3,
 214         e1000_82541,
 215         e1000_82541_rev_2,
 216         e1000_82547,
 217         e1000_82547_rev_2,
 218         e1000_82571,
 219         e1000_82572,
 220         e1000_82573,
 221         e1000_82574,
 222         e1000_82583,
 223         e1000_80003es2lan,
 224         e1000_ich8lan,
 225         e1000_ich9lan,
 226         e1000_ich10lan,
 227         e1000_pchlan,
 228         e1000_pch2lan,
 229         e1000_pch_lpt,
 230         e1000_pch_spt,
 231         e1000_82575,
 232         e1000_82576,
 233         e1000_82580,
 234         e1000_i350,
 235         e1000_i354,
 236         e1000_i210,
 237         e1000_i211,
 238         e1000_vfadapt,
 239         e1000_vfadapt_i350,
 240         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 241 };
 242
 243 enum e1000_media_type {
 244         e1000_media_type_unknown = 0,
 245         e1000_media_type_copper = 1,
 246         e1000_media_type_fiber = 2,
 247         e1000_media_type_internal_serdes = 3,
 248         e1000_num_media_types
 249 };
 250
 251 enum e1000_nvm_type {
 252         e1000_nvm_unknown = 0,
 253         e1000_nvm_none,
 254         e1000_nvm_eeprom_spi,
 255         e1000_nvm_eeprom_microwire,
 256         e1000_nvm_flash_hw,
 257         e1000_nvm_invm,
 258         e1000_nvm_flash_sw
 259 };
 260
 261 enum e1000_nvm_override {
 262         e1000_nvm_override_none = 0,
 263         e1000_nvm_override_spi_small,
 264         e1000_nvm_override_spi_large,
 265         e1000_nvm_override_microwire_small,
 266         e1000_nvm_override_microwire_large
 267 };
 268
 269 enum e1000_phy_type {
 270         e1000_phy_unknown = 0,
 271         e1000_phy_none,
 272         e1000_phy_m88,
 273         e1000_phy_igp,
 274         e1000_phy_igp_2,
 275         e1000_phy_gg82563,
 276         e1000_phy_igp_3,
 277         e1000_phy_ife,
 278         e1000_phy_bm,
 279         e1000_phy_82578,
 280         e1000_phy_82577,
 281         e1000_phy_82579,
 282         e1000_phy_i217,
 283         e1000_phy_82580,
 284         e1000_phy_vf,
 285         e1000_phy_i210,
 286 };
 287
 288 enum e1000_bus_type {
 289         e1000_bus_type_unknown = 0,
 290         e1000_bus_type_pci,
 291         e1000_bus_type_pcix,
 292         e1000_bus_type_pci_express,
 293         e1000_bus_type_reserved
 294 };
 295
 296 enum e1000_bus_speed {
 297         e1000_bus_speed_unknown = 0,
 298         e1000_bus_speed_33,
 299         e1000_bus_speed_66,
 300         e1000_bus_speed_100,
 301         e1000_bus_speed_120,
 302         e1000_bus_speed_133,
 303         e1000_bus_speed_2500,
 304         e1000_bus_speed_5000,
 305         e1000_bus_speed_reserved
 306 };
 307
 308 enum e1000_bus_width {
 309         e1000_bus_width_unknown = 0,
 310         e1000_bus_width_pcie_x1,
 311         e1000_bus_width_pcie_x2,
 312         e1000_bus_width_pcie_x4 = 4,
 313         e1000_bus_width_pcie_x8 = 8,
 314         e1000_bus_width_32,
 315         e1000_bus_width_64,
 316         e1000_bus_width_reserved
 317 };
 318
 319 enum e1000_1000t_rx_status {
 320         e1000_1000t_rx_status_not_ok = 0,
 321         e1000_1000t_rx_status_ok,
 322         e1000_1000t_rx_status_undefined = 0xFF
 323 };
 324
 325 enum e1000_rev_polarity {
 326         e1000_rev_polarity_normal = 0,
 327         e1000_rev_polarity_reversed,
 328         e1000_rev_polarity_undefined = 0xFF
 329 };
 330
 331 enum e1000_fc_mode {
 332         e1000_fc_none = 0,
 333         e1000_fc_rx_pause,
 334         e1000_fc_tx_pause,
 335         e1000_fc_full,
 336         e1000_fc_default = 0xFF
 337 };
 338
 339 enum e1000_ffe_config {
 340         e1000_ffe_config_enabled = 0,
 341         e1000_ffe_config_active,
 342         e1000_ffe_config_blocked
 343 };
 344
 345 enum e1000_dsp_config {
 346         e1000_dsp_config_disabled = 0,
 347         e1000_dsp_config_enabled,
 348         e1000_dsp_config_activated,
 349         e1000_dsp_config_undefined = 0xFF
 350 };
 351
 352 enum e1000_ms_type {
 353         e1000_ms_hw_default = 0,
 354         e1000_ms_force_master,
 355         e1000_ms_force_slave,
 356         e1000_ms_auto
 357 };
 358
 359 enum e1000_smart_speed {
 360         e1000_smart_speed_default = 0,
 361         e1000_smart_speed_on,
 362         e1000_smart_speed_off
 363 };
 364
 365 enum e1000_serdes_link_state {
 366         e1000_serdes_link_down = 0,
 367         e1000_serdes_link_autoneg_progress,
 368         e1000_serdes_link_autoneg_complete,
 369         e1000_serdes_link_forced_up
 370 };
 371
 372 #define __le16 u16
 373 #define __le32 u32
 374 #define __le64 u64
 375 /* Receive Descriptor */
 376 struct e1000_rx_desc {
 377         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 378         __le16 length;      /* Length of data DMAed into data buffer */
 379         __le16 csum; /* Packet checksum */
 380         u8  status;  /* Descriptor status */
 381         u8  errors;  /* Descriptor Errors */
 382         __le16 special;
 383 };
 384
 385 /* Receive Descriptor - Extended */
 386 union e1000_rx_desc_extended {
 387         struct {
 388                 __le64 buffer_addr;
 389                 __le64 reserved;
 390         } read;
 391         struct {
 392                 struct {
 393                         __le32 mrq; /* Multiple Rx Queues */
 394                         union {
 395                                 __le32 rss; /* RSS Hash */
 396                                 struct {
 397                                         __le16 ip_id;  /* IP id */
 398                                         __le16 csum;   /* Packet Checksum */
 399                                 } csum_ip;
 400                         } hi_dword;
 401                 } lower;
 402                 struct {
 403                         __le32 status_error;  /* ext status/error */
 404                         __le16 length;
 405                         __le16 vlan; /* VLAN tag */
 406                 } upper;
 407         } wb;  /* writeback */
 408 };
 409
 410 #define MAX_PS_BUFFERS 4
 411
 412 /* Number of packet split data buffers (not including the header buffer) */
 413 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 414
 415 /* Receive Descriptor - Packet Split */
 416 union e1000_rx_desc_packet_split {
 417         struct {
 418                 /* one buffer for protocol header(s), three data buffers */
 419                 __le64 buffer_addr[MAX_PS_BUFFERS];
 420         } read;
 421         struct {
 422                 struct {
 423                         __le32 mrq;  /* Multiple Rx Queues */
 424                         union {
 425                                 __le32 rss; /* RSS Hash */
 426                                 struct {
 427                                         __le16 ip_id;    /* IP id */
 428                                         __le16 csum;     /* Packet Checksum */
 429                                 } csum_ip;
 430                         } hi_dword;
 431                 } lower;
 432                 struct {
 433                         __le32 status_error;  /* ext status/error */
 434                         __le16 length0;  /* length of buffer 0 */
 435                         __le16 vlan;  /* VLAN tag */
 436                 } middle;
 437                 struct {
 438                         __le16 header_status;
 439                         /* length of buffers 1-3 */
 440                         __le16 length[PS_PAGE_BUFFERS];
 441                 } upper;
 442                 __le64 reserved;
 443         } wb; /* writeback */
 444 };
 445
 446 /* Transmit Descriptor */
 447 struct e1000_tx_desc {
 448         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 449         union {
 450                 __le32 data;
 451                 struct {
 452                         __le16 length;  /* Data buffer length */
 453                         u8 cso;  /* Checksum offset */
 454                         u8 cmd;  /* Descriptor control */
 455                 } flags;
 456         } lower;
 457         union {
 458                 __le32 data;
 459                 struct {
 460                         u8 status; /* Descriptor status */
 461                         u8 css;  /* Checksum start */
 462                         __le16 special;
 463                 } fields;
 464         } upper;
 465 };
 466
 467 /* Offload Context Descriptor */
 468 struct e1000_context_desc {
 469         union {
 470                 __le32 ip_config;
 471                 struct {
 472                         u8 ipcss;  /* IP checksum start */
 473                         u8 ipcso;  /* IP checksum offset */
 474                         __le16 ipcse;  /* IP checksum end */
 475                 } ip_fields;
 476         } lower_setup;
 477         union {
 478                 __le32 tcp_config;
 479                 struct {
 480                         u8 tucss;  /* TCP checksum start */
 481                         u8 tucso;  /* TCP checksum offset */
 482                         __le16 tucse;  /* TCP checksum end */
 483                 } tcp_fields;
 484         } upper_setup;
 485         __le32 cmd_and_length;
 486         union {
 487                 __le32 data;
 488                 struct {
 489                         u8 status;  /* Descriptor status */
 490                         u8 hdr_len;  /* Header length */
 491                         __le16 mss;  /* Maximum segment size */
 492                 } fields;
 493         } tcp_seg_setup;
 494 };
 495
 496 /* Offload data descriptor */
 497 struct e1000_data_desc {
 498         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 499         union {
 500                 __le32 data;
 501                 struct {
 502                         __le16 length;  /* Data buffer length */
 503                         u8 typ_len_ext;
 504                         u8 cmd;
 505                 } flags;
 506         } lower;
 507         union {
 508                 __le32 data;
 509                 struct {
 510                         u8 status;  /* Descriptor status */
 511                         u8 popts;  /* Packet Options */
 512                         __le16 special;
 513                 } fields;
 514         } upper;
 515 };
 516
 517 /* Statistics counters collected by the MAC */
 518 struct e1000_hw_stats {
 519         u64 crcerrs;
 520         u64 algnerrc;
 521         u64 symerrs;
 522         u64 rxerrc;
 523         u64 mpc;
 524         u64 scc;
 525         u64 ecol;
 526         u64 mcc;
 527         u64 latecol;
 528         u64 colc;
 529         u64 dc;
 530         u64 tncrs;
 531         u64 sec;
 532         u64 cexterr;
 533         u64 rlec;
 534         u64 xonrxc;
 535         u64 xontxc;
 536         u64 xoffrxc;
 537         u64 xofftxc;
 538         u64 fcruc;
 539         u64 prc64;
 540         u64 prc127;
 541         u64 prc255;
 542         u64 prc511;
 543         u64 prc1023;
 544         u64 prc1522;
 545         u64 gprc;
 546         u64 bprc;
 547         u64 mprc;
 548         u64 gptc;
 549         u64 gorc;
 550         u64 gotc;
 551         u64 rnbc;
 552         u64 ruc;
 553         u64 rfc;
 554         u64 roc;
 555         u64 rjc;
 556         u64 mgprc;
 557         u64 mgpdc;
 558         u64 mgptc;
 559         u64 tor;
 560         u64 tot;
 561         u64 tpr;
 562         u64 tpt;
 563         u64 ptc64;
 564         u64 ptc127;
 565         u64 ptc255;
 566         u64 ptc511;
 567         u64 ptc1023;
 568         u64 ptc1522;
 569         u64 mptc;
 570         u64 bptc;
 571         u64 tsctc;
 572         u64 tsctfc;
 573         u64 iac;
 574         u64 icrxptc;
 575         u64 icrxatc;
 576         u64 ictxptc;
 577         u64 ictxatc;
 578         u64 ictxqec;
 579         u64 ictxqmtc;
 580         u64 icrxdmtc;
 581         u64 icrxoc;
 582         u64 cbtmpc;
 583         u64 htdpmc;
 584         u64 cbrdpc;
 585         u64 cbrmpc;
 586         u64 rpthc;
 587         u64 hgptc;
 588         u64 htcbdpc;
 589         u64 hgorc;
 590         u64 hgotc;
 591         u64 lenerrs;
 592         u64 scvpc;
 593         u64 hrmpc;
 594         u64 doosync;
 595         u64 o2bgptc;
 596         u64 o2bspc;
 597         u64 b2ospc;
 598         u64 b2ogprc;
 599 };
 600
 601 struct e1000_vf_stats {
 602         u64 base_gprc;
 603         u64 base_gptc;
 604         u64 base_gorc;
 605         u64 base_gotc;
 606         u64 base_mprc;
 607         u64 base_gotlbc;
 608         u64 base_gptlbc;
 609         u64 base_gorlbc;
 610         u64 base_gprlbc;
 611
 612         u32 last_gprc;
 613         u32 last_gptc;
 614         u32 last_gorc;
 615         u32 last_gotc;
 616         u32 last_mprc;
 617         u32 last_gotlbc;
 618         u32 last_gptlbc;
 619         u32 last_gorlbc;
 620         u32 last_gprlbc;
 621
 622         u64 gprc;
 623         u64 gptc;
 624         u64 gorc;
 625         u64 gotc;
 626         u64 mprc;
 627         u64 gotlbc;
 628         u64 gptlbc;
 629         u64 gorlbc;
 630         u64 gprlbc;
 631 };
 632
 633 struct e1000_phy_stats {
 634         u32 idle_errors;
 635         u32 receive_errors;
 636 };
 637
 638 struct e1000_host_mng_dhcp_cookie {
 639         u32 signature;
 640         u8  status;
 641         u8  reserved0;
 642         u16 vlan_id;
 643         u32 reserved1;
 644         u16 reserved2;
 645         u8  reserved3;
 646         u8  checksum;
 647 };
 648
 649 /* Host Interface "Rev 1" */
 650 struct e1000_host_command_header {
 651         u8 command_id;
 652         u8 command_length;
 653         u8 command_options;
 654         u8 checksum;
 655 };
 656
 657 #define E1000_HI_MAX_DATA_LENGTH        252
 658 struct e1000_host_command_info {
 659         struct e1000_host_command_header command_header;
 660         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 661 };
 662
 663 /* Host Interface "Rev 2" */
 664 struct e1000_host_mng_command_header {
 665         u8  command_id;
 666         u8  checksum;
 667         u16 reserved1;
 668         u16 reserved2;
 669         u16 command_length;
 670 };
 671
 672 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 673 struct e1000_host_mng_command_info {
 674         struct e1000_host_mng_command_header command_header;
 675         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 676 };
 677
 678 #include "e1000_mac.h"
 679 #include "e1000_phy.h"
 680 #include "e1000_nvm.h"
 681 #include "e1000_manage.h"
 682 #include "e1000_mbx.h"
 683
 684 /* Function pointers for the MAC. */
 685 struct e1000_mac_operations {
 686         s32  (*init_params)(struct e1000_hw *);
 687         s32  (*id_led_init)(struct e1000_hw *);
 688         s32  (*blink_led)(struct e1000_hw *);
 689         bool (*check_mng_mode)(struct e1000_hw *);
 690         s32  (*check_for_link)(struct e1000_hw *);
 691         s32  (*cleanup_led)(struct e1000_hw *);
 692         void (*clear_hw_cntrs)(struct e1000_hw *);
 693         void (*clear_vfta)(struct e1000_hw *);
 694         s32  (*get_bus_info)(struct e1000_hw *);
 695         void (*set_lan_id)(struct e1000_hw *);
 696         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 697         s32  (*led_on)(struct e1000_hw *);
 698         s32  (*led_off)(struct e1000_hw *);
 699         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 700         s32  (*reset_hw)(struct e1000_hw *);
 701         s32  (*init_hw)(struct e1000_hw *);
 702         void (*shutdown_serdes)(struct e1000_hw *);
 703         void (*power_up_serdes)(struct e1000_hw *);
 704         s32  (*setup_link)(struct e1000_hw *);
 705         s32  (*setup_physical_interface)(struct e1000_hw *);
 706         s32  (*setup_led)(struct e1000_hw *);
 707         void (*write_vfta)(struct e1000_hw *, u32, u32);
 708         void (*config_collision_dist)(struct e1000_hw *);
 709         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 710         s32  (*read_mac_addr)(struct e1000_hw *);
 711         s32  (*validate_mdi_setting)(struct e1000_hw *);
 712         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 713         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 714         void (*release_swfw_sync)(struct e1000_hw *, u16);
 715 };
 716
 717 /* When to use various PHY register access functions:
 718  *
 719  *                 Func   Caller
 720  *   Function      Does   Does    When to use
 721  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 722  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 723  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 724  *                                on different pages
 725  *   X_reg_page    A      L,P     for multiple accesses of different regs
 726  *                                on the same page
 727  *
 728  * Where X=[read|write], L=locking, P=sets page, A=register access
 729  *
 730  */
 731 struct e1000_phy_operations {
 732         s32  (*init_params)(struct e1000_hw *);
 733         s32  (*acquire)(struct e1000_hw *);
 734         s32  (*cfg_on_link_up)(struct e1000_hw *);
 735         s32  (*check_polarity)(struct e1000_hw *);
 736         s32  (*check_reset_block)(struct e1000_hw *);
 737         s32  (*commit)(struct e1000_hw *);
 738         s32  (*force_speed_duplex)(struct e1000_hw *);
 739         s32  (*get_cfg_done)(struct e1000_hw *hw);
 740         s32  (*get_cable_length)(struct e1000_hw *);
 741         s32  (*get_info)(struct e1000_hw *);
 742         s32  (*set_page)(struct e1000_hw *, u16);
 743         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 744         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 745         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 746         void (*release)(struct e1000_hw *);
 747         s32  (*reset)(struct e1000_hw *);
 748         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 749         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 750         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 751         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 752         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 753         void (*power_up)(struct e1000_hw *);
 754         void (*power_down)(struct e1000_hw *);
 755         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 756         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 757 };
 758
 759 /* Function pointers for the NVM. */
 760 struct e1000_nvm_operations {
 761         s32  (*init_params)(struct e1000_hw *);
 762         s32  (*acquire)(struct e1000_hw *);
 763         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 764         void (*release)(struct e1000_hw *);
 765         void (*reload)(struct e1000_hw *);
 766         s32  (*update)(struct e1000_hw *);
 767         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 768         s32  (*validate)(struct e1000_hw *);
 769         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 770 };
 771
 772 struct e1000_mac_info {
 773         struct e1000_mac_operations ops;
 774         u8 addr[ETH_ADDR_LEN];
 775         u8 perm_addr[ETH_ADDR_LEN];
 776
 777         enum e1000_mac_type type;
 778
 779         u32 collision_delta;
 780         u32 ledctl_default;
 781         u32 ledctl_mode1;
 782         u32 ledctl_mode2;
 783         u32 mc_filter_type;
 784         u32 tx_packet_delta;
 785         u32 txcw;
 786
 787         u16 current_ifs_val;
 788         u16 ifs_max_val;
 789         u16 ifs_min_val;
 790         u16 ifs_ratio;
 791         u16 ifs_step_size;
 792         u16 mta_reg_count;
 793         u16 uta_reg_count;
 794
 795         /* Maximum size of the MTA register table in all supported adapters */
 796 #define MAX_MTA_REG 128
 797         u32 mta_shadow[MAX_MTA_REG];
 798         u16 rar_entry_count;
 799
 800         u8  forced_speed_duplex;
 801
 802         bool adaptive_ifs;
 803         bool has_fwsm;
 804         bool arc_subsystem_valid;
 805         bool asf_firmware_present;
 806         bool autoneg;
 807         bool autoneg_failed;
 808         bool get_link_status;
 809         bool in_ifs_mode;
 810         bool report_tx_early;
 811         enum e1000_serdes_link_state serdes_link_state;
 812         bool serdes_has_link;
 813         bool tx_pkt_filtering;
 814         u32  max_frame_size;
 815 };
 816
 817 struct e1000_phy_info {
 818         struct e1000_phy_operations ops;
 819         enum e1000_phy_type type;
 820
 821         enum e1000_1000t_rx_status local_rx;
 822         enum e1000_1000t_rx_status remote_rx;
 823         enum e1000_ms_type ms_type;
 824         enum e1000_ms_type original_ms_type;
 825         enum e1000_rev_polarity cable_polarity;
 826         enum e1000_smart_speed smart_speed;
 827
 828         u32 addr;
 829         u32 id;
 830         u32 reset_delay_us; /* in usec */
 831         u32 revision;
 832
 833         enum e1000_media_type media_type;
 834
 835         u16 autoneg_advertised;
 836         u16 autoneg_mask;
 837         u16 cable_length;
 838         u16 max_cable_length;
 839         u16 min_cable_length;
 840
 841         u8 mdix;
 842
 843         bool disable_polarity_correction;
 844         bool is_mdix;
 845         bool polarity_correction;
 846         bool speed_downgraded;
 847         bool autoneg_wait_to_complete;
 848 };
 849
 850 struct e1000_nvm_info {
 851         struct e1000_nvm_operations ops;
 852         enum e1000_nvm_type type;
 853         enum e1000_nvm_override override;
 854
 855         u32 flash_bank_size;
 856         u32 flash_base_addr;
 857
 858         u16 word_size;
 859         u16 delay_usec;
 860         u16 address_bits;
 861         u16 opcode_bits;
 862         u16 page_size;
 863 };
 864
 865 struct e1000_bus_info {
 866         enum e1000_bus_type type;
 867         enum e1000_bus_speed speed;
 868         enum e1000_bus_width width;
 869
 870         u16 func;
 871         u16 pci_cmd_word;
 872 };
 873
 874 struct e1000_fc_info {
 875         u32 high_water;  /* Flow control high-water mark */
 876         u32 low_water;  /* Flow control low-water mark */
 877         u16 pause_time;  /* Flow control pause timer */
 878         u16 refresh_time;  /* Flow control refresh timer */
 879         bool send_xon;  /* Flow control send XON */
 880         bool strict_ieee;  /* Strict IEEE mode */
 881         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 882         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 883 };
 884
 885 struct e1000_mbx_operations {
 886         s32 (*init_params)(struct e1000_hw *hw);
 887         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 888         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 889         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 890         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 891         s32 (*check_for_msg)(struct e1000_hw *, u16);
 892         s32 (*check_for_ack)(struct e1000_hw *, u16);
 893         s32 (*check_for_rst)(struct e1000_hw *, u16);
 894 };
 895
 896 struct e1000_mbx_stats {
 897         u32 msgs_tx;
 898         u32 msgs_rx;
 899
 900         u32 acks;
 901         u32 reqs;
 902         u32 rsts;
 903 };
 904
 905 struct e1000_mbx_info {
 906         struct e1000_mbx_operations ops;
 907         struct e1000_mbx_stats stats;
 908         u32 timeout;
 909         u32 usec_delay;
 910         u16 size;
 911 };
 912
 913 struct e1000_dev_spec_82541 {
 914         enum e1000_dsp_config dsp_config;
 915         enum e1000_ffe_config ffe_config;
 916         u16 spd_default;
 917         bool phy_init_script;
 918 };
 919
 920 struct e1000_dev_spec_82542 {
 921         bool dma_fairness;
 922 };
 923
 924 struct e1000_dev_spec_82543 {
 925         u32  tbi_compatibility;
 926         bool dma_fairness;
 927         bool init_phy_disabled;
 928 };
 929
 930 struct e1000_dev_spec_82571 {
 931         bool laa_is_present;
 932         u32 smb_counter;
 933         E1000_MUTEX swflag_mutex;
 934 };
 935
 936 struct e1000_dev_spec_80003es2lan {
 937         bool  mdic_wa_enable;
 938 };
 939
 940 struct e1000_shadow_ram {
 941         u16  value;
 942         bool modified;
 943 };
 944
 945 #define E1000_SHADOW_RAM_WORDS          2048
 946
 947 /* I218 PHY Ultra Low Power (ULP) states */
 948 enum e1000_ulp_state {
 949         e1000_ulp_state_unknown,
 950         e1000_ulp_state_off,
 951         e1000_ulp_state_on,
 952 };
 953
 954 struct e1000_dev_spec_ich8lan {
 955         bool kmrn_lock_loss_workaround_enabled;
 956         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 957         E1000_MUTEX nvm_mutex;
 958         E1000_MUTEX swflag_mutex;
 959         bool nvm_k1_enabled;
 960         bool eee_disable;
 961         u16 eee_lp_ability;
 962         enum e1000_ulp_state ulp_state;
 963 };
 964
 965 struct e1000_dev_spec_82575 {
 966         bool sgmii_active;
 967         bool global_device_reset;
 968         bool eee_disable;
 969         bool module_plugged;
 970         bool clear_semaphore_once;
 971         u32 mtu;
 972         struct sfp_e1000_flags eth_flags;
 973         u8 media_port;
 974         bool media_changed;
 975 };
 976
 977 struct e1000_dev_spec_vf {
 978         u32 vf_number;
 979         u32 v2p_mailbox;
 980 };
 981
 982 struct e1000_hw {
 983         void *back;
 984
 985         u8 *hw_addr;
 986         u8 *flash_address;
 987         unsigned long io_base;
 988
 989         struct e1000_mac_info  mac;
 990         struct e1000_fc_info   fc;
 991         struct e1000_phy_info  phy;
 992         struct e1000_nvm_info  nvm;
 993         struct e1000_bus_info  bus;
 994         struct e1000_mbx_info mbx;
 995         struct e1000_host_mng_dhcp_cookie mng_cookie;
 996
 997         union {
 998                 struct e1000_dev_spec_82541 _82541;
 999                 struct e1000_dev_spec_82542 _82542;
1000                 struct e1000_dev_spec_82543 _82543;
1001                 struct e1000_dev_spec_82571 _82571;
1002                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1003                 struct e1000_dev_spec_ich8lan ich8lan;
1004                 struct e1000_dev_spec_82575 _82575;
1005                 struct e1000_dev_spec_vf vf;
1006         } dev_spec;
1007
1008         u16 device_id;
1009         u16 subsystem_vendor_id;
1010         u16 subsystem_device_id;
1011         u16 vendor_id;
1012
1013         u8  revision_id;
1014 };
1015
1016 #include "e1000_82541.h"
1017 #include "e1000_82543.h"
1018 #include "e1000_82571.h"
1019 #include "e1000_80003es2lan.h"
1020 #include "e1000_ich8lan.h"
1021 #include "e1000_82575.h"
1022 #include "e1000_i210.h"
1023
1024 /* These functions must be implemented by drivers */
1025 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1026 void e1000_pci_set_mwi(struct e1000_hw *hw);
1027 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1028 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1029 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1030 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1031
1032 #endif