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32 ******************************************************************************/
36 #ifndef _EM_H_DEFINED_
37 #define _EM_H_DEFINED_
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
55 #define EM_MAX_TXD 4096
57 #define EM_DEFAULT_TXD 4096
59 #define EM_DEFAULT_TXD 1024
63 * EM_RXD - Maximum number of receive Descriptors
64 * Valid Range: 80-256 for 82542 and 82543-based adapters
67 * This value is the number of receive descriptors allocated by the driver.
68 * Increasing this value allows the driver to buffer more incoming packets.
69 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
70 * descriptor. The maximum MTU size is 16110.
71 * Since TDLEN should be multiple of 128bytes, the number of transmit
72 * desscriptors should meet the following condition.
73 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
76 #define EM_MAX_RXD 4096
78 #define EM_DEFAULT_RXD 4096
80 #define EM_DEFAULT_RXD 1024
84 * EM_TIDV - Transmit Interrupt Delay Value
85 * Valid Range: 0-65535 (0=off)
87 * This value delays the generation of transmit interrupts in units of
88 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
89 * efficiency if properly tuned for specific network traffic. If the
90 * system is reporting dropped transmits, this value may be set too high
91 * causing the driver to run out of available transmit descriptors.
96 * EM_TADV - Transmit Absolute Interrupt Delay Value
97 * (Not valid for 82542/82543/82544)
98 * Valid Range: 0-65535 (0=off)
100 * This value, in units of 1.024 microseconds, limits the delay in which a
101 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
102 * this value ensures that an interrupt is generated after the initial
103 * packet is sent on the wire within the set amount of time. Proper tuning,
104 * along with EM_TIDV, may improve traffic throughput in specific
105 * network conditions.
110 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
111 * Valid Range: 0-65535 (0=off)
113 * This value delays the generation of receive interrupts in units of 1.024
114 * microseconds. Receive interrupt reduction can improve CPU efficiency if
115 * properly tuned for specific network traffic. Increasing this value adds
116 * extra latency to frame reception and can end up decreasing the throughput
117 * of TCP traffic. If the system is reporting dropped receives, this value
118 * may be set too high, causing the driver to run out of available receive
121 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
122 * may hang (stop transmitting) under certain network conditions.
123 * If this occurs a WATCHDOG message is logged in the system
124 * event log. In addition, the controller is automatically reset,
125 * restoring the network connection. To eliminate the potential
126 * for the hang ensure that EM_RDTR is set to 0.
135 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
136 * Valid Range: 0-65535 (0=off)
138 * This value, in units of 1.024 microseconds, limits the delay in which a
139 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
140 * this value ensures that an interrupt is generated after the initial
141 * packet is received within the set amount of time. Proper tuning,
142 * along with EM_RDTR, may improve traffic throughput in specific network
152 * This parameter controls the max duration of transmit watchdog.
154 #define EM_WATCHDOG (10 * hz)
157 * This parameter controls when the driver calls the routine to reclaim
158 * transmit descriptors.
160 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
163 * This parameter controls whether or not autonegotation is enabled.
164 * 0 - Disable autonegotiation
165 * 1 - Enable autonegotiation
167 #define DO_AUTO_NEG 1
170 * This parameter control whether or not the driver will wait for
171 * autonegotiation to complete.
172 * 1 - Wait for autonegotiation to complete
173 * 0 - Don't wait for autonegotiation to complete
175 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
177 /* Tunables -- End */
179 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
180 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
183 #define AUTO_ALL_MODES 0
185 /* PHY master/slave setting */
186 #define EM_MASTER_SLAVE e1000_ms_hw_default
189 * Micellaneous constants
191 #define EM_VENDOR_ID 0x8086
192 #define EM_FLASH 0x0014
194 #define EM_JUMBO_PBA 0x00000028
195 #define EM_DEFAULT_PBA 0x00000030
196 #define EM_SMARTSPEED_DOWNSHIFT 3
197 #define EM_SMARTSPEED_MAX 15
198 #define EM_MAX_LOOP 10
200 #define MAX_NUM_MULTICAST_ADDRESSES 128
201 #define PCI_ANY_ID (~0U)
202 #define ETHER_ALIGN 2
203 #define EM_FC_PAUSE_TIME 0x0680
204 #define EM_EEPROM_APME 0x400;
205 #define EM_82544_APME 0x0004;
208 * Driver state logic for the detection of a hung state
209 * in hardware. Set TX_HUNG whenever a TX packet is used
210 * (data is sent) and clear it when txeof() is invoked if
211 * any descriptors from the ring are cleaned/reclaimed.
212 * Increment internal counter if no descriptors are cleaned
213 * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES,
216 #define EM_TX_IDLE 0x00000000
217 #define EM_TX_BUSY 0x00000001
218 #define EM_TX_HUNG 0x80000000
219 #define EM_TX_MAXTRIES 10
221 #define PCICFG_DESC_RING_STATUS 0xe4
222 #define FLUSH_DESC_REQUIRED 0x100
225 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
226 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
227 * also optimize cache line size effect. H/W supports up to cache line size 128.
229 #define EM_DBA_ALIGN 128
232 * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9
234 #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */
235 #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
236 #define TARC_MQ_FIX (1 << 23) | \
238 (1 << 25) /* Handle errata in MQ mode */
239 #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */
241 /* PCI Config defines */
242 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
243 #define EM_BAR_TYPE_MASK 0x00000001
244 #define EM_BAR_TYPE_MMEM 0x00000000
245 #define EM_BAR_TYPE_FLASH 0x0014
246 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
247 #define EM_BAR_MEM_TYPE_MASK 0x00000006
248 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
249 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
250 #define EM_MSIX_BAR 3 /* On 82575 */
252 /* More backward compatibility */
253 #if __FreeBSD_version < 900000
254 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
257 /* Defines for printing debug information */
259 #define DEBUG_IOCTL 0
262 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
263 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
264 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
265 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
266 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
267 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
268 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
269 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
270 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
272 #define EM_MAX_SCATTER 40
273 #define EM_VFTA_SIZE 128
274 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
275 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
276 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
277 #define EM_MSIX_LINK 0x01000000 /* For 82574 use */
279 #define ETH_ADDR_LEN 6
280 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
283 * 82574 has a nonstandard address for EIAC
284 * and since its only used in MSIX, and in
285 * the em driver only 82574 uses MSIX we can
286 * solve it just using this define.
288 #define EM_EIAC 0x000DC
290 * 82574 only reports 3 MSI-X vectors by default;
291 * defines assisting with making it report 5 are
294 #define EM_NVM_PCIE_CTRL 0x1B
295 #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT)
296 #define EM_NVM_MSIX_N_SHIFT 7
299 * Bus dma allocation structure used by
300 * e1000_dma_malloc and e1000_dma_free.
302 struct em_dma_alloc {
303 bus_addr_t dma_paddr;
305 bus_dma_tag_t dma_tag;
306 bus_dmamap_t dma_map;
307 bus_dma_segment_t dma_seg;
313 struct em_int_delay_info {
314 struct adapter *adapter; /* Back-pointer to the adapter struct */
315 int offset; /* Register offset to read/write */
316 int value; /* Current value in usecs */
320 * The transmit ring, one per tx queue
323 struct adapter *adapter;
330 struct em_dma_alloc txdma;
331 struct e1000_tx_desc *tx_base;
333 struct taskqueue *tq;
336 struct em_txbuffer *tx_buffers;
337 volatile u16 tx_avail;
338 u32 tx_tso; /* last tx was tso */
344 #if __FreeBSD_version >= 800000
347 /* Interrupt resources */
350 struct resource *res;
351 unsigned long tx_irq;
352 unsigned long no_desc_avail;
356 * The Receive ring, one per rx queue
359 struct adapter *adapter;
367 struct taskqueue *tq;
368 union e1000_rx_desc_extended *rx_base;
369 struct em_dma_alloc rxdma;
372 struct em_rxbuffer *rx_buffers;
376 /* Interrupt resources */
378 struct resource *res;
383 unsigned long rx_irq;
384 unsigned long rx_discarded;
385 unsigned long rx_packets;
386 unsigned long rx_bytes;
390 /* Our adapter structure */
395 /* FreeBSD operating-system-specific structures. */
396 struct e1000_osdep osdep;
398 struct cdev *led_dev;
400 struct resource *memory;
401 struct resource *flash;
402 struct resource *msix_mem;
404 struct resource *res;
409 struct ifmedia media;
410 struct callout timer;
416 int em_insert_vlan_header;
420 /* Task for FAST handling */
421 struct task link_task;
422 struct task que_task;
423 struct taskqueue *tq; /* private task queue */
425 eventhandler_tag vlan_attach;
426 eventhandler_tag vlan_detach;
433 * Allocated at run time, an array of rings.
435 struct tx_ring *tx_rings;
441 * Allocated at run time, an array of rings.
443 struct rx_ring *rx_rings;
445 u32 rx_process_limit;
448 /* Management and WOL features */
453 /* Multicast array memory */
457 ** Shadow VFTA table, this is needed because
458 ** the real vlan filter table gets cleared during
459 ** a soft reset and the driver needs to be able
462 u32 shadow_vfta[EM_VFTA_SIZE];
464 /* Info about the interface */
471 struct em_int_delay_info tx_int_delay;
472 struct em_int_delay_info tx_abs_int_delay;
473 struct em_int_delay_info rx_int_delay;
474 struct em_int_delay_info rx_abs_int_delay;
475 struct em_int_delay_info tx_itr;
477 /* Misc stats maintained by the driver */
478 unsigned long dropped_pkts;
479 unsigned long link_irq;
480 unsigned long mbuf_defrag_failed;
481 unsigned long no_tx_dma_setup;
482 unsigned long no_tx_map_avail;
483 unsigned long rx_overruns;
484 unsigned long watchdog_events;
486 struct e1000_hw_stats stats;
489 /********************************************************************************
492 * This array contains the list of Subvendor/Subdevice IDs on which the driver
495 ********************************************************************************/
496 typedef struct _em_vendor_info_t {
497 unsigned int vendor_id;
498 unsigned int device_id;
499 unsigned int subvendor_id;
500 unsigned int subdevice_id;
505 int next_eop; /* Index of the desc to watch */
507 bus_dmamap_t map; /* bus_dma map for packet */
511 int next_eop; /* Index of the desc to watch */
513 bus_dmamap_t map; /* bus_dma map for packet */
519 ** Find the number of unrefreshed RX descriptors
522 e1000_rx_unrefreshed(struct rx_ring *rxr)
524 struct adapter *adapter = rxr->adapter;
526 if (rxr->next_to_check > rxr->next_to_refresh)
527 return (rxr->next_to_check - rxr->next_to_refresh - 1);
529 return ((adapter->num_rx_desc + rxr->next_to_check) -
530 rxr->next_to_refresh - 1);
533 #define EM_CORE_LOCK_INIT(_sc, _name) \
534 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
535 #define EM_TX_LOCK_INIT(_sc, _name) \
536 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
537 #define EM_RX_LOCK_INIT(_sc, _name) \
538 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
539 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
540 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
541 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
542 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
543 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
544 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
545 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
546 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
547 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
548 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
549 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
550 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
551 #define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED)
553 #define EM_RSSRK_SIZE 4
554 #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \
555 key[(i) * EM_RSSRK_SIZE + 1] << 8 | \
556 key[(i) * EM_RSSRK_SIZE + 2] << 16 | \
557 key[(i) * EM_RSSRK_SIZE + 3] << 24)
558 #endif /* _EM_H_DEFINED_ */