1 /******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
36 #ifndef _LEM_H_DEFINED_
37 #define _LEM_H_DEFINED_
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
55 #define EM_MAX_TXD_82543 256
56 #define EM_MAX_TXD 4096
57 #define EM_DEFAULT_TXD EM_MAX_TXD_82543
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
73 #define EM_MAX_RXD_82543 256
74 #define EM_MAX_RXD 4096
75 #define EM_DEFAULT_RXD EM_MAX_RXD_82543
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
81 * This value delays the generation of transmit interrupts in units of
82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
83 * efficiency if properly tuned for specific network traffic. If the
84 * system is reporting dropped transmits, this value may be set too high
85 * causing the driver to run out of available transmit descriptors.
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
105 * Valid Range: 0-65535 (0=off)
107 * This value delays the generation of receive interrupts in units of 1.024
108 * microseconds. Receive interrupt reduction can improve CPU efficiency if
109 * properly tuned for specific network traffic. Increasing this value adds
110 * extra latency to frame reception and can end up decreasing the throughput
111 * of TCP traffic. If the system is reporting dropped receives, this value
112 * may be set too high, causing the driver to run out of available receive
115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
116 * may hang (stop transmitting) under certain network conditions.
117 * If this occurs a WATCHDOG message is logged in the system
118 * event log. In addition, the controller is automatically reset,
119 * restoring the network connection. To eliminate the potential
120 * for the hang ensure that EM_RDTR is set to 0.
125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
126 * Valid Range: 0-65535 (0=off)
128 * This value, in units of 1.024 microseconds, limits the delay in which a
129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
130 * this value ensures that an interrupt is generated after the initial
131 * packet is received within the set amount of time. Proper tuning,
132 * along with EM_RDTR, may improve traffic throughput in specific network
138 * This parameter controls the max duration of transmit watchdog.
140 #define EM_WATCHDOG (10 * hz)
143 * This parameter controls when the driver calls the routine to reclaim
144 * transmit descriptors.
146 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
147 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
150 * This parameter controls whether or not autonegotation is enabled.
151 * 0 - Disable autonegotiation
152 * 1 - Enable autonegotiation
154 #define DO_AUTO_NEG 1
157 * This parameter control whether or not the driver will wait for
158 * autonegotiation to complete.
159 * 1 - Wait for autonegotiation to complete
160 * 0 - Don't wait for autonegotiation to complete
162 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
164 /* Tunables -- End */
166 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
167 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
170 #define AUTO_ALL_MODES 0
172 /* PHY master/slave setting */
173 #define EM_MASTER_SLAVE e1000_ms_hw_default
176 * Micellaneous constants
178 #define EM_VENDOR_ID 0x8086
179 #define EM_FLASH 0x0014
181 #define EM_JUMBO_PBA 0x00000028
182 #define EM_DEFAULT_PBA 0x00000030
183 #define EM_SMARTSPEED_DOWNSHIFT 3
184 #define EM_SMARTSPEED_MAX 15
185 #define EM_MAX_LOOP 10
187 #define MAX_NUM_MULTICAST_ADDRESSES 128
188 #define PCI_ANY_ID (~0U)
189 #define ETHER_ALIGN 2
190 #define EM_FC_PAUSE_TIME 0x0680
191 #define EM_EEPROM_APME 0x400;
192 #define EM_82544_APME 0x0004;
194 /* Code compatilbility between 6 and 7 */
195 #ifndef ETHER_BPF_MTAP
196 #define ETHER_BPF_MTAP BPF_MTAP
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
204 #define EM_DBA_ALIGN 128
206 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
208 /* PCI Config defines */
209 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210 #define EM_BAR_TYPE_MASK 0x00000001
211 #define EM_BAR_TYPE_MMEM 0x00000000
212 #define EM_BAR_TYPE_IO 0x00000001
213 #define EM_BAR_TYPE_FLASH 0x0014
214 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
215 #define EM_BAR_MEM_TYPE_MASK 0x00000006
216 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
217 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
218 #define EM_MSIX_BAR 3 /* On 82575 */
220 #if __FreeBSD_version < 900000
221 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
224 /* Defines for printing debug information */
226 #define DEBUG_IOCTL 0
229 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
230 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
231 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
232 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
233 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
234 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
235 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
236 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
237 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
239 #define EM_MAX_SCATTER 40
240 #define EM_VFTA_SIZE 128
241 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
243 #define ETH_ADDR_LEN 6
244 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
247 * 82574 has a nonstandard address for EIAC
248 * and since its only used in MSIX, and in
249 * the em driver only 82574 uses MSIX we can
250 * solve it just using this define.
252 #define EM_EIAC 0x000DC
254 /* Used in for 82547 10Mb Half workaround */
255 #define EM_PBA_BYTES_SHIFT 0xA
256 #define EM_TX_HEAD_ADDR_SHIFT 7
257 #define EM_PBA_TX_MASK 0xFFFF0000
258 #define EM_FIFO_HDR 0x10
259 #define EM_82547_PKT_THRESH 0x3e0
261 /* Precision Time Sync (IEEE 1588) defines */
262 #define ETHERTYPE_IEEE1588 0x88F7
263 #define PICOSECS_PER_TICK 20833
264 #define TSYNC_PORT 319 /* UDP port for the protocol */
267 #define E1000_PARA_SUBDEV 0x1101 /* special id */
268 #define E1000_CSBAL 0x02830 /* csb phys. addr. low */
269 #define E1000_CSBAH 0x02834 /* csb phys. addr. hi */
270 #include <net/paravirt.h>
271 #endif /* NIC_PARAVIRT */
274 * Bus dma allocation structure used by
275 * e1000_dma_malloc and e1000_dma_free.
277 struct em_dma_alloc {
278 bus_addr_t dma_paddr;
280 bus_dma_tag_t dma_tag;
281 bus_dmamap_t dma_map;
282 bus_dma_segment_t dma_seg;
288 struct em_int_delay_info {
289 struct adapter *adapter; /* Back-pointer to the adapter struct */
290 int offset; /* Register offset to read/write */
291 int value; /* Current value in usecs */
294 /* Our adapter structure */
299 /* FreeBSD operating-system-specific structures. */
300 struct e1000_osdep osdep;
302 struct cdev *led_dev;
304 struct resource *memory;
305 struct resource *flash;
306 struct resource *msix;
308 struct resource *ioport;
311 /* 82574 may use 3 int vectors */
312 struct resource *res[3];
316 struct ifmedia media;
317 struct callout timer;
318 struct callout tx_fifo_timer;
328 int em_insert_vlan_header;
330 /* Task for FAST handling */
331 struct task link_task;
332 struct task rxtx_task;
335 struct taskqueue *tq; /* private task queue */
337 eventhandler_tag vlan_attach;
338 eventhandler_tag vlan_detach;
341 /* Management and WOL features */
346 /* Multicast array memory */
350 ** Shadow VFTA table, this is needed because
351 ** the real vlan filter table gets cleared during
352 ** a soft reset and the driver needs to be able
355 u32 shadow_vfta[EM_VFTA_SIZE];
357 /* Info about the interface */
360 uint16_t link_duplex;
364 struct em_int_delay_info tx_int_delay;
365 struct em_int_delay_info tx_abs_int_delay;
366 struct em_int_delay_info rx_int_delay;
367 struct em_int_delay_info rx_abs_int_delay;
368 struct em_int_delay_info tx_itr;
371 * Transmit definitions
373 * We have an array of num_tx_desc descriptors (handled
374 * by the controller) paired with an array of tx_buffers
375 * (at tx_buffer_area).
376 * The index of the next available descriptor is next_avail_tx_desc.
377 * The number of remaining tx_desc is num_tx_desc_avail.
379 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
380 struct e1000_tx_desc *tx_desc_base;
381 uint32_t next_avail_tx_desc;
382 uint32_t next_tx_to_clean;
383 volatile uint16_t num_tx_desc_avail;
384 uint16_t num_tx_desc;
385 uint16_t last_hw_offload;
387 struct em_buffer *tx_buffer_area;
388 bus_dma_tag_t txtag; /* dma tag for tx */
389 uint32_t tx_tso; /* last tx was tso */
392 * Receive definitions
394 * we have an array of num_rx_desc rx_desc (handled by the
395 * controller), and paired with an array of rx_buffers
396 * (at rx_buffer_area).
397 * The next pair to check on receive is at offset next_rx_desc_to_check
399 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
400 struct e1000_rx_desc *rx_desc_base;
401 uint32_t next_rx_desc_to_check;
402 uint32_t rx_buffer_len;
403 uint16_t num_rx_desc;
404 int rx_process_limit;
405 struct em_buffer *rx_buffer_area;
407 bus_dmamap_t rx_sparemap;
410 * First/last mbuf pointers, for
411 * collecting multisegment RX packets.
416 /* Misc stats maintained by the driver */
417 unsigned long dropped_pkts;
418 unsigned long link_irq;
419 unsigned long mbuf_cluster_failed;
420 unsigned long mbuf_defrag_failed;
421 unsigned long no_tx_desc_avail1;
422 unsigned long no_tx_desc_avail2;
423 unsigned long no_tx_dma_setup;
424 unsigned long no_tx_map_avail;
425 unsigned long watchdog_events;
426 unsigned long rx_irq;
427 unsigned long rx_overruns;
428 unsigned long tx_irq;
430 /* 82547 workaround */
431 uint32_t tx_fifo_size;
432 uint32_t tx_fifo_head;
433 uint32_t tx_fifo_head_addr;
434 uint64_t tx_fifo_reset_cnt;
435 uint64_t tx_fifo_wrk_cnt;
436 uint32_t tx_head_addr;
438 /* For 82544 PCIX Workaround */
439 boolean_t pcix_82544;
442 #ifdef NIC_SEND_COMBINING
443 /* 0 = idle; 1xxxx int-pending; 3xxxx int + d pending + tdt */
444 #define MIT_PENDING_INT 0x10000 /* pending interrupt */
445 #define MIT_PENDING_TDT 0x30000 /* both intr and tdt write are pending */
448 #endif /* NIC_SEND_COMBINING */
449 #ifdef BATCH_DISPATCH
450 uint32_t batch_enable;
451 #endif /* BATCH_DISPATCH */
454 struct em_dma_alloc csb_mem; /* phys address */
455 struct paravirt_csb *csb; /* virtual addr */
456 uint32_t rx_retries; /* optimize rx loop */
457 uint32_t tdt_csb_count;// XXX stat
458 uint32_t tdt_reg_count;// XXX stat
459 uint32_t tdt_int_count;// XXX stat
460 uint32_t guest_need_kick_count;// XXX stat
461 #endif /* NIC_PARAVIRT */
463 struct e1000_hw_stats stats;
466 /* ******************************************************************************
469 * This array contains the list of Subvendor/Subdevice IDs on which the driver
472 * ******************************************************************************/
473 typedef struct _em_vendor_info_t {
474 unsigned int vendor_id;
475 unsigned int device_id;
476 unsigned int subvendor_id;
477 unsigned int subdevice_id;
482 int next_eop; /* Index of the desc to watch */
484 bus_dmamap_t map; /* bus_dma map for packet */
487 /* For 82544 PCIX Workaround */
488 typedef struct _ADDRESS_LENGTH_PAIR
492 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
494 typedef struct _DESCRIPTOR_PAIR
496 ADDRESS_LENGTH_PAIR descriptor[4];
498 } DESC_ARRAY, *PDESC_ARRAY;
500 #define EM_CORE_LOCK_INIT(_sc, _name) \
501 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
502 #define EM_TX_LOCK_INIT(_sc, _name) \
503 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
504 #define EM_RX_LOCK_INIT(_sc, _name) \
505 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
506 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
507 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
508 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
509 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
510 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
511 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
512 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
513 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
514 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
515 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
516 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
517 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
519 #endif /* _LEM_H_DEFINED_ */