2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Common code for handling Intel CPUs.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/pmckern.h>
37 #include <sys/systm.h>
39 #include <machine/cpu.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
49 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
52 /* allow the RDPMC instruction if needed */
53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
54 load_cr4(rcr4() | CR4_PCE);
56 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
65 (void) pp; /* can be NULL */
67 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
70 /* always turn off the RDPMC instruction */
71 load_cr4(rcr4() & ~CR4_PCE);
77 pmc_intel_initialize(void)
79 struct pmc_mdep *pmc_mdep;
80 enum pmc_cputype cputype;
81 int error, model, nclasses, ncpus;
83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
84 ("[intel,%d] Initializing non-intel processor", __LINE__));
86 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
91 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
93 switch (cpu_id & 0xF00) {
95 case 0x500: /* Pentium family processors */
96 cputype = PMC_CPU_INTEL_P5;
99 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
101 #if defined(__i386__)
103 cputype = PMC_CPU_INTEL_P6;
106 cputype = PMC_CPU_INTEL_PII;
109 cputype = PMC_CPU_INTEL_CL;
111 case 0x7: case 0x8: case 0xA: case 0xB:
112 cputype = PMC_CPU_INTEL_PIII;
115 cputype = PMC_CPU_INTEL_PM;
119 cputype = PMC_CPU_INTEL_CORE;
122 cputype = PMC_CPU_INTEL_CORE2;
126 cputype = PMC_CPU_INTEL_CORE2EXTREME;
129 case 0x1C: /* Per Intel document 320047-002. */
130 cputype = PMC_CPU_INTEL_ATOM;
135 * Per Intel document 253669-032 9/2009,
139 * Per Intel document 253669-032 9/2009,
142 cputype = PMC_CPU_INTEL_COREI7;
146 cputype = PMC_CPU_INTEL_NEHALEM_EX;
149 case 0x25: /* Per Intel document 253669-033US 12/2009. */
150 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
151 cputype = PMC_CPU_INTEL_WESTMERE;
154 case 0x2F: /* Westmere-EX, seen in wild */
155 cputype = PMC_CPU_INTEL_WESTMERE_EX;
158 case 0x2A: /* Per Intel document 253669-039US 05/2011. */
159 cputype = PMC_CPU_INTEL_SANDYBRIDGE;
162 case 0x2D: /* Per Intel document 253669-044US 08/2012. */
163 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
166 case 0x3A: /* Per Intel document 253669-043US 05/2012. */
167 cputype = PMC_CPU_INTEL_IVYBRIDGE;
170 case 0x3E: /* Per Intel document 325462-045US 01/2013. */
171 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
174 case 0x3F: /* Per Intel document 325462-045US 09/2014. */
175 case 0x46: /* Per Intel document 325462-045US 09/2014. */
176 /* Should 46 be XEON. probably its own? */
177 cputype = PMC_CPU_INTEL_HASWELL_XEON;
180 case 0x3C: /* Per Intel document 325462-045US 01/2013. */
181 case 0x45: /* Per Intel document 325462-045US 09/2014. */
182 cputype = PMC_CPU_INTEL_HASWELL;
185 case 0x4D: /* Per Intel document 330061-001 01/2014. */
186 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
191 #if defined(__i386__) || defined(__amd64__)
193 if (model >= 0 && model <= 6) /* known models */
194 cputype = PMC_CPU_INTEL_PIV;
199 if ((int) cputype == -1) {
200 printf("pmc: Unknown Intel CPU.\n");
204 /* Allocate base class and initialize machine dependent struct */
205 pmc_mdep = pmc_mdep_alloc(nclasses);
207 pmc_mdep->pmd_cputype = cputype;
208 pmc_mdep->pmd_switch_in = intel_switch_in;
209 pmc_mdep->pmd_switch_out = intel_switch_out;
211 ncpus = pmc_cpu_max();
212 error = pmc_tsc_initialize(pmc_mdep, ncpus);
216 #if defined(__i386__) || defined(__amd64__)
218 * Intel Core, Core 2 and Atom processors.
220 case PMC_CPU_INTEL_ATOM:
221 case PMC_CPU_INTEL_ATOM_SILVERMONT:
222 case PMC_CPU_INTEL_CORE:
223 case PMC_CPU_INTEL_CORE2:
224 case PMC_CPU_INTEL_CORE2EXTREME:
225 case PMC_CPU_INTEL_COREI7:
226 case PMC_CPU_INTEL_NEHALEM_EX:
227 case PMC_CPU_INTEL_IVYBRIDGE:
228 case PMC_CPU_INTEL_SANDYBRIDGE:
229 case PMC_CPU_INTEL_WESTMERE:
230 case PMC_CPU_INTEL_WESTMERE_EX:
231 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
232 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
233 case PMC_CPU_INTEL_HASWELL:
234 case PMC_CPU_INTEL_HASWELL_XEON:
235 error = pmc_core_initialize(pmc_mdep, ncpus);
239 * Intel Pentium 4 Processors, and P4/EMT64 processors.
242 case PMC_CPU_INTEL_PIV:
243 error = pmc_p4_initialize(pmc_mdep, ncpus);
247 #if defined(__i386__)
249 * P6 Family Processors
252 case PMC_CPU_INTEL_P6:
253 case PMC_CPU_INTEL_CL:
254 case PMC_CPU_INTEL_PII:
255 case PMC_CPU_INTEL_PIII:
256 case PMC_CPU_INTEL_PM:
257 error = pmc_p6_initialize(pmc_mdep, ncpus);
261 * Intel Pentium PMCs.
264 case PMC_CPU_INTEL_P5:
265 error = pmc_p5_initialize(pmc_mdep, ncpus);
270 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
274 pmc_tsc_finalize(pmc_mdep);
279 * Init the uncore class.
281 #if defined(__i386__) || defined(__amd64__)
284 * Intel Corei7 and Westmere processors.
286 case PMC_CPU_INTEL_COREI7:
287 case PMC_CPU_INTEL_HASWELL:
288 case PMC_CPU_INTEL_SANDYBRIDGE:
289 case PMC_CPU_INTEL_WESTMERE:
290 error = pmc_uncore_initialize(pmc_mdep, ncpus);
298 pmc_mdep_free(pmc_mdep);
306 pmc_intel_finalize(struct pmc_mdep *md)
308 pmc_tsc_finalize(md);
310 switch (md->pmd_cputype) {
311 #if defined(__i386__) || defined(__amd64__)
312 case PMC_CPU_INTEL_ATOM:
313 case PMC_CPU_INTEL_ATOM_SILVERMONT:
314 case PMC_CPU_INTEL_CORE:
315 case PMC_CPU_INTEL_CORE2:
316 case PMC_CPU_INTEL_CORE2EXTREME:
317 case PMC_CPU_INTEL_COREI7:
318 case PMC_CPU_INTEL_NEHALEM_EX:
319 case PMC_CPU_INTEL_HASWELL:
320 case PMC_CPU_INTEL_HASWELL_XEON:
321 case PMC_CPU_INTEL_IVYBRIDGE:
322 case PMC_CPU_INTEL_SANDYBRIDGE:
323 case PMC_CPU_INTEL_WESTMERE:
324 case PMC_CPU_INTEL_WESTMERE_EX:
325 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
326 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
327 pmc_core_finalize(md);
330 case PMC_CPU_INTEL_PIV:
334 #if defined(__i386__)
335 case PMC_CPU_INTEL_P6:
336 case PMC_CPU_INTEL_CL:
337 case PMC_CPU_INTEL_PII:
338 case PMC_CPU_INTEL_PIII:
339 case PMC_CPU_INTEL_PM:
342 case PMC_CPU_INTEL_P5:
347 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
353 #if defined(__i386__) || defined(__amd64__)
354 switch (md->pmd_cputype) {
355 case PMC_CPU_INTEL_COREI7:
356 case PMC_CPU_INTEL_HASWELL:
357 case PMC_CPU_INTEL_SANDYBRIDGE:
358 case PMC_CPU_INTEL_WESTMERE:
359 pmc_uncore_finalize(md);