3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
48 #include <net/if_arp.h>
49 #include <net/if_media.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
55 #include <dev/mii/rgephyreg.h>
57 #include "miibus_if.h"
59 #include <machine/bus.h>
60 #include <dev/rl/if_rlreg.h>
62 static int rgephy_probe(device_t);
63 static int rgephy_attach(device_t);
65 static device_method_t rgephy_methods[] = {
66 /* device interface */
67 DEVMETHOD(device_probe, rgephy_probe),
68 DEVMETHOD(device_attach, rgephy_attach),
69 DEVMETHOD(device_detach, mii_phy_detach),
70 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 static devclass_t rgephy_devclass;
76 static driver_t rgephy_driver = {
79 sizeof(struct mii_softc)
82 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
84 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
85 static void rgephy_status(struct mii_softc *);
86 static int rgephy_mii_phy_auto(struct mii_softc *, int);
87 static void rgephy_reset(struct mii_softc *);
88 static int rgephy_linkup(struct mii_softc *);
89 static void rgephy_loop(struct mii_softc *);
90 static void rgephy_load_dspcode(struct mii_softc *);
92 static const struct mii_phydesc rgephys[] = {
93 MII_PHY_DESC(REALTEK, RTL8169S),
94 MII_PHY_DESC(REALTEK, RTL8251),
98 static const struct mii_phy_funcs rgephy_funcs = {
105 rgephy_probe(device_t dev)
108 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
112 rgephy_attach(device_t dev)
114 struct mii_softc *sc;
115 struct mii_attach_args *ma;
118 sc = device_get_softc(dev);
119 ma = device_get_ivars(dev);
121 if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0)
122 flags |= MIIF_PHYPRIV0;
123 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0);
125 /* RTL8169S do not report auto-sense; add manually. */
126 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
128 if (sc->mii_capabilities & BMSR_EXTSTAT)
129 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
130 device_printf(dev, " ");
131 mii_phy_add_media(sc);
134 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with
135 * manual configuration, which is used to work around issues with
136 * certain setups by default, should not be triggered as it may in
137 * turn cause harm in some edge cases.
139 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0;
143 MIIBUS_MEDIAINIT(sc->mii_dev);
148 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
150 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
151 int speed, gig, anar;
159 * If the interface is not up, don't do anything.
161 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
164 PHY_RESET(sc); /* XXX hardware bug work-around */
166 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
167 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
168 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
169 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
171 switch (IFM_SUBTYPE(ife->ifm_media)) {
175 * If we're already in auto mode, just return.
177 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
180 (void)rgephy_mii_phy_auto(sc, ife->ifm_media);
183 speed = RGEPHY_S1000;
187 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
191 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
193 if ((ife->ifm_media & IFM_FLOW) != 0 &&
194 (mii->mii_media.ifm_media & IFM_FLAG0) != 0)
197 if ((ife->ifm_media & IFM_FDX) != 0) {
198 speed |= RGEPHY_BMCR_FDX;
199 gig = RGEPHY_1000CTL_AFD;
200 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
201 if ((ife->ifm_media & IFM_FLOW) != 0 ||
202 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
204 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
206 gig = RGEPHY_1000CTL_AHD;
208 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
210 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
211 gig |= RGEPHY_1000CTL_MSE;
212 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
213 gig |= RGEPHY_1000CTL_MSC;
216 anar &= ~RGEPHY_ANAR_ASP;
218 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0)
220 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG;
222 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
223 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
224 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
227 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
236 * Is the interface even up?
238 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
242 * Only used for autonegotiation.
244 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
250 * Check to see if we have link. If we do, we don't
251 * need to restart the autonegotiation process.
253 if (rgephy_linkup(sc) != 0) {
258 /* Announce link loss right after it happens. */
259 if (sc->mii_ticks++ == 0)
262 /* Only retry autonegotiation every mii_anegticks seconds. */
263 if (sc->mii_ticks <= sc->mii_anegticks)
267 rgephy_mii_phy_auto(sc, ife->ifm_media);
271 /* Update the media status. */
275 * Callback if something changed. Note that we need to poke
276 * the DSP on the RealTek PHYs if the media changes.
279 if (sc->mii_media_active != mii->mii_media_active ||
280 sc->mii_media_status != mii->mii_media_status ||
281 cmd == MII_MEDIACHG) {
282 rgephy_load_dspcode(sc);
284 mii_phy_update(sc, cmd);
289 rgephy_linkup(struct mii_softc *sc)
295 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
296 sc->mii_mpd_rev >= RGEPHY_8211B) {
297 if (sc->mii_mpd_rev == RGEPHY_8211F) {
298 reg = PHY_READ(sc, RGEPHY_F_MII_SSR);
299 if (reg & RGEPHY_F_SSR_LINK)
302 reg = PHY_READ(sc, RGEPHY_MII_SSR);
303 if (reg & RGEPHY_SSR_LINK)
307 reg = PHY_READ(sc, RL_GMEDIASTAT);
308 if (reg & RL_GMEDIASTAT_LINK)
316 rgephy_status(struct mii_softc *sc)
318 struct mii_data *mii = sc->mii_pdata;
322 mii->mii_media_status = IFM_AVALID;
323 mii->mii_media_active = IFM_ETHER;
325 if (rgephy_linkup(sc) != 0)
326 mii->mii_media_status |= IFM_ACTIVE;
328 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
329 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
330 if (bmcr & RGEPHY_BMCR_ISO) {
331 mii->mii_media_active |= IFM_NONE;
332 mii->mii_media_status = 0;
336 if (bmcr & RGEPHY_BMCR_LOOP)
337 mii->mii_media_active |= IFM_LOOP;
339 if (bmcr & RGEPHY_BMCR_AUTOEN) {
340 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
341 /* Erg, still trying, I guess... */
342 mii->mii_media_active |= IFM_NONE;
347 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
348 sc->mii_mpd_rev >= RGEPHY_8211B) {
349 if (sc->mii_mpd_rev == RGEPHY_8211F) {
350 ssr = PHY_READ(sc, RGEPHY_F_MII_SSR);
351 switch (ssr & RGEPHY_F_SSR_SPD_MASK) {
352 case RGEPHY_F_SSR_S1000:
353 mii->mii_media_active |= IFM_1000_T;
355 case RGEPHY_F_SSR_S100:
356 mii->mii_media_active |= IFM_100_TX;
358 case RGEPHY_F_SSR_S10:
359 mii->mii_media_active |= IFM_10_T;
362 mii->mii_media_active |= IFM_NONE;
365 if (ssr & RGEPHY_F_SSR_FDX)
366 mii->mii_media_active |= IFM_FDX;
368 mii->mii_media_active |= IFM_HDX;
371 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
372 switch (ssr & RGEPHY_SSR_SPD_MASK) {
373 case RGEPHY_SSR_S1000:
374 mii->mii_media_active |= IFM_1000_T;
376 case RGEPHY_SSR_S100:
377 mii->mii_media_active |= IFM_100_TX;
380 mii->mii_media_active |= IFM_10_T;
383 mii->mii_media_active |= IFM_NONE;
386 if (ssr & RGEPHY_SSR_FDX)
387 mii->mii_media_active |= IFM_FDX;
389 mii->mii_media_active |= IFM_HDX;
392 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
393 if (bmsr & RL_GMEDIASTAT_1000MBPS)
394 mii->mii_media_active |= IFM_1000_T;
395 else if (bmsr & RL_GMEDIASTAT_100MBPS)
396 mii->mii_media_active |= IFM_100_TX;
397 else if (bmsr & RL_GMEDIASTAT_10MBPS)
398 mii->mii_media_active |= IFM_10_T;
400 mii->mii_media_active |= IFM_NONE;
401 if (bmsr & RL_GMEDIASTAT_FDX)
402 mii->mii_media_active |= IFM_FDX;
404 mii->mii_media_active |= IFM_HDX;
407 if ((mii->mii_media_active & IFM_FDX) != 0)
408 mii->mii_media_active |= mii_phy_flowstatus(sc);
410 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
411 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
412 mii->mii_media_active |= IFM_ETH_MASTER;
416 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
423 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
424 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
425 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
426 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
428 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
429 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
431 PHY_WRITE(sc, RGEPHY_MII_BMCR,
432 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
435 return (EJUSTRETURN);
439 rgephy_loop(struct mii_softc *sc)
443 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
444 sc->mii_mpd_rev < RGEPHY_8211B) {
445 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
449 for (i = 0; i < 15000; i++) {
450 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
452 device_printf(sc->mii_dev, "looped %d\n", i);
460 #define PHY_SETBIT(x, y, z) \
461 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
462 #define PHY_CLRBIT(x, y, z) \
463 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
466 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
467 * existing revisions of the 8169S/8110S chips need to be tuned in
468 * order to reliably negotiate a 1000Mbps link. This is only needed
469 * for rev 0 and rev 1 of the PHY. Later versions work without
473 rgephy_load_dspcode(struct mii_softc *sc)
477 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 ||
478 sc->mii_mpd_rev >= RGEPHY_8211B)
481 PHY_WRITE(sc, 31, 0x0001);
482 PHY_WRITE(sc, 21, 0x1000);
483 PHY_WRITE(sc, 24, 0x65C7);
484 PHY_CLRBIT(sc, 4, 0x0800);
485 val = PHY_READ(sc, 4) & 0xFFF;
486 PHY_WRITE(sc, 4, val);
487 PHY_WRITE(sc, 3, 0x00A1);
488 PHY_WRITE(sc, 2, 0x0008);
489 PHY_WRITE(sc, 1, 0x1020);
490 PHY_WRITE(sc, 0, 0x1000);
491 PHY_SETBIT(sc, 4, 0x0800);
492 PHY_CLRBIT(sc, 4, 0x0800);
493 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
494 PHY_WRITE(sc, 4, val);
495 PHY_WRITE(sc, 3, 0xFF41);
496 PHY_WRITE(sc, 2, 0xDE60);
497 PHY_WRITE(sc, 1, 0x0140);
498 PHY_WRITE(sc, 0, 0x0077);
499 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
500 PHY_WRITE(sc, 4, val);
501 PHY_WRITE(sc, 3, 0xDF01);
502 PHY_WRITE(sc, 2, 0xDF20);
503 PHY_WRITE(sc, 1, 0xFF95);
504 PHY_WRITE(sc, 0, 0xFA00);
505 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
506 PHY_WRITE(sc, 4, val);
507 PHY_WRITE(sc, 3, 0xFF41);
508 PHY_WRITE(sc, 2, 0xDE20);
509 PHY_WRITE(sc, 1, 0x0140);
510 PHY_WRITE(sc, 0, 0x00BB);
511 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
512 PHY_WRITE(sc, 4, val);
513 PHY_WRITE(sc, 3, 0xDF01);
514 PHY_WRITE(sc, 2, 0xDF20);
515 PHY_WRITE(sc, 1, 0xFF95);
516 PHY_WRITE(sc, 0, 0xBF00);
517 PHY_SETBIT(sc, 4, 0x0800);
518 PHY_CLRBIT(sc, 4, 0x0800);
519 PHY_WRITE(sc, 31, 0x0000);
525 rgephy_reset(struct mii_softc *sc)
529 switch (sc->mii_mpd_rev) {
531 pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1);
532 if ((pcr & RGEPHY_F_PCR1_MDI_MM) != 0) {
533 pcr &= ~RGEPHY_F_PCR1_MDI_MM;
534 PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr);
538 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) {
540 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
541 if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
542 ssr &= ~RGEPHY_SSR_ALDPS;
543 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
548 if (sc->mii_mpd_rev >= RGEPHY_8211B) {
549 pcr = PHY_READ(sc, RGEPHY_MII_PCR);
550 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) {
551 pcr &= ~RGEPHY_PCR_MDI_MASK;
552 pcr |= RGEPHY_PCR_MDIX_AUTO;
553 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
561 rgephy_load_dspcode(sc);