sys/dev/mlx5/qp.h

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_QP_H
  29 #define MLX5_QP_H
  30
  31 #include <dev/mlx5/device.h>
  32 #include <dev/mlx5/driver.h>
  33 #include <dev/mlx5/mlx5_ifc.h>
  34
  35 #define MLX5_INVALID_LKEY       0x100
  36 #define MLX5_SIG_WQE_SIZE       (MLX5_SEND_WQE_BB * 5)
  37 #define MLX5_DIF_SIZE           8
  38 #define MLX5_STRIDE_BLOCK_OP    0x400
  39 #define MLX5_CPY_GRD_MASK       0xc0
  40 #define MLX5_CPY_APP_MASK       0x30
  41 #define MLX5_CPY_REF_MASK       0x0f
  42 #define MLX5_BSF_INC_REFTAG     (1 << 6)
  43 #define MLX5_BSF_INL_VALID      (1 << 15)
  44 #define MLX5_BSF_REFRESH_DIF    (1 << 14)
  45 #define MLX5_BSF_REPEAT_BLOCK   (1 << 7)
  46 #define MLX5_BSF_APPTAG_ESCAPE  0x1
  47 #define MLX5_BSF_APPREF_ESCAPE  0x2
  48
  49 enum mlx5_qp_optpar {
  50         MLX5_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  51         MLX5_QP_OPTPAR_RRE                      = 1 << 1,
  52         MLX5_QP_OPTPAR_RAE                      = 1 << 2,
  53         MLX5_QP_OPTPAR_RWE                      = 1 << 3,
  54         MLX5_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  55         MLX5_QP_OPTPAR_Q_KEY                    = 1 << 5,
  56         MLX5_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  57         MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  58         MLX5_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  59         MLX5_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  60         MLX5_QP_OPTPAR_PM_STATE                 = 1 << 10,
  61         MLX5_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  62         MLX5_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  63         MLX5_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  64         MLX5_QP_OPTPAR_PRI_PORT                 = 1 << 16,
  65         MLX5_QP_OPTPAR_SRQN                     = 1 << 18,
  66         MLX5_QP_OPTPAR_CQN_RCV                  = 1 << 19,
  67         MLX5_QP_OPTPAR_DC_HS                    = 1 << 20,
  68         MLX5_QP_OPTPAR_DC_KEY                   = 1 << 21,
  69 };
  70
  71 enum mlx5_qp_state {
  72         MLX5_QP_STATE_RST                       = 0,
  73         MLX5_QP_STATE_INIT                      = 1,
  74         MLX5_QP_STATE_RTR                       = 2,
  75         MLX5_QP_STATE_RTS                       = 3,
  76         MLX5_QP_STATE_SQER                      = 4,
  77         MLX5_QP_STATE_SQD                       = 5,
  78         MLX5_QP_STATE_ERR                       = 6,
  79         MLX5_QP_STATE_SQ_DRAINING               = 7,
  80         MLX5_QP_STATE_SUSPENDED                 = 9,
  81         MLX5_QP_NUM_STATE
  82 };
  83
  84 enum {
  85         MLX5_QP_ST_RC                           = 0x0,
  86         MLX5_QP_ST_UC                           = 0x1,
  87         MLX5_QP_ST_UD                           = 0x2,
  88         MLX5_QP_ST_XRC                          = 0x3,
  89         MLX5_QP_ST_MLX                          = 0x4,
  90         MLX5_QP_ST_DCI                          = 0x5,
  91         MLX5_QP_ST_DCT                          = 0x6,
  92         MLX5_QP_ST_QP0                          = 0x7,
  93         MLX5_QP_ST_QP1                          = 0x8,
  94         MLX5_QP_ST_RAW_ETHERTYPE                = 0x9,
  95         MLX5_QP_ST_RAW_IPV6                     = 0xa,
  96         MLX5_QP_ST_SNIFFER                      = 0xb,
  97         MLX5_QP_ST_SYNC_UMR                     = 0xe,
  98         MLX5_QP_ST_PTP_1588                     = 0xd,
  99         MLX5_QP_ST_REG_UMR                      = 0xc,
 100         MLX5_QP_ST_MAX
 101 };
 102
 103 enum {
 104         MLX5_NON_ZERO_RQ        = 0 << 24,
 105         MLX5_SRQ_RQ             = 1 << 24,
 106         MLX5_CRQ_RQ             = 2 << 24,
 107         MLX5_ZERO_LEN_RQ        = 3 << 24
 108 };
 109
 110 enum {
 111         /* params1 */
 112         MLX5_QP_BIT_SRE                         = 1 << 15,
 113         MLX5_QP_BIT_SWE                         = 1 << 14,
 114         MLX5_QP_BIT_SAE                         = 1 << 13,
 115         /* params2 */
 116         MLX5_QP_BIT_RRE                         = 1 << 15,
 117         MLX5_QP_BIT_RWE                         = 1 << 14,
 118         MLX5_QP_BIT_RAE                         = 1 << 13,
 119         MLX5_QP_BIT_RIC                         = 1 <<  4,
 120 };
 121
 122 enum {
 123         MLX5_WQE_CTRL_CQ_UPDATE         = 2 << 2,
 124         MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
 125         MLX5_WQE_CTRL_SOLICITED         = 1 << 1,
 126 };
 127
 128 enum {
 129         MLX5_SEND_WQE_DS        = 16,
 130         MLX5_SEND_WQE_BB        = 64,
 131 };
 132
 133 #define MLX5_SEND_WQEBB_NUM_DS  (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
 134
 135 enum {
 136         MLX5_SEND_WQE_MAX_WQEBBS        = 16,
 137 };
 138
 139 enum {
 140         MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 141         MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 142         MLX5_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 143         MLX5_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 144         MLX5_WQE_FMR_PERM_ATOMIC        = 1 << 31
 145 };
 146
 147 enum {
 148         MLX5_FENCE_MODE_NONE                    = 0 << 5,
 149         MLX5_FENCE_MODE_INITIATOR_SMALL         = 1 << 5,
 150         MLX5_FENCE_MODE_STRONG_ORDERING         = 3 << 5,
 151         MLX5_FENCE_MODE_SMALL_AND_FENCE         = 4 << 5,
 152 };
 153
 154 enum {
 155         MLX5_QP_LAT_SENSITIVE   = 1 << 28,
 156         MLX5_QP_BLOCK_MCAST     = 1 << 30,
 157         MLX5_QP_ENABLE_SIG      = 1 << 31,
 158 };
 159
 160 enum {
 161         MLX5_RCV_DBR    = 0,
 162         MLX5_SND_DBR    = 1,
 163 };
 164
 165 enum {
 166         MLX5_FLAGS_INLINE       = 1<<7,
 167         MLX5_FLAGS_CHECK_FREE   = 1<<5,
 168 };
 169
 170 struct mlx5_wqe_fmr_seg {
 171         __be32                  flags;
 172         __be32                  mem_key;
 173         __be64                  buf_list;
 174         __be64                  start_addr;
 175         __be64                  reg_len;
 176         __be32                  offset;
 177         __be32                  page_size;
 178         u32                     reserved[2];
 179 };
 180
 181 struct mlx5_wqe_ctrl_seg {
 182         __be32                  opmod_idx_opcode;
 183         __be32                  qpn_ds;
 184         u8                      signature;
 185         u8                      rsvd[2];
 186         u8                      fm_ce_se;
 187         __be32                  imm;
 188 };
 189
 190 enum {
 191         MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
 192         MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
 193         MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
 194         MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
 195 };
 196
 197 struct mlx5_wqe_eth_seg {
 198         u8              rsvd0[4];
 199         u8              cs_flags;
 200         u8              rsvd1;
 201         __be16          mss;
 202         __be32          rsvd2;
 203         __be16          inline_hdr_sz;
 204         u8              inline_hdr_start[2];
 205 };
 206
 207 struct mlx5_wqe_xrc_seg {
 208         __be32                  xrc_srqn;
 209         u8                      rsvd[12];
 210 };
 211
 212 struct mlx5_wqe_masked_atomic_seg {
 213         __be64                  swap_add;
 214         __be64                  compare;
 215         __be64                  swap_add_mask;
 216         __be64                  compare_mask;
 217 };
 218
 219 struct mlx5_av {
 220         union {
 221                 struct {
 222                         __be32  qkey;
 223                         __be32  reserved;
 224                 } qkey;
 225                 __be64  dc_key;
 226         } key;
 227         __be32  dqp_dct;
 228         u8      stat_rate_sl;
 229         u8      fl_mlid;
 230         union {
 231                 __be16  rlid;
 232                 __be16  udp_sport;
 233         };
 234         u8      reserved0[4];
 235         u8      rmac[6];
 236         u8      tclass;
 237         u8      hop_limit;
 238         __be32  grh_gid_fl;
 239         u8      rgid[16];
 240 };
 241
 242 struct mlx5_wqe_datagram_seg {
 243         struct mlx5_av  av;
 244 };
 245
 246 struct mlx5_wqe_raddr_seg {
 247         __be64                  raddr;
 248         __be32                  rkey;
 249         u32                     reserved;
 250 };
 251
 252 struct mlx5_wqe_atomic_seg {
 253         __be64                  swap_add;
 254         __be64                  compare;
 255 };
 256
 257 struct mlx5_wqe_data_seg {
 258         __be32                  byte_count;
 259         __be32                  lkey;
 260         __be64                  addr;
 261 };
 262
 263 struct mlx5_wqe_umr_ctrl_seg {
 264         u8              flags;
 265         u8              rsvd0[3];
 266         __be16          klm_octowords;
 267         __be16          bsf_octowords;
 268         __be64          mkey_mask;
 269         u8              rsvd1[32];
 270 };
 271
 272 struct mlx5_seg_set_psv {
 273         __be32          psv_num;
 274         __be16          syndrome;
 275         __be16          status;
 276         __be32          transient_sig;
 277         __be32          ref_tag;
 278 };
 279
 280 struct mlx5_seg_get_psv {
 281         u8              rsvd[19];
 282         u8              num_psv;
 283         __be32          l_key;
 284         __be64          va;
 285         __be32          psv_index[4];
 286 };
 287
 288 struct mlx5_seg_check_psv {
 289         u8              rsvd0[2];
 290         __be16          err_coalescing_op;
 291         u8              rsvd1[2];
 292         __be16          xport_err_op;
 293         u8              rsvd2[2];
 294         __be16          xport_err_mask;
 295         u8              rsvd3[7];
 296         u8              num_psv;
 297         __be32          l_key;
 298         __be64          va;
 299         __be32          psv_index[4];
 300 };
 301
 302 struct mlx5_rwqe_sig {
 303         u8      rsvd0[4];
 304         u8      signature;
 305         u8      rsvd1[11];
 306 };
 307
 308 struct mlx5_wqe_signature_seg {
 309         u8      rsvd0[4];
 310         u8      signature;
 311         u8      rsvd1[11];
 312 };
 313
 314 struct mlx5_wqe_inline_seg {
 315         __be32  byte_count;
 316 };
 317
 318 enum mlx5_sig_type {
 319         MLX5_DIF_CRC = 0x1,
 320         MLX5_DIF_IPCS = 0x2,
 321 };
 322
 323 struct mlx5_bsf_inl {
 324         __be16          vld_refresh;
 325         __be16          dif_apptag;
 326         __be32          dif_reftag;
 327         u8              sig_type;
 328         u8              rp_inv_seed;
 329         u8              rsvd[3];
 330         u8              dif_inc_ref_guard_check;
 331         __be16          dif_app_bitmask_check;
 332 };
 333
 334 struct mlx5_bsf {
 335         struct mlx5_bsf_basic {
 336                 u8              bsf_size_sbs;
 337                 u8              check_byte_mask;
 338                 union {
 339                         u8      copy_byte_mask;
 340                         u8      bs_selector;
 341                         u8      rsvd_wflags;
 342                 } wire;
 343                 union {
 344                         u8      bs_selector;
 345                         u8      rsvd_mflags;
 346                 } mem;
 347                 __be32          raw_data_size;
 348                 __be32          w_bfs_psv;
 349                 __be32          m_bfs_psv;
 350         } basic;
 351         struct mlx5_bsf_ext {
 352                 __be32          t_init_gen_pro_size;
 353                 __be32          rsvd_epi_size;
 354                 __be32          w_tfs_psv;
 355                 __be32          m_tfs_psv;
 356         } ext;
 357         struct mlx5_bsf_inl     w_inl;
 358         struct mlx5_bsf_inl     m_inl;
 359 };
 360
 361 struct mlx5_klm {
 362         __be32          bcount;
 363         __be32          key;
 364         __be64          va;
 365 };
 366
 367 struct mlx5_stride_block_entry {
 368         __be16          stride;
 369         __be16          bcount;
 370         __be32          key;
 371         __be64          va;
 372 };
 373
 374 struct mlx5_stride_block_ctrl_seg {
 375         __be32          bcount_per_cycle;
 376         __be32          op;
 377         __be32          repeat_count;
 378         u16             rsvd;
 379         __be16          num_entries;
 380 };
 381
 382 struct mlx5_core_qp {
 383         struct mlx5_core_rsc_common     common; /* must be first */
 384         void (*event)           (struct mlx5_core_qp *, int);
 385         int                     qpn;
 386         struct mlx5_rsc_debug   *dbg;
 387         int                     pid;
 388 };
 389
 390 struct mlx5_qp_path {
 391         u8                      fl_free_ar;
 392         u8                      rsvd3;
 393         __be16                  pkey_index;
 394         u8                      rsvd0;
 395         u8                      grh_mlid;
 396         __be16                  rlid;
 397         u8                      ackto_lt;
 398         u8                      mgid_index;
 399         u8                      static_rate;
 400         u8                      hop_limit;
 401         __be32                  tclass_flowlabel;
 402         union {
 403                 u8              rgid[16];
 404                 u8              rip[16];
 405         };
 406         u8                      f_dscp_ecn_prio;
 407         u8                      ecn_dscp;
 408         __be16                  udp_sport;
 409         u8                      dci_cfi_prio_sl;
 410         u8                      port;
 411         u8                      rmac[6];
 412 };
 413
 414 struct mlx5_qp_context {
 415         __be32                  flags;
 416         __be32                  flags_pd;
 417         u8                      mtu_msgmax;
 418         u8                      rq_size_stride;
 419         __be16                  sq_crq_size;
 420         __be32                  qp_counter_set_usr_page;
 421         __be32                  wire_qpn;
 422         __be32                  log_pg_sz_remote_qpn;
 423         struct                  mlx5_qp_path pri_path;
 424         struct                  mlx5_qp_path alt_path;
 425         __be32                  params1;
 426         u8                      reserved2[4];
 427         __be32                  next_send_psn;
 428         __be32                  cqn_send;
 429         u8                      reserved3[8];
 430         __be32                  last_acked_psn;
 431         __be32                  ssn;
 432         __be32                  params2;
 433         __be32                  rnr_nextrecvpsn;
 434         __be32                  xrcd;
 435         __be32                  cqn_recv;
 436         __be64                  db_rec_addr;
 437         __be32                  qkey;
 438         __be32                  rq_type_srqn;
 439         __be32                  rmsn;
 440         __be16                  hw_sq_wqe_counter;
 441         __be16                  sw_sq_wqe_counter;
 442         __be16                  hw_rcyclic_byte_counter;
 443         __be16                  hw_rq_counter;
 444         __be16                  sw_rcyclic_byte_counter;
 445         __be16                  sw_rq_counter;
 446         u8                      rsvd0[5];
 447         u8                      cgs;
 448         u8                      cs_req;
 449         u8                      cs_res;
 450         __be64                  dc_access_key;
 451         u8                      rsvd1[24];
 452 };
 453
 454 struct mlx5_create_qp_mbox_in {
 455         struct mlx5_inbox_hdr   hdr;
 456         __be32                  input_qpn;
 457         u8                      rsvd0[4];
 458         __be32                  opt_param_mask;
 459         u8                      rsvd1[4];
 460         struct mlx5_qp_context  ctx;
 461         u8                      rsvd3[16];
 462         __be64                  pas[0];
 463 };
 464
 465 struct mlx5_create_qp_mbox_out {
 466         struct mlx5_outbox_hdr  hdr;
 467         __be32                  qpn;
 468         u8                      rsvd0[4];
 469 };
 470
 471 struct mlx5_destroy_qp_mbox_in {
 472         struct mlx5_inbox_hdr   hdr;
 473         __be32                  qpn;
 474         u8                      rsvd0[4];
 475 };
 476
 477 struct mlx5_destroy_qp_mbox_out {
 478         struct mlx5_outbox_hdr  hdr;
 479         u8                      rsvd0[8];
 480 };
 481
 482 struct mlx5_modify_qp_mbox_in {
 483         struct mlx5_inbox_hdr   hdr;
 484         __be32                  qpn;
 485         u8                      rsvd1[4];
 486         __be32                  optparam;
 487         u8                      rsvd0[4];
 488         struct mlx5_qp_context  ctx;
 489 };
 490
 491 struct mlx5_modify_qp_mbox_out {
 492         struct mlx5_outbox_hdr  hdr;
 493         u8                      rsvd0[8];
 494 };
 495
 496 struct mlx5_query_qp_mbox_in {
 497         struct mlx5_inbox_hdr   hdr;
 498         __be32                  qpn;
 499         u8                      rsvd[4];
 500 };
 501
 502 struct mlx5_query_qp_mbox_out {
 503         struct mlx5_outbox_hdr  hdr;
 504         u8                      rsvd1[8];
 505         __be32                  optparam;
 506         u8                      rsvd0[4];
 507         struct mlx5_qp_context  ctx;
 508         u8                      rsvd2[16];
 509         __be64                  pas[0];
 510 };
 511
 512 struct mlx5_conf_sqp_mbox_in {
 513         struct mlx5_inbox_hdr   hdr;
 514         __be32                  qpn;
 515         u8                      rsvd[3];
 516         u8                      type;
 517 };
 518
 519 struct mlx5_conf_sqp_mbox_out {
 520         struct mlx5_outbox_hdr  hdr;
 521         u8                      rsvd[8];
 522 };
 523
 524 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
 525 {
 526         return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
 527 }
 528
 529 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
 530 {
 531         return radix_tree_lookup(&dev->priv.mr_table.tree, key);
 532 }
 533
 534 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
 535                         struct mlx5_core_qp *qp,
 536                         struct mlx5_create_qp_mbox_in *in,
 537                         int inlen);
 538 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
 539                         enum mlx5_qp_state new_state,
 540                         struct mlx5_modify_qp_mbox_in *in, int sqd_event,
 541                         struct mlx5_core_qp *qp);
 542 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
 543                          struct mlx5_core_qp *qp);
 544 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
 545                        struct mlx5_query_qp_mbox_out *out, int outlen);
 546
 547 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
 548 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
 549 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
 550 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
 551 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 552 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 553
 554 static inline const char *mlx5_qp_type_str(int type)
 555 {
 556         switch (type) {
 557         case MLX5_QP_ST_RC: return "RC";
 558         case MLX5_QP_ST_UC: return "C";
 559         case MLX5_QP_ST_UD: return "UD";
 560         case MLX5_QP_ST_XRC: return "XRC";
 561         case MLX5_QP_ST_MLX: return "MLX";
 562         case MLX5_QP_ST_QP0: return "QP0";
 563         case MLX5_QP_ST_QP1: return "QP1";
 564         case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
 565         case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
 566         case MLX5_QP_ST_SNIFFER: return "SNIFFER";
 567         case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
 568         case MLX5_QP_ST_PTP_1588: return "PTP_1588";
 569         case MLX5_QP_ST_REG_UMR: return "REG_UMR";
 570         default: return "Invalid transport type";
 571         }
 572 }
 573
 574 static inline const char *mlx5_qp_state_str(int state)
 575 {
 576         switch (state) {
 577         case MLX5_QP_STATE_RST:
 578         return "RST";
 579         case MLX5_QP_STATE_INIT:
 580         return "INIT";
 581         case MLX5_QP_STATE_RTR:
 582         return "RTR";
 583         case MLX5_QP_STATE_RTS:
 584         return "RTS";
 585         case MLX5_QP_STATE_SQER:
 586         return "SQER";
 587         case MLX5_QP_STATE_SQD:
 588         return "SQD";
 589         case MLX5_QP_STATE_ERR:
 590         return "ERR";
 591         case MLX5_QP_STATE_SQ_DRAINING:
 592         return "SQ_DRAINING";
 593         case MLX5_QP_STATE_SUSPENDED:
 594         return "SUSPENDED";
 595         default: return "Invalid QP state";
 596         }
 597 }
 598
 599 #endif /* MLX5_QP_H */