2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
46 #include <dev/pci/pcivar.h>
50 #include <cam/cam_ccb.h>
51 #include <cam/cam_sim.h>
52 #include <cam/cam_xpt_sim.h>
53 #include <cam/cam_debug.h>
55 /* local prototypes */
56 static int mvs_ch_init(device_t dev);
57 static int mvs_ch_deinit(device_t dev);
58 static int mvs_ch_suspend(device_t dev);
59 static int mvs_ch_resume(device_t dev);
60 static void mvs_dmainit(device_t dev);
61 static void mvs_dmasetupc_cb(void *xsc,
62 bus_dma_segment_t *segs, int nsegs, int error);
63 static void mvs_dmafini(device_t dev);
64 static void mvs_slotsalloc(device_t dev);
65 static void mvs_slotsfree(device_t dev);
66 static void mvs_setup_edma_queues(device_t dev);
67 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode);
68 static void mvs_ch_pm(void *arg);
69 static void mvs_ch_intr_locked(void *data);
70 static void mvs_ch_intr(void *data);
71 static void mvs_reset(device_t dev);
72 static void mvs_softreset(device_t dev, union ccb *ccb);
74 static int mvs_sata_connect(struct mvs_channel *ch);
75 static int mvs_sata_phy_reset(device_t dev);
76 static int mvs_wait(device_t dev, u_int s, u_int c, int t);
77 static void mvs_tfd_read(device_t dev, union ccb *ccb);
78 static void mvs_tfd_write(device_t dev, union ccb *ccb);
79 static void mvs_legacy_intr(device_t dev, int poll);
80 static void mvs_crbq_intr(device_t dev);
81 static void mvs_begin_transaction(device_t dev, union ccb *ccb);
82 static void mvs_legacy_execute_transaction(struct mvs_slot *slot);
83 static void mvs_timeout(struct mvs_slot *slot);
84 static void mvs_dmasetprd(void *arg,
85 bus_dma_segment_t *segs, int nsegs, int error);
86 static void mvs_requeue_frozen(device_t dev);
87 static void mvs_execute_transaction(struct mvs_slot *slot);
88 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et);
90 static void mvs_issue_recovery(device_t dev);
91 static void mvs_process_read_log(device_t dev, union ccb *ccb);
92 static void mvs_process_request_sense(device_t dev, union ccb *ccb);
94 static void mvsaction(struct cam_sim *sim, union ccb *ccb);
95 static void mvspoll(struct cam_sim *sim);
97 static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers");
99 #define recovery_type spriv_field0
100 #define RECOVERY_NONE 0
101 #define RECOVERY_READ_LOG 1
102 #define RECOVERY_REQUEST_SENSE 2
103 #define recovery_slot spriv_field1
106 mvs_ch_probe(device_t dev)
109 device_set_desc_copy(dev, "Marvell SATA channel");
110 return (BUS_PROBE_DEFAULT);
114 mvs_ch_attach(device_t dev)
116 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev));
117 struct mvs_channel *ch = device_get_softc(dev);
118 struct cam_devq *devq;
119 int rid, error, i, sata_rev = 0;
122 ch->unit = (intptr_t)device_get_ivars(dev);
123 ch->quirks = ctlr->quirks;
124 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF);
125 resource_int_value(device_get_name(dev),
126 device_get_unit(dev), "pm_level", &ch->pm_level);
127 if (ch->pm_level > 3)
128 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
129 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
130 resource_int_value(device_get_name(dev),
131 device_get_unit(dev), "sata_rev", &sata_rev);
132 for (i = 0; i < 16; i++) {
133 ch->user[i].revision = sata_rev;
134 ch->user[i].mode = 0;
135 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048;
136 ch->user[i].tags = MVS_MAX_SLOTS;
137 ch->curr[i] = ch->user[i];
139 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
140 CTS_SATA_CAPS_H_APST |
141 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
143 ch->user[i].caps |= CTS_SATA_CAPS_H_AN;
146 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
154 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
155 &rid, RF_SHAREABLE | RF_ACTIVE))) {
156 device_printf(dev, "Unable to map interrupt\n");
160 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
161 mvs_ch_intr_locked, dev, &ch->ih))) {
162 device_printf(dev, "Unable to setup interrupt\n");
166 /* Create the device queue for our SIM. */
167 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1);
169 device_printf(dev, "Unable to allocate simq\n");
173 /* Construct SIM entry */
174 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch,
175 device_get_unit(dev), &ch->mtx,
176 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1,
178 if (ch->sim == NULL) {
180 device_printf(dev, "unable to allocate sim\n");
184 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
185 device_printf(dev, "unable to register xpt bus\n");
189 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
190 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
191 device_printf(dev, "unable to create path\n");
195 if (ch->pm_level > 3) {
196 callout_reset(&ch->pm_timer,
197 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
200 mtx_unlock(&ch->mtx);
204 xpt_bus_deregister(cam_sim_path(ch->sim));
206 cam_sim_free(ch->sim, /*free_devq*/TRUE);
208 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
210 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
211 mtx_unlock(&ch->mtx);
212 mtx_destroy(&ch->mtx);
217 mvs_ch_detach(device_t dev)
219 struct mvs_channel *ch = device_get_softc(dev);
222 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
223 /* Forget about reset. */
226 xpt_release_simq(ch->sim, TRUE);
228 xpt_free_path(ch->path);
229 xpt_bus_deregister(cam_sim_path(ch->sim));
230 cam_sim_free(ch->sim, /*free_devq*/TRUE);
231 mtx_unlock(&ch->mtx);
233 if (ch->pm_level > 3)
234 callout_drain(&ch->pm_timer);
235 callout_drain(&ch->reset_timer);
236 bus_teardown_intr(dev, ch->r_irq, ch->ih);
237 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
243 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
244 mtx_destroy(&ch->mtx);
249 mvs_ch_init(device_t dev)
251 struct mvs_channel *ch = device_get_softc(dev);
254 /* Disable port interrupts */
255 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
257 ch->curr_mode = MVS_EDMA_UNKNOWN;
258 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
259 /* Clear and configure FIS interrupts. */
260 ATA_OUTL(ch->r_mem, SATA_FISIC, 0);
261 reg = ATA_INL(ch->r_mem, SATA_FISC);
262 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
263 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
264 reg = ATA_INL(ch->r_mem, SATA_FISIM);
265 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
266 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
267 /* Clear SATA error register. */
268 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
269 /* Clear any outstanding error interrupts. */
270 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
271 /* Unmask all error interrupts */
272 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
277 mvs_ch_deinit(device_t dev)
279 struct mvs_channel *ch = device_get_softc(dev);
282 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
283 /* Disable port interrupts. */
284 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
289 mvs_ch_suspend(device_t dev)
291 struct mvs_channel *ch = device_get_softc(dev);
294 xpt_freeze_simq(ch->sim, 1);
296 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100);
297 /* Forget about reset. */
300 callout_stop(&ch->reset_timer);
301 xpt_release_simq(ch->sim, TRUE);
304 mtx_unlock(&ch->mtx);
309 mvs_ch_resume(device_t dev)
311 struct mvs_channel *ch = device_get_softc(dev);
316 xpt_release_simq(ch->sim, TRUE);
317 mtx_unlock(&ch->mtx);
321 struct mvs_dc_cb_args {
327 mvs_dmainit(device_t dev)
329 struct mvs_channel *ch = device_get_softc(dev);
330 struct mvs_dc_cb_args dcba;
332 /* EDMA command request area. */
333 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
334 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
335 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE,
336 0, NULL, NULL, &ch->dma.workrq_tag))
338 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0,
339 &ch->dma.workrq_map))
341 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map,
342 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
344 bus_dmamem_free(ch->dma.workrq_tag,
345 ch->dma.workrq, ch->dma.workrq_map);
348 ch->dma.workrq_bus = dcba.maddr;
349 /* EDMA command response area. */
350 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0,
351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
352 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE,
353 0, NULL, NULL, &ch->dma.workrp_tag))
355 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0,
356 &ch->dma.workrp_map))
358 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map,
359 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
361 bus_dmamem_free(ch->dma.workrp_tag,
362 ch->dma.workrp, ch->dma.workrp_map);
365 ch->dma.workrp_bus = dcba.maddr;
367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX,
368 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
370 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS,
371 MVS_SG_ENTRIES, MVS_EPRD_MAX,
372 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
378 device_printf(dev, "WARNING - DMA initialization failed\n");
383 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
385 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc;
387 if (!(dcba->error = error))
388 dcba->maddr = segs[0].ds_addr;
392 mvs_dmafini(device_t dev)
394 struct mvs_channel *ch = device_get_softc(dev);
396 if (ch->dma.data_tag) {
397 bus_dma_tag_destroy(ch->dma.data_tag);
398 ch->dma.data_tag = NULL;
400 if (ch->dma.workrp_bus) {
401 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map);
402 bus_dmamem_free(ch->dma.workrp_tag,
403 ch->dma.workrp, ch->dma.workrp_map);
404 ch->dma.workrp_bus = 0;
405 ch->dma.workrp_map = NULL;
406 ch->dma.workrp = NULL;
408 if (ch->dma.workrp_tag) {
409 bus_dma_tag_destroy(ch->dma.workrp_tag);
410 ch->dma.workrp_tag = NULL;
412 if (ch->dma.workrq_bus) {
413 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map);
414 bus_dmamem_free(ch->dma.workrq_tag,
415 ch->dma.workrq, ch->dma.workrq_map);
416 ch->dma.workrq_bus = 0;
417 ch->dma.workrq_map = NULL;
418 ch->dma.workrq = NULL;
420 if (ch->dma.workrq_tag) {
421 bus_dma_tag_destroy(ch->dma.workrq_tag);
422 ch->dma.workrq_tag = NULL;
427 mvs_slotsalloc(device_t dev)
429 struct mvs_channel *ch = device_get_softc(dev);
432 /* Alloc and setup command/dma slots */
433 bzero(ch->slot, sizeof(ch->slot));
434 for (i = 0; i < MVS_MAX_SLOTS; i++) {
435 struct mvs_slot *slot = &ch->slot[i];
439 slot->state = MVS_SLOT_EMPTY;
441 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
443 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
444 device_printf(ch->dev, "FAILURE - create data_map\n");
449 mvs_slotsfree(device_t dev)
451 struct mvs_channel *ch = device_get_softc(dev);
454 /* Free all dma slots */
455 for (i = 0; i < MVS_MAX_SLOTS; i++) {
456 struct mvs_slot *slot = &ch->slot[i];
458 callout_drain(&slot->timeout);
459 if (slot->dma.data_map) {
460 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
461 slot->dma.data_map = NULL;
467 mvs_setup_edma_queues(device_t dev)
469 struct mvs_channel *ch = device_get_softc(dev);
472 /* Requests queue. */
473 work = ch->dma.workrq_bus;
474 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32);
475 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff);
476 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff);
477 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
478 BUS_DMASYNC_PREWRITE);
479 /* Reponses queue. */
480 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE);
481 work = ch->dma.workrp_bus;
482 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32);
483 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff);
484 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff);
485 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
486 BUS_DMASYNC_PREREAD);
492 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode)
494 struct mvs_channel *ch = device_get_softc(dev);
496 uint32_t ecfg, fcfg, hc, ltm, unkn;
498 if (mode == ch->curr_mode)
500 /* If we are running, we should stop first. */
501 if (ch->curr_mode != MVS_EDMA_OFF) {
502 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA);
504 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) {
506 if (timeout++ > 1000) {
507 device_printf(dev, "stopping EDMA engine failed\n");
512 ch->curr_mode = mode;
515 /* Report mode to controller. Needed for correct CCC operation. */
516 MVS_EDMA(device_get_parent(dev), dev, mode);
517 /* Configure new mode. */
518 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN;
519 if (ch->pm_present) {
520 ecfg |= EDMA_CFG_EMASKRXPM;
521 if (ch->quirks & MVS_Q_GENIIE) {
522 ecfg |= EDMA_CFG_EEDMAFBS;
526 if (ch->quirks & MVS_Q_GENI)
527 ecfg |= EDMA_CFG_ERDBSZ;
528 else if (ch->quirks & MVS_Q_GENII)
529 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN;
530 if (ch->quirks & MVS_Q_CT)
531 ecfg |= EDMA_CFG_ECUTTHROUGHEN;
532 if (mode != MVS_EDMA_OFF)
533 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN;
534 if (mode == MVS_EDMA_QUEUED)
535 ecfg |= EDMA_CFG_EQUE;
536 else if (mode == MVS_EDMA_NCQ)
537 ecfg |= EDMA_CFG_ESATANATVCMDQUE;
538 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg);
539 mvs_setup_edma_queues(dev);
540 if (ch->quirks & MVS_Q_GENIIE) {
541 /* Configure FBS-related registers */
542 fcfg = ATA_INL(ch->r_mem, SATA_FISC);
543 ltm = ATA_INL(ch->r_mem, SATA_LTM);
544 hc = ATA_INL(ch->r_mem, EDMA_HC);
545 if (ch->fbs_enabled) {
546 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP;
547 if (mode == MVS_EDMA_NCQ) {
548 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
549 hc &= ~EDMA_IE_EDEVERR;
551 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0;
552 hc |= EDMA_IE_EDEVERR;
556 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP;
557 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
558 hc |= EDMA_IE_EDEVERR;
561 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg);
562 ATA_OUTL(ch->r_mem, SATA_LTM, ltm);
563 ATA_OUTL(ch->r_mem, EDMA_HC, hc);
564 /* This is some magic, required to handle several DRQs
566 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD);
567 if (mode == MVS_EDMA_OFF)
571 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn);
574 if (mode != MVS_EDMA_OFF)
575 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA);
578 devclass_t mvs_devclass;
579 devclass_t mvsch_devclass;
580 static device_method_t mvsch_methods[] = {
581 DEVMETHOD(device_probe, mvs_ch_probe),
582 DEVMETHOD(device_attach, mvs_ch_attach),
583 DEVMETHOD(device_detach, mvs_ch_detach),
584 DEVMETHOD(device_suspend, mvs_ch_suspend),
585 DEVMETHOD(device_resume, mvs_ch_resume),
588 static driver_t mvsch_driver = {
591 sizeof(struct mvs_channel)
593 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0);
594 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0);
597 mvs_phy_check_events(device_t dev, u_int32_t serr)
599 struct mvs_channel *ch = device_get_softc(dev);
601 if (ch->pm_level == 0) {
602 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS);
606 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
607 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
608 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) {
609 device_printf(dev, "CONNECT requested\n");
611 device_printf(dev, "DISCONNECT requested\n");
614 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
616 if (xpt_create_path(&ccb->ccb_h.path, NULL,
617 cam_sim_path(ch->sim),
618 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
627 mvs_notify_events(device_t dev)
629 struct mvs_channel *ch = device_get_softc(dev);
630 struct cam_path *dpath;
634 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */
635 fis = ATA_INL(ch->r_mem, SATA_FISDW0);
636 if ((fis & 0x80ff) == 0x80a1)
637 d = (fis & 0x0f00) >> 8;
639 d = ch->pm_present ? 15 : 0;
641 device_printf(dev, "SNTF %d\n", d);
642 if (xpt_create_path(&dpath, NULL,
643 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) {
644 xpt_async(AC_SCSI_AEN, dpath, NULL);
645 xpt_free_path(dpath);
650 mvs_ch_intr_locked(void *data)
652 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
653 device_t dev = (device_t)arg->arg;
654 struct mvs_channel *ch = device_get_softc(dev);
658 mtx_unlock(&ch->mtx);
664 device_t dev = (device_t)arg;
665 struct mvs_channel *ch = device_get_softc(dev);
668 if (ch->numrslots != 0)
670 /* If we are idle - request power state transition. */
671 work = ATA_INL(ch->r_mem, SATA_SC);
672 work &= ~SATA_SC_SPM_MASK;
673 if (ch->pm_level == 4)
674 work |= SATA_SC_SPM_PARTIAL;
676 work |= SATA_SC_SPM_SLUMBER;
677 ATA_OUTL(ch->r_mem, SATA_SC, work);
681 mvs_ch_pm_wake(device_t dev)
683 struct mvs_channel *ch = device_get_softc(dev);
687 work = ATA_INL(ch->r_mem, SATA_SS);
688 if (work & SATA_SS_IPM_ACTIVE)
690 /* If we are not in active state - request power state transition. */
691 work = ATA_INL(ch->r_mem, SATA_SC);
692 work &= ~SATA_SC_SPM_MASK;
693 work |= SATA_SC_SPM_ACTIVE;
694 ATA_OUTL(ch->r_mem, SATA_SC, work);
695 /* Wait for transition to happen. */
696 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 &&
703 mvs_ch_intr(void *data)
705 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
706 device_t dev = (device_t)arg->arg;
707 struct mvs_channel *ch = device_get_softc(dev);
708 uint32_t iec, serr = 0, fisic = 0;
709 enum mvs_err_type et;
710 int i, ccs, port = -1, selfdis = 0;
711 int edma = (ch->numtslots != 0 || ch->numdslots != 0);
713 /* New item in response queue. */
714 if ((arg->cause & 2) && edma)
716 /* Some error or special event. */
717 if (arg->cause & 1) {
718 iec = ATA_INL(ch->r_mem, EDMA_IEC);
719 if (iec & EDMA_IE_SERRINT) {
720 serr = ATA_INL(ch->r_mem, SATA_SE);
721 ATA_OUTL(ch->r_mem, SATA_SE, serr);
723 /* EDMA self-disabled due to error. */
724 if (iec & EDMA_IE_ESELFDIS)
726 /* Transport interrupt. */
727 if (iec & EDMA_IE_ETRANSINT) {
728 /* For Gen-I this bit means self-disable. */
729 if (ch->quirks & MVS_Q_GENI)
731 /* For Gen-II this bit means SDB-N. */
732 else if (ch->quirks & MVS_Q_GENII)
733 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1;
734 else /* For Gen-IIe - read FIS interrupt cause. */
735 fisic = ATA_INL(ch->r_mem, SATA_FISIC);
738 ch->curr_mode = MVS_EDMA_UNKNOWN;
739 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec);
740 /* Interface errors or Device error. */
741 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) {
743 if (ch->numpslots != 0) {
746 if (ch->quirks & MVS_Q_GENIIE)
747 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S));
749 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S));
750 /* Check if error is one-PMP-port-specific, */
751 if (ch->fbs_enabled) {
752 /* Which ports were active. */
753 for (i = 0; i < 16; i++) {
754 if (ch->numrslotspd[i] == 0)
758 else if (port != i) {
763 /* If several ports were active and EDMA still enabled -
764 * other ports are probably unaffected and may continue.
766 if (port == -2 && !selfdis) {
767 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16;
769 if (port != (fls(p) - 1))
774 mvs_requeue_frozen(dev);
775 for (i = 0; i < MVS_MAX_SLOTS; i++) {
776 /* XXX: reqests in loading state. */
777 if (((ch->rslots >> i) & 1) == 0)
780 ch->slot[i].ccb->ccb_h.target_id != port)
782 if (iec & EDMA_IE_EDEVERR) { /* Device error. */
784 if (ch->numtslots == 0) {
785 /* Untagged operation. */
789 et = MVS_ERR_INNOCENT;
791 /* Tagged operation. */
798 } else if (iec & 0xfc1e9000) {
799 if (ch->numtslots == 0 &&
800 i != ccs && port != -2)
801 et = MVS_ERR_INNOCENT;
805 et = MVS_ERR_INVALID;
806 mvs_end_transaction(&ch->slot[i], et);
810 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1)
811 mvs_notify_events(dev);
813 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic);
814 /* Process hot-plug. */
815 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) ||
816 (serr & SATA_SE_PHY_CHANGED))
817 mvs_phy_check_events(dev, serr);
819 /* Legacy mode device interrupt. */
820 if ((arg->cause & 2) && !edma)
821 mvs_legacy_intr(dev, arg->cause & 4);
825 mvs_getstatus(device_t dev, int clear)
827 struct mvs_channel *ch = device_get_softc(dev);
828 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT);
831 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR))
834 status |= ATA_S_BUSY;
840 mvs_legacy_intr(device_t dev, int poll)
842 struct mvs_channel *ch = device_get_softc(dev);
843 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */
844 union ccb *ccb = slot->ccb;
845 enum mvs_err_type et = MVS_ERR_NONE;
847 u_int length, resid, size;
849 uint8_t status, ireason;
851 /* Clear interrupt and get status. */
852 status = mvs_getstatus(dev, 1);
853 if (slot->state < MVS_SLOT_RUNNING)
855 port = ccb->ccb_h.target_id & 0x0f;
856 /* Wait a bit for late !BUSY status update. */
857 if (status & ATA_S_BUSY) {
861 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) {
863 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY)
867 /* If we got an error, we are done. */
868 if (status & ATA_S_ERROR) {
872 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */
873 ccb->ataio.res.status = status;
874 /* Are we moving data? */
875 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
876 /* If data read command - get them. */
877 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
878 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
879 device_printf(dev, "timeout waiting for read DRQ\n");
880 et = MVS_ERR_TIMEOUT;
881 xpt_freeze_simq(ch->sim, 1);
882 ch->toslots |= (1 << slot->slot);
885 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
886 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
887 ch->transfersize / 2);
889 /* Update how far we've gotten. */
890 ch->donecount += ch->transfersize;
891 /* Do we need more? */
892 if (ccb->ataio.dxfer_len > ch->donecount) {
893 /* Set this transfer size according to HW capabilities */
894 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount,
896 /* If data write command - put them */
897 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
898 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
900 "timeout waiting for write DRQ\n");
901 et = MVS_ERR_TIMEOUT;
902 xpt_freeze_simq(ch->sim, 1);
903 ch->toslots |= (1 << slot->slot);
906 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
907 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
908 ch->transfersize / 2);
911 /* If data read command, return & wait for interrupt */
912 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
916 } else if (ch->basic_dma) { /* ATAPI DMA */
917 if (status & ATA_S_DWF)
919 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR)
921 /* Stop basic DMA. */
922 ATA_OUTL(ch->r_mem, DMA_C, 0);
924 } else { /* ATAPI PIO */
925 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) |
926 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8);
927 size = min(ch->transfersize, length);
928 ireason = ATA_INB(ch->r_mem,ATA_IREASON);
929 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) |
930 (status & ATA_S_DRQ)) {
933 device_printf(dev, "ATAPI CMDOUT\n");
934 /* Return wait for interrupt */
938 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
939 device_printf(dev, "trying to write on read buffer\n");
944 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
945 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
947 for (resid = ch->transfersize + (size & 1);
948 resid < length; resid += sizeof(int16_t))
949 ATA_OUTW(ch->r_mem, ATA_DATA, 0);
950 ch->donecount += length;
951 /* Set next transfer size according to HW capabilities */
952 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
953 ch->curr[ccb->ccb_h.target_id].bytecount);
954 /* Return wait for interrupt */
958 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
959 device_printf(dev, "trying to read on write buffer\n");
964 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
965 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
969 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1);
970 ((uint8_t *)ccb->csio.data_ptr + ch->donecount +
971 (size & ~1))[0] = buf[0];
973 for (resid = ch->transfersize + (size & 1);
974 resid < length; resid += sizeof(int16_t))
975 ATA_INW(ch->r_mem, ATA_DATA);
976 ch->donecount += length;
977 /* Set next transfer size according to HW capabilities */
978 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
979 ch->curr[ccb->ccb_h.target_id].bytecount);
980 /* Return wait for interrupt */
983 case ATAPI_P_DONEDRQ:
985 "WARNING - DONEDRQ non conformant device\n");
986 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
987 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
988 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
990 ch->donecount += length;
992 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
993 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
994 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
996 ch->donecount += length;
1004 if (status & (ATA_S_ERROR | ATA_S_DWF))
1009 device_printf(dev, "unknown transfer phase"
1010 " (status %02x, ireason %02x)\n",
1017 mvs_end_transaction(slot, et);
1021 mvs_crbq_intr(device_t dev)
1023 struct mvs_channel *ch = device_get_softc(dev);
1024 struct mvs_crpb *crpb;
1026 int in_idx, fin_idx, cin_idx, slot;
1030 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1032 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1033 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >>
1034 EDMA_RESQP_ERPQP_SHIFT;
1035 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1036 BUS_DMASYNC_POSTREAD);
1037 fin_idx = cin_idx = ch->in_idx;
1038 ch->in_idx = in_idx;
1039 while (in_idx != cin_idx) {
1040 crpb = (struct mvs_crpb *)
1041 (ch->dma.workrp + MVS_CRPB_OFFSET +
1042 (MVS_CRPB_SIZE * cin_idx));
1043 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK;
1044 flags = le16toh(crpb->rspflg);
1046 * Handle only successfull completions here.
1047 * Errors will be handled by main intr handler.
1049 #if defined(__i386__) || defined(__amd64__)
1050 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) {
1051 device_printf(dev, "Unfilled CRPB "
1052 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1053 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots);
1056 if (ch->numtslots != 0 ||
1057 (flags & EDMA_IE_EDEVERR) == 0) {
1058 #if defined(__i386__) || defined(__amd64__)
1060 crpb->rspflg = 0xffff;
1062 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) {
1063 ccb = ch->slot[slot].ccb;
1064 ccb->ataio.res.status =
1065 (flags & MVS_CRPB_ATASTS_MASK) >>
1066 MVS_CRPB_ATASTS_SHIFT;
1067 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE);
1069 device_printf(dev, "Unused tag in CRPB "
1070 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1071 cin_idx, fin_idx, in_idx, slot, flags,
1076 "CRPB with error %d tag %d flags %04x\n",
1077 cin_idx, slot, flags);
1079 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1);
1081 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1082 BUS_DMASYNC_PREREAD);
1083 if (cin_idx == ch->in_idx) {
1084 ATA_OUTL(ch->r_mem, EDMA_RESQOP,
1085 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT));
1089 /* Must be called with channel locked. */
1091 mvs_check_collision(device_t dev, union ccb *ccb)
1093 struct mvs_channel *ch = device_get_softc(dev);
1095 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1097 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1098 /* Can't mix NCQ and non-NCQ DMA commands. */
1099 if (ch->numdslots != 0)
1101 /* Can't mix NCQ and PIO commands. */
1102 if (ch->numpslots != 0)
1104 /* If we have no FBS */
1105 if (!ch->fbs_enabled) {
1106 /* Tagged command while tagged to other target is active. */
1107 if (ch->numtslots != 0 &&
1108 ch->taggedtarget != ccb->ccb_h.target_id)
1112 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1113 /* Can't mix non-NCQ DMA and NCQ commands. */
1114 if (ch->numtslots != 0)
1116 /* Can't mix non-NCQ DMA and PIO commands. */
1117 if (ch->numpslots != 0)
1121 /* Can't mix PIO with anything. */
1122 if (ch->numrslots != 0)
1125 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1126 /* Atomic command while anything active. */
1127 if (ch->numrslots != 0)
1130 } else { /* ATAPI */
1131 /* ATAPI goes without EDMA, so can't mix it with anything. */
1132 if (ch->numrslots != 0)
1135 /* We have some atomic command running. */
1136 if (ch->aslots != 0)
1142 mvs_tfd_read(device_t dev, union ccb *ccb)
1144 struct mvs_channel *ch = device_get_softc(dev);
1145 struct ata_res *res = &ccb->ataio.res;
1147 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT);
1148 res->error = ATA_INB(ch->r_mem, ATA_ERROR);
1149 res->device = ATA_INB(ch->r_mem, ATA_DRIVE);
1150 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB);
1151 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT);
1152 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR);
1153 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1154 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1155 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
1156 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT);
1157 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR);
1158 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1159 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1163 mvs_tfd_write(device_t dev, union ccb *ccb)
1165 struct mvs_channel *ch = device_get_softc(dev);
1166 struct ata_cmd *cmd = &ccb->ataio.cmd;
1168 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device);
1169 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control);
1170 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp);
1171 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features);
1172 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp);
1173 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count);
1174 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp);
1175 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low);
1176 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp);
1177 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid);
1178 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp);
1179 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high);
1180 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command);
1184 /* Must be called with channel locked. */
1186 mvs_begin_transaction(device_t dev, union ccb *ccb)
1188 struct mvs_channel *ch = device_get_softc(dev);
1189 struct mvs_slot *slot;
1192 if (ch->pm_level > 0)
1193 mvs_ch_pm_wake(dev);
1194 /* Softreset is a special case. */
1195 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1196 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1197 mvs_softreset(dev, ccb);
1200 /* Choose empty slot. */
1201 slotn = ffs(~ch->oslots) - 1;
1202 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1203 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1204 if (ch->quirks & MVS_Q_GENIIE)
1205 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1;
1210 /* Occupy chosen slot. */
1211 slot = &ch->slot[slotn];
1214 /* Stop PM timer. */
1215 if (ch->numrslots == 0 && ch->pm_level > 3)
1216 callout_stop(&ch->pm_timer);
1217 /* Update channel stats. */
1218 ch->oslots |= (1 << slot->slot);
1220 ch->numrslotspd[ccb->ccb_h.target_id]++;
1221 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1222 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1223 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag);
1225 ch->numtslotspd[ccb->ccb_h.target_id]++;
1226 ch->taggedtarget = ccb->ccb_h.target_id;
1227 mvs_set_edma_mode(dev, MVS_EDMA_NCQ);
1228 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1230 mvs_set_edma_mode(dev, MVS_EDMA_ON);
1233 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1235 if (ccb->ataio.cmd.flags &
1236 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1237 ch->aslots |= (1 << slot->slot);
1240 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1241 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes;
1243 /* Use ATAPI DMA only for commands without under-/overruns. */
1244 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1245 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA &&
1246 (ch->quirks & MVS_Q_SOC) == 0 &&
1258 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1260 if (ch->numpslots == 0 || ch->basic_dma) {
1261 slot->state = MVS_SLOT_LOADING;
1262 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map,
1263 ccb, mvs_dmasetprd, slot, 0);
1265 mvs_legacy_execute_transaction(slot);
1268 /* Locked by busdma engine. */
1270 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1272 struct mvs_slot *slot = arg;
1273 struct mvs_channel *ch = device_get_softc(slot->dev);
1274 struct mvs_eprd *eprd;
1278 device_printf(slot->dev, "DMA load error\n");
1279 mvs_end_transaction(slot, MVS_ERR_INVALID);
1282 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n"));
1283 /* If there is only one segment - no need to use S/G table on Gen-IIe. */
1284 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) {
1285 slot->dma.addr = segs[0].ds_addr;
1286 slot->dma.len = segs[0].ds_len;
1289 /* Get a piece of the workspace for this EPRD */
1290 eprd = (struct mvs_eprd *)
1291 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot));
1292 /* Fill S/G table */
1293 for (i = 0; i < nsegs; i++) {
1294 eprd[i].prdbal = htole32(segs[i].ds_addr);
1295 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK);
1296 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16);
1298 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF);
1300 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1301 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1302 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1304 mvs_legacy_execute_transaction(slot);
1306 mvs_execute_transaction(slot);
1310 mvs_legacy_execute_transaction(struct mvs_slot *slot)
1312 device_t dev = slot->dev;
1313 struct mvs_channel *ch = device_get_softc(dev);
1315 union ccb *ccb = slot->ccb;
1316 int port = ccb->ccb_h.target_id & 0x0f;
1319 slot->state = MVS_SLOT_RUNNING;
1320 ch->rslots |= (1 << slot->slot);
1321 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
1322 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1323 mvs_tfd_write(dev, ccb);
1324 /* Device reset doesn't interrupt. */
1325 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) {
1326 int timeout = 1000000;
1329 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS);
1330 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--);
1331 mvs_legacy_intr(dev, 1);
1335 if (ccb->ataio.cmd.command == ATA_READ_MUL ||
1336 ccb->ataio.cmd.command == ATA_READ_MUL48 ||
1337 ccb->ataio.cmd.command == ATA_WRITE_MUL ||
1338 ccb->ataio.cmd.command == ATA_WRITE_MUL48) {
1339 ch->transfersize = min(ccb->ataio.dxfer_len,
1340 ch->curr[port].bytecount);
1342 ch->transfersize = min(ccb->ataio.dxfer_len, 512);
1343 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE)
1345 /* If data write command - output the data */
1346 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1347 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
1349 "timeout waiting for write DRQ\n");
1350 xpt_freeze_simq(ch->sim, 1);
1351 ch->toslots |= (1 << slot->slot);
1352 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1355 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1356 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
1357 ch->transfersize / 2);
1361 ch->transfersize = min(ccb->csio.dxfer_len,
1362 ch->curr[port].bytecount);
1363 /* Write ATA PACKET command. */
1364 if (ch->basic_dma) {
1365 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA);
1366 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0);
1367 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0);
1369 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0);
1370 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize);
1371 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8);
1373 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD);
1375 /* Wait for ready to write ATAPI command block */
1376 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) {
1377 device_printf(dev, "timeout waiting for ATAPI !BUSY\n");
1378 xpt_freeze_simq(ch->sim, 1);
1379 ch->toslots |= (1 << slot->slot);
1380 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1385 int reason = ATA_INB(ch->r_mem, ATA_IREASON);
1386 int status = ATA_INB(ch->r_mem, ATA_STATUS);
1388 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
1389 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
1395 "timeout waiting for ATAPI command ready\n");
1396 xpt_freeze_simq(ch->sim, 1);
1397 ch->toslots |= (1 << slot->slot);
1398 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1401 /* Write ATAPI command. */
1402 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1403 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1404 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes),
1405 ch->curr[port].atapi / 2);
1407 if (ch->basic_dma) {
1408 /* Start basic DMA. */
1409 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET +
1410 (MVS_EPRD_SIZE * slot->slot);
1411 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd);
1412 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16);
1413 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START |
1414 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ?
1418 /* Start command execution timeout */
1419 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0,
1420 (timeout_t*)mvs_timeout, slot, 0);
1423 /* Must be called with channel locked. */
1425 mvs_execute_transaction(struct mvs_slot *slot)
1427 device_t dev = slot->dev;
1428 struct mvs_channel *ch = device_get_softc(dev);
1430 struct mvs_crqb *crqb;
1431 struct mvs_crqb_gen2e *crqb2e;
1432 union ccb *ccb = slot->ccb;
1433 int port = ccb->ccb_h.target_id & 0x0f;
1436 /* Get address of the prepared EPRD */
1437 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot);
1438 /* Prepare CRQB. Gen IIe uses different CRQB format. */
1439 if (ch->quirks & MVS_Q_GENIIE) {
1440 crqb2e = (struct mvs_crqb_gen2e *)
1441 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1442 crqb2e->ctrlflg = htole32(
1443 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) |
1444 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) |
1445 (port << MVS_CRQB2E_PMP_SHIFT) |
1446 (slot->slot << MVS_CRQB2E_HTAG_SHIFT));
1447 /* If there is only one segment - no need to use S/G table. */
1448 if (slot->dma.addr != 0) {
1449 eprd = slot->dma.addr;
1450 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD);
1451 crqb2e->drbc = slot->dma.len;
1453 crqb2e->cprdbl = htole32(eprd);
1454 crqb2e->cprdbh = htole32((eprd >> 16) >> 16);
1457 crqb2e->cmd[2] = ccb->ataio.cmd.command;
1458 crqb2e->cmd[3] = ccb->ataio.cmd.features;
1459 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low;
1460 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid;
1461 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high;
1462 crqb2e->cmd[7] = ccb->ataio.cmd.device;
1463 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp;
1464 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp;
1465 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp;
1466 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp;
1467 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1468 crqb2e->cmd[12] = slot->tag << 3;
1469 crqb2e->cmd[13] = 0;
1471 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count;
1472 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp;
1474 crqb2e->cmd[14] = 0;
1475 crqb2e->cmd[15] = 0;
1477 crqb = (struct mvs_crqb *)
1478 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1479 crqb->cprdbl = htole32(eprd);
1480 crqb->cprdbh = htole32((eprd >> 16) >> 16);
1481 crqb->ctrlflg = htole16(
1482 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) |
1483 (slot->slot << MVS_CRQB_TAG_SHIFT) |
1484 (port << MVS_CRQB_PMP_SHIFT));
1487 * Controller can handle only 11 of 12 ATA registers,
1488 * so we have to choose which one to skip.
1490 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1491 crqb->cmd[i++] = ccb->ataio.cmd.features_exp;
1492 crqb->cmd[i++] = 0x11;
1494 crqb->cmd[i++] = ccb->ataio.cmd.features;
1495 crqb->cmd[i++] = 0x11;
1496 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1497 crqb->cmd[i++] = slot->tag << 3;
1498 crqb->cmd[i++] = 0x12;
1500 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp;
1501 crqb->cmd[i++] = 0x12;
1502 crqb->cmd[i++] = ccb->ataio.cmd.sector_count;
1503 crqb->cmd[i++] = 0x12;
1505 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp;
1506 crqb->cmd[i++] = 0x13;
1507 crqb->cmd[i++] = ccb->ataio.cmd.lba_low;
1508 crqb->cmd[i++] = 0x13;
1509 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp;
1510 crqb->cmd[i++] = 0x14;
1511 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid;
1512 crqb->cmd[i++] = 0x14;
1513 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp;
1514 crqb->cmd[i++] = 0x15;
1515 crqb->cmd[i++] = ccb->ataio.cmd.lba_high;
1516 crqb->cmd[i++] = 0x15;
1517 crqb->cmd[i++] = ccb->ataio.cmd.device;
1518 crqb->cmd[i++] = 0x16;
1519 crqb->cmd[i++] = ccb->ataio.cmd.command;
1520 crqb->cmd[i++] = 0x97;
1522 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1523 BUS_DMASYNC_PREWRITE);
1524 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1525 BUS_DMASYNC_PREREAD);
1526 slot->state = MVS_SLOT_RUNNING;
1527 ch->rslots |= (1 << slot->slot);
1528 /* Issue command to the controller. */
1529 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1);
1530 ATA_OUTL(ch->r_mem, EDMA_REQQIP,
1531 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1532 /* Start command execution timeout */
1533 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0,
1534 (timeout_t*)mvs_timeout, slot, 0);
1538 /* Must be called with channel locked. */
1540 mvs_process_timeout(device_t dev)
1542 struct mvs_channel *ch = device_get_softc(dev);
1545 mtx_assert(&ch->mtx, MA_OWNED);
1546 /* Handle the rest of commands. */
1547 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1548 /* Do we have a running request on slot? */
1549 if (ch->slot[i].state < MVS_SLOT_RUNNING)
1551 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT);
1555 /* Must be called with channel locked. */
1557 mvs_rearm_timeout(device_t dev)
1559 struct mvs_channel *ch = device_get_softc(dev);
1562 mtx_assert(&ch->mtx, MA_OWNED);
1563 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1564 struct mvs_slot *slot = &ch->slot[i];
1566 /* Do we have a running request on slot? */
1567 if (slot->state < MVS_SLOT_RUNNING)
1569 if ((ch->toslots & (1 << i)) == 0)
1571 callout_reset_sbt(&slot->timeout,
1572 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1573 (timeout_t*)mvs_timeout, slot, 0);
1577 /* Locked by callout mechanism. */
1579 mvs_timeout(struct mvs_slot *slot)
1581 device_t dev = slot->dev;
1582 struct mvs_channel *ch = device_get_softc(dev);
1584 /* Check for stale timeout. */
1585 if (slot->state < MVS_SLOT_RUNNING)
1587 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1588 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x "
1589 "dma_c %08x dma_s %08x rs %08x status %02x\n",
1590 ATA_INL(ch->r_mem, EDMA_IEC),
1591 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE),
1592 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C),
1593 ATA_INL(ch->r_mem, DMA_S), ch->rslots,
1594 ATA_INB(ch->r_mem, ATA_ALTSTAT));
1595 /* Handle frozen command. */
1596 mvs_requeue_frozen(dev);
1597 /* We wait for other commands timeout and pray. */
1598 if (ch->toslots == 0)
1599 xpt_freeze_simq(ch->sim, 1);
1600 ch->toslots |= (1 << slot->slot);
1601 if ((ch->rslots & ~ch->toslots) == 0)
1602 mvs_process_timeout(dev);
1604 device_printf(dev, " ... waiting for slots %08x\n",
1605 ch->rslots & ~ch->toslots);
1608 /* Must be called with channel locked. */
1610 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
1612 device_t dev = slot->dev;
1613 struct mvs_channel *ch = device_get_softc(dev);
1614 union ccb *ccb = slot->ccb;
1617 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1618 BUS_DMASYNC_POSTWRITE);
1619 /* Read result registers to the result struct
1620 * May be incorrect if several commands finished same time,
1621 * so read only when sure or have to.
1623 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1624 struct ata_res *res = &ccb->ataio.res;
1626 if ((et == MVS_ERR_TFE) ||
1627 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1628 mvs_tfd_read(dev, ccb);
1630 bzero(res, sizeof(*res));
1632 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1634 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount;
1636 if (ch->numpslots == 0 || ch->basic_dma) {
1637 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1638 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1639 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1640 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1641 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1644 if (et != MVS_ERR_NONE)
1645 ch->eslots |= (1 << slot->slot);
1646 /* In case of error, freeze device for proper recovery. */
1647 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) &&
1648 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1649 xpt_freeze_devq(ccb->ccb_h.path, 1);
1650 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1652 /* Set proper result status. */
1653 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1656 ccb->ccb_h.status |= CAM_REQ_CMP;
1657 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1658 ccb->csio.scsi_status = SCSI_STATUS_OK;
1660 case MVS_ERR_INVALID:
1662 ccb->ccb_h.status |= CAM_REQ_INVALID;
1664 case MVS_ERR_INNOCENT:
1665 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1669 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1670 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1671 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1673 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1678 if (!ch->recoverycmd) {
1679 xpt_freeze_simq(ch->sim, 1);
1680 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1681 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1683 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1685 case MVS_ERR_TIMEOUT:
1686 if (!ch->recoverycmd) {
1687 xpt_freeze_simq(ch->sim, 1);
1688 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1689 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1691 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1695 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1698 ch->oslots &= ~(1 << slot->slot);
1699 ch->rslots &= ~(1 << slot->slot);
1700 ch->aslots &= ~(1 << slot->slot);
1701 slot->state = MVS_SLOT_EMPTY;
1703 /* Update channel stats. */
1705 ch->numrslotspd[ccb->ccb_h.target_id]--;
1706 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1707 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1708 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag);
1710 ch->numtslotspd[ccb->ccb_h.target_id]--;
1711 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1720 /* Cancel timeout state if request completed normally. */
1721 if (et != MVS_ERR_TIMEOUT) {
1722 lastto = (ch->toslots == (1 << slot->slot));
1723 ch->toslots &= ~(1 << slot->slot);
1725 xpt_release_simq(ch->sim, TRUE);
1727 /* If it was our READ LOG command - process it. */
1728 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1729 mvs_process_read_log(dev, ccb);
1730 /* If it was our REQUEST SENSE command - process it. */
1731 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1732 mvs_process_request_sense(dev, ccb);
1733 /* If it was NCQ or ATAPI command error, put result on hold. */
1734 } else if (et == MVS_ERR_NCQ ||
1735 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1736 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1737 ch->hold[slot->slot] = ccb;
1738 ch->holdtag[slot->slot] = slot->tag;
1742 /* If we have no other active commands, ... */
1743 if (ch->rslots == 0) {
1744 /* if there was fatal error - reset port. */
1745 if (ch->toslots != 0 || ch->fatalerr) {
1748 /* if we have slots in error, we can reinit port. */
1749 if (ch->eslots != 0) {
1750 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1753 /* if there commands on hold, we can do READ LOG. */
1754 if (!ch->recoverycmd && ch->numhslots)
1755 mvs_issue_recovery(dev);
1757 /* If all the rest of commands are in timeout - give them chance. */
1758 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1759 et != MVS_ERR_TIMEOUT)
1760 mvs_rearm_timeout(dev);
1761 /* Unfreeze frozen command. */
1762 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
1763 union ccb *fccb = ch->frozen;
1765 mvs_begin_transaction(dev, fccb);
1766 xpt_release_simq(ch->sim, TRUE);
1768 /* Start PM timer. */
1769 if (ch->numrslots == 0 && ch->pm_level > 3 &&
1770 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1771 callout_schedule(&ch->pm_timer,
1772 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1777 mvs_issue_recovery(device_t dev)
1779 struct mvs_channel *ch = device_get_softc(dev);
1781 struct ccb_ataio *ataio;
1782 struct ccb_scsiio *csio;
1785 /* Find some held command. */
1786 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1790 ccb = xpt_alloc_ccb_nowait();
1792 device_printf(dev, "Unable to allocate recovery command\n");
1794 /* We can't do anything -- complete held commands. */
1795 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1796 if (ch->hold[i] == NULL)
1798 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1799 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
1800 xpt_done(ch->hold[i]);
1807 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
1808 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1810 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
1811 ccb->ccb_h.func_code = XPT_ATA_IO;
1812 ccb->ccb_h.flags = CAM_DIR_IN;
1813 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1814 ataio = &ccb->ataio;
1815 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT);
1816 if (ataio->data_ptr == NULL) {
1819 "Unable to allocate memory for READ LOG command\n");
1822 ataio->dxfer_len = 512;
1823 bzero(&ataio->cmd, sizeof(ataio->cmd));
1824 ataio->cmd.flags = CAM_ATAIO_48BIT;
1825 ataio->cmd.command = 0x2F; /* READ LOG EXT */
1826 ataio->cmd.sector_count = 1;
1827 ataio->cmd.sector_count_exp = 0;
1828 ataio->cmd.lba_low = 0x10;
1829 ataio->cmd.lba_mid = 0;
1830 ataio->cmd.lba_mid_exp = 0;
1833 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
1834 ccb->ccb_h.recovery_slot = i;
1835 ccb->ccb_h.func_code = XPT_SCSI_IO;
1836 ccb->ccb_h.flags = CAM_DIR_IN;
1837 ccb->ccb_h.status = 0;
1838 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1840 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
1841 csio->dxfer_len = ch->hold[i]->csio.sense_len;
1843 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
1844 csio->cdb_io.cdb_bytes[0] = 0x03;
1845 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
1847 /* Freeze SIM while doing recovery. */
1848 ch->recoverycmd = 1;
1849 xpt_freeze_simq(ch->sim, 1);
1850 mvs_begin_transaction(dev, ccb);
1854 mvs_process_read_log(device_t dev, union ccb *ccb)
1856 struct mvs_channel *ch = device_get_softc(dev);
1858 struct ata_res *res;
1861 ch->recoverycmd = 0;
1863 data = ccb->ataio.data_ptr;
1864 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
1865 (data[0] & 0x80) == 0) {
1866 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1869 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1871 if ((data[0] & 0x1F) == ch->holdtag[i]) {
1872 res = &ch->hold[i]->ataio.res;
1873 res->status = data[2];
1874 res->error = data[3];
1875 res->lba_low = data[4];
1876 res->lba_mid = data[5];
1877 res->lba_high = data[6];
1878 res->device = data[7];
1879 res->lba_low_exp = data[8];
1880 res->lba_mid_exp = data[9];
1881 res->lba_high_exp = data[10];
1882 res->sector_count = data[12];
1883 res->sector_count_exp = data[13];
1885 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1886 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
1888 xpt_done(ch->hold[i]);
1893 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
1894 device_printf(dev, "Error while READ LOG EXT\n");
1895 else if ((data[0] & 0x80) == 0) {
1897 "Non-queued command error in READ LOG EXT\n");
1899 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1902 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1904 xpt_done(ch->hold[i]);
1909 free(ccb->ataio.data_ptr, M_MVS);
1911 xpt_release_simq(ch->sim, TRUE);
1915 mvs_process_request_sense(device_t dev, union ccb *ccb)
1917 struct mvs_channel *ch = device_get_softc(dev);
1920 ch->recoverycmd = 0;
1922 i = ccb->ccb_h.recovery_slot;
1923 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
1924 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
1926 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1927 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
1929 xpt_done(ch->hold[i]);
1933 xpt_release_simq(ch->sim, TRUE);
1937 mvs_wait(device_t dev, u_int s, u_int c, int t)
1942 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) {
1945 device_printf(dev, "Wait status %02x\n", st);
1955 mvs_requeue_frozen(device_t dev)
1957 struct mvs_channel *ch = device_get_softc(dev);
1958 union ccb *fccb = ch->frozen;
1962 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1963 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1964 xpt_freeze_devq(fccb->ccb_h.path, 1);
1965 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1972 mvs_reset_to(void *arg)
1975 struct mvs_channel *ch = device_get_softc(dev);
1978 if (ch->resetting == 0)
1981 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) {
1984 "MVS reset: device ready after %dms\n",
1985 (310 - ch->resetting) * 100);
1988 xpt_release_simq(ch->sim, TRUE);
1991 if (ch->resetting == 0) {
1993 "MVS reset: device not ready after 31000ms\n");
1994 xpt_release_simq(ch->sim, TRUE);
1997 callout_schedule(&ch->reset_timer, hz / 10);
2001 mvs_errata(device_t dev)
2003 struct mvs_channel *ch = device_get_softc(dev);
2006 if (ch->quirks & MVS_Q_SOC65) {
2007 val = ATA_INL(ch->r_mem, SATA_PHYM3);
2008 val &= ~(0x3 << 27); /* SELMUPF = 1 */
2010 val &= ~(0x3 << 29); /* SELMUPI = 1 */
2012 ATA_OUTL(ch->r_mem, SATA_PHYM3, val);
2014 val = ATA_INL(ch->r_mem, SATA_PHYM4);
2015 val &= ~0x1; /* SATU_OD8 = 0 */
2016 val |= (0x1 << 16); /* reserved bit 16 = 1 */
2017 ATA_OUTL(ch->r_mem, SATA_PHYM4, val);
2019 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2);
2020 val &= ~0xf; /* TXAMP[3:0] = 8 */
2022 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2023 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val);
2025 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1);
2026 val &= ~0xf; /* TXAMP[3:0] = 8 */
2028 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2029 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val);
2034 mvs_reset(device_t dev)
2036 struct mvs_channel *ch = device_get_softc(dev);
2039 xpt_freeze_simq(ch->sim, 1);
2041 device_printf(dev, "MVS reset...\n");
2042 /* Forget about previous reset. */
2043 if (ch->resetting) {
2045 callout_stop(&ch->reset_timer);
2046 xpt_release_simq(ch->sim, TRUE);
2048 /* Requeue freezed command. */
2049 mvs_requeue_frozen(dev);
2050 /* Kill the engine and requeue all running commands. */
2051 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2052 ATA_OUTL(ch->r_mem, DMA_C, 0);
2053 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2054 /* Do we have a running request on slot? */
2055 if (ch->slot[i].state < MVS_SLOT_RUNNING)
2057 /* XXX; Commands in loading state. */
2058 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT);
2060 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2063 xpt_done(ch->hold[i]);
2067 if (ch->toslots != 0)
2068 xpt_release_simq(ch->sim, TRUE);
2073 /* Tell the XPT about the event */
2074 xpt_async(AC_BUS_RESET, ch->path, NULL);
2075 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
2076 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST);
2078 ATA_OUTL(ch->r_mem, EDMA_CMD, 0);
2080 /* Reset and reconnect PHY, */
2081 if (!mvs_sata_phy_reset(dev)) {
2083 device_printf(dev, "MVS reset: device not found\n");
2085 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2086 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2087 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2088 xpt_release_simq(ch->sim, TRUE);
2092 device_printf(dev, "MVS reset: device found\n");
2093 /* Wait for clearing busy status. */
2094 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ,
2095 dumping ? 31000 : 0)) < 0) {
2098 "MVS reset: device not ready after 31000ms\n");
2100 ch->resetting = 310;
2101 } else if (bootverbose)
2102 device_printf(dev, "MVS reset: device ready after %dms\n", i);
2104 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2105 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2106 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2108 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev);
2110 xpt_release_simq(ch->sim, TRUE);
2114 mvs_softreset(device_t dev, union ccb *ccb)
2116 struct mvs_channel *ch = device_get_softc(dev);
2117 int port = ccb->ccb_h.target_id & 0x0f;
2121 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2122 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
2123 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2125 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2126 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2127 /* Wait for clearing busy status. */
2128 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) {
2129 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2132 status = mvs_getstatus(dev, 0);
2133 if (status & ATA_S_ERROR)
2134 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2136 ccb->ccb_h.status |= CAM_REQ_CMP;
2137 if (status & ATA_S_DRQ)
2142 mvs_tfd_read(dev, ccb);
2145 * XXX: If some device on PMP failed to soft-reset,
2146 * try to recover by sending dummy soft-reset to PMP.
2148 if (stuck && ch->pm_present && port != 15) {
2149 ATA_OUTB(ch->r_mem, SATA_SATAICTL,
2150 15 << SATA_SATAICTL_PMPTX_SHIFT);
2151 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2153 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2154 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout);
2161 mvs_sata_connect(struct mvs_channel *ch)
2164 int timeout, found = 0;
2166 /* Wait up to 100ms for "connect well" */
2167 for (timeout = 0; timeout < 1000 ; timeout++) {
2168 status = ATA_INL(ch->r_mem, SATA_SS);
2169 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE)
2171 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
2172 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
2173 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE))
2175 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) {
2177 device_printf(ch->dev, "SATA offline status=%08x\n",
2182 if (found == 0 && timeout >= 100)
2186 if (timeout >= 1000 || !found) {
2188 device_printf(ch->dev,
2189 "SATA connect timeout time=%dus status=%08x\n",
2190 timeout * 100, status);
2195 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2196 timeout * 100, status);
2198 /* Clear SATA error register */
2199 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2204 mvs_sata_phy_reset(device_t dev)
2206 struct mvs_channel *ch = device_get_softc(dev);
2210 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2212 val = SATA_SC_SPD_SPEED_GEN1;
2213 else if (sata_rev == 2)
2214 val = SATA_SC_SPD_SPEED_GEN2;
2215 else if (sata_rev == 3)
2216 val = SATA_SC_SPD_SPEED_GEN3;
2219 ATA_OUTL(ch->r_mem, SATA_SC,
2220 SATA_SC_DET_RESET | val |
2221 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER);
2223 ATA_OUTL(ch->r_mem, SATA_SC,
2224 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2225 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER)));
2226 if (!mvs_sata_connect(ch)) {
2227 if (ch->pm_level > 0)
2228 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE);
2235 mvs_check_ids(device_t dev, union ccb *ccb)
2237 struct mvs_channel *ch = device_get_softc(dev);
2239 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) {
2240 ccb->ccb_h.status = CAM_TID_INVALID;
2244 if (ccb->ccb_h.target_lun != 0) {
2245 ccb->ccb_h.status = CAM_LUN_INVALID;
2253 mvsaction(struct cam_sim *sim, union ccb *ccb)
2255 device_t dev, parent;
2256 struct mvs_channel *ch;
2258 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n",
2259 ccb->ccb_h.func_code));
2261 ch = (struct mvs_channel *)cam_sim_softc(sim);
2263 switch (ccb->ccb_h.func_code) {
2264 /* Common cases first */
2265 case XPT_ATA_IO: /* Execute the requested I/O operation */
2267 if (mvs_check_ids(dev, ccb))
2269 if (ch->devices == 0 ||
2270 (ch->pm_present == 0 &&
2271 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2272 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2275 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2276 /* Check for command collision. */
2277 if (mvs_check_collision(dev, ccb)) {
2278 /* Freeze command. */
2280 /* We have only one frozen slot, so freeze simq also. */
2281 xpt_freeze_simq(ch->sim, 1);
2284 mvs_begin_transaction(dev, ccb);
2286 case XPT_EN_LUN: /* Enable LUN as a target */
2287 case XPT_TARGET_IO: /* Execute target I/O request */
2288 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2289 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2290 case XPT_ABORT: /* Abort the specified CCB */
2292 ccb->ccb_h.status = CAM_REQ_INVALID;
2294 case XPT_SET_TRAN_SETTINGS:
2296 struct ccb_trans_settings *cts = &ccb->cts;
2297 struct mvs_device *d;
2299 if (mvs_check_ids(dev, ccb))
2301 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2302 d = &ch->curr[ccb->ccb_h.target_id];
2304 d = &ch->user[ccb->ccb_h.target_id];
2305 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2306 d->revision = cts->xport_specific.sata.revision;
2307 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2308 d->mode = cts->xport_specific.sata.mode;
2309 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) {
2310 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048,
2311 cts->xport_specific.sata.bytecount);
2313 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2314 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags);
2315 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2316 ch->pm_present = cts->xport_specific.sata.pm_present;
2317 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2318 d->atapi = cts->xport_specific.sata.atapi;
2319 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2320 d->caps = cts->xport_specific.sata.caps;
2321 ccb->ccb_h.status = CAM_REQ_CMP;
2324 case XPT_GET_TRAN_SETTINGS:
2325 /* Get default/user set transfer settings for the target */
2327 struct ccb_trans_settings *cts = &ccb->cts;
2328 struct mvs_device *d;
2331 if (mvs_check_ids(dev, ccb))
2333 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2334 d = &ch->curr[ccb->ccb_h.target_id];
2336 d = &ch->user[ccb->ccb_h.target_id];
2337 cts->protocol = PROTO_UNSPECIFIED;
2338 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2339 cts->transport = XPORT_SATA;
2340 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2341 cts->proto_specific.valid = 0;
2342 cts->xport_specific.sata.valid = 0;
2343 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2344 (ccb->ccb_h.target_id == 15 ||
2345 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2346 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK;
2347 if (status & 0x0f0) {
2348 cts->xport_specific.sata.revision =
2349 (status & 0x0f0) >> 4;
2350 cts->xport_specific.sata.valid |=
2351 CTS_SATA_VALID_REVISION;
2353 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2354 // if (ch->pm_level)
2355 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2356 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2357 cts->xport_specific.sata.caps &=
2358 ch->user[ccb->ccb_h.target_id].caps;
2359 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2361 cts->xport_specific.sata.revision = d->revision;
2362 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2363 cts->xport_specific.sata.caps = d->caps;
2364 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* &&
2365 (ch->quirks & MVS_Q_GENIIE) == 0*/)
2366 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN;
2367 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2369 cts->xport_specific.sata.mode = d->mode;
2370 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2371 cts->xport_specific.sata.bytecount = d->bytecount;
2372 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2373 cts->xport_specific.sata.pm_present = ch->pm_present;
2374 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2375 cts->xport_specific.sata.tags = d->tags;
2376 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2377 cts->xport_specific.sata.atapi = d->atapi;
2378 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2379 ccb->ccb_h.status = CAM_REQ_CMP;
2382 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2383 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2385 ccb->ccb_h.status = CAM_REQ_CMP;
2387 case XPT_TERM_IO: /* Terminate the I/O process */
2389 ccb->ccb_h.status = CAM_REQ_INVALID;
2391 case XPT_PATH_INQ: /* Path routing inquiry */
2393 struct ccb_pathinq *cpi = &ccb->cpi;
2395 parent = device_get_parent(dev);
2396 cpi->version_num = 1; /* XXX??? */
2397 cpi->hba_inquiry = PI_SDTR_ABLE;
2398 if (!(ch->quirks & MVS_Q_GENI)) {
2399 cpi->hba_inquiry |= PI_SATAPM;
2400 /* Gen-II is extremely slow with NCQ on PMP. */
2401 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0)
2402 cpi->hba_inquiry |= PI_TAG_ABLE;
2404 cpi->target_sprt = 0;
2405 cpi->hba_misc = PIM_SEQSCAN;
2406 cpi->hba_eng_cnt = 0;
2407 if (!(ch->quirks & MVS_Q_GENI))
2408 cpi->max_target = 15;
2410 cpi->max_target = 0;
2412 cpi->initiator_id = 0;
2413 cpi->bus_id = cam_sim_bus(sim);
2414 cpi->base_transfer_speed = 150000;
2415 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2416 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN);
2417 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2418 cpi->unit_number = cam_sim_unit(sim);
2419 cpi->transport = XPORT_SATA;
2420 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2421 cpi->protocol = PROTO_ATA;
2422 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2423 cpi->maxio = MAXPHYS;
2424 if ((ch->quirks & MVS_Q_SOC) == 0) {
2425 cpi->hba_vendor = pci_get_vendor(parent);
2426 cpi->hba_device = pci_get_device(parent);
2427 cpi->hba_subvendor = pci_get_subvendor(parent);
2428 cpi->hba_subdevice = pci_get_subdevice(parent);
2430 cpi->ccb_h.status = CAM_REQ_CMP;
2434 ccb->ccb_h.status = CAM_REQ_INVALID;
2441 mvspoll(struct cam_sim *sim)
2443 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim);
2444 struct mvs_intr_arg arg;
2447 arg.cause = 2 | 4; /* XXX */
2449 if (ch->resetting != 0 &&
2450 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2451 ch->resetpolldiv = 1000;
2452 mvs_reset_to(ch->dev);