1 /*******************************************************************************
2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided
5 *that the following conditions are met:
6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
8 *2. Redistributions in binary form must reproduce the above copyright notice,
9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided
10 *with the distribution.
12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
23 ********************************************************************************/
24 /********************************************************************************
26 ** Version Control Information:
29 *******************************************************************************/
30 /********************************************************************************
34 ** Abstract: This module contains data structure definition used
35 ** by the Transport Independent API (TIAPI) Layer.
37 ********************************************************************************/
39 #include <dev/pms/RefTisa/tisa/api/tidefs.h>
44 /*****************************************************************************
46 *****************************************************************************/
48 typedef struct tiPortalContext
54 typedef struct tiDeviceHandle
74 bit32 singleElementLength;
80 typedef struct tiLoLevelMem
83 tiMem_t mem[MAX_LL_LAYER_MEM_DESCRIPTORS];
86 typedef struct tiLoLevelOption
89 bit32 numOfQueuesPerPort;
91 bit32 pciFunctionNumber;
95 bit32 maxInterruptVectors;
97 bit32 max_MSI_InterruptVectors;
98 #ifdef SA_ENABLE_PCI_TRIGGER
100 #endif /* SA_ENABLE_PCI_TRIGGER */
104 typedef struct tiLoLevelResource
106 tiLoLevelOption_t loLevelOption;
107 tiLoLevelMem_t loLevelMem;
108 } tiLoLevelResource_t;
110 typedef struct tiTdSharedMem
112 tiMem_t tdSharedCachedMem1;
115 typedef struct tiIORequest
121 typedef struct tiSgl_s
129 typedef struct tiSenseData
135 typedef struct tiIOCTLPayload
142 bit32 Reserved; /* required for 64 bit alignment */
143 bit8 FunctionSpecificArea[1];
147 typedef struct tiIOCTLPayload_wwn
154 bit32 Reserved; /* required for 64 bit alignment */
155 bit8 FunctionSpecificArea[8];
156 }tiIOCTLPayload_wwn_t;
158 typedef struct tiPortInfo
168 typedef struct tiDif_s
170 agBOOLEAN enableDIFPerLA;
174 bit32 DIFPerLAAddrLo;
175 bit32 DIFPerLAAddrHi;
176 bit16 DIFPerLARegion0SecCount;
177 bit16 DIFPerLANumOfRegions;
178 bit8 udtArray[DIF_UDT_SIZE];
179 bit8 udtrArray[DIF_UDT_SIZE];
183 #define DIF_VERIFY_FORWARD 1
184 #define DIF_VERIFY_DELETE 2
185 #define DIF_VERIFY_REPLACE 3
186 #define DIF_VERIFY_UDT_REPLACE_CRC 5
187 #define DIF_REPLACE_UDT_REPLACE_CRC 7
189 #define DIF_BLOCK_SIZE_512 0x00
190 #define DIF_BLOCK_SIZE_520 0x01
191 #define DIF_BLOCK_SIZE_4096 0x02
192 #define DIF_BLOCK_SIZE_4160 0x03
194 #define DIF_ACTION_FLAG_MASK 0x00000007 /* 0 - 2 */
195 #define DIF_CRC_VERIFICATION 0x00000008 /* 3 */
196 #define DIF_CRC_INVERSION 0x00000010 /* 4 */
197 #define DIF_CRC_IO_SEED 0x00000020 /* 5 */
198 #define DIF_UDT_REF_BLOCK_COUNT 0x00000040 /* 6 */
199 #define DIF_UDT_APP_BLOCK_COUNT 0x00000080 /* 7 */
200 #define DIF_UDTR_REF_BLOCK_COUNT 0x00000100 /* 8 */
201 #define DIF_UDTR_APP_BLOCK_COUNT 0x00000200 /* 9 */
202 #define DIF_CUST_APP_TAG 0x00000C00 /* 10 - 11 */
203 #define DIF_FLAG_RESERVED 0x0000F000 /* 12 - 15 */
204 #define DIF_DATA_BLOCK_SIZE_MASK 0x000F0000 /* 16 - 19 */
205 #define DIF_DATA_BLOCK_SIZE_SHIFT 16
206 #define DIF_TAG_VERIFY_MASK 0x03F00000 /* 20 - 25 */
207 #define DIF_TAG_UPDATE_MASK 0xFC000000 /* 26 - 31 */
210 #define NORMAL_BLOCK_SIZE_512 512
211 #define NORMAL_BLOCK_SIZE_4K 4096
213 #define DIF_PHY_BLOCK_SIZE_512 512
214 #define DIF_PHY_BLOCK_SIZE_520 520
215 #define DIF_PHY_BLOCK_SIZE_4096 4096
216 #define DIF_PHY_BLOCK_SIZE_4160 4160
218 #define DIF_LOGIC_BLOCK_SIZE_520 520
219 #define DIF_LOGIC_BLOCK_SIZE_528 528
220 #define DIF_LOGIC_BLOCK_SIZE_4104 4104
221 #define DIF_LOGIC_BLOCK_SIZE_4168 4168
226 typedef struct tiDetailedDeviceInfo
230 Bit 4-5: Two bits flag to specify a SAS or SATA (STP) device:
231 00: SATA or STP device
232 01: SSP or SMP device
233 10: Direct SATA device
234 Bit 0-3: Connection Rate field when opening the device.
236 00h: Device has not been registered
244 } tiDetailedDeviceInfo_t;
246 typedef struct tiDeviceInfo
255 tiDetailedDeviceInfo_t info;
259 #define KEK_BLOB_SIZE 48
260 #define KEK_AUTH_SIZE 40
261 #define KEK_MAX_TABLE_ENTRIES 8
263 #define DEK_MAX_TABLES 2
264 #define DEK_MAX_TABLE_ENTRIES (1024*4)
266 #define DEK_BLOB_SIZE_07 72
267 #define DEK_BLOB_SIZE_08 80
269 #define OPERATOR_ROLE_ID_SIZE 1024
271 #define HMAC_SECRET_KEY_SIZE 72
273 typedef struct tiEncryptKekBlob
275 bit8 kekBlob[KEK_BLOB_SIZE];
276 } tiEncryptKekBlob_t;
278 typedef struct tiEncryptDekBlob
280 bit8 dekBlob[DEK_BLOB_SIZE_08];
281 } tiEncryptDekBlob_t;
283 typedef struct DEK_Table_s {
284 tiEncryptDekBlob_t Dek[DEK_MAX_TABLE_ENTRIES];
287 typedef struct DEK_Tables_s {
288 tiDEK_Table_t DekTable[DEK_MAX_TABLES];
292 #define OPR_MGMT_ID_STRING_SIZE 31
294 typedef struct tiID_s {
295 bit8 ID[OPR_MGMT_ID_STRING_SIZE];
298 typedef struct tiEncryptInfo
300 bit32 securityCipherMode;
305 typedef struct tiEncryptPort
312 typedef struct tiEncryptDek
318 typedef struct tiEncrypt
320 tiEncryptDek_t dekInfo;
322 agBOOLEAN keyTagCheck;
323 agBOOLEAN enableEncryptionPerLA;
324 bit32 sectorSizeIndex;
332 bit32 EncryptionPerLAAddrLo;
333 bit32 EncryptionPerLAAddrHi;
334 bit16 EncryptionPerLRegion0SecCount;
338 typedef struct tiHWEventMode_s
340 bit32 modePageOperation;
347 /*****************************************************************************
349 *****************************************************************************/
351 typedef struct tiInitiatorMem
354 tiMem_t tdCachedMem[6];
357 typedef struct tiInitiatorOption
361 tiMem_t dynamicDmaMem;
362 tiMem_t dynamicCachedMem;
363 bit32 ioRequestBodySize;
364 } tiInitiatorOption_t;
367 typedef struct tiInitiatorResource
369 tiInitiatorOption_t initiatorOption;
370 tiInitiatorMem_t initiatorMem;
371 } tiInitiatorResource_t;
378 typedef struct tiIniScsiCmnd
387 typedef struct tiScsiInitiatorRequest
389 void *sglVirtualAddr;
390 tiIniScsiCmnd_t scsiCmnd;
392 tiDataDirection_t dataDirection;
393 } tiScsiInitiatorRequest_t;
395 /* This is the standard request body for I/O that requires DIF or encryption. */
396 typedef struct tiSuperScsiInitiatorRequest
398 void *sglVirtualAddr;
399 tiIniScsiCmnd_t scsiCmnd;
401 tiDataDirection_t dataDirection;
403 #ifdef CCBUILD_INDIRECT_CDB
404 bit32 IndCDBLowAddr; /* The low physical address of indirect CDB buffer in host memory */
405 bit32 IndCDBHighAddr; /* The high physical address of indirect CDB buffer in host memory */
406 bit32 IndCDBLength; /* Indirect CDB length */
407 void *IndCDBBuffer; /* Indirect SSPIU buffer */
411 } tiSuperScsiInitiatorRequest_t;
413 typedef struct tiSMPFrame
416 bit32 outFrameAddrUpper32;
417 bit32 outFrameAddrLower32;
419 bit32 inFrameAddrUpper32;
420 bit32 inFrameAddrLower32;
422 bit32 expectedRespLen;
425 typedef struct tiEVTData
432 bit8 BinaryDataLength;
433 bit8 DataAndMessage[EVENTLOG_MAX_MSG_LEN];
436 typedef bit32 (*IsrHandler_t)(
440 typedef void (*DeferedHandler_t)(
447 /*****************************************************************************
449 *****************************************************************************/
451 typedef struct tiTargetMem {
456 typedef struct tiTargetOption {
462 tiMem_t dynamicDmaMem;
463 tiMem_t dynamicCachedMem;
468 tiTargetOption_t targetOption;
469 tiTargetMem_t targetMem;
470 } tiTargetResource_t;
479 } tiTargetScsiCmnd_t;
481 typedef struct tiSuperScsiTargetRequest
487 void *sglVirtualAddr;
489 void *sglVirtualAddrMirror;
492 } tiSuperScsiTargetRequest_t;
494 /* SPCv controller mode page definitions */
495 typedef struct tiEncryptGeneralPage_s {
496 bit32 pageCode; /* 0x20 */
498 } tiEncryptGeneralPage_t;
500 #define TD_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
501 #define TD_ENC_CONFIG_PAGE_KEK_SHIFT 8
503 typedef struct tiEncryptDekConfigPage
505 bit32 pageCode; /* 0x21 */
514 } tiEncryptDekConfigPage_t;
516 #define TD_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
517 #define TD_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAYS 0x0F000000
518 #define TD_ENC_DEK_CONFIG_PAGE_DPR 0x00000200
519 #define TD_ENC_DEK_CONFIG_PAGE_DER 0x00000100
520 #define TD_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT 24
521 #define TD_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT 28
522 #define TD_ENC_DEK_CONFIG_PAGE_DEK_HDP_SHIFT 8
525 /* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */
526 /* NAR, CORCAP and USRCAP are valid only when AUT==1 */
527 typedef struct tiEncryptControlParamPage_s {
528 bit32 PageCode; /* 0x22 */
529 bit32 CORCAP; /* Crypto Officer Role Capabilities */
530 bit32 USRCAP; /* User Role Capabilities */
531 bit32 CCS; /* Current Crypto Services */
532 bit32 NOPR; /* Number of Operators */
533 } tiEncryptControlParamPage_t;
535 typedef struct tiEncryptHMACConfigPage_s
541 } tiEncryptHMACConfigPage_t;
543 typedef struct tiInterruptConfigPage_s {
544 bit32 pageCode; /* 0x05 */
555 } tiInterruptConfigPage_t;
557 /* brief data structure for SAS protocol timer configuration page. */
558 typedef struct tiSASProtocolTimerConfigurationPage_s{
559 bit32 pageCode; /* 0x04 */
561 bit32 STP_SSP_MCT_TMO;
564 bit32 OPNRJT_RTRY_INTVL;
565 bit32 Data_Cmd_OPNRJT_RTRY_TMO;
566 bit32 Data_Cmd_OPNRJT_RTRY_THR;
567 } tiSASProtocolTimerConfigurationPage_t;
571 /* The command is for an operator to login to/logout from SPCve. */
572 /* Only when all IOs are quiesced, can an operator logout. */
573 typedef struct tiOperatorCommandSet_s {
574 bit32 OPRIDX_PIN_ACS; /* Access type (ACS) [4 bits] */
575 /* KEYopr pinned in the KEK RAM (PIN) [1 bit] */
576 /* KEYopr Index in the KEK RAM (OPRIDX) [8 bits] */
577 bit8 cert[40]; /* Operator Certificate (CERT) [40 bytes] */
578 bit32 reserved[3]; /* reserved */
579 } tiOperatorCommandSet_t;
581 #define FIPS_SELFTEST_MAX_MSG_LEN (128*1024)
582 #define FIPS_SELFTEST_MAX_DIGEST_SIZE 64
584 typedef struct tiEncryptSelfTestDescriptor_s {
585 bit32 AESNTC_AESPTC; /* AES Negative/Positive Test Case Bit Map */
586 bit32 KWPNTC_PKWPPTC; /* Key Wrap Negative/Positive Test Case Bit Map */
587 bit32 HMACNTC_HMACPTC; /* HMAC Negative Test Case Bit Map */
588 } tiEncryptSelfTestDescriptor_t;
590 typedef struct tiEncryptSelfTestResult_s{
591 bit32 AESNTCS_AESPTCS; /* AES Negative/Positive Test Case Status */
592 bit32 KWPNTCS_PKWPPTCS; /* Key Wrap Negative/Positive Test Case Status */
593 bit32 HMACNTCS_HMACPTCS; /* HMAC Negative Test Case Status */
594 } tiEncryptSelfTestResult_t;
597 Tell SPCve controller the underlying SHA algorithm, where to fetch the message,
598 the size of the message, where to store the digest, where to fetch the secret key and the size of the key.
600 typedef struct tiEncryptHMACTestDescriptor_s
611 } tiEncryptHMACTestDescriptor_t;
613 typedef struct tiEncryptHMACTestResult_s
617 } tiEncryptHMACTestResult_t;
619 typedef struct tiEncryptSHATestDescriptor_s
627 } tiEncryptSHATestDescriptor_t;
629 typedef struct tiEncryptSHATestResult_s
633 } tiEncryptSHATestResult_t;
636 #endif /* TITYPES_H */