2 * Copyright (c) 2011, Aleksandr Rybalko
4 * by Alexander Egorenkov <egorenar@gmail.com>
5 * and by Damien Bergamini <damien.bergamini@free.fr>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
38 #include <net/if_arp.h>
39 #include <net/ethernet.h>
40 #include <net/if_dl.h>
41 #include <net/if_media.h>
42 #include <net/if_types.h>
43 #include <net/if_vlan_var.h>
47 #include <machine/bus.h>
48 #include <machine/cache.h>
49 #include <machine/cpufunc.h>
50 #include <machine/resource.h>
51 #include <vm/vm_param.h>
54 #include <machine/pmap.h>
58 #include <dev/mii/mii.h>
59 #include <dev/mii/miivar.h>
61 #include <mips/rt305x/rt305x_sysctlvar.h>
62 #include <mips/rt305x/rt305xreg.h>
64 #ifdef IF_RT_PHY_SUPPORT
65 #include "miibus_if.h"
71 #define RT_MAX_AGG_SIZE 3840
73 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
75 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
76 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
78 #define RT_TX_WATCHDOG_TIMEOUT 5
81 * Static function prototypes
83 static int rt_probe(device_t dev);
84 static int rt_attach(device_t dev);
85 static int rt_detach(device_t dev);
86 static int rt_shutdown(device_t dev);
87 static int rt_suspend(device_t dev);
88 static int rt_resume(device_t dev);
89 static void rt_init_locked(void *priv);
90 static void rt_init(void *priv);
91 static void rt_stop_locked(void *priv);
92 static void rt_stop(void *priv);
93 static void rt_start(struct ifnet *ifp);
94 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
95 static void rt_periodic(void *arg);
96 static void rt_tx_watchdog(void *arg);
97 static void rt_intr(void *arg);
98 static void rt_tx_coherent_intr(struct rt_softc *sc);
99 static void rt_rx_coherent_intr(struct rt_softc *sc);
100 static void rt_rx_delay_intr(struct rt_softc *sc);
101 static void rt_tx_delay_intr(struct rt_softc *sc);
102 static void rt_rx_intr(struct rt_softc *sc);
103 static void rt_tx_intr(struct rt_softc *sc, int qid);
104 static void rt_rx_done_task(void *context, int pending);
105 static void rt_tx_done_task(void *context, int pending);
106 static void rt_periodic_task(void *context, int pending);
107 static int rt_rx_eof(struct rt_softc *sc, int limit);
108 static void rt_tx_eof(struct rt_softc *sc,
109 struct rt_softc_tx_ring *ring);
110 static void rt_update_stats(struct rt_softc *sc);
111 static void rt_watchdog(struct rt_softc *sc);
112 static void rt_update_raw_counters(struct rt_softc *sc);
113 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
114 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
115 static int rt_txrx_enable(struct rt_softc *sc);
116 static int rt_alloc_rx_ring(struct rt_softc *sc,
117 struct rt_softc_rx_ring *ring);
118 static void rt_reset_rx_ring(struct rt_softc *sc,
119 struct rt_softc_rx_ring *ring);
120 static void rt_free_rx_ring(struct rt_softc *sc,
121 struct rt_softc_rx_ring *ring);
122 static int rt_alloc_tx_ring(struct rt_softc *sc,
123 struct rt_softc_tx_ring *ring, int qid);
124 static void rt_reset_tx_ring(struct rt_softc *sc,
125 struct rt_softc_tx_ring *ring);
126 static void rt_free_tx_ring(struct rt_softc *sc,
127 struct rt_softc_tx_ring *ring);
128 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
129 int nseg, int error);
130 static void rt_sysctl_attach(struct rt_softc *sc);
131 #ifdef IF_RT_PHY_SUPPORT
132 void rt_miibus_statchg(device_t);
133 static int rt_miibus_readreg(device_t, int, int);
134 static int rt_miibus_writereg(device_t, int, int, int);
136 static int rt_ifmedia_upd(struct ifnet *);
137 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD, 0, "RT driver parameters");
141 static int rt_debug = 0;
142 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RW, &rt_debug, 0,
144 TUNABLE_INT("hw.rt.debug", &rt_debug);
148 rt_probe(device_t dev)
150 device_set_desc(dev, "Ralink RT305XF onChip Ethernet MAC");
151 return (BUS_PROBE_NOWILDCARD);
155 * macaddr_atoi - translate string MAC address to uint8_t array
158 macaddr_atoi(const char *str, uint8_t *mac)
161 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
163 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
164 &amac[0], &amac[1], &amac[2],
165 &amac[3], &amac[4], &amac[5]);
166 if (count < ETHER_ADDR_LEN) {
167 memset(mac, 0, ETHER_ADDR_LEN);
171 /* Copy aligned to result */
172 for (i = 0; i < ETHER_ADDR_LEN; i ++)
173 mac[i] = (amac[i] & 0xff);
178 #ifdef USE_GENERATED_MAC_ADDRESS
180 * generate_mac(uin8_t *mac)
181 * This is MAC address generator for cases when real device MAC address
182 * unknown or not yet accessible.
183 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
184 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
186 * Output - MAC address, that do not change between reboots, if hints or
187 * bootloader info unchange.
190 generate_mac(uint8_t *mac)
194 uint32_t crc = 0xffffffff;
196 /* Generate CRC32 on kenv */
197 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
198 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
205 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
206 mac[4] = (crc >> 8) & 0xff;
212 * ether_request_mac - try to find usable MAC address.
215 ether_request_mac(device_t dev, uint8_t *mac)
220 * "ethaddr" is passed via envp on RedBoot platforms
221 * "kmac" is passed via argv on RouterBOOT platforms
223 #if defined(__U_BOOT__) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
224 if ((var = getenv("ethaddr")) != NULL ||
225 (var = getenv("kmac")) != NULL ) {
227 if(!macaddr_atoi(var, mac)) {
228 printf("%s: use %s macaddr from KENV\n",
229 device_get_nameunit(dev), var);
239 * hint.[dev].[unit].macaddr
241 if (!resource_string_value(device_get_name(dev),
242 device_get_unit(dev), "macaddr", (const char **)&var)) {
244 if(!macaddr_atoi(var, mac)) {
245 printf("%s: use %s macaddr from hints\n",
246 device_get_nameunit(dev), var);
251 #ifdef USE_GENERATED_MAC_ADDRESS
254 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
255 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
265 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
272 rt_attach(device_t dev)
278 sc = device_get_softc(dev);
281 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
282 MTX_DEF | MTX_RECURSE);
285 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
287 if (sc->mem == NULL) {
288 device_printf(dev, "could not allocate memory resource\n");
293 sc->bst = rman_get_bustag(sc->mem);
294 sc->bsh = rman_get_bushandle(sc->mem);
297 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
299 if (sc->irq == NULL) {
301 "could not allocate interrupt resource\n");
307 sc->debug = rt_debug;
309 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
310 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
311 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
314 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
318 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
320 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
322 GDM_ICS_EN | /* Enable IP Csum */
323 GDM_TCS_EN | /* Enable TCP Csum */
324 GDM_UCS_EN | /* Enable UDP Csum */
325 GDM_STRPCRC | /* Strip CRC from packet */
326 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
327 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
328 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
329 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
332 /* allocate Tx and Rx rings */
333 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
334 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
336 device_printf(dev, "could not allocate Tx ring #%d\n",
342 sc->tx_ring_mgtqid = 5;
344 error = rt_alloc_rx_ring(sc, &sc->rx_ring);
346 device_printf(dev, "could not allocate Rx ring\n");
350 callout_init(&sc->periodic_ch, 0);
351 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
353 ifp = sc->ifp = if_alloc(IFT_ETHER);
355 device_printf(dev, "could not if_alloc()\n");
361 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
362 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
363 ifp->if_init = rt_init;
364 ifp->if_ioctl = rt_ioctl;
365 ifp->if_start = rt_start;
366 #define RT_TX_QLEN 256
368 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
369 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
370 IFQ_SET_READY(&ifp->if_snd);
372 #ifdef IF_RT_PHY_SUPPORT
373 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
374 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
376 device_printf(dev, "attaching PHYs failed\n");
381 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
382 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
384 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
386 #endif /* IF_RT_PHY_SUPPORT */
388 ether_request_mac(dev, sc->mac_addr);
389 ether_ifattach(ifp, sc->mac_addr);
392 * Tell the upper layer(s) we support long frames.
394 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
395 ifp->if_capabilities |= IFCAP_VLAN_MTU;
396 ifp->if_capenable |= IFCAP_VLAN_MTU;
397 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
398 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
400 /* init task queue */
401 TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
402 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
403 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc);
405 sc->rx_process_limit = 100;
407 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
408 taskqueue_thread_enqueue, &sc->taskqueue);
410 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
411 device_get_nameunit(sc->dev));
413 rt_sysctl_attach(sc);
415 /* set up interrupt */
416 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
417 NULL, rt_intr, sc, &sc->irqh);
419 printf("%s: could not set up interrupt\n",
420 device_get_nameunit(dev));
424 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
430 /* free Tx and Rx rings */
431 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
432 rt_free_tx_ring(sc, &sc->tx_ring[i]);
434 rt_free_rx_ring(sc, &sc->rx_ring);
436 mtx_destroy(&sc->lock);
439 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
443 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
453 rt_ifmedia_upd(struct ifnet *ifp)
456 #ifdef IF_RT_PHY_SUPPORT
457 struct mii_data *mii;
458 struct mii_softc *miisc;
464 mii = device_get_softc(sc->rt_miibus);
465 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
467 error = mii_mediachg(mii);
472 #else /* !IF_RT_PHY_SUPPORT */
475 struct ifmedia_entry *ife;
478 ifm = &sc->rt_ifmedia;
481 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
484 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
485 device_printf(sc->dev,
486 "AUTO is not supported for multiphy MAC");
494 #endif /* IF_RT_PHY_SUPPORT */
498 * Report current media status.
501 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
503 #ifdef IF_RT_PHY_SUPPORT
505 struct mii_data *mii;
510 mii = device_get_softc(sc->rt_miibus);
512 ifmr->ifm_active = mii->mii_media_active;
513 ifmr->ifm_status = mii->mii_media_status;
514 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
515 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
517 #else /* !IF_RT_PHY_SUPPORT */
519 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
520 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
521 #endif /* IF_RT_PHY_SUPPORT */
525 rt_detach(device_t dev)
531 sc = device_get_softc(dev);
534 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
538 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
540 callout_stop(&sc->periodic_ch);
541 callout_stop(&sc->tx_watchdog_ch);
543 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
544 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
545 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
547 /* free Tx and Rx rings */
548 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
549 rt_free_tx_ring(sc, &sc->tx_ring[i]);
551 rt_free_rx_ring(sc, &sc->rx_ring);
555 #ifdef IF_RT_PHY_SUPPORT
556 if (sc->rt_miibus != NULL)
557 device_delete_child(dev, sc->rt_miibus);
563 taskqueue_free(sc->taskqueue);
565 mtx_destroy(&sc->lock);
567 bus_generic_detach(dev);
568 bus_teardown_intr(dev, sc->irq, sc->irqh);
569 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
570 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
576 rt_shutdown(device_t dev)
580 sc = device_get_softc(dev);
581 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
588 rt_suspend(device_t dev)
592 sc = device_get_softc(dev);
593 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
600 rt_resume(device_t dev)
605 sc = device_get_softc(dev);
608 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
610 if (ifp->if_flags & IFF_UP)
617 * rt_init_locked - Run initialization process having locked mtx.
620 rt_init_locked(void *priv)
624 #ifdef IF_RT_PHY_SUPPORT
625 struct mii_data *mii;
632 #ifdef IF_RT_PHY_SUPPORT
633 mii = device_get_softc(sc->rt_miibus);
636 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
638 RT_SOFTC_ASSERT_LOCKED(sc);
641 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
642 rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
644 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
645 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
647 GDM_ICS_EN | /* Enable IP Csum */
648 GDM_TCS_EN | /* Enable TCP Csum */
649 GDM_UCS_EN | /* Enable UDP Csum */
650 GDM_STRPCRC | /* Strip CRC from packet */
651 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
652 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
653 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
654 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
657 /* disable DMA engine */
658 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, 0);
659 RT_WRITE(sc, PDMA_BASE + PDMA_RST_IDX, 0xffffffff);
661 /* wait while DMA engine is busy */
662 for (ntries = 0; ntries < 100; ntries++) {
663 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
664 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
670 device_printf(sc->dev, "timeout waiting for DMA engine\n");
674 /* reset Rx and Tx rings */
675 tmp = FE_RST_DRX_IDX0 |
681 RT_WRITE(sc, PDMA_BASE + PDMA_RST_IDX, tmp);
683 /* XXX switch set mac address */
684 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
685 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
687 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
688 /* update TX_BASE_PTRx */
689 RT_WRITE(sc, PDMA_BASE + TX_BASE_PTR(i),
690 sc->tx_ring[i].desc_phys_addr);
691 RT_WRITE(sc, PDMA_BASE + TX_MAX_CNT(i),
692 RT_SOFTC_TX_RING_DESC_COUNT);
693 RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(i), 0);
697 rt_reset_rx_ring(sc, &sc->rx_ring);
699 /* update RX_BASE_PTR0 */
700 RT_WRITE(sc, PDMA_BASE + RX_BASE_PTR0,
701 sc->rx_ring.desc_phys_addr);
702 RT_WRITE(sc, PDMA_BASE + RX_MAX_CNT0,
703 RT_SOFTC_RX_RING_DATA_COUNT);
704 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
705 RT_SOFTC_RX_RING_DATA_COUNT - 1);
707 /* write back DDONE, 16byte burst enable RX/TX DMA */
708 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG,
709 FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN);
711 /* disable interrupts mitigation */
712 RT_WRITE(sc, PDMA_BASE + DELAY_INT_CFG, 0);
714 /* clear pending interrupts */
715 RT_WRITE(sc, GE_PORT_BASE + FE_INT_STATUS, 0xffffffff);
717 /* enable interrupts */
735 sc->intr_enable_mask = tmp;
737 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
739 if (rt_txrx_enable(sc) != 0)
742 #ifdef IF_RT_PHY_SUPPORT
743 if (mii) mii_mediachg(mii);
744 #endif /* IF_RT_PHY_SUPPORT */
746 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
747 ifp->if_drv_flags |= IFF_DRV_RUNNING;
749 sc->periodic_round = 0;
751 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
760 * rt_init - lock and initialize device.
774 * rt_stop_locked - stop TX/RX w/ lock
777 rt_stop_locked(void *priv)
785 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
787 RT_SOFTC_ASSERT_LOCKED(sc);
789 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
790 callout_stop(&sc->periodic_ch);
791 callout_stop(&sc->tx_watchdog_ch);
793 taskqueue_block(sc->taskqueue);
796 * Sometime rt_stop_locked called from isr and we get panic
797 * When found, I fix it
800 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
801 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
802 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
806 /* disable interrupts */
807 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, 0);
810 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
812 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
814 GDM_ICS_EN | /* Enable IP Csum */
815 GDM_TCS_EN | /* Enable TCP Csum */
816 GDM_UCS_EN | /* Enable UDP Csum */
817 GDM_STRPCRC | /* Strip CRC from packet */
818 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
819 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
820 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
821 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
837 * rt_tx_data - transmit packet.
840 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
843 struct rt_softc_tx_ring *ring;
844 struct rt_softc_tx_data *data;
845 struct rt_txdesc *desc;
847 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
848 int error, ndmasegs, ndescs, i;
850 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
851 ("%s: Tx data: invalid qid=%d\n",
852 device_get_nameunit(sc->dev), qid));
854 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
857 ring = &sc->tx_ring[qid];
858 desc = &ring->desc[ring->desc_cur];
859 data = &ring->data[ring->data_cur];
861 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
862 dma_seg, &ndmasegs, 0);
864 /* too many fragments, linearize */
866 RT_DPRINTF(sc, RT_DEBUG_TX,
867 "could not load mbuf DMA map, trying to linearize "
868 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
869 ndmasegs, m->m_pkthdr.len, error);
871 m_d = m_collapse(m, M_NOWAIT, 16);
879 sc->tx_defrag_packets++;
881 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
882 data->dma_map, m, dma_seg, &ndmasegs, 0);
884 device_printf(sc->dev, "could not load mbuf DMA map: "
885 "ndmasegs=%d, len=%d, error=%d\n",
886 ndmasegs, m->m_pkthdr.len, error);
892 if (m->m_pkthdr.len == 0)
895 /* determine how many Tx descs are required */
896 ndescs = 1 + ndmasegs / 2;
897 if ((ring->desc_queued + ndescs) >
898 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
899 RT_DPRINTF(sc, RT_DEBUG_TX,
900 "there are not enough Tx descs\n");
902 sc->no_tx_desc_avail++;
904 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
911 /* set up Tx descs */
912 for (i = 0; i < ndmasegs; i += 2) {
913 /* Set destenation */
914 desc->dst = (TXDSCR_DST_PORT_GDMA1);
915 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
916 desc->dst |= (TXDSCR_IP_CSUM_GEN|TXDSCR_UDP_CSUM_GEN|
917 TXDSCR_TCP_CSUM_GEN);
925 desc->sdp0 = htole32(dma_seg[i].ds_addr);
926 desc->sdl0 = htole16(dma_seg[i].ds_len |
927 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
929 if ((i+1) < ndmasegs) {
930 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
931 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
932 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
938 if ((i+2) < ndmasegs) {
940 ring->desc_cur = (ring->desc_cur + 1) %
941 RT_SOFTC_TX_RING_DESC_COUNT;
943 desc = &ring->desc[ring->desc_cur];
946 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
947 "DMA ds_len=%d/%d/%d/%d/%d\n",
948 m->m_pkthdr.len, ndmasegs,
949 (int) dma_seg[0].ds_len,
950 (int) dma_seg[1].ds_len,
951 (int) dma_seg[2].ds_len,
952 (int) dma_seg[3].ds_len,
953 (int) dma_seg[4].ds_len);
955 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
956 BUS_DMASYNC_PREWRITE);
957 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
958 BUS_DMASYNC_PREWRITE);
959 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
960 BUS_DMASYNC_PREWRITE);
963 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
966 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
969 RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(qid), ring->desc_cur);
975 * rt_start - start Transmit/Receive
978 rt_start(struct ifnet *ifp)
982 int qid = 0 /* XXX must check QoS priority */;
986 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
990 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
994 m->m_pkthdr.rcvif = NULL;
996 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
998 if (sc->tx_ring[qid].data_queued >=
999 RT_SOFTC_TX_RING_DATA_COUNT) {
1000 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1002 RT_DPRINTF(sc, RT_DEBUG_TX,
1003 "if_start: Tx ring with qid=%d is full\n", qid);
1007 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1010 sc->tx_data_queue_full[qid]++;
1015 if (rt_tx_data(sc, m, qid) != 0) {
1016 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1023 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1024 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1025 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1030 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1031 * filtering done by attached Ethernet switch.
1034 rt_update_promisc(struct ifnet *ifp)
1036 struct rt_softc *sc;
1039 printf("%s: %s promiscuous mode\n",
1040 device_get_nameunit(sc->dev),
1041 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1045 * rt_ioctl - ioctl handler.
1048 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1050 struct rt_softc *sc;
1052 #ifdef IF_RT_PHY_SUPPORT
1053 struct mii_data *mii;
1054 #endif /* IF_RT_PHY_SUPPORT */
1055 int error, startall;
1058 ifr = (struct ifreq *) data;
1066 if (ifp->if_flags & IFF_UP) {
1067 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1068 if ((ifp->if_flags ^ sc->if_flags) &
1070 rt_update_promisc(ifp);
1076 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1079 sc->if_flags = ifp->if_flags;
1080 RT_SOFTC_UNLOCK(sc);
1084 #ifdef IF_RT_PHY_SUPPORT
1085 mii = device_get_softc(sc->rt_miibus);
1086 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1088 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1089 #endif /* IF_RT_PHY_SUPPORT */
1092 error = ether_ioctl(ifp, cmd, data);
1099 * rt_periodic - Handler of PERIODIC interrupt
1102 rt_periodic(void *arg)
1104 struct rt_softc *sc;
1107 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n");
1108 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task);
1112 * rt_tx_watchdog - Handler of TX Watchdog
1115 rt_tx_watchdog(void *arg)
1117 struct rt_softc *sc;
1123 if (sc->tx_timer == 0)
1126 if (--sc->tx_timer == 0) {
1127 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1130 * XXX: Commented out, because reset break input.
1136 sc->tx_watchdog_timeouts++;
1138 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1142 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1145 rt_cnt_ppe_af(struct rt_softc *sc)
1148 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1152 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1155 rt_cnt_gdm_af(struct rt_softc *sc)
1158 RT_DPRINTF(sc, RT_DEBUG_INTR,
1159 "GDMA 1 & 2 Counter Table Almost Full\n");
1163 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1166 rt_pse_p2_fc(struct rt_softc *sc)
1169 RT_DPRINTF(sc, RT_DEBUG_INTR,
1170 "PSE port2 (GDMA 2) flow control asserted.\n");
1174 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1178 rt_gdm_crc_drop(struct rt_softc *sc)
1181 RT_DPRINTF(sc, RT_DEBUG_INTR,
1182 "GDMA 1 & 2 discard a packet due to CRC error\n");
1186 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1189 rt_pse_buf_drop(struct rt_softc *sc)
1192 RT_DPRINTF(sc, RT_DEBUG_INTR,
1193 "PSE discards a packet due to buffer sharing limitation\n");
1197 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1200 rt_gdm_other_drop(struct rt_softc *sc)
1203 RT_DPRINTF(sc, RT_DEBUG_INTR,
1204 "GDMA 1 & 2 discard a packet due to other reason\n");
1208 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1211 rt_pse_p1_fc(struct rt_softc *sc)
1214 RT_DPRINTF(sc, RT_DEBUG_INTR,
1215 "PSE port1 (GDMA 1) flow control asserted.\n");
1219 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1222 rt_pse_p0_fc(struct rt_softc *sc)
1225 RT_DPRINTF(sc, RT_DEBUG_INTR,
1226 "PSE port0 (CDMA) flow control asserted.\n");
1230 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1233 rt_pse_fq_empty(struct rt_softc *sc)
1236 RT_DPRINTF(sc, RT_DEBUG_INTR,
1237 "PSE free Q empty threshold reached & forced drop "
1238 "condition occurred.\n");
1242 * rt_intr - main ISR
1247 struct rt_softc *sc;
1254 /* acknowledge interrupts */
1255 status = RT_READ(sc, GE_PORT_BASE + FE_INT_STATUS);
1256 RT_WRITE(sc, GE_PORT_BASE + FE_INT_STATUS, status);
1258 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1260 if (status == 0xffffffff || /* device likely went away */
1261 status == 0) /* not for us */
1266 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1269 if (status & CNT_PPE_AF)
1272 if (status & CNT_GDM_AF)
1275 if (status & PSE_P2_FC)
1278 if (status & GDM_CRC_DROP)
1279 rt_gdm_crc_drop(sc);
1281 if (status & PSE_BUF_DROP)
1282 rt_pse_buf_drop(sc);
1284 if (status & GDM_OTHER_DROP)
1285 rt_gdm_other_drop(sc);
1287 if (status & PSE_P1_FC)
1290 if (status & PSE_P0_FC)
1293 if (status & PSE_FQ_EMPTY)
1294 rt_pse_fq_empty(sc);
1296 if (status & INT_TX_COHERENT)
1297 rt_tx_coherent_intr(sc);
1299 if (status & INT_RX_COHERENT)
1300 rt_rx_coherent_intr(sc);
1302 if (status & RX_DLY_INT)
1303 rt_rx_delay_intr(sc);
1305 if (status & TX_DLY_INT)
1306 rt_tx_delay_intr(sc);
1308 if (status & INT_RX_DONE)
1311 if (status & INT_TXQ3_DONE)
1314 if (status & INT_TXQ2_DONE)
1317 if (status & INT_TXQ1_DONE)
1320 if (status & INT_TXQ0_DONE)
1325 rt_tx_coherent_intr(struct rt_softc *sc)
1330 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1332 sc->tx_coherent_interrupts++;
1334 /* restart DMA engine */
1335 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
1336 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1337 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
1339 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1340 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1342 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1343 RT_WRITE(sc, PDMA_BASE + TX_BASE_PTR(i),
1344 sc->tx_ring[i].desc_phys_addr);
1345 RT_WRITE(sc, PDMA_BASE + TX_MAX_CNT(i),
1346 RT_SOFTC_TX_RING_DESC_COUNT);
1347 RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(i), 0);
1354 * rt_rx_coherent_intr
1357 rt_rx_coherent_intr(struct rt_softc *sc)
1361 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1363 sc->rx_coherent_interrupts++;
1365 /* restart DMA engine */
1366 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
1367 tmp &= ~(FE_RX_DMA_EN);
1368 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
1371 rt_reset_rx_ring(sc, &sc->rx_ring);
1372 RT_WRITE(sc, PDMA_BASE + RX_BASE_PTR0,
1373 sc->rx_ring.desc_phys_addr);
1374 RT_WRITE(sc, PDMA_BASE + RX_MAX_CNT0,
1375 RT_SOFTC_RX_RING_DATA_COUNT);
1376 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
1377 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1383 * rt_rx_intr - a packet received
1386 rt_rx_intr(struct rt_softc *sc)
1389 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1390 sc->rx_interrupts++;
1393 if (!(sc->intr_disable_mask & INT_RX_DONE)) {
1394 rt_intr_disable(sc, INT_RX_DONE);
1395 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1398 sc->intr_pending_mask |= INT_RX_DONE;
1399 RT_SOFTC_UNLOCK(sc);
1403 rt_rx_delay_intr(struct rt_softc *sc)
1406 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1407 sc->rx_delay_interrupts++;
1411 rt_tx_delay_intr(struct rt_softc *sc)
1414 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1415 sc->tx_delay_interrupts++;
1419 * rt_tx_intr - Transsmition of packet done
1422 rt_tx_intr(struct rt_softc *sc, int qid)
1425 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1426 ("%s: Tx interrupt: invalid qid=%d\n",
1427 device_get_nameunit(sc->dev), qid));
1429 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1431 sc->tx_interrupts[qid]++;
1434 if (!(sc->intr_disable_mask & (INT_TXQ0_DONE << qid))) {
1435 rt_intr_disable(sc, (INT_TXQ0_DONE << qid));
1436 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1439 sc->intr_pending_mask |= (INT_TXQ0_DONE << qid);
1440 RT_SOFTC_UNLOCK(sc);
1444 * rt_rx_done_task - run RX task
1447 rt_rx_done_task(void *context, int pending)
1449 struct rt_softc *sc;
1456 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1458 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1461 sc->intr_pending_mask &= ~INT_RX_DONE;
1463 again = rt_rx_eof(sc, sc->rx_process_limit);
1467 if ((sc->intr_pending_mask & INT_RX_DONE) || again) {
1468 RT_DPRINTF(sc, RT_DEBUG_RX,
1469 "Rx done task: scheduling again\n");
1470 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1472 rt_intr_enable(sc, INT_RX_DONE);
1475 RT_SOFTC_UNLOCK(sc);
1479 * rt_tx_done_task - check for pending TX task in all queues
1482 rt_tx_done_task(void *context, int pending)
1484 struct rt_softc *sc;
1492 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1494 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1497 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1498 if (sc->intr_pending_mask & (INT_TXQ0_DONE << i)) {
1499 sc->intr_pending_mask &= ~(INT_TXQ0_DONE << i);
1500 rt_tx_eof(sc, &sc->tx_ring[i]);
1506 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1516 rt_intr_enable(sc, ~sc->intr_pending_mask &
1517 (sc->intr_disable_mask & intr_mask));
1519 if (sc->intr_pending_mask & intr_mask) {
1520 RT_DPRINTF(sc, RT_DEBUG_TX,
1521 "Tx done task: scheduling again\n");
1522 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1525 RT_SOFTC_UNLOCK(sc);
1527 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1532 * rt_periodic_task - run periodic task
1535 rt_periodic_task(void *context, int pending)
1537 struct rt_softc *sc;
1543 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1544 sc->periodic_round);
1546 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1550 sc->periodic_round++;
1551 rt_update_stats(sc);
1553 if ((sc->periodic_round % 10) == 0) {
1554 rt_update_raw_counters(sc);
1558 RT_SOFTC_UNLOCK(sc);
1559 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
1563 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1564 * network subsystem.
1567 rt_rx_eof(struct rt_softc *sc, int limit)
1570 struct rt_softc_rx_ring *ring;
1571 struct rt_rxdesc *desc;
1572 struct rt_softc_rx_data *data;
1573 struct mbuf *m, *mnew;
1574 bus_dma_segment_t segs[1];
1575 bus_dmamap_t dma_map;
1576 uint32_t index, desc_flags;
1577 int error, nsegs, len, nframes;
1580 ring = &sc->rx_ring;
1584 while (limit != 0) {
1585 index = RT_READ(sc, PDMA_BASE + RX_DRX_IDX0);
1586 if (ring->cur == index)
1589 desc = &ring->desc[ring->cur];
1590 data = &ring->data[ring->cur];
1592 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1593 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1596 if ( sc->debug & RT_DEBUG_RX ) {
1597 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1598 hexdump(desc, 16, 0, 0);
1599 printf("-----------------------------------\n");
1603 /* XXX Sometime device don`t set DDONE bit */
1605 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1606 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1611 len = le16toh(desc->sdl0) & 0x3fff;
1612 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1616 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1619 sc->rx_mbuf_alloc_errors++;
1624 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1626 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1627 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1629 RT_DPRINTF(sc, RT_DEBUG_RX,
1630 "could not load Rx mbuf DMA map: "
1631 "error=%d, nsegs=%d\n",
1636 sc->rx_mbuf_dmamap_errors++;
1642 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1643 device_get_nameunit(sc->dev)));
1645 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1646 BUS_DMASYNC_POSTREAD);
1647 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1649 dma_map = data->dma_map;
1650 data->dma_map = ring->spare_dma_map;
1651 ring->spare_dma_map = dma_map;
1653 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1654 BUS_DMASYNC_PREREAD);
1657 desc_flags = desc->src;
1660 /* Add 2 for proper align of RX IP header */
1661 desc->sdp0 = htole32(segs[0].ds_addr+2);
1662 desc->sdl0 = htole32(segs[0].ds_len-2);
1667 RT_DPRINTF(sc, RT_DEBUG_RX,
1668 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1670 m->m_pkthdr.rcvif = ifp;
1671 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1673 m->m_pkthdr.len = m->m_len = len;
1675 /* check for crc errors */
1676 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1677 /*check for valid checksum*/
1678 if (desc_flags & (RXDSXR_SRC_IP_CSUM_FAIL|
1679 RXDSXR_SRC_L4_CSUM_FAIL)) {
1680 RT_DPRINTF(sc, RT_DEBUG_RX,
1681 "rxdesc: crc error\n");
1685 if (!(ifp->if_flags & IFF_PROMISC)) {
1690 if ((desc_flags & RXDSXR_SRC_IP_CSUM_FAIL) != 0) {
1691 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1692 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1693 m->m_pkthdr.csum_data = 0xffff;
1695 m->m_flags &= ~M_HASFCS;
1698 (*ifp->if_input)(ifp, m);
1700 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1702 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1705 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1711 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
1712 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1714 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
1717 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1719 sc->rx_packets += nframes;
1721 return (limit == 0);
1725 * rt_tx_eof - check for successful transmitted frames and mark their
1726 * descriptor as free.
1729 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
1732 struct rt_txdesc *desc;
1733 struct rt_softc_tx_data *data;
1735 int ndescs, nframes;
1743 index = RT_READ(sc, PDMA_BASE + TX_DTX_IDX(ring->qid));
1744 if (ring->desc_next == index)
1749 desc = &ring->desc[ring->desc_next];
1751 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1752 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1754 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
1755 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
1758 data = &ring->data[ring->data_next];
1760 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1761 BUS_DMASYNC_POSTWRITE);
1762 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1770 RT_SOFTC_TX_RING_LOCK(ring);
1771 ring->data_queued--;
1772 ring->data_next = (ring->data_next + 1) %
1773 RT_SOFTC_TX_RING_DATA_COUNT;
1774 RT_SOFTC_TX_RING_UNLOCK(ring);
1777 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
1779 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1782 RT_SOFTC_TX_RING_LOCK(ring);
1783 ring->desc_queued--;
1784 ring->desc_next = (ring->desc_next + 1) %
1785 RT_SOFTC_TX_RING_DESC_COUNT;
1786 RT_SOFTC_TX_RING_UNLOCK(ring);
1789 RT_DPRINTF(sc, RT_DEBUG_TX,
1790 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
1795 * rt_update_stats - query statistics counters and update related variables.
1798 rt_update_stats(struct rt_softc *sc)
1803 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
1804 /* XXX do update stats here */
1808 * rt_watchdog - reinit device on watchdog event.
1811 rt_watchdog(struct rt_softc *sc)
1818 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
1820 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, "watchdog: PSE_IQ_STA=0x%08x\n",
1823 /* XXX: do not reset */
1825 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
1826 sc->tx_queue_not_empty[0]++;
1828 for (ntries = 0; ntries < 10; ntries++) {
1829 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
1830 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
1837 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
1838 sc->tx_queue_not_empty[1]++;
1840 for (ntries = 0; ntries < 10; ntries++) {
1841 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
1842 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
1852 * rt_update_raw_counters - update counters.
1855 rt_update_raw_counters(struct rt_softc *sc)
1858 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
1859 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
1860 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
1861 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
1863 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
1864 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
1865 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
1866 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
1867 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
1868 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
1869 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
1873 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
1877 sc->intr_disable_mask &= ~intr_mask;
1878 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
1879 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
1883 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
1887 sc->intr_disable_mask |= intr_mask;
1888 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
1889 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
1893 * rt_txrx_enable - enable TX/RX DMA
1896 rt_txrx_enable(struct rt_softc *sc)
1904 /* enable Tx/Rx DMA engine */
1905 for (ntries = 0; ntries < 200; ntries++) {
1906 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
1907 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
1913 if (ntries == 200) {
1914 device_printf(sc->dev, "timeout waiting for DMA engine\n");
1920 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1921 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
1923 /* XXX set Rx filter */
1928 * rt_alloc_rx_ring - allocate RX DMA ring buffer
1931 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
1933 struct rt_rxdesc *desc;
1934 struct rt_softc_rx_data *data;
1935 bus_dma_segment_t segs[1];
1936 int i, nsegs, error;
1938 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
1939 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1940 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
1941 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
1942 0, NULL, NULL, &ring->desc_dma_tag);
1944 device_printf(sc->dev,
1945 "could not create Rx desc DMA tag\n");
1949 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
1950 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
1952 device_printf(sc->dev,
1953 "could not allocate Rx desc DMA memory\n");
1957 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
1959 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
1960 rt_dma_map_addr, &ring->desc_phys_addr, 0);
1962 device_printf(sc->dev, "could not load Rx desc DMA map\n");
1966 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
1967 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1968 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
1969 &ring->data_dma_tag);
1971 device_printf(sc->dev,
1972 "could not create Rx data DMA tag\n");
1976 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
1977 desc = &ring->desc[i];
1978 data = &ring->data[i];
1980 error = bus_dmamap_create(ring->data_dma_tag, 0,
1983 device_printf(sc->dev, "could not create Rx data DMA "
1988 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1990 if (data->m == NULL) {
1991 device_printf(sc->dev, "could not allocate Rx mbuf\n");
1996 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
1998 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1999 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2001 device_printf(sc->dev,
2002 "could not load Rx mbuf DMA map\n");
2006 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2007 device_get_nameunit(sc->dev)));
2009 /* Add 2 for proper align of RX IP header */
2010 desc->sdp0 = htole32(segs[0].ds_addr+2);
2011 desc->sdl0 = htole32(segs[0].ds_len-2);
2014 error = bus_dmamap_create(ring->data_dma_tag, 0,
2015 &ring->spare_dma_map);
2017 device_printf(sc->dev,
2018 "could not create Rx spare DMA map\n");
2022 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2027 rt_free_rx_ring(sc, ring);
2032 * rt_reset_rx_ring - reset RX ring buffer
2035 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2037 struct rt_rxdesc *desc;
2040 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2041 desc = &ring->desc[i];
2042 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2045 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2051 * rt_free_rx_ring - free memory used by RX ring buffer
2054 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2056 struct rt_softc_rx_data *data;
2059 if (ring->desc != NULL) {
2060 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2061 BUS_DMASYNC_POSTWRITE);
2062 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2063 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2064 ring->desc_dma_map);
2067 if (ring->desc_dma_tag != NULL)
2068 bus_dma_tag_destroy(ring->desc_dma_tag);
2070 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2071 data = &ring->data[i];
2073 if (data->m != NULL) {
2074 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2075 BUS_DMASYNC_POSTREAD);
2076 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2080 if (data->dma_map != NULL)
2081 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2084 if (ring->spare_dma_map != NULL)
2085 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2087 if (ring->data_dma_tag != NULL)
2088 bus_dma_tag_destroy(ring->data_dma_tag);
2092 * rt_alloc_tx_ring - allocate TX ring buffer
2095 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2097 struct rt_softc_tx_data *data;
2100 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2102 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2103 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2104 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2105 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2106 0, NULL, NULL, &ring->desc_dma_tag);
2108 device_printf(sc->dev,
2109 "could not create Tx desc DMA tag\n");
2113 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2114 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2116 device_printf(sc->dev,
2117 "could not allocate Tx desc DMA memory\n");
2121 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2122 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2123 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2124 &ring->desc_phys_addr, 0);
2126 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2130 ring->desc_queued = 0;
2132 ring->desc_next = 0;
2134 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2135 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2136 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2137 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2138 0, NULL, NULL, &ring->seg0_dma_tag);
2140 device_printf(sc->dev,
2141 "could not create Tx seg0 DMA tag\n");
2145 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2146 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2148 device_printf(sc->dev,
2149 "could not allocate Tx seg0 DMA memory\n");
2153 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2155 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2156 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2158 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2162 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2163 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2164 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2165 &ring->data_dma_tag);
2167 device_printf(sc->dev,
2168 "could not create Tx data DMA tag\n");
2172 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2173 data = &ring->data[i];
2175 error = bus_dmamap_create(ring->data_dma_tag, 0,
2178 device_printf(sc->dev, "could not create Tx data DMA "
2184 ring->data_queued = 0;
2186 ring->data_next = 0;
2192 rt_free_tx_ring(sc, ring);
2197 * rt_reset_tx_ring - reset TX ring buffer to empty state
2200 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2202 struct rt_softc_tx_data *data;
2203 struct rt_txdesc *desc;
2206 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2207 desc = &ring->desc[i];
2213 ring->desc_queued = 0;
2215 ring->desc_next = 0;
2217 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2218 BUS_DMASYNC_PREWRITE);
2220 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2221 BUS_DMASYNC_PREWRITE);
2223 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2224 data = &ring->data[i];
2226 if (data->m != NULL) {
2227 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2228 BUS_DMASYNC_POSTWRITE);
2229 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2235 ring->data_queued = 0;
2237 ring->data_next = 0;
2241 * rt_free_tx_ring - free RX ring buffer
2244 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2246 struct rt_softc_tx_data *data;
2249 if (ring->desc != NULL) {
2250 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2251 BUS_DMASYNC_POSTWRITE);
2252 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2253 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2254 ring->desc_dma_map);
2257 if (ring->desc_dma_tag != NULL)
2258 bus_dma_tag_destroy(ring->desc_dma_tag);
2260 if (ring->seg0 != NULL) {
2261 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2262 BUS_DMASYNC_POSTWRITE);
2263 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2264 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2265 ring->seg0_dma_map);
2268 if (ring->seg0_dma_tag != NULL)
2269 bus_dma_tag_destroy(ring->seg0_dma_tag);
2271 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2272 data = &ring->data[i];
2274 if (data->m != NULL) {
2275 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2276 BUS_DMASYNC_POSTWRITE);
2277 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2281 if (data->dma_map != NULL)
2282 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2285 if (ring->data_dma_tag != NULL)
2286 bus_dma_tag_destroy(ring->data_dma_tag);
2288 mtx_destroy(&ring->lock);
2292 * rt_dma_map_addr - get address of busdma segment
2295 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2300 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2302 *(bus_addr_t *) arg = segs[0].ds_addr;
2306 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2309 rt_sysctl_attach(struct rt_softc *sc)
2311 struct sysctl_ctx_list *ctx;
2312 struct sysctl_oid *tree;
2313 struct sysctl_oid *stats;
2315 ctx = device_get_sysctl_ctx(sc->dev);
2316 tree = device_get_sysctl_tree(sc->dev);
2318 /* statistic counters */
2319 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2320 "stats", CTLFLAG_RD, 0, "statistic");
2322 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2323 "interrupts", CTLFLAG_RD, &sc->interrupts,
2326 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2327 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2328 "Tx coherent interrupts");
2330 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2331 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2332 "Rx coherent interrupts");
2334 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2335 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts,
2338 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2339 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2340 "Rx delay interrupts");
2342 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2343 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2344 "Tx AC3 interrupts");
2346 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2347 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2348 "Tx AC2 interrupts");
2350 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2351 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2352 "Tx AC1 interrupts");
2354 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2355 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2356 "Tx AC0 interrupts");
2358 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2359 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2360 "Tx delay interrupts");
2362 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2363 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2364 0, "Tx AC3 descriptors queued");
2366 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2367 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2368 0, "Tx AC3 data queued");
2370 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2371 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2372 0, "Tx AC2 descriptors queued");
2374 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2375 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2376 0, "Tx AC2 data queued");
2378 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2379 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2380 0, "Tx AC1 descriptors queued");
2382 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2383 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2384 0, "Tx AC1 data queued");
2386 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2387 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2388 0, "Tx AC0 descriptors queued");
2390 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2391 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2392 0, "Tx AC0 data queued");
2394 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2395 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2396 "Tx AC3 data queue full");
2398 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2399 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2400 "Tx AC2 data queue full");
2402 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2403 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2404 "Tx AC1 data queue full");
2406 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2407 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2408 "Tx AC0 data queue full");
2410 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2411 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2412 "Tx watchdog timeouts");
2414 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2415 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2416 "Tx defragmented packets");
2418 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2419 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2420 "no Tx descriptors available");
2422 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2423 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2424 "Rx mbuf allocation errors");
2426 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2427 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2428 "Rx mbuf DMA mapping errors");
2430 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2431 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2432 "Tx queue 0 not empty");
2434 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2435 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2436 "Tx queue 1 not empty");
2438 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2439 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2442 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2443 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2446 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2447 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2450 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2451 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2452 "Rx duplicate packets");
2454 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2455 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2456 "Rx FIFO overflows");
2458 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2459 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2462 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2463 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2464 "Rx too long frame errors");
2466 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2467 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2468 "Rx too short frame errors");
2470 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2471 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2474 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2475 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2478 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2479 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2480 "Tx skip count for GDMA ports");
2482 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2483 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2484 "Tx collision count for GDMA ports");
2487 #ifdef IF_RT_PHY_SUPPORT
2489 rt_miibus_readreg(device_t dev, int phy, int reg)
2491 struct rt_softc *sc = device_get_softc(dev);
2494 * PSEUDO_PHYAD is a special value for indicate switch attached.
2495 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2498 /* Fake PHY ID for bfeswitch attach */
2501 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2503 return (0x40); /* As result of faking */
2504 case MII_PHYIDR2: /* PHY will detect as */
2505 return (0x6250); /* bfeswitch */
2509 /* Wait prev command done if any */
2510 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2511 RT_WRITE(sc, MDIO_ACCESS,
2513 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
2514 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK));
2515 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2517 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2521 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2523 struct rt_softc *sc = device_get_softc(dev);
2525 /* Wait prev command done if any */
2526 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2527 RT_WRITE(sc, MDIO_ACCESS,
2528 MDIO_CMD_ONGO || MDIO_CMD_WR ||
2529 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
2530 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) ||
2531 (val & MDIO_PHY_DATA_MASK));
2532 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2538 rt_miibus_statchg(device_t dev)
2540 struct rt_softc *sc = device_get_softc(dev);
2541 struct mii_data *mii;
2543 mii = device_get_softc(sc->rt_miibus);
2545 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2546 (IFM_ACTIVE | IFM_AVALID)) {
2547 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2550 /* XXX check link here */
2558 #endif /* IF_RT_PHY_SUPPORT */
2560 static device_method_t rt_dev_methods[] =
2562 DEVMETHOD(device_probe, rt_probe),
2563 DEVMETHOD(device_attach, rt_attach),
2564 DEVMETHOD(device_detach, rt_detach),
2565 DEVMETHOD(device_shutdown, rt_shutdown),
2566 DEVMETHOD(device_suspend, rt_suspend),
2567 DEVMETHOD(device_resume, rt_resume),
2569 #ifdef IF_RT_PHY_SUPPORT
2571 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2572 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2573 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2579 static driver_t rt_driver =
2583 sizeof(struct rt_softc)
2586 static devclass_t rt_dev_class;
2588 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2589 MODULE_DEPEND(rt, ether, 1, 1, 1);
2590 MODULE_DEPEND(rt, miibus, 1, 1, 1);