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33 /* These structures define the layouts for the TLV items stored in static and
34 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
36 * They contain the same sort of information that was kept in the
37 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
38 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
41 * These are used directly by the MC and should also be usable directly on host
42 * systems which are little-endian and do not do strange things with structure
43 * padding. (Big-endian host systems will require some byte-swapping.)
47 * Please refer to SF-108797-SW for a general overview of the TLV partition
52 * The current tag IDs have a general structure: with the exception of the
53 * special values defined in the document, they are of the form 0xLTTTNNNN,
56 * - L is a location, indicating where this tag is expected to be found:
57 * 0 for static configuration, or 1 for dynamic configuration. Other
58 * values are reserved.
60 * - TTT is a type, which is just a unique value. The same type value
61 * might appear in both locations, indicating a relationship between
62 * the items (e.g. static and dynamic VPD below).
64 * - NNNN is an index of some form. Some item types are per-port, some
65 * are per-PF, some are per-partition-type.
69 * As with the previous Siena structures, each structure here is laid out
70 * carefully: values are aligned to their natural boundary, with explicit
71 * padding fields added where necessary. (No, technically this does not
72 * absolutely guarantee portability. But, in practice, compilers are generally
73 * sensible enough not to introduce completely pointless padding, and it works
78 #ifndef CI_MGMT_TLV_LAYOUT_H
79 #define CI_MGMT_TLV_LAYOUT_H
82 /* ----------------------------------------------------------------------------
83 * General structure (defined by SF-108797-SW)
84 * ----------------------------------------------------------------------------
90 * (Note that this is *not* followed by length or value fields: anything after
91 * the tag itself is irrelevant.)
94 #define TLV_TAG_END (0xEEEEEEEE)
97 /* Other special reserved tag values.
100 #define TLV_TAG_SKIP (0x00000000)
101 #define TLV_TAG_INVALID (0xFFFFFFFF)
104 /* TLV partition header.
106 * In a TLV partition, this must be the first item in the sequence, at offset
110 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
112 struct tlv_partition_header {
116 /* 0 indicates the default segment (always located at offset 0), while other values
117 * are for RFID-selectable presets that should immediately follow the default segment.
118 * The default segment may also have preset > 0, which means that it is a preset
119 * selected through an RFID command and copied by FW to the location at offset 0. */
122 uint32_t total_length;
126 /* TLV partition trailer.
128 * In a TLV partition, this must be the last item in the sequence, immediately
129 * preceding the TLV_TAG_END word.
132 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
134 struct tlv_partition_trailer {
142 /* Appendable TLV partition header.
144 * In an appendable TLV partition, this must be the first item in the sequence,
145 * at offset 0. (Note that, unlike the configuration partitions, there is no
146 * trailer before the TLV_TAG_END word.)
149 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
151 struct tlv_appendable_partition_header {
159 /* ----------------------------------------------------------------------------
160 * Configuration items
161 * ----------------------------------------------------------------------------
165 /* NIC global capabilities.
168 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
170 struct tlv_global_capabilities {
177 /* Siena-style per-port MAC address allocation.
179 * There are <count> addresses, starting at <base_address> and incrementing
180 * by adding <stride> to the low-order byte(s).
182 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
183 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
186 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
188 struct tlv_port_mac {
191 uint8_t base_address[6];
200 * This is the portion of VPD which is set at manufacturing time and not
201 * expected to change. It is formatted as a standard PCI VPD block. There are
202 * global and per-pf TLVs for this, the global TLV is new for Medford and is
203 * used in preference to the per-pf TLV.
206 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
208 struct tlv_pf_static_vpd {
214 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
216 struct tlv_global_static_vpd {
225 * This is the portion of VPD which may be changed (e.g. by firmware updates).
226 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
227 * for this, the global TLV is new for Medford and is used in preference to the
231 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
233 struct tlv_pf_dynamic_vpd {
239 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
241 struct tlv_global_dynamic_vpd {
248 /* "DBI" PCI config space changes.
250 * This is a set of edits made to the default PCI config space values before
251 * the device is allowed to enumerate. There are global and per-pf TLVs for
252 * this, the global TLV is new for Medford and is used in preference to the
256 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
263 uint16_t byte_enables;
269 #define TLV_TAG_GLOBAL_DBI (0x00210000)
271 struct tlv_global_dbi {
276 uint16_t byte_enables;
282 /* Partition subtype codes.
284 * A subtype may optionally be stored for each type of partition present in
285 * the NVRAM. For example, this may be used to allow a generic firmware update
286 * utility to select a specific variant of firmware for a specific variant of
289 * The description[] field is an optional string which is returned in the
290 * MC_CMD_NVRAM_METADATA response if present.
293 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
295 struct tlv_partition_subtype {
299 uint8_t description[];
303 /* Partition version codes.
305 * A version may optionally be stored for each type of partition present in
306 * the NVRAM. This provides a standard way of tracking the currently stored
307 * version of each of the various component images.
310 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
312 struct tlv_partition_version {
321 /* Global PCIe configuration */
323 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
325 struct tlv_pcie_config {
328 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
329 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
330 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
331 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
332 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
333 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
336 /* Per-PF configuration. Note that not all these fields are necessarily useful
337 * as the apertures are constrained by the BIU settings (the one case we do
338 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
339 * tidy things up later */
341 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
343 struct tlv_per_pf_pcie_config {
347 uint8_t port_allocation;
348 uint16_t vectors_per_pf;
349 uint16_t vectors_per_vf;
350 uint8_t pf_bar0_aperture;
351 uint8_t pf_bar2_aperture;
352 uint8_t vf_bar0_aperture;
354 uint16_t supp_pagesz;
355 uint16_t msix_vec_base;
359 /* Development ONLY. This is a single TLV tag for all the gubbins
360 * that can be set through the MC command-line other than the PCIe
361 * settings. This is a temporary measure. */
362 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
363 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
365 struct tlv_tmp_gubbins {
368 /* Consumed by dpcpu.c */
369 uint64_t tx0_tags; /* Bitmap */
370 uint64_t tx1_tags; /* Bitmap */
371 uint64_t dl_tags; /* Bitmap */
373 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
374 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
375 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
376 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
377 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
378 /* Consumed by features.c */
379 uint32_t dut_features; /* All 1s -> leave alone */
380 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
381 /* Consumed by clocks_hunt.c */
382 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
383 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
384 int8_t rx_dc_size; /* -1 -> leave alone */
386 int16_t num_q_allocs;
389 /* Global port configuration
391 * This is now deprecated in favour of a platform-provided default
392 * and dynamic config override via tlv_global_port_options.
394 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
396 struct tlv_global_port_config {
399 uint32_t ports_per_core;
400 uint32_t max_port_speed;
406 * This is intended for user-configurable selection of optional firmware
407 * features and variants.
409 * Initially, this consists only of the satellite CPU firmware variant
410 * selection, but this tag could be extended in the future (using the
411 * tag length to determine whether additional fields are present).
414 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
416 struct tlv_firmware_options {
419 uint32_t firmware_variant;
420 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
422 /* These are the values for overriding the driver's choice; the definitions
423 * are taken from MCDI so that they don't get out of step. Include
424 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
425 * you need to use these constants.
427 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
428 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
429 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
430 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
431 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
432 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
437 * Intended for boards with A0 silicon where the core voltage may
438 * need tweaking. Most likely set once when the pass voltage is
441 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
443 struct tlv_0v9_settings {
446 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
447 #define TLV_TAG_0V9_REQUIRES_FAN (1)
448 uint16_t target_voltage; /* In millivolts */
449 /* Since the limits are meant to be centred to the target (and must at least
450 * contain it) they need setting as well. */
451 uint16_t warn_low; /* In millivolts */
452 uint16_t warn_high; /* In millivolts */
453 uint16_t panic_low; /* In millivolts */
454 uint16_t panic_high; /* In millivolts */
458 /* Clock configuration */
460 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
461 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
463 struct tlv_clock_config {
466 uint16_t clk_sys; /* MHz */
467 uint16_t clk_dpcpu; /* MHz */
468 uint16_t clk_icore; /* MHz */
469 uint16_t clk_pcs; /* MHz */
472 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
474 struct tlv_clock_config_medford {
477 uint16_t clk_sys; /* MHz */
478 uint16_t clk_mc; /* MHz */
479 uint16_t clk_rmon; /* MHz */
480 uint16_t clk_vswitch; /* MHz */
481 uint16_t clk_dpcpu; /* MHz */
482 uint16_t clk_pcs; /* MHz */
486 /* EF10-style global pool of MAC addresses.
488 * There are <count> addresses, starting at <base_address>, which are
489 * contiguous. Firmware is responsible for allocating addresses from this
490 * pool to ports / PFs as appropriate.
493 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
495 struct tlv_global_mac {
498 uint8_t base_address[6];
504 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
505 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
507 /* The target value for the 0v9 power rail measured on-chip at the
508 * analogue test bus */
509 struct tlv_0v9_atb_target {
516 /* Global PCIe configuration, second revision. This represents the visible PFs
517 * by a bitmap rather than having the number of the highest visible one. As such
518 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
519 * can and it should be used in place of that tag in future (but compatibility with
520 * the old tag will be left in the firmware indefinitely). */
522 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
524 struct tlv_pcie_config_r2 {
527 uint16_t visible_pfs; /**< Bitmap of visible PFs */
528 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
529 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
530 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
533 /* Dynamic port mode.
535 * Allows selecting alternate port configuration for platforms that support it
536 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
537 * number of externally visible ports (and, hence, PF to port mapping), so must
538 * be done at boot time.
540 * This tag supercedes tlv_global_port_config.
543 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
545 struct tlv_global_port_mode {
549 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
550 #define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */
551 #define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */
552 #define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
553 #define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
554 #define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */
555 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */
556 #define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
557 #define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
558 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */
559 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2
562 /* Type of the v-switch created implicitly by the firmware */
564 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
566 struct tlv_vswitch_type {
569 uint32_t vswitch_type;
570 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
571 #define TLV_VSWITCH_TYPE_NONE (0)
572 #define TLV_VSWITCH_TYPE_VLAN (1)
573 #define TLV_VSWITCH_TYPE_VEB (2)
574 #define TLV_VSWITCH_TYPE_VEPA (3)
575 #define TLV_VSWITCH_TYPE_MUX (4)
576 #define TLV_VSWITCH_TYPE_TEST (5)
579 /* A VLAN tag for the v-port created implicitly by the firmware */
581 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
583 struct tlv_vport_vlan_tag {
587 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
590 /* Offset to be applied to the 0v9 setting, wherever it came from */
592 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
594 struct tlv_0v9_atb_offset {
597 int16_t offset_millivolts;
601 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
602 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
603 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
604 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
605 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
607 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
609 struct tlv_privilege_mask { /* legacy structure - do not use */
612 uint32_t privilege_mask;
615 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
617 struct tlv_privilege_mask_add {
620 uint32_t privilege_mask_add;
623 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
625 struct tlv_privilege_mask_rem {
628 uint32_t privilege_mask_rem;
631 /* Additional privileges given to all PFs.
632 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
634 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
636 struct tlv_privilege_mask_add_all_pfs {
639 uint32_t privilege_mask_add;
642 /* Additional privileges given to a selected PF.
643 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
645 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
647 struct tlv_privilege_mask_add_single_pf {
650 uint32_t privilege_mask_add;
653 /* Turning on/off the PFIOV mode.
654 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
656 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
662 #define TLV_PFIOV_OFF (0) /* Default */
663 #define TLV_PFIOV_ON (1)
666 /* Multicast filter chaining mode selection.
668 * When enabled, multicast packets are delivered to all recipients of all
669 * matching multicast filters, with the exception that IP multicast filters
670 * will steal traffic from MAC multicast filters on a per-function basis.
673 * When disabled, multicast packets will always be delivered only to the
674 * recipients of the highest priority matching multicast filter.
675 * (Legacy behaviour.)
677 * The DEFAULT mode (which is the same as the tag not being present at all)
678 * is equivalent to ENABLED in production builds, and DISABLED in eftest
681 * This option is intended to provide run-time control over this feature
682 * while it is being stabilised and may be withdrawn at some point in the
683 * future; the new behaviour is intended to become the standard behaviour.
686 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
688 struct tlv_mcast_filter_chaining {
692 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
693 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
694 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
697 /* Pacer rate limit per PF */
698 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
700 struct tlv_rate_limit {
706 /* OCSD Enable/Disable
708 * This setting allows OCSD to be disabled. This is a requirement for HP
709 * servers to support PCI passthrough for virtualization.
711 * The DEFAULT mode (which is the same as the tag not being present) is
712 * equivalent to ENABLED.
714 * This option is not used by the MCFW, and is entirely handled by the various
715 * drivers that support OCSD, by reading the setting before they attempt
718 * bit0: OCSD Disabled/Enabled
721 #define TLV_TAG_OCSD (0x101C0000)
727 #define TLV_OCSD_DISABLED 0
728 #define TLV_OCSD_ENABLED 1 /* Default */
731 /* Descriptor cache config.
733 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
734 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
735 * away from the highest numbered port first, so a vi_count of 1024 means 1024
736 * VIs on the first port and 0 on the second (on a Torino).
739 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
741 struct tlv_descriptor_cache_config {
744 uint8_t rx_desc_cache_size;
745 uint8_t tx_desc_cache_size;
748 #define TLV_DESC_CACHE_DEFAULT (0xff)
749 #define TLV_VI_COUNT_DEFAULT (0xffff)
751 /* RX event merging config (read batching).
753 * Sets the global maximum number of events for the merging bins, and the
754 * global timeout configuration for the bins.
757 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
759 struct tlv_rx_event_merging_config {
763 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
766 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7
767 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740
769 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
770 struct tlv_pcie_link_settings {
773 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
774 uint16_t width; /* Number of lanes */
777 #define TLV_TAG_LICENSE (0x20800000)
779 typedef struct tlv_license {
785 #endif /* CI_MGMT_TLV_LAYOUT_H */