sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efsys.h"
  37 #include "efx.h"
  38 #include "efx_regs.h"
  39 #include "efx_regs_ef10.h"
  40
  41 /* FIXME: Add definition for driver generated software events */
  42 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  43 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  44 #endif
  45
  46 #include "efx_check.h"
  47
  48
  49 #if EFSYS_OPT_FALCON
  50 #include "falcon_impl.h"
  51 #endif  /* EFSYS_OPT_FALCON */
  52
  53 #if EFSYS_OPT_SIENA
  54 #include "siena_impl.h"
  55 #endif  /* EFSYS_OPT_SIENA */
  56
  57 #if EFSYS_OPT_HUNTINGTON
  58 #include "hunt_impl.h"
  59 #endif  /* EFSYS_OPT_HUNTINGTON */
  60
  61 #if EFSYS_OPT_MEDFORD
  62 #include "medford_impl.h"
  63 #endif  /* EFSYS_OPT_MEDFORD */
  64
  65 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  66 #include "ef10_impl.h"
  67 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  68
  69 #ifdef  __cplusplus
  70 extern "C" {
  71 #endif
  72
  73 #define EFX_MOD_MCDI            0x00000001
  74 #define EFX_MOD_PROBE           0x00000002
  75 #define EFX_MOD_NVRAM           0x00000004
  76 #define EFX_MOD_VPD             0x00000008
  77 #define EFX_MOD_NIC             0x00000010
  78 #define EFX_MOD_INTR            0x00000020
  79 #define EFX_MOD_EV              0x00000040
  80 #define EFX_MOD_RX              0x00000080
  81 #define EFX_MOD_TX              0x00000100
  82 #define EFX_MOD_PORT            0x00000200
  83 #define EFX_MOD_MON             0x00000400
  84 #define EFX_MOD_WOL             0x00000800
  85 #define EFX_MOD_FILTER          0x00001000
  86 #define EFX_MOD_PKTFILTER       0x00002000
  87 #define EFX_MOD_LIC             0x00004000
  88
  89 #define EFX_RESET_MAC           0x00000001
  90 #define EFX_RESET_PHY           0x00000002
  91 #define EFX_RESET_RXQ_ERR       0x00000004
  92 #define EFX_RESET_TXQ_ERR       0x00000008
  93
  94 typedef enum efx_mac_type_e {
  95         EFX_MAC_INVALID = 0,
  96         EFX_MAC_FALCON_GMAC,
  97         EFX_MAC_FALCON_XMAC,
  98         EFX_MAC_SIENA,
  99         EFX_MAC_HUNTINGTON,
 100         EFX_MAC_MEDFORD,
 101         EFX_MAC_NTYPES
 102 } efx_mac_type_t;
 103
 104 typedef struct efx_ev_ops_s {
 105         efx_rc_t        (*eevo_init)(efx_nic_t *);
 106         void            (*eevo_fini)(efx_nic_t *);
 107         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
 108                                           efsys_mem_t *, size_t, uint32_t,
 109                                           efx_evq_t *);
 110         void            (*eevo_qdestroy)(efx_evq_t *);
 111         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 112         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 113         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 114 #if EFSYS_OPT_QSTATS
 115         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 116 #endif
 117 } efx_ev_ops_t;
 118
 119 typedef struct efx_tx_ops_s {
 120         efx_rc_t        (*etxo_init)(efx_nic_t *);
 121         void            (*etxo_fini)(efx_nic_t *);
 122         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 123                                         unsigned int, unsigned int,
 124                                         efsys_mem_t *, size_t,
 125                                         uint32_t, uint16_t,
 126                                         efx_evq_t *, efx_txq_t *,
 127                                         unsigned int *);
 128         void            (*etxo_qdestroy)(efx_txq_t *);
 129         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 130                                       unsigned int, unsigned int,
 131                                       unsigned int *);
 132         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 133         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 134         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 135         void            (*etxo_qenable)(efx_txq_t *);
 136         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 137         void            (*etxo_qpio_disable)(efx_txq_t *);
 138         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 139                                            size_t);
 140         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 141                                            unsigned int *);
 142         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 143                                       unsigned int, unsigned int,
 144                                       unsigned int *);
 145         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 146                                                 size_t, boolean_t,
 147                                                 efx_desc_t *);
 148         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 149                                                 uint32_t, uint8_t,
 150                                                 efx_desc_t *);
 151         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 152                                                 uint32_t, uint16_t,
 153                                                 efx_desc_t *, int);
 154         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 155                                                 efx_desc_t *);
 156 #if EFSYS_OPT_QSTATS
 157         void            (*etxo_qstats_update)(efx_txq_t *,
 158                                               efsys_stat_t *);
 159 #endif
 160 } efx_tx_ops_t;
 161
 162 typedef struct efx_rx_ops_s {
 163         efx_rc_t        (*erxo_init)(efx_nic_t *);
 164         void            (*erxo_fini)(efx_nic_t *);
 165 #if EFSYS_OPT_RX_SCATTER
 166         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 167 #endif
 168 #if EFSYS_OPT_RX_SCALE
 169         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 170                                                efx_rx_hash_type_t, boolean_t);
 171         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 172         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 173                                               size_t);
 174         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 175                                             uint8_t *);
 176 #endif /* EFSYS_OPT_RX_SCALE */
 177         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 178                                               uint16_t *);
 179         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 180                                       unsigned int, unsigned int,
 181                                       unsigned int);
 182         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 183         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 184         void            (*erxo_qenable)(efx_rxq_t *);
 185         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 186                                         unsigned int, efx_rxq_type_t,
 187                                         efsys_mem_t *, size_t, uint32_t,
 188                                         efx_evq_t *, efx_rxq_t *);
 189         void            (*erxo_qdestroy)(efx_rxq_t *);
 190 } efx_rx_ops_t;
 191
 192 typedef struct efx_mac_ops_s {
 193         efx_rc_t        (*emo_reset)(efx_nic_t *); /* optional */
 194         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 195         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 196         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 197         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 199         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 200         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 201                                                       efx_rxq_t *, boolean_t);
 202         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 203 #if EFSYS_OPT_LOOPBACK
 204         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 205                                             efx_loopback_type_t);
 206 #endif  /* EFSYS_OPT_LOOPBACK */
 207 #if EFSYS_OPT_MAC_STATS
 208         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 209         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 210                                               uint16_t, boolean_t);
 211         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             efsys_stat_t *, uint32_t *);
 213 #endif  /* EFSYS_OPT_MAC_STATS */
 214 } efx_mac_ops_t;
 215
 216 typedef struct efx_phy_ops_s {
 217         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 218         efx_rc_t        (*epo_reset)(efx_nic_t *);
 219         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 220         efx_rc_t        (*epo_verify)(efx_nic_t *);
 221         efx_rc_t        (*epo_uplink_check)(efx_nic_t *,
 222                                             boolean_t *); /* optional */
 223         efx_rc_t        (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
 224                                               unsigned int *, uint32_t *);
 225         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 226 #if EFSYS_OPT_PHY_STATS
 227         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 228                                             uint32_t *);
 229 #endif  /* EFSYS_OPT_PHY_STATS */
 230 #if EFSYS_OPT_PHY_PROPS
 231 #if EFSYS_OPT_NAMES
 232         const char      *(*epo_prop_name)(efx_nic_t *, unsigned int);
 233 #endif  /* EFSYS_OPT_PHY_PROPS */
 234         efx_rc_t        (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
 235                                         uint32_t *);
 236         efx_rc_t        (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
 237 #endif  /* EFSYS_OPT_PHY_PROPS */
 238 #if EFSYS_OPT_BIST
 239         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 240         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 241         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 242                                          efx_bist_result_t *, uint32_t *,
 243                                          unsigned long *, size_t);
 244         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 245 #endif  /* EFSYS_OPT_BIST */
 246 } efx_phy_ops_t;
 247
 248 #if EFSYS_OPT_FILTER
 249 typedef struct efx_filter_ops_s {
 250         efx_rc_t        (*efo_init)(efx_nic_t *);
 251         void            (*efo_fini)(efx_nic_t *);
 252         efx_rc_t        (*efo_restore)(efx_nic_t *);
 253         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 254                                    boolean_t may_replace);
 255         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 256         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 257         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 258                                    boolean_t, boolean_t, boolean_t,
 259                                    uint8_t const *, int);
 260 } efx_filter_ops_t;
 261
 262 extern  __checkReturn   efx_rc_t
 263 efx_filter_reconfigure(
 264         __in                            efx_nic_t *enp,
 265         __in_ecount(6)                  uint8_t const *mac_addr,
 266         __in                            boolean_t all_unicst,
 267         __in                            boolean_t mulcst,
 268         __in                            boolean_t all_mulcst,
 269         __in                            boolean_t brdcst,
 270         __in_ecount(6*count)            uint8_t const *addrs,
 271         __in                            int count);
 272
 273 #endif /* EFSYS_OPT_FILTER */
 274
 275
 276 typedef struct efx_port_s {
 277         efx_mac_type_t          ep_mac_type;
 278         uint32_t                ep_phy_type;
 279         uint8_t                 ep_port;
 280         uint32_t                ep_mac_pdu;
 281         uint8_t                 ep_mac_addr[6];
 282         efx_link_mode_t         ep_link_mode;
 283         boolean_t               ep_all_unicst;
 284         boolean_t               ep_mulcst;
 285         boolean_t               ep_all_mulcst;
 286         boolean_t               ep_brdcst;
 287         unsigned int            ep_fcntl;
 288         boolean_t               ep_fcntl_autoneg;
 289         efx_oword_t             ep_multicst_hash[2];
 290         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 291                                                     EFX_MAC_MULTICAST_LIST_MAX];
 292         uint32_t                ep_mulcst_addr_count;
 293 #if EFSYS_OPT_LOOPBACK
 294         efx_loopback_type_t     ep_loopback_type;
 295         efx_link_mode_t         ep_loopback_link_mode;
 296 #endif  /* EFSYS_OPT_LOOPBACK */
 297 #if EFSYS_OPT_PHY_FLAGS
 298         uint32_t                ep_phy_flags;
 299 #endif  /* EFSYS_OPT_PHY_FLAGS */
 300 #if EFSYS_OPT_PHY_LED_CONTROL
 301         efx_phy_led_mode_t      ep_phy_led_mode;
 302 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 303         efx_phy_media_type_t    ep_fixed_port_type;
 304         efx_phy_media_type_t    ep_module_type;
 305         uint32_t                ep_adv_cap_mask;
 306         uint32_t                ep_lp_cap_mask;
 307         uint32_t                ep_default_adv_cap_mask;
 308         uint32_t                ep_phy_cap_mask;
 309 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
 310         union {
 311                 struct {
 312                         unsigned int    bug10934_count;
 313                 } ep_txc43128;
 314                 struct {
 315                         unsigned int    bug17190_count;
 316                 } ep_qt2025c;
 317         };
 318 #endif
 319         boolean_t               ep_mac_poll_needed; /* falcon only */
 320         boolean_t               ep_mac_up; /* falcon only */
 321         uint32_t                ep_fwver; /* falcon only */
 322         boolean_t               ep_mac_drain;
 323         boolean_t               ep_mac_stats_pending;
 324 #if EFSYS_OPT_BIST
 325         efx_bist_type_t         ep_current_bist;
 326 #endif
 327         efx_mac_ops_t           *ep_emop;
 328         efx_phy_ops_t           *ep_epop;
 329 } efx_port_t;
 330
 331 typedef struct efx_mon_ops_s {
 332         efx_rc_t        (*emo_reset)(efx_nic_t *);
 333         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 334 #if EFSYS_OPT_MON_STATS
 335         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 336                                             efx_mon_stat_value_t *);
 337 #endif  /* EFSYS_OPT_MON_STATS */
 338 } efx_mon_ops_t;
 339
 340 typedef struct efx_mon_s {
 341         efx_mon_type_t  em_type;
 342         efx_mon_ops_t   *em_emop;
 343 } efx_mon_t;
 344
 345 typedef struct efx_intr_ops_s {
 346         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 347         void            (*eio_enable)(efx_nic_t *);
 348         void            (*eio_disable)(efx_nic_t *);
 349         void            (*eio_disable_unlocked)(efx_nic_t *);
 350         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 351         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 352         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 353                                  boolean_t *);
 354         void            (*eio_fatal)(efx_nic_t *);
 355         void            (*eio_fini)(efx_nic_t *);
 356 } efx_intr_ops_t;
 357
 358 typedef struct efx_intr_s {
 359         efx_intr_ops_t  *ei_eiop;
 360         efsys_mem_t     *ei_esmp;
 361         efx_intr_type_t ei_type;
 362         unsigned int    ei_level;
 363 } efx_intr_t;
 364
 365 typedef struct efx_nic_ops_s {
 366         efx_rc_t        (*eno_probe)(efx_nic_t *);
 367         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 368         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 369         efx_rc_t        (*eno_reset)(efx_nic_t *);
 370         efx_rc_t        (*eno_init)(efx_nic_t *);
 371         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 372         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 373                                         uint32_t *, size_t *);
 374 #if EFSYS_OPT_DIAG
 375         efx_rc_t        (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
 376         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 377 #endif  /* EFSYS_OPT_DIAG */
 378         void            (*eno_fini)(efx_nic_t *);
 379         void            (*eno_unprobe)(efx_nic_t *);
 380 } efx_nic_ops_t;
 381
 382 #ifndef EFX_TXQ_LIMIT_TARGET
 383 #define EFX_TXQ_LIMIT_TARGET 259
 384 #endif
 385 #ifndef EFX_RXQ_LIMIT_TARGET
 386 #define EFX_RXQ_LIMIT_TARGET 512
 387 #endif
 388 #ifndef EFX_TXQ_DC_SIZE
 389 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 390 #endif
 391 #ifndef EFX_RXQ_DC_SIZE
 392 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 393 #endif
 394
 395 #if EFSYS_OPT_FILTER
 396
 397 typedef struct falconsiena_filter_spec_s {
 398         uint8_t         fsfs_type;
 399         uint32_t        fsfs_flags;
 400         uint32_t        fsfs_dmaq_id;
 401         uint32_t        fsfs_dword[3];
 402 } falconsiena_filter_spec_t;
 403
 404 typedef enum falconsiena_filter_type_e {
 405         EFX_FS_FILTER_RX_TCP_FULL,      /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
 406         EFX_FS_FILTER_RX_TCP_WILD,      /* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
 407         EFX_FS_FILTER_RX_UDP_FULL,      /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
 408         EFX_FS_FILTER_RX_UDP_WILD,      /* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
 409
 410 #if EFSYS_OPT_SIENA
 411         EFX_FS_FILTER_RX_MAC_FULL,      /* Ethernet {dMAC,VLAN} */
 412         EFX_FS_FILTER_RX_MAC_WILD,      /* Ethernet {dMAC,   -} */
 413
 414         EFX_FS_FILTER_TX_TCP_FULL,              /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 415         EFX_FS_FILTER_TX_TCP_WILD,              /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 416         EFX_FS_FILTER_TX_UDP_FULL,              /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 417         EFX_FS_FILTER_TX_UDP_WILD,              /* UDP/IPv4 source (host, port) */
 418
 419         EFX_FS_FILTER_TX_MAC_FULL,              /* Ethernet source (MAC address, VLAN ID) */
 420         EFX_FS_FILTER_TX_MAC_WILD,              /* Ethernet source (MAC address) */
 421 #endif /* EFSYS_OPT_SIENA */
 422
 423         EFX_FS_FILTER_NTYPES
 424 } falconsiena_filter_type_t;
 425
 426 typedef enum falconsiena_filter_tbl_id_e {
 427         EFX_FS_FILTER_TBL_RX_IP = 0,
 428         EFX_FS_FILTER_TBL_RX_MAC,
 429         EFX_FS_FILTER_TBL_TX_IP,
 430         EFX_FS_FILTER_TBL_TX_MAC,
 431         EFX_FS_FILTER_NTBLS
 432 } falconsiena_filter_tbl_id_t;
 433
 434 typedef struct falconsiena_filter_tbl_s {
 435         int                             fsft_size;      /* number of entries */
 436         int                             fsft_used;      /* active count */
 437         uint32_t                        *fsft_bitmap;   /* active bitmap */
 438         falconsiena_filter_spec_t       *fsft_spec;     /* array of saved specs */
 439 } falconsiena_filter_tbl_t;
 440
 441 typedef struct falconsiena_filter_s {
 442         falconsiena_filter_tbl_t        fsf_tbl[EFX_FS_FILTER_NTBLS];
 443         unsigned int                    fsf_depth[EFX_FS_FILTER_NTYPES];
 444 } falconsiena_filter_t;
 445
 446 typedef struct efx_filter_s {
 447 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
 448         falconsiena_filter_t    *ef_falconsiena_filter;
 449 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
 450 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 451         ef10_filter_table_t     *ef_ef10_filter_table;
 452 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 453 } efx_filter_t;
 454
 455 extern                  void
 456 falconsiena_filter_tbl_clear(
 457         __in            efx_nic_t *enp,
 458         __in            falconsiena_filter_tbl_id_t tbl);
 459
 460 #endif  /* EFSYS_OPT_FILTER */
 461
 462 #if EFSYS_OPT_MCDI
 463
 464 typedef struct efx_mcdi_ops_s {
 465         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 466         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 467                                         void *, size_t);
 468         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 469         boolean_t       (*emco_poll_response)(efx_nic_t *);
 470         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 471         void            (*emco_fini)(efx_nic_t *);
 472         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 473 } efx_mcdi_ops_t;
 474
 475 typedef struct efx_mcdi_s {
 476         efx_mcdi_ops_t                  *em_emcop;
 477         const efx_mcdi_transport_t      *em_emtp;
 478         efx_mcdi_iface_t                em_emip;
 479 } efx_mcdi_t;
 480
 481 #endif /* EFSYS_OPT_MCDI */
 482
 483 #if EFSYS_OPT_NVRAM
 484 typedef struct efx_nvram_ops_s {
 485 #if EFSYS_OPT_DIAG
 486         efx_rc_t        (*envo_test)(efx_nic_t *);
 487 #endif  /* EFSYS_OPT_DIAG */
 488         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 489                                             uint32_t *);
 490         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 491         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 492         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 493                                             unsigned int, caddr_t, size_t);
 494         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 495                                             unsigned int, size_t);
 496         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 497                                             unsigned int, caddr_t, size_t);
 498         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 499         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 500                                             uint32_t *, uint16_t *);
 501         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 502                                             uint16_t *);
 503 } efx_nvram_ops_t;
 504 #endif /* EFSYS_OPT_NVRAM */
 505
 506 #if EFSYS_OPT_VPD
 507 typedef struct efx_vpd_ops_s {
 508         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 509         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 510         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 511         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 512         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 513         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 514                                         efx_vpd_value_t *);
 515         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 516                                         efx_vpd_value_t *);
 517         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 518                                         efx_vpd_value_t *, unsigned int *);
 519         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 520         void            (*evpdo_fini)(efx_nic_t *);
 521 } efx_vpd_ops_t;
 522 #endif  /* EFSYS_OPT_VPD */
 523
 524 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 525
 526         __checkReturn           efx_rc_t
 527 efx_mcdi_nvram_partitions(
 528         __in                    efx_nic_t *enp,
 529         __out_bcount(size)      caddr_t data,
 530         __in                    size_t size,
 531         __out                   unsigned int *npartnp);
 532
 533         __checkReturn           efx_rc_t
 534 efx_mcdi_nvram_metadata(
 535         __in                    efx_nic_t *enp,
 536         __in                    uint32_t partn,
 537         __out                   uint32_t *subtypep,
 538         __out_ecount(4)         uint16_t version[4],
 539         __out_bcount_opt(size)  char *descp,
 540         __in                    size_t size);
 541
 542         __checkReturn           efx_rc_t
 543 efx_mcdi_nvram_info(
 544         __in                    efx_nic_t *enp,
 545         __in                    uint32_t partn,
 546         __out_opt               size_t *sizep,
 547         __out_opt               uint32_t *addressp,
 548         __out_opt               uint32_t *erase_sizep,
 549         __out_opt               uint32_t *write_sizep);
 550
 551         __checkReturn           efx_rc_t
 552 efx_mcdi_nvram_update_start(
 553         __in                    efx_nic_t *enp,
 554         __in                    uint32_t partn);
 555
 556         __checkReturn           efx_rc_t
 557 efx_mcdi_nvram_read(
 558         __in                    efx_nic_t *enp,
 559         __in                    uint32_t partn,
 560         __in                    uint32_t offset,
 561         __out_bcount(size)      caddr_t data,
 562         __in                    size_t size,
 563         __in                    uint32_t mode);
 564
 565         __checkReturn           efx_rc_t
 566 efx_mcdi_nvram_erase(
 567         __in                    efx_nic_t *enp,
 568         __in                    uint32_t partn,
 569         __in                    uint32_t offset,
 570         __in                    size_t size);
 571
 572         __checkReturn           efx_rc_t
 573 efx_mcdi_nvram_write(
 574         __in                    efx_nic_t *enp,
 575         __in                    uint32_t partn,
 576         __in                    uint32_t offset,
 577         __out_bcount(size)      caddr_t data,
 578         __in                    size_t size);
 579
 580         __checkReturn           efx_rc_t
 581 efx_mcdi_nvram_update_finish(
 582         __in                    efx_nic_t *enp,
 583         __in                    uint32_t partn,
 584         __in                    boolean_t reboot);
 585
 586 #if EFSYS_OPT_DIAG
 587
 588         __checkReturn           efx_rc_t
 589 efx_mcdi_nvram_test(
 590         __in                    efx_nic_t *enp,
 591         __in                    uint32_t partn);
 592
 593 #endif  /* EFSYS_OPT_DIAG */
 594
 595 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 596
 597 #if EFSYS_OPT_LICENSING
 598
 599 typedef struct efx_lic_ops_s {
 600         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 601         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 602         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 603         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 604                                       size_t *, uint8_t *);
 605 } efx_lic_ops_t;
 606
 607 #endif
 608
 609 typedef struct efx_drv_cfg_s {
 610         uint32_t                edc_min_vi_count;
 611         uint32_t                edc_max_vi_count;
 612
 613         uint32_t                edc_max_piobuf_count;
 614         uint32_t                edc_pio_alloc_size;
 615 } efx_drv_cfg_t;
 616
 617 struct efx_nic_s {
 618         uint32_t                en_magic;
 619         efx_family_t            en_family;
 620         uint32_t                en_features;
 621         efsys_identifier_t      *en_esip;
 622         efsys_lock_t            *en_eslp;
 623         efsys_bar_t             *en_esbp;
 624         unsigned int            en_mod_flags;
 625         unsigned int            en_reset_flags;
 626         efx_nic_cfg_t           en_nic_cfg;
 627         efx_drv_cfg_t           en_drv_cfg;
 628         efx_port_t              en_port;
 629         efx_mon_t               en_mon;
 630         efx_intr_t              en_intr;
 631         uint32_t                en_ev_qcount;
 632         uint32_t                en_rx_qcount;
 633         uint32_t                en_tx_qcount;
 634         efx_nic_ops_t           *en_enop;
 635         efx_ev_ops_t            *en_eevop;
 636         efx_tx_ops_t            *en_etxop;
 637         efx_rx_ops_t            *en_erxop;
 638 #if EFSYS_OPT_FILTER
 639         efx_filter_t            en_filter;
 640         efx_filter_ops_t        *en_efop;
 641 #endif  /* EFSYS_OPT_FILTER */
 642 #if EFSYS_OPT_MCDI
 643         efx_mcdi_t              en_mcdi;
 644 #endif  /* EFSYS_OPT_MCDI */
 645 #if EFSYS_OPT_NVRAM
 646         efx_nvram_type_t        en_nvram_locked;
 647         efx_nvram_ops_t         *en_envop;
 648 #endif  /* EFSYS_OPT_NVRAM */
 649 #if EFSYS_OPT_VPD
 650         efx_vpd_ops_t           *en_evpdop;
 651 #endif  /* EFSYS_OPT_VPD */
 652 #if EFSYS_OPT_RX_SCALE
 653         efx_rx_hash_support_t   en_hash_support;
 654         efx_rx_scale_support_t  en_rss_support;
 655         uint32_t                en_rss_context;
 656 #endif  /* EFSYS_OPT_RX_SCALE */
 657         uint32_t                en_vport_id;
 658 #if EFSYS_OPT_LICENSING
 659         efx_lic_ops_t           *en_elop;
 660 #endif
 661         union {
 662 #if EFSYS_OPT_FALCON
 663                 struct {
 664                         falcon_spi_dev_t        enu_fsd[FALCON_SPI_NTYPES];
 665                         falcon_i2c_t            enu_fip;
 666                         boolean_t               enu_i2c_locked;
 667 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
 668                         const uint8_t           *enu_forced_cfg;
 669 #endif  /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
 670                         uint8_t                 enu_mon_devid;
 671 #if EFSYS_OPT_PCIE_TUNE
 672                         unsigned int            enu_nlanes;
 673 #endif  /* EFSYS_OPT_PCIE_TUNE */
 674                         uint16_t                enu_board_rev;
 675                         boolean_t               enu_internal_sram;
 676                         uint8_t                 enu_sram_num_bank;
 677                         uint8_t                 enu_sram_bank_size;
 678                 } falcon;
 679 #endif  /* EFSYS_OPT_FALCON */
 680 #if EFSYS_OPT_SIENA
 681                 struct {
 682 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 683                         unsigned int            enu_partn_mask;
 684 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 685 #if EFSYS_OPT_VPD
 686                         caddr_t                 enu_svpd;
 687                         size_t                  enu_svpd_length;
 688 #endif  /* EFSYS_OPT_VPD */
 689                         int                     enu_unused;
 690                 } siena;
 691 #endif  /* EFSYS_OPT_SIENA */
 692                 int     enu_unused;
 693         } en_u;
 694 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 695         union en_arch {
 696                 struct {
 697                         int                     ena_vi_base;
 698                         int                     ena_vi_count;
 699                         int                     ena_vi_shift;
 700 #if EFSYS_OPT_VPD
 701                         caddr_t                 ena_svpd;
 702                         size_t                  ena_svpd_length;
 703 #endif  /* EFSYS_OPT_VPD */
 704                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 705                         uint32_t                ena_piobuf_count;
 706                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 707                         uint32_t                ena_pio_write_vi_base;
 708                         /* Memory BAR mapping regions */
 709                         uint32_t                ena_uc_mem_map_offset;
 710                         size_t                  ena_uc_mem_map_size;
 711                         uint32_t                ena_wc_mem_map_offset;
 712                         size_t                  ena_wc_mem_map_size;
 713                 } ef10;
 714         } en_arch;
 715 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 716 };
 717
 718
 719 #define EFX_NIC_MAGIC   0x02121996
 720
 721 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 722     const efx_ev_callbacks_t *, void *);
 723
 724 typedef struct efx_evq_rxq_state_s {
 725         unsigned int                    eers_rx_read_ptr;
 726         unsigned int                    eers_rx_mask;
 727 } efx_evq_rxq_state_t;
 728
 729 struct efx_evq_s {
 730         uint32_t                        ee_magic;
 731         efx_nic_t                       *ee_enp;
 732         unsigned int                    ee_index;
 733         unsigned int                    ee_mask;
 734         efsys_mem_t                     *ee_esmp;
 735 #if EFSYS_OPT_QSTATS
 736         uint32_t                        ee_stat[EV_NQSTATS];
 737 #endif  /* EFSYS_OPT_QSTATS */
 738
 739         efx_ev_handler_t                ee_rx;
 740         efx_ev_handler_t                ee_tx;
 741         efx_ev_handler_t                ee_driver;
 742         efx_ev_handler_t                ee_global;
 743         efx_ev_handler_t                ee_drv_gen;
 744 #if EFSYS_OPT_MCDI
 745         efx_ev_handler_t                ee_mcdi;
 746 #endif  /* EFSYS_OPT_MCDI */
 747
 748         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 749 };
 750
 751 #define EFX_EVQ_MAGIC   0x08081997
 752
 753 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
 754 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 755
 756 struct efx_rxq_s {
 757         uint32_t                        er_magic;
 758         efx_nic_t                       *er_enp;
 759         efx_evq_t                       *er_eep;
 760         unsigned int                    er_index;
 761         unsigned int                    er_label;
 762         unsigned int                    er_mask;
 763         efsys_mem_t                     *er_esmp;
 764 };
 765
 766 #define EFX_RXQ_MAGIC   0x15022005
 767
 768 struct efx_txq_s {
 769         uint32_t                        et_magic;
 770         efx_nic_t                       *et_enp;
 771         unsigned int                    et_index;
 772         unsigned int                    et_mask;
 773         efsys_mem_t                     *et_esmp;
 774 #if EFSYS_OPT_HUNTINGTON
 775         uint32_t                        et_pio_bufnum;
 776         uint32_t                        et_pio_blknum;
 777         uint32_t                        et_pio_write_offset;
 778         uint32_t                        et_pio_offset;
 779         size_t                          et_pio_size;
 780 #endif
 781 #if EFSYS_OPT_QSTATS
 782         uint32_t                        et_stat[TX_NQSTATS];
 783 #endif  /* EFSYS_OPT_QSTATS */
 784 };
 785
 786 #define EFX_TXQ_MAGIC   0x05092005
 787
 788 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 789         do {                                                            \
 790                 (_dst)[0] = (_src)[0];                                  \
 791                 (_dst)[1] = (_src)[1];                                  \
 792                 (_dst)[2] = (_src)[2];                                  \
 793                 (_dst)[3] = (_src)[3];                                  \
 794                 (_dst)[4] = (_src)[4];                                  \
 795                 (_dst)[5] = (_src)[5];                                  \
 796         _NOTE(CONSTANTCONDITION)                                        \
 797         } while (B_FALSE)
 798
 799 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 800         do {                                                            \
 801                 uint16_t *_d = (uint16_t *)(_dst);                      \
 802                 _d[0] = 0xffff;                                         \
 803                 _d[1] = 0xffff;                                         \
 804                 _d[2] = 0xffff;                                         \
 805         _NOTE(CONSTANTCONDITION)                                        \
 806         } while (B_FALSE)
 807
 808 #if EFSYS_OPT_CHECK_REG
 809 #define EFX_CHECK_REG(_enp, _reg)                                       \
 810         do {                                                            \
 811                 const char *name = #_reg;                               \
 812                 char min = name[4];                                     \
 813                 char max = name[5];                                     \
 814                 char rev;                                               \
 815                                                                         \
 816                 switch ((_enp)->en_family) {                            \
 817                 case EFX_FAMILY_FALCON:                                 \
 818                         rev = 'B';                                      \
 819                         break;                                          \
 820                                                                         \
 821                 case EFX_FAMILY_SIENA:                                  \
 822                         rev = 'C';                                      \
 823                         break;                                          \
 824                                                                         \
 825                 case EFX_FAMILY_HUNTINGTON:                             \
 826                         rev = 'D';                                      \
 827                         break;                                          \
 828                                                                         \
 829                 case EFX_FAMILY_MEDFORD:                                \
 830                         rev = 'E';                                      \
 831                         break;                                          \
 832                                                                         \
 833                 default:                                                \
 834                         rev = '?';                                      \
 835                         break;                                          \
 836                 }                                                       \
 837                                                                         \
 838                 EFSYS_ASSERT3S(rev, >=, min);                           \
 839                 EFSYS_ASSERT3S(rev, <=, max);                           \
 840                                                                         \
 841         _NOTE(CONSTANTCONDITION)                                        \
 842         } while (B_FALSE)
 843 #else
 844 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 845         _NOTE(CONSTANTCONDITION)                                        \
 846         } while(B_FALSE)
 847 #endif
 848
 849 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 850         do {                                                            \
 851                 EFX_CHECK_REG((_enp), (_reg));                          \
 852                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 853                     (_edp), (_lock));                                   \
 854                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 855                     uint32_t, _reg ## _OFST,                            \
 856                     uint32_t, (_edp)->ed_u32[0]);                       \
 857         _NOTE(CONSTANTCONDITION)                                        \
 858         } while (B_FALSE)
 859
 860 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 861         do {                                                            \
 862                 EFX_CHECK_REG((_enp), (_reg));                          \
 863                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 864                     uint32_t, _reg ## _OFST,                            \
 865                     uint32_t, (_edp)->ed_u32[0]);                       \
 866                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 867                     (_edp), (_lock));                                   \
 868         _NOTE(CONSTANTCONDITION)                                        \
 869         } while (B_FALSE)
 870
 871 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 872         do {                                                            \
 873                 EFX_CHECK_REG((_enp), (_reg));                          \
 874                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 875                     (_eqp));                                            \
 876                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 877                     uint32_t, _reg ## _OFST,                            \
 878                     uint32_t, (_eqp)->eq_u32[1],                        \
 879                     uint32_t, (_eqp)->eq_u32[0]);                       \
 880         _NOTE(CONSTANTCONDITION)                                        \
 881         } while (B_FALSE)
 882
 883 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 884         do {                                                            \
 885                 EFX_CHECK_REG((_enp), (_reg));                          \
 886                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 887                     uint32_t, _reg ## _OFST,                            \
 888                     uint32_t, (_eqp)->eq_u32[1],                        \
 889                     uint32_t, (_eqp)->eq_u32[0]);                       \
 890                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 891                     (_eqp));                                            \
 892         _NOTE(CONSTANTCONDITION)                                        \
 893         } while (B_FALSE)
 894
 895 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 896         do {                                                            \
 897                 EFX_CHECK_REG((_enp), (_reg));                          \
 898                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 899                     (_eop), B_TRUE);                                    \
 900                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 901                     uint32_t, _reg ## _OFST,                            \
 902                     uint32_t, (_eop)->eo_u32[3],                        \
 903                     uint32_t, (_eop)->eo_u32[2],                        \
 904                     uint32_t, (_eop)->eo_u32[1],                        \
 905                     uint32_t, (_eop)->eo_u32[0]);                       \
 906         _NOTE(CONSTANTCONDITION)                                        \
 907         } while (B_FALSE)
 908
 909 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 910         do {                                                            \
 911                 EFX_CHECK_REG((_enp), (_reg));                          \
 912                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 913                     uint32_t, _reg ## _OFST,                            \
 914                     uint32_t, (_eop)->eo_u32[3],                        \
 915                     uint32_t, (_eop)->eo_u32[2],                        \
 916                     uint32_t, (_eop)->eo_u32[1],                        \
 917                     uint32_t, (_eop)->eo_u32[0]);                       \
 918                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 919                     (_eop), B_TRUE);                                    \
 920         _NOTE(CONSTANTCONDITION)                                        \
 921         } while (B_FALSE)
 922
 923 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 924         do {                                                            \
 925                 EFX_CHECK_REG((_enp), (_reg));                          \
 926                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 927                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 928                     (_edp), (_lock));                                   \
 929                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 930                     uint32_t, (_index),                                 \
 931                     uint32_t, _reg ## _OFST,                            \
 932                     uint32_t, (_edp)->ed_u32[0]);                       \
 933         _NOTE(CONSTANTCONDITION)                                        \
 934         } while (B_FALSE)
 935
 936 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 937         do {                                                            \
 938                 EFX_CHECK_REG((_enp), (_reg));                          \
 939                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 940                     uint32_t, (_index),                                 \
 941                     uint32_t, _reg ## _OFST,                            \
 942                     uint32_t, (_edp)->ed_u32[0]);                       \
 943                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 944                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 945                     (_edp), (_lock));                                   \
 946         _NOTE(CONSTANTCONDITION)                                        \
 947         } while (B_FALSE)
 948
 949 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 950         do {                                                            \
 951                 EFX_CHECK_REG((_enp), (_reg));                          \
 952                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 953                     uint32_t, (_index),                                 \
 954                     uint32_t, _reg ## _OFST,                            \
 955                     uint32_t, (_edp)->ed_u32[0]);                       \
 956                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 957                     (_reg ## _OFST +                                    \
 958                     (2 * sizeof (efx_dword_t)) +                        \
 959                     ((_index) * _reg ## _STEP)),                        \
 960                     (_edp), (_lock));                                   \
 961         _NOTE(CONSTANTCONDITION)                                        \
 962         } while (B_FALSE)
 963
 964 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 965         do {                                                            \
 966                 EFX_CHECK_REG((_enp), (_reg));                          \
 967                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 968                     uint32_t, (_index),                                 \
 969                     uint32_t, _reg ## _OFST,                            \
 970                     uint32_t, (_edp)->ed_u32[0]);                       \
 971                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 972                     (_reg ## _OFST +                                    \
 973                     (3 * sizeof (efx_dword_t)) +                        \
 974                     ((_index) * _reg ## _STEP)),                        \
 975                     (_edp), (_lock));                                   \
 976         _NOTE(CONSTANTCONDITION)                                        \
 977         } while (B_FALSE)
 978
 979 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 980         do {                                                            \
 981                 EFX_CHECK_REG((_enp), (_reg));                          \
 982                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 983                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 984                     (_eqp));                                            \
 985                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 986                     uint32_t, (_index),                                 \
 987                     uint32_t, _reg ## _OFST,                            \
 988                     uint32_t, (_eqp)->eq_u32[1],                        \
 989                     uint32_t, (_eqp)->eq_u32[0]);                       \
 990         _NOTE(CONSTANTCONDITION)                                        \
 991         } while (B_FALSE)
 992
 993 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 994         do {                                                            \
 995                 EFX_CHECK_REG((_enp), (_reg));                          \
 996                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 997                     uint32_t, (_index),                                 \
 998                     uint32_t, _reg ## _OFST,                            \
 999                     uint32_t, (_eqp)->eq_u32[1],                        \
1000                     uint32_t, (_eqp)->eq_u32[0]);                       \
1001                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1002                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1003                     (_eqp));                                            \
1004         _NOTE(CONSTANTCONDITION)                                        \
1005         } while (B_FALSE)
1006
1007 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1008         do {                                                            \
1009                 EFX_CHECK_REG((_enp), (_reg));                          \
1010                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1011                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1012                     (_eop), (_lock));                                   \
1013                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1014                     uint32_t, (_index),                                 \
1015                     uint32_t, _reg ## _OFST,                            \
1016                     uint32_t, (_eop)->eo_u32[3],                        \
1017                     uint32_t, (_eop)->eo_u32[2],                        \
1018                     uint32_t, (_eop)->eo_u32[1],                        \
1019                     uint32_t, (_eop)->eo_u32[0]);                       \
1020         _NOTE(CONSTANTCONDITION)                                        \
1021         } while (B_FALSE)
1022
1023 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1024         do {                                                            \
1025                 EFX_CHECK_REG((_enp), (_reg));                          \
1026                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1027                     uint32_t, (_index),                                 \
1028                     uint32_t, _reg ## _OFST,                            \
1029                     uint32_t, (_eop)->eo_u32[3],                        \
1030                     uint32_t, (_eop)->eo_u32[2],                        \
1031                     uint32_t, (_eop)->eo_u32[1],                        \
1032                     uint32_t, (_eop)->eo_u32[0]);                       \
1033                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1034                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1035                     (_eop), (_lock));                                   \
1036         _NOTE(CONSTANTCONDITION)                                        \
1037         } while (B_FALSE)
1038
1039 /*
1040  * Allow drivers to perform optimised 128-bit doorbell writes.
1041  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1042  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1043  * the need for locking in the host, and are the only ones known to be safe to
1044  * use 128-bites write with.
1045  */
1046 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1047         do {                                                            \
1048                 EFX_CHECK_REG((_enp), (_reg));                          \
1049                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1050                     const char *,                                       \
1051                     #_reg,                                              \
1052                     uint32_t, (_index),                                 \
1053                     uint32_t, _reg ## _OFST,                            \
1054                     uint32_t, (_eop)->eo_u32[3],                        \
1055                     uint32_t, (_eop)->eo_u32[2],                        \
1056                     uint32_t, (_eop)->eo_u32[1],                        \
1057                     uint32_t, (_eop)->eo_u32[0]);                       \
1058                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1059                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1060                     (_eop));                                            \
1061         _NOTE(CONSTANTCONDITION)                                        \
1062         } while (B_FALSE)
1063
1064 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1065         do {                                                            \
1066                 unsigned int _new = (_wptr);                            \
1067                 unsigned int _old = (_owptr);                           \
1068                                                                         \
1069                 if ((_new) >= (_old))                                   \
1070                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1071                             (_old) * sizeof (efx_desc_t),               \
1072                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1073                 else                                                    \
1074                         /*                                              \
1075                          * It is cheaper to sync entire map than sync   \
1076                          * two parts especially when offset/size are    \
1077                          * ignored and entire map is synced in any case.\
1078                          */                                             \
1079                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1080                             0,                                          \
1081                             (_entries) * sizeof (efx_desc_t));          \
1082         _NOTE(CONSTANTCONDITION)                                        \
1083         } while (B_FALSE)
1084
1085 extern  __checkReturn   efx_rc_t
1086 efx_nic_biu_test(
1087         __in            efx_nic_t *enp);
1088
1089 extern  __checkReturn   efx_rc_t
1090 efx_mac_select(
1091         __in            efx_nic_t *enp);
1092
1093 extern  void
1094 efx_mac_multicast_hash_compute(
1095         __in_ecount(6*count)            uint8_t const *addrs,
1096         __in                            int count,
1097         __out                           efx_oword_t *hash_low,
1098         __out                           efx_oword_t *hash_high);
1099
1100 extern  __checkReturn   efx_rc_t
1101 efx_phy_probe(
1102         __in            efx_nic_t *enp);
1103
1104 extern                  void
1105 efx_phy_unprobe(
1106         __in            efx_nic_t *enp);
1107
1108 #if EFSYS_OPT_VPD
1109
1110 /* VPD utility functions */
1111
1112 extern  __checkReturn           efx_rc_t
1113 efx_vpd_hunk_length(
1114         __in_bcount(size)       caddr_t data,
1115         __in                    size_t size,
1116         __out                   size_t *lengthp);
1117
1118 extern  __checkReturn           efx_rc_t
1119 efx_vpd_hunk_verify(
1120         __in_bcount(size)       caddr_t data,
1121         __in                    size_t size,
1122         __out_opt               boolean_t *cksummedp);
1123
1124 extern  __checkReturn           efx_rc_t
1125 efx_vpd_hunk_reinit(
1126         __in_bcount(size)       caddr_t data,
1127         __in                    size_t size,
1128         __in                    boolean_t wantpid);
1129
1130 extern  __checkReturn           efx_rc_t
1131 efx_vpd_hunk_get(
1132         __in_bcount(size)       caddr_t data,
1133         __in                    size_t size,
1134         __in                    efx_vpd_tag_t tag,
1135         __in                    efx_vpd_keyword_t keyword,
1136         __out                   unsigned int *payloadp,
1137         __out                   uint8_t *paylenp);
1138
1139 extern  __checkReturn                   efx_rc_t
1140 efx_vpd_hunk_next(
1141         __in_bcount(size)               caddr_t data,
1142         __in                            size_t size,
1143         __out                           efx_vpd_tag_t *tagp,
1144         __out                           efx_vpd_keyword_t *keyword,
1145         __out_opt                       unsigned int *payloadp,
1146         __out_opt                       uint8_t *paylenp,
1147         __inout                         unsigned int *contp);
1148
1149 extern  __checkReturn           efx_rc_t
1150 efx_vpd_hunk_set(
1151         __in_bcount(size)       caddr_t data,
1152         __in                    size_t size,
1153         __in                    efx_vpd_value_t *evvp);
1154
1155 #endif  /* EFSYS_OPT_VPD */
1156
1157 #if EFSYS_OPT_DIAG
1158
1159 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1160
1161 typedef struct efx_register_set_s {
1162         unsigned int            address;
1163         unsigned int            step;
1164         unsigned int            rows;
1165         efx_oword_t             mask;
1166 } efx_register_set_t;
1167
1168 extern  __checkReturn   efx_rc_t
1169 efx_nic_test_registers(
1170         __in            efx_nic_t *enp,
1171         __in            efx_register_set_t *rsp,
1172         __in            size_t count);
1173
1174 extern  __checkReturn   efx_rc_t
1175 efx_nic_test_tables(
1176         __in            efx_nic_t *enp,
1177         __in            efx_register_set_t *rsp,
1178         __in            efx_pattern_type_t pattern,
1179         __in            size_t count);
1180
1181 #endif  /* EFSYS_OPT_DIAG */
1182
1183 #if EFSYS_OPT_MCDI
1184
1185 extern  __checkReturn           efx_rc_t
1186 efx_mcdi_set_workaround(
1187         __in                    efx_nic_t *enp,
1188         __in                    uint32_t type,
1189         __in                    boolean_t enabled,
1190         __out_opt               uint32_t *flagsp);
1191
1192 extern  __checkReturn           efx_rc_t
1193 efx_mcdi_get_workarounds(
1194         __in                    efx_nic_t *enp,
1195         __out_opt               uint32_t *implementedp,
1196         __out_opt               uint32_t *enabledp);
1197
1198 #endif /* EFSYS_OPT_MCDI */
1199
1200 #ifdef  __cplusplus
1201 }
1202 #endif
1203
1204 #endif  /* _SYS_EFX_IMPL_H */