2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
37 #include "falcon_nvram.h"
40 #if EFSYS_OPT_MAC_FALCON_XMAC
41 #include "falcon_xmac.h"
44 #if EFSYS_OPT_MAC_FALCON_GMAC
45 #include "falcon_gmac.h"
48 #if EFSYS_OPT_PHY_NULL
52 #if EFSYS_OPT_PHY_QT2022C2
56 #if EFSYS_OPT_PHY_SFX7101
60 #if EFSYS_OPT_PHY_TXC43128
64 #if EFSYS_OPT_PHY_SFT9001
68 #if EFSYS_OPT_PHY_QT2025C
72 #if EFSYS_OPT_PHY_NULL
73 static efx_phy_ops_t __efx_phy_null_ops = {
75 nullphy_reset, /* epo_reset */
76 nullphy_reconfigure, /* epo_reconfigure */
77 nullphy_verify, /* epo_verify */
78 NULL, /* epo_uplink_check */
79 nullphy_downlink_check, /* epo_downlink_check */
80 nullphy_oui_get, /* epo_oui_get */
81 #if EFSYS_OPT_PHY_STATS
82 nullphy_stats_update, /* epo_stats_update */
83 #endif /* EFSYS_OPT_PHY_STATS */
84 #if EFSYS_OPT_PHY_PROPS
86 nullphy_prop_name, /* epo_prop_name */
88 nullphy_prop_get, /* epo_prop_get */
89 nullphy_prop_set, /* epo_prop_set */
90 #endif /* EFSYS_OPT_PHY_PROPS */
92 NULL, /* epo_bist_enable_offline */
93 NULL, /* epo_bist_start */
94 NULL, /* epo_bist_poll */
95 NULL, /* epo_bist_stop */
96 #endif /* EFSYS_OPT_BIST */
98 #endif /* EFSYS_OPT_PHY_NULL */
100 #if EFSYS_OPT_PHY_QT2022C2
101 static efx_phy_ops_t __efx_phy_qt2022c2_ops = {
102 NULL, /* epo_power */
103 qt2022c2_reset, /* epo_reset */
104 qt2022c2_reconfigure, /* epo_reconfigure */
105 qt2022c2_verify, /* epo_verify */
106 qt2022c2_uplink_check, /* epo_uplink_check */
107 qt2022c2_downlink_check, /* epo_downlink_check */
108 qt2022c2_oui_get, /* epo_oui_get */
109 #if EFSYS_OPT_PHY_STATS
110 qt2022c2_stats_update, /* epo_stats_update */
111 #endif /* EFSYS_OPT_PHY_STATS */
112 #if EFSYS_OPT_PHY_PROPS
114 qt2022c2_prop_name, /* epo_prop_name */
116 qt2022c2_prop_get, /* epo_prop_get */
117 qt2022c2_prop_set, /* epo_prop_set */
118 #endif /* EFSYS_OPT_PHY_PROPS */
120 NULL, /* epo_bist_enable_offline */
121 NULL, /* epo_bist_start */
122 NULL, /* epo_bist_poll */
123 NULL, /* epo_bist_stop */
124 #endif /* EFSYS_OPT_BIST */
126 #endif /* EFSYS_OPT_PHY_QT2022C2 */
128 #if EFSYS_OPT_PHY_SFX7101
129 static efx_phy_ops_t __efx_phy_sfx7101_ops = {
130 sfx7101_power, /* epo_power */
131 sfx7101_reset, /* epo_reset */
132 sfx7101_reconfigure, /* epo_reconfigure */
133 sfx7101_verify, /* epo_verify */
134 sfx7101_uplink_check, /* epo_uplink_check */
135 sfx7101_downlink_check, /* epo_downlink_check */
136 sfx7101_oui_get, /* epo_oui_get */
137 #if EFSYS_OPT_PHY_STATS
138 sfx7101_stats_update, /* epo_stats_update */
139 #endif /* EFSYS_OPT_PHY_STATS */
140 #if EFSYS_OPT_PHY_PROPS
142 sfx7101_prop_name, /* epo_prop_name */
144 sfx7101_prop_get, /* epo_prop_get */
145 sfx7101_prop_set, /* epo_prop_set */
146 #endif /* EFSYS_OPT_PHY_PROPS */
148 NULL, /* epo_bist_enable_offline */
149 NULL, /* epo_bist_start */
150 NULL, /* epo_bist_poll */
151 NULL, /* epo_bist_stop */
152 #endif /* EFSYS_OPT_BIST */
154 #endif /* EFSYS_OPT_PHY_SFX7101 */
156 #if EFSYS_OPT_PHY_TXC43128
157 static efx_phy_ops_t __efx_phy_txc43128_ops = {
158 NULL, /* epo_power */
159 txc43128_reset, /* epo_reset */
160 txc43128_reconfigure, /* epo_reconfigure */
161 txc43128_verify, /* epo_verify */
162 txc43128_uplink_check, /* epo_uplink_check */
163 txc43128_downlink_check, /* epo_downlink_check */
164 txc43128_oui_get, /* epo_oui_get */
165 #if EFSYS_OPT_PHY_STATS
166 txc43128_stats_update, /* epo_stats_update */
167 #endif /* EFSYS_OPT_PHY_STATS */
168 #if EFSYS_OPT_PHY_PROPS
170 txc43128_prop_name, /* epo_prop_name */
172 txc43128_prop_get, /* epo_prop_get */
173 txc43128_prop_set, /* epo_prop_set */
174 #endif /* EFSYS_OPT_PHY_PROPS */
176 NULL, /* epo_bist_enable_offline */
177 NULL, /* epo_bist_start */
178 NULL, /* epo_bist_poll */
179 NULL, /* epo_bist_stop */
180 #endif /* EFSYS_OPT_BIST */
182 #endif /* EFSYS_OPT_PHY_TXC43128 */
184 #if EFSYS_OPT_PHY_SFT9001
185 static efx_phy_ops_t __efx_phy_sft9001_ops = {
186 NULL, /* epo_power */
187 sft9001_reset, /* epo_reset */
188 sft9001_reconfigure, /* epo_reconfigure */
189 sft9001_verify, /* epo_verify */
190 sft9001_uplink_check, /* epo_uplink_check */
191 sft9001_downlink_check, /* epo_downlink_check */
192 sft9001_oui_get, /* epo_oui_get */
193 #if EFSYS_OPT_PHY_STATS
194 sft9001_stats_update, /* epo_stats_update */
195 #endif /* EFSYS_OPT_PHY_STATS */
196 #if EFSYS_OPT_PHY_PROPS
198 sft9001_prop_name, /* epo_prop_name */
200 sft9001_prop_get, /* epo_prop_get */
201 sft9001_prop_set, /* epo_prop_set */
202 #endif /* EFSYS_OPT_PHY_PROPS */
204 NULL, /* epo_bist_enable_offline */
205 sft9001_bist_start, /* epo_bist_start */
206 sft9001_bist_poll, /* epo_bist_poll */
207 sft9001_bist_stop, /* epo_bist_stop */
208 #endif /* EFSYS_OPT_BIST */
210 #endif /* EFSYS_OPT_PHY_SFT9001 */
212 #if EFSYS_OPT_PHY_QT2025C
213 static efx_phy_ops_t __efx_phy_qt2025c_ops = {
214 NULL, /* epo_power */
215 qt2025c_reset, /* epo_reset */
216 qt2025c_reconfigure, /* epo_reconfigure */
217 qt2025c_verify, /* epo_verify */
218 qt2025c_uplink_check, /* epo_uplink_check */
219 qt2025c_downlink_check, /* epo_downlink_check */
220 qt2025c_oui_get, /* epo_oui_get */
221 #if EFSYS_OPT_PHY_STATS
222 qt2025c_stats_update, /* epo_stats_update */
223 #endif /* EFSYS_OPT_PHY_STATS */
224 #if EFSYS_OPT_PHY_PROPS
226 qt2025c_prop_name, /* epo_prop_name */
228 qt2025c_prop_get, /* epo_prop_get */
229 qt2025c_prop_set, /* epo_prop_set */
230 #endif /* EFSYS_OPT_PHY_PROPS */
232 NULL, /* epo_bist_enable_offline */
233 NULL, /* epo_bist_start */
234 NULL, /* epo_bist_poll */
235 NULL, /* epo_bist_stop */
236 #endif /* EFSYS_OPT_BIST */
238 #endif /* EFSYS_OPT_PHY_QT2025C */
241 static efx_phy_ops_t __efx_phy_siena_ops = {
242 siena_phy_power, /* epo_power */
243 NULL, /* epo_reset */
244 siena_phy_reconfigure, /* epo_reconfigure */
245 siena_phy_verify, /* epo_verify */
246 NULL, /* epo_uplink_check */
247 NULL, /* epo_downlink_check */
248 siena_phy_oui_get, /* epo_oui_get */
249 #if EFSYS_OPT_PHY_STATS
250 siena_phy_stats_update, /* epo_stats_update */
251 #endif /* EFSYS_OPT_PHY_STATS */
252 #if EFSYS_OPT_PHY_PROPS
254 siena_phy_prop_name, /* epo_prop_name */
256 siena_phy_prop_get, /* epo_prop_get */
257 siena_phy_prop_set, /* epo_prop_set */
258 #endif /* EFSYS_OPT_PHY_PROPS */
260 NULL, /* epo_bist_enable_offline */
261 siena_phy_bist_start, /* epo_bist_start */
262 siena_phy_bist_poll, /* epo_bist_poll */
263 siena_phy_bist_stop, /* epo_bist_stop */
264 #endif /* EFSYS_OPT_BIST */
266 #endif /* EFSYS_OPT_SIENA */
268 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
269 static efx_phy_ops_t __efx_phy_ef10_ops = {
270 ef10_phy_power, /* epo_power */
271 NULL, /* epo_reset */
272 ef10_phy_reconfigure, /* epo_reconfigure */
273 ef10_phy_verify, /* epo_verify */
274 NULL, /* epo_uplink_check */
275 NULL, /* epo_downlink_check */
276 ef10_phy_oui_get, /* epo_oui_get */
277 #if EFSYS_OPT_PHY_STATS
278 ef10_phy_stats_update, /* epo_stats_update */
279 #endif /* EFSYS_OPT_PHY_STATS */
280 #if EFSYS_OPT_PHY_PROPS
282 ef10_phy_prop_name, /* epo_prop_name */
284 ef10_phy_prop_get, /* epo_prop_get */
285 ef10_phy_prop_set, /* epo_prop_set */
286 #endif /* EFSYS_OPT_PHY_PROPS */
288 /* FIXME: Are these BIST methods appropriate for Medford? */
289 hunt_bist_enable_offline, /* epo_bist_enable_offline */
290 hunt_bist_start, /* epo_bist_start */
291 hunt_bist_poll, /* epo_bist_poll */
292 hunt_bist_stop, /* epo_bist_stop */
293 #endif /* EFSYS_OPT_BIST */
295 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
297 __checkReturn efx_rc_t
301 efx_port_t *epp = &(enp->en_port);
302 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
306 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
308 epp->ep_port = encp->enc_port;
309 epp->ep_phy_type = encp->enc_phy_type;
311 /* Hook in operations structure */
312 switch (enp->en_family) {
314 case EFX_FAMILY_FALCON:
315 switch (epp->ep_phy_type) {
316 #if EFSYS_OPT_PHY_NULL
317 case PHY_TYPE_NONE_DECODE:
318 epop = (efx_phy_ops_t *)&__efx_phy_null_ops;
321 #if EFSYS_OPT_PHY_QT2022C2
322 case PHY_TYPE_QT2022C2_DECODE:
323 epop = (efx_phy_ops_t *)&__efx_phy_qt2022c2_ops;
326 #if EFSYS_OPT_PHY_SFX7101
327 case PHY_TYPE_SFX7101_DECODE:
328 epop = (efx_phy_ops_t *)&__efx_phy_sfx7101_ops;
331 #if EFSYS_OPT_PHY_TXC43128
332 case PHY_TYPE_TXC43128_DECODE:
333 epop = (efx_phy_ops_t *)&__efx_phy_txc43128_ops;
336 #if EFSYS_OPT_PHY_SFT9001
337 case PHY_TYPE_SFT9001A_DECODE:
338 case PHY_TYPE_SFT9001B_DECODE:
339 epop = (efx_phy_ops_t *)&__efx_phy_sft9001_ops;
342 #if EFSYS_OPT_PHY_QT2025C
343 case EFX_PHY_QT2025C:
344 epop = (efx_phy_ops_t *)&__efx_phy_qt2025c_ops;
352 #endif /* EFSYS_OPT_FALCON */
354 case EFX_FAMILY_SIENA:
355 epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
357 #endif /* EFSYS_OPT_SIENA */
358 #if EFSYS_OPT_HUNTINGTON
359 case EFX_FAMILY_HUNTINGTON:
360 epop = (efx_phy_ops_t *)&__efx_phy_ef10_ops;
362 #endif /* EFSYS_OPT_HUNTINGTON */
363 #if EFSYS_OPT_MEDFORD
364 case EFX_FAMILY_MEDFORD:
365 epop = (efx_phy_ops_t *)&__efx_phy_ef10_ops;
367 #endif /* EFSYS_OPT_MEDFORD */
378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
381 epp->ep_phy_type = 0;
386 __checkReturn efx_rc_t
390 efx_port_t *epp = &(enp->en_port);
391 efx_phy_ops_t *epop = epp->ep_epop;
393 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
394 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
396 return (epop->epo_verify(enp));
399 #if EFSYS_OPT_PHY_LED_CONTROL
401 __checkReturn efx_rc_t
404 __in efx_phy_led_mode_t mode)
406 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
407 efx_port_t *epp = &(enp->en_port);
408 efx_phy_ops_t *epop = epp->ep_epop;
412 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
413 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
415 if (epp->ep_phy_led_mode == mode)
418 mask = (1 << EFX_PHY_LED_DEFAULT);
419 mask |= encp->enc_led_mask;
421 if (!((1 << mode) & mask)) {
426 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
427 epp->ep_phy_led_mode = mode;
429 if ((rc = epop->epo_reconfigure(enp)) != 0)
438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
442 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
448 __out uint32_t *maskp)
450 efx_port_t *epp = &(enp->en_port);
452 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
453 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
456 case EFX_PHY_CAP_CURRENT:
457 *maskp = epp->ep_adv_cap_mask;
459 case EFX_PHY_CAP_DEFAULT:
460 *maskp = epp->ep_default_adv_cap_mask;
462 case EFX_PHY_CAP_PERM:
463 *maskp = epp->ep_phy_cap_mask;
466 EFSYS_ASSERT(B_FALSE);
471 __checkReturn efx_rc_t
476 efx_port_t *epp = &(enp->en_port);
477 efx_phy_ops_t *epop = epp->ep_epop;
481 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
482 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
484 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
489 if (epp->ep_adv_cap_mask == mask)
492 old_mask = epp->ep_adv_cap_mask;
493 epp->ep_adv_cap_mask = mask;
495 if ((rc = epop->epo_reconfigure(enp)) != 0)
504 epp->ep_adv_cap_mask = old_mask;
505 /* Reconfigure for robustness */
506 if (epop->epo_reconfigure(enp) != 0) {
508 * We may have an inconsistent view of our advertised speed
515 EFSYS_PROBE1(fail1, efx_rc_t, rc);
523 __out uint32_t *maskp)
525 efx_port_t *epp = &(enp->en_port);
527 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
528 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
530 *maskp = epp->ep_lp_cap_mask;
533 __checkReturn efx_rc_t
536 __out uint32_t *ouip)
538 efx_port_t *epp = &(enp->en_port);
539 efx_phy_ops_t *epop = epp->ep_epop;
541 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
542 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
544 return (epop->epo_oui_get(enp, ouip));
548 efx_phy_media_type_get(
550 __out efx_phy_media_type_t *typep)
552 efx_port_t *epp = &(enp->en_port);
554 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
555 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
557 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
558 *typep = epp->ep_module_type;
560 *typep = epp->ep_fixed_port_type;
563 __checkReturn efx_rc_t
564 efx_phy_module_get_info(
566 __in uint8_t dev_addr,
569 __out_bcount(len) uint8_t *data)
573 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
574 EFSYS_ASSERT(data != NULL);
576 if ((uint32_t)offset + len > 0xff) {
581 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
582 offset, len, data)) != 0)
590 EFSYS_PROBE1(fail1, efx_rc_t, rc);
595 #if EFSYS_OPT_PHY_STATS
599 /* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
600 static const char *__efx_phy_stat_name[] = {
649 /* END MKCONFIG GENERATED PhyStatNamesBlock */
654 __in efx_phy_stat_t type)
656 _NOTE(ARGUNUSED(enp))
657 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
658 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
660 return (__efx_phy_stat_name[type]);
663 #endif /* EFSYS_OPT_NAMES */
665 __checkReturn efx_rc_t
666 efx_phy_stats_update(
668 __in efsys_mem_t *esmp,
669 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
671 efx_port_t *epp = &(enp->en_port);
672 efx_phy_ops_t *epop = epp->ep_epop;
674 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
675 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
677 return (epop->epo_stats_update(enp, esmp, stat));
680 #endif /* EFSYS_OPT_PHY_STATS */
682 #if EFSYS_OPT_PHY_PROPS
688 __in unsigned int id)
690 efx_port_t *epp = &(enp->en_port);
691 efx_phy_ops_t *epop = epp->ep_epop;
693 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
694 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
696 return (epop->epo_prop_name(enp, id));
698 #endif /* EFSYS_OPT_NAMES */
700 __checkReturn efx_rc_t
703 __in unsigned int id,
705 __out uint32_t *valp)
707 efx_port_t *epp = &(enp->en_port);
708 efx_phy_ops_t *epop = epp->ep_epop;
710 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
711 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
713 return (epop->epo_prop_get(enp, id, flags, valp));
716 __checkReturn efx_rc_t
719 __in unsigned int id,
722 efx_port_t *epp = &(enp->en_port);
723 efx_phy_ops_t *epop = epp->ep_epop;
725 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
726 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
728 return (epop->epo_prop_set(enp, id, val));
730 #endif /* EFSYS_OPT_PHY_STATS */
734 __checkReturn efx_rc_t
735 efx_bist_enable_offline(
738 efx_port_t *epp = &(enp->en_port);
739 efx_phy_ops_t *epop = epp->ep_epop;
742 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
744 if (epop->epo_bist_enable_offline == NULL) {
749 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
757 EFSYS_PROBE1(fail1, efx_rc_t, rc);
763 __checkReturn efx_rc_t
766 __in efx_bist_type_t type)
768 efx_port_t *epp = &(enp->en_port);
769 efx_phy_ops_t *epop = epp->ep_epop;
772 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
774 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
775 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
776 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
778 if (epop->epo_bist_start == NULL) {
783 if ((rc = epop->epo_bist_start(enp, type)) != 0)
786 epp->ep_current_bist = type;
793 EFSYS_PROBE1(fail1, efx_rc_t, rc);
798 __checkReturn efx_rc_t
801 __in efx_bist_type_t type,
802 __out efx_bist_result_t *resultp,
803 __out_opt uint32_t *value_maskp,
804 __out_ecount_opt(count) unsigned long *valuesp,
807 efx_port_t *epp = &(enp->en_port);
808 efx_phy_ops_t *epop = epp->ep_epop;
811 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
813 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
814 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
815 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
817 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
818 if (epop->epo_bist_poll == NULL) {
823 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
824 valuesp, count)) != 0)
832 EFSYS_PROBE1(fail1, efx_rc_t, rc);
840 __in efx_bist_type_t type)
842 efx_port_t *epp = &(enp->en_port);
843 efx_phy_ops_t *epop = epp->ep_epop;
845 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
847 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
848 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
849 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
851 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
853 if (epop->epo_bist_stop != NULL)
854 epop->epo_bist_stop(enp, type);
856 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
859 #endif /* EFSYS_OPT_BIST */
864 efx_port_t *epp = &(enp->en_port);
866 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
870 epp->ep_adv_cap_mask = 0;
873 epp->ep_phy_type = 0;