2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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33 #ifndef _SYS_HUNT_IMPL_H
34 #define _SYS_HUNT_IMPL_H
38 #include "efx_regs_ef10.h"
46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
47 * possibly be increased, or the write size reported by newer firmware used
50 #define EF10_NVRAM_CHUNK 0x80
52 /* Alignment requirement for value written to RX WPTR:
53 * the WPTR must be aligned to an 8 descriptor boundary
55 #define EF10_RX_WPTR_ALIGN 8
58 * Max byte offset into the packet the TCP header must start for the hardware
59 * to be able to parse the packet correctly.
60 * FIXME: Move to ef10_impl.h when it is included in all driver builds.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
91 __checkReturn efx_rc_t
94 __in unsigned int count);
101 __checkReturn efx_rc_t
104 __in unsigned int us);
108 ef10_ev_qstats_update(
110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
111 #endif /* EFSYS_OPT_QSTATS */
114 ef10_ev_rxlabel_init(
117 __in unsigned int label);
120 ef10_ev_rxlabel_fini(
122 __in unsigned int label);
126 __checkReturn efx_rc_t
129 __in efx_intr_type_t type,
130 __in efsys_mem_t *esmp);
134 __in efx_nic_t *enp);
138 __in efx_nic_t *enp);
141 ef10_intr_disable_unlocked(
142 __in efx_nic_t *enp);
144 __checkReturn efx_rc_t
147 __in unsigned int level);
150 ef10_intr_status_line(
152 __out boolean_t *fatalp,
153 __out uint32_t *qmaskp);
156 ef10_intr_status_message(
158 __in unsigned int message,
159 __out boolean_t *fatalp);
163 __in efx_nic_t *enp);
166 __in efx_nic_t *enp);
170 extern __checkReturn efx_rc_t
172 __in efx_nic_t *enp);
174 extern __checkReturn efx_rc_t
176 __in efx_nic_t *enp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_set_drv_limits(
180 __inout efx_nic_t *enp,
181 __in efx_drv_limits_t *edlp);
183 extern __checkReturn efx_rc_t
184 ef10_nic_get_vi_pool(
186 __out uint32_t *vi_countp);
188 extern __checkReturn efx_rc_t
189 ef10_nic_get_bar_region(
191 __in efx_nic_region_t region,
192 __out uint32_t *offsetp,
193 __out size_t *sizep);
195 extern __checkReturn efx_rc_t
197 __in efx_nic_t *enp);
199 extern __checkReturn efx_rc_t
201 __in efx_nic_t *enp);
205 extern __checkReturn efx_rc_t
206 ef10_nic_register_test(
207 __in efx_nic_t *enp);
209 #endif /* EFSYS_OPT_DIAG */
213 __in efx_nic_t *enp);
217 __in efx_nic_t *enp);
222 extern __checkReturn efx_rc_t
225 __out efx_link_mode_t *link_modep);
227 extern __checkReturn efx_rc_t
230 __out boolean_t *mac_upp);
232 extern __checkReturn efx_rc_t
234 __in efx_nic_t *enp);
236 extern __checkReturn efx_rc_t
238 __in efx_nic_t *enp);
240 extern __checkReturn efx_rc_t
241 ef10_mac_reconfigure(
242 __in efx_nic_t *enp);
244 extern __checkReturn efx_rc_t
245 ef10_mac_multicast_list_set(
246 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_mac_filter_default_rxq_set(
252 __in boolean_t using_rss);
255 ef10_mac_filter_default_rxq_clear(
256 __in efx_nic_t *enp);
258 #if EFSYS_OPT_LOOPBACK
260 extern __checkReturn efx_rc_t
261 ef10_mac_loopback_set(
263 __in efx_link_mode_t link_mode,
264 __in efx_loopback_type_t loopback_type);
266 #endif /* EFSYS_OPT_LOOPBACK */
268 #if EFSYS_OPT_MAC_STATS
270 extern __checkReturn efx_rc_t
271 ef10_mac_stats_update(
273 __in efsys_mem_t *esmp,
274 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
275 __inout_opt uint32_t *generationp);
277 #endif /* EFSYS_OPT_MAC_STATS */
284 extern __checkReturn efx_rc_t
287 __in const efx_mcdi_transport_t *mtp);
291 __in efx_nic_t *enp);
294 ef10_mcdi_send_request(
299 __in size_t sdu_len);
301 extern __checkReturn boolean_t
302 ef10_mcdi_poll_response(
303 __in efx_nic_t *enp);
306 ef10_mcdi_read_response(
308 __out_bcount(length) void *bufferp,
313 ef10_mcdi_poll_reboot(
314 __in efx_nic_t *enp);
316 extern __checkReturn efx_rc_t
317 ef10_mcdi_feature_supported(
319 __in efx_mcdi_feature_id_t id,
320 __out boolean_t *supportedp);
322 #endif /* EFSYS_OPT_MCDI */
326 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
328 extern __checkReturn efx_rc_t
329 ef10_nvram_buf_read_tlv(
331 __in_bcount(max_seg_size) caddr_t seg_data,
332 __in size_t max_seg_size,
334 __deref_out_bcount_opt(*sizep) caddr_t *datap,
335 __out size_t *sizep);
337 extern __checkReturn efx_rc_t
338 ef10_nvram_buf_write_tlv(
339 __inout_bcount(partn_size) caddr_t partn_data,
340 __in size_t partn_size,
342 __in_bcount(tag_size) caddr_t tag_data,
343 __in size_t tag_size,
344 __out size_t *total_lengthp);
346 extern __checkReturn efx_rc_t
347 ef10_nvram_partn_read_tlv(
351 __deref_out_bcount_opt(*sizep) caddr_t *datap,
352 __out size_t *sizep);
354 extern __checkReturn efx_rc_t
355 ef10_nvram_partn_write_tlv(
359 __in_bcount(size) caddr_t data,
362 extern __checkReturn efx_rc_t
363 ef10_nvram_partn_write_segment_tlv(
367 __in_bcount(size) caddr_t data,
369 __in boolean_t all_segments);
371 extern __checkReturn efx_rc_t
372 ef10_nvram_partn_lock(
374 __in uint32_t partn);
377 ef10_nvram_partn_unlock(
379 __in uint32_t partn);
381 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
387 extern __checkReturn efx_rc_t
389 __in efx_nic_t *enp);
391 #endif /* EFSYS_OPT_DIAG */
393 extern __checkReturn efx_rc_t
394 ef10_nvram_type_to_partn(
396 __in efx_nvram_type_t type,
397 __out uint32_t *partnp);
399 extern __checkReturn efx_rc_t
400 ef10_nvram_partn_size(
403 __out size_t *sizep);
405 extern __checkReturn efx_rc_t
406 ef10_nvram_partn_rw_start(
409 __out size_t *chunk_sizep);
411 extern __checkReturn efx_rc_t
412 ef10_nvram_partn_read_mode(
415 __in unsigned int offset,
416 __out_bcount(size) caddr_t data,
420 extern __checkReturn efx_rc_t
421 ef10_nvram_partn_read(
424 __in unsigned int offset,
425 __out_bcount(size) caddr_t data,
428 extern __checkReturn efx_rc_t
429 ef10_nvram_partn_erase(
432 __in unsigned int offset,
435 extern __checkReturn efx_rc_t
436 ef10_nvram_partn_write(
439 __in unsigned int offset,
440 __out_bcount(size) caddr_t data,
444 ef10_nvram_partn_rw_finish(
446 __in uint32_t partn);
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_get_version(
452 __out uint32_t *subtypep,
453 __out_ecount(4) uint16_t version[4]);
455 extern __checkReturn efx_rc_t
456 ef10_nvram_partn_set_version(
459 __in_ecount(4) uint16_t version[4]);
461 #endif /* EFSYS_OPT_NVRAM */
466 typedef struct ef10_link_state_s {
467 uint32_t els_adv_cap_mask;
468 uint32_t els_lp_cap_mask;
469 unsigned int els_fcntl;
470 efx_link_mode_t els_link_mode;
471 #if EFSYS_OPT_LOOPBACK
472 efx_loopback_type_t els_loopback;
474 boolean_t els_mac_up;
480 __in efx_qword_t *eqp,
481 __out efx_link_mode_t *link_modep);
483 extern __checkReturn efx_rc_t
486 __out ef10_link_state_t *elsp);
488 extern __checkReturn efx_rc_t
493 extern __checkReturn efx_rc_t
494 ef10_phy_reconfigure(
495 __in efx_nic_t *enp);
497 extern __checkReturn efx_rc_t
499 __in efx_nic_t *enp);
501 extern __checkReturn efx_rc_t
504 __out uint32_t *ouip);
506 #if EFSYS_OPT_PHY_STATS
508 extern __checkReturn efx_rc_t
509 ef10_phy_stats_update(
511 __in efsys_mem_t *esmp,
512 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
514 #endif /* EFSYS_OPT_PHY_STATS */
516 #if EFSYS_OPT_PHY_PROPS
523 __in unsigned int id);
525 #endif /* EFSYS_OPT_NAMES */
527 extern __checkReturn efx_rc_t
530 __in unsigned int id,
532 __out uint32_t *valp);
534 extern __checkReturn efx_rc_t
537 __in unsigned int id,
540 #endif /* EFSYS_OPT_PHY_PROPS */
544 extern __checkReturn efx_rc_t
545 hunt_bist_enable_offline(
546 __in efx_nic_t *enp);
548 extern __checkReturn efx_rc_t
551 __in efx_bist_type_t type);
553 extern __checkReturn efx_rc_t
556 __in efx_bist_type_t type,
557 __out efx_bist_result_t *resultp,
558 __out_opt __drv_when(count > 0, __notnull)
559 uint32_t *value_maskp,
560 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
561 unsigned long *valuesp,
567 __in efx_bist_type_t type);
569 #endif /* EFSYS_OPT_BIST */
576 extern __checkReturn efx_rc_t
579 __in efx_sram_pattern_fn_t func);
581 #endif /* EFSYS_OPT_DIAG */
586 extern __checkReturn efx_rc_t
588 __in efx_nic_t *enp);
592 __in efx_nic_t *enp);
594 extern __checkReturn efx_rc_t
597 __in unsigned int index,
598 __in unsigned int label,
599 __in efsys_mem_t *esmp,
605 __out unsigned int *addedp);
609 __in efx_txq_t *etp);
611 extern __checkReturn efx_rc_t
614 __in_ecount(n) efx_buffer_t *eb,
616 __in unsigned int completed,
617 __inout unsigned int *addedp);
622 __in unsigned int added,
623 __in unsigned int pushed);
625 extern __checkReturn efx_rc_t
628 __in unsigned int ns);
630 extern __checkReturn efx_rc_t
632 __in efx_txq_t *etp);
636 __in efx_txq_t *etp);
638 extern __checkReturn efx_rc_t
640 __in efx_txq_t *etp);
643 ef10_tx_qpio_disable(
644 __in efx_txq_t *etp);
646 extern __checkReturn efx_rc_t
649 __in_ecount(buf_length) uint8_t *buffer,
650 __in size_t buf_length,
651 __in size_t pio_buf_offset);
653 extern __checkReturn efx_rc_t
656 __in size_t pkt_length,
657 __in unsigned int completed,
658 __inout unsigned int *addedp);
660 extern __checkReturn efx_rc_t
663 __in_ecount(n) efx_desc_t *ed,
665 __in unsigned int completed,
666 __inout unsigned int *addedp);
669 ef10_tx_qdesc_dma_create(
671 __in efsys_dma_addr_t addr,
674 __out efx_desc_t *edp);
677 hunt_tx_qdesc_tso_create(
679 __in uint16_t ipv4_id,
680 __in uint32_t tcp_seq,
681 __in uint8_t tcp_flags,
682 __out efx_desc_t *edp);
685 ef10_tx_qdesc_tso2_create(
687 __in uint16_t ipv4_id,
688 __in uint32_t tcp_seq,
689 __in uint16_t tcp_mss,
690 __out_ecount(count) efx_desc_t *edp,
694 ef10_tx_qdesc_vlantci_create(
696 __in uint16_t vlan_tci,
697 __out efx_desc_t *edp);
703 ef10_tx_qstats_update(
705 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
707 #endif /* EFSYS_OPT_QSTATS */
711 /* Missing register definitions */
712 #ifndef ER_DZ_TX_PIOBUF_OFST
713 #define ER_DZ_TX_PIOBUF_OFST 0x00001000
715 #ifndef ER_DZ_TX_PIOBUF_STEP
716 #define ER_DZ_TX_PIOBUF_STEP 8192
718 #ifndef ER_DZ_TX_PIOBUF_ROWS
719 #define ER_DZ_TX_PIOBUF_ROWS 2048
722 #ifndef ER_DZ_TX_PIOBUF_SIZE
723 #define ER_DZ_TX_PIOBUF_SIZE 2048
726 #define HUNT_PIOBUF_NBUFS (16)
727 #define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE)
729 #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32)
731 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
732 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
733 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
734 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
735 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
736 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
737 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
738 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
739 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
740 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
741 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
742 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
744 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
746 typedef uint32_t efx_piobuf_handle_t;
748 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
750 extern __checkReturn efx_rc_t
752 __inout efx_nic_t *enp,
753 __out uint32_t *bufnump,
754 __out efx_piobuf_handle_t *handlep,
755 __out uint32_t *blknump,
756 __out uint32_t *offsetp,
757 __out size_t *sizep);
759 extern __checkReturn efx_rc_t
761 __inout efx_nic_t *enp,
762 __in uint32_t bufnum,
763 __in uint32_t blknum);
765 extern __checkReturn efx_rc_t
767 __inout efx_nic_t *enp,
768 __in uint32_t vi_index,
769 __in efx_piobuf_handle_t handle);
771 extern __checkReturn efx_rc_t
773 __inout efx_nic_t *enp,
774 __in uint32_t vi_index);
781 extern __checkReturn efx_rc_t
783 __in efx_nic_t *enp);
785 extern __checkReturn efx_rc_t
788 __out size_t *sizep);
790 extern __checkReturn efx_rc_t
793 __out_bcount(size) caddr_t data,
796 extern __checkReturn efx_rc_t
799 __in_bcount(size) caddr_t data,
802 extern __checkReturn efx_rc_t
805 __in_bcount(size) caddr_t data,
808 extern __checkReturn efx_rc_t
811 __in_bcount(size) caddr_t data,
813 __inout efx_vpd_value_t *evvp);
815 extern __checkReturn efx_rc_t
818 __in_bcount(size) caddr_t data,
820 __in efx_vpd_value_t *evvp);
822 extern __checkReturn efx_rc_t
825 __in_bcount(size) caddr_t data,
827 __out efx_vpd_value_t *evvp,
828 __inout unsigned int *contp);
830 extern __checkReturn efx_rc_t
833 __in_bcount(size) caddr_t data,
838 __in efx_nic_t *enp);
840 #endif /* EFSYS_OPT_VPD */
845 extern __checkReturn efx_rc_t
847 __in efx_nic_t *enp);
849 #if EFSYS_OPT_RX_SCATTER
850 extern __checkReturn efx_rc_t
851 ef10_rx_scatter_enable(
853 __in unsigned int buf_size);
854 #endif /* EFSYS_OPT_RX_SCATTER */
857 #if EFSYS_OPT_RX_SCALE
859 extern __checkReturn efx_rc_t
860 ef10_rx_scale_mode_set(
862 __in efx_rx_hash_alg_t alg,
863 __in efx_rx_hash_type_t type,
864 __in boolean_t insert);
866 extern __checkReturn efx_rc_t
867 ef10_rx_scale_key_set(
869 __in_ecount(n) uint8_t *key,
872 extern __checkReturn efx_rc_t
873 ef10_rx_scale_tbl_set(
875 __in_ecount(n) unsigned int *table,
878 extern __checkReturn uint32_t
881 __in efx_rx_hash_alg_t func,
882 __in uint8_t *buffer);
884 #endif /* EFSYS_OPT_RX_SCALE */
886 extern __checkReturn efx_rc_t
887 ef10_rx_prefix_pktlen(
889 __in uint8_t *buffer,
890 __out uint16_t *lengthp);
895 __in_ecount(n) efsys_dma_addr_t *addrp,
898 __in unsigned int completed,
899 __in unsigned int added);
904 __in unsigned int added,
905 __inout unsigned int *pushedp);
907 extern __checkReturn efx_rc_t
909 __in efx_rxq_t *erp);
913 __in efx_rxq_t *erp);
915 extern __checkReturn efx_rc_t
918 __in unsigned int index,
919 __in unsigned int label,
920 __in efx_rxq_type_t type,
921 __in efsys_mem_t *esmp,
925 __in efx_rxq_t *erp);
929 __in efx_rxq_t *erp);
933 __in efx_nic_t *enp);
937 typedef struct ef10_filter_handle_s {
940 } ef10_filter_handle_t;
942 typedef struct ef10_filter_entry_s {
943 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
944 ef10_filter_handle_t efe_handle;
945 } ef10_filter_entry_t;
948 * BUSY flag indicates that an update is in progress.
949 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
951 #define EFX_EF10_FILTER_FLAG_BUSY 1U
952 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
953 #define EFX_EF10_FILTER_FLAGS 3U
956 * Size of the hash table used by the driver. Doesn't need to be the
957 * same size as the hardware's table.
959 #define EFX_EF10_FILTER_TBL_ROWS 8192
961 /* Allow for the broadcast address to be added to the multicast list */
962 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
964 typedef struct ef10_filter_table_s {
965 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
966 efx_rxq_t * eft_default_rxq;
967 boolean_t eft_using_rss;
968 uint32_t eft_unicst_filter_index;
969 boolean_t eft_unicst_filter_set;
970 uint32_t eft_mulcst_filter_indexes[
971 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
972 uint32_t eft_mulcst_filter_count;
973 } ef10_filter_table_t;
975 __checkReturn efx_rc_t
977 __in efx_nic_t *enp);
981 __in efx_nic_t *enp);
983 __checkReturn efx_rc_t
985 __in efx_nic_t *enp);
987 __checkReturn efx_rc_t
990 __inout efx_filter_spec_t *spec,
991 __in boolean_t may_replace);
993 __checkReturn efx_rc_t
996 __inout efx_filter_spec_t *spec);
998 extern __checkReturn efx_rc_t
999 ef10_filter_supported_filters(
1000 __in efx_nic_t *enp,
1001 __out uint32_t *list,
1002 __out size_t *length);
1004 extern __checkReturn efx_rc_t
1005 ef10_filter_reconfigure(
1006 __in efx_nic_t *enp,
1007 __in_ecount(6) uint8_t const *mac_addr,
1008 __in boolean_t all_unicst,
1009 __in boolean_t mulcst,
1010 __in boolean_t all_mulcst,
1011 __in boolean_t brdcst,
1012 __in_ecount(6*count) uint8_t const *addrs,
1016 ef10_filter_get_default_rxq(
1017 __in efx_nic_t *enp,
1018 __out efx_rxq_t **erpp,
1019 __out boolean_t *using_rss);
1022 ef10_filter_default_rxq_set(
1023 __in efx_nic_t *enp,
1024 __in efx_rxq_t *erp,
1025 __in boolean_t using_rss);
1028 ef10_filter_default_rxq_clear(
1029 __in efx_nic_t *enp);
1032 #endif /* EFSYS_OPT_FILTER */
1034 extern __checkReturn efx_rc_t
1035 efx_mcdi_get_function_info(
1036 __in efx_nic_t *enp,
1037 __out uint32_t *pfp,
1038 __out_opt uint32_t *vfp);
1040 extern __checkReturn efx_rc_t
1041 efx_mcdi_privilege_mask(
1042 __in efx_nic_t *enp,
1045 __out uint32_t *maskp);
1051 #endif /* _SYS_HUNT_IMPL_H */