2 * Copyright (c) 2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
40 #include "ef10_tlv_layout.h"
42 static __checkReturn efx_rc_t
43 efx_mcdi_get_rxdp_config(
45 __out uint32_t *end_paddingp)
48 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
49 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
53 memset(payload, 0, sizeof (payload));
54 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
55 req.emr_in_buf = payload;
56 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
57 req.emr_out_buf = payload;
58 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
60 efx_mcdi_execute(enp, &req);
61 if (req.emr_rc != 0) {
66 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
67 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
68 /* RX DMA end padding is disabled */
71 switch(MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
72 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
73 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
76 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
79 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
88 *end_paddingp = end_padding;
95 EFSYS_PROBE1(fail1, efx_rc_t, rc);
100 __checkReturn efx_rc_t
104 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
105 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
106 uint8_t mac_addr[6] = { 0 };
107 uint32_t board_type = 0;
108 ef10_link_state_t els;
109 efx_port_t *epp = &(enp->en_port);
117 uint32_t end_padding;
121 * FIXME: Likely to be incomplete and incorrect.
122 * Parts of this should be shared with Huntington.
125 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
129 * NOTE: The MCDI protocol numbers ports from zero.
130 * The common code MCDI interface numbers ports from one.
132 emip->emi_port = port + 1;
134 if ((rc = ef10_external_port_mapping(enp, port,
135 &encp->enc_external_port)) != 0)
139 * Get PCIe function number from firmware (used for
140 * per-function privilege and dynamic config info).
141 * - PCIe PF: pf = PF number, vf = 0xffff.
142 * - PCIe VF: pf = parent PF, vf = VF number.
144 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
150 /* MAC address for this function */
151 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
152 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
153 if ((rc == 0) && (mac_addr[0] & 0x02)) {
155 * If the static config does not include a global MAC
156 * address pool then the board may return a locally
157 * administered MAC address (this should only happen on
158 * incorrectly programmed boards).
163 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
168 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
170 /* Board configuration */
171 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
173 /* Unprivileged functions may not be able to read board cfg */
180 encp->enc_board_type = board_type;
181 encp->enc_clk_mult = 1; /* not used for Medford */
183 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
184 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
187 /* Obtain the default PHY advertised capabilities */
188 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
190 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
191 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
193 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
195 * Interrupt testing does not work for VFs. See bug50084.
196 * FIXME: Does this still apply to Medford?
198 encp->enc_bug41750_workaround = B_TRUE;
201 /* Chained multicast is always enabled on Medford */
202 encp->enc_bug26807_workaround = B_TRUE;
204 /* Get sysclk frequency (in MHz). */
205 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
209 * The timer quantum is 1536 sysclk cycles, documented for the
210 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
212 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
213 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
214 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
216 /* Check capabilities of running datapath firmware */
217 if ((rc = ef10_get_datapath_caps(enp)) != 0)
220 /* Alignment for receive packet DMA buffers */
221 encp->enc_rx_buf_align_start = 1;
223 /* Get the RX DMA end padding alignment configuration */
224 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0)
226 encp->enc_rx_buf_align_end = end_padding;
228 /* Alignment for WPTR updates */
229 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
232 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
233 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
234 * resources (allocated to this PCIe function), which is zero until
235 * after we have allocated VIs.
237 encp->enc_evq_limit = 1024;
238 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
239 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
241 encp->enc_buftbl_limit = 0xFFFFFFFF;
243 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
244 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
245 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
248 * Get the current privilege mask. Note that this may be modified
249 * dynamically, so this value is informational only. DO NOT use
250 * the privilege mask to check for sufficient privileges, as that
251 * can result in time-of-check/time-of-use bugs.
253 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
255 encp->enc_privilege_mask = mask;
257 /* Get interrupt vector limits */
258 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
259 if (EFX_PCI_FUNCTION_IS_PF(encp))
262 /* Ignore error (cannot query vector limits from a VF). */
266 encp->enc_intr_vec_base = base;
267 encp->enc_intr_limit = nvec;
270 * Maximum number of bytes into the frame the TCP header can start for
271 * firmware assisted TSO to work.
273 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
276 * Medford stores a single global copy of VPD, not per-PF as on
279 encp->enc_vpd_is_global = B_TRUE;
306 EFSYS_PROBE1(fail1, efx_rc_t, rc);
311 #endif /* EFSYS_OPT_MEDFORD */