2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 /* Qualcomm MSM7K/8K uart driver */
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
39 #include <machine/bus.h>
40 #include <machine/fdt.h>
42 #include <dev/uart/uart.h>
43 #include <dev/uart/uart_cpu.h>
44 #include <dev/uart/uart_cpu_fdt.h>
45 #include <dev/uart/uart_bus.h>
46 #include <dev/uart/uart_dev_msm.h>
50 #define DEF_CLK 7372800
52 #define GETREG(bas, reg) \
53 bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
54 #define SETREG(bas, reg, value) \
55 bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
57 static int msm_uart_param(struct uart_bas *, int, int, int, int);
60 * Low-level UART interface.
62 static int msm_probe(struct uart_bas *bas);
63 static void msm_init(struct uart_bas *bas, int, int, int, int);
64 static void msm_term(struct uart_bas *bas);
65 static void msm_putc(struct uart_bas *bas, int);
66 static int msm_rxready(struct uart_bas *bas);
67 static int msm_getc(struct uart_bas *bas, struct mtx *mtx);
69 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
72 msm_uart_param(struct uart_bas *bas, int baudrate, int databits,
73 int stopbits, int parity)
81 ulcon |= (UART_DM_5_BPS << 4);
84 ulcon |= (UART_DM_6_BPS << 4);
87 ulcon |= (UART_DM_7_BPS << 4);
90 ulcon |= (UART_DM_8_BPS << 4);
97 case UART_PARITY_NONE:
98 ulcon |= UART_DM_NO_PARITY;
100 case UART_PARITY_ODD:
101 ulcon |= UART_DM_ODD_PARITY;
103 case UART_PARITY_EVEN:
104 ulcon |= UART_DM_EVEN_PARITY;
106 case UART_PARITY_SPACE:
107 ulcon |= UART_DM_SPACE_PARITY;
109 case UART_PARITY_MARK:
116 ulcon |= (UART_DM_SBL_1 << 2);
119 ulcon |= (UART_DM_SBL_2 << 2);
124 uart_setreg(bas, UART_DM_MR2, ulcon);
126 /* Set 115200 for both TX and RX. */;
127 uart_setreg(bas, UART_DM_CSR, UART_DM_CSR_115200);
133 struct uart_ops uart_msm_ops = {
138 .rxready = msm_rxready,
143 msm_probe(struct uart_bas *bas)
150 msm_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
157 KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));
159 /* Set default parameters */
160 msm_uart_param(bas, baudrate, databits, stopbits, parity);
163 * Configure UART mode registers MR1 and MR2.
164 * Hardware flow control isn't supported.
166 uart_setreg(bas, UART_DM_MR1, 0x0);
168 /* Reset interrupt mask register. */
169 uart_setreg(bas, UART_DM_IMR, 0);
172 * Configure Tx and Rx watermarks configuration registers.
173 * TX watermark value is set to 0 - interrupt is generated when
174 * FIFO level is less than or equal to 0.
176 uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);
178 /* Set RX watermark value */
179 uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);
182 * Configure Interrupt Programming Register.
183 * Set initial Stale timeout value.
185 uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);
187 /* Disable IRDA mode */
188 uart_setreg(bas, UART_DM_IRDA, 0x0);
191 * Configure and enable sim interface if required.
192 * Configure hunt character value in HCR register.
193 * Keep it in reset state.
195 uart_setreg(bas, UART_DM_HCR, 0x0);
197 /* Issue soft reset command */
198 SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);
199 SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);
200 SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);
201 SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);
202 SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
204 /* Enable/Disable Rx/Tx DM interfaces */
205 /* Disable Data Mover for now. */
206 uart_setreg(bas, UART_DM_DMEN, 0x0);
208 /* Enable transmitter and receiver */
209 uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);
210 uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);
216 msm_term(struct uart_bas *bas)
223 msm_putc(struct uart_bas *bas, int c)
228 * Write to NO_CHARS_FOR_TX register the number of characters
229 * to be transmitted. However, before writing TX_FIFO must
230 * be empty as indicated by TX_READY interrupt in IMR register
234 * Check if transmit FIFO is empty.
235 * If not wait for TX_READY interrupt.
238 if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {
239 while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0
243 /* FIFO is ready, write number of characters to be written */
244 uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);
246 /* Wait till TX FIFO has space */
247 while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)
250 /* TX FIFO has space. Write char */
251 SETREG(bas, UART_DM_TF(0), (c & 0xff));
255 msm_rxready(struct uart_bas *bas)
258 /* Wait for a character to come ready */
259 return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) ==
264 msm_getc(struct uart_bas *bas, struct mtx *mtx)
270 /* Wait for a character to come ready */
271 while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=
275 /* Check for Overrun error. If so reset Error Status */
276 if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)
277 uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);
280 c = uart_getreg(bas, UART_DM_RF(0));
288 * High-level UART interface.
290 struct msm_uart_softc {
291 struct uart_softc base;
295 static int msm_bus_probe(struct uart_softc *sc);
296 static int msm_bus_attach(struct uart_softc *sc);
297 static int msm_bus_flush(struct uart_softc *, int);
298 static int msm_bus_getsig(struct uart_softc *);
299 static int msm_bus_ioctl(struct uart_softc *, int, intptr_t);
300 static int msm_bus_ipend(struct uart_softc *);
301 static int msm_bus_param(struct uart_softc *, int, int, int, int);
302 static int msm_bus_receive(struct uart_softc *);
303 static int msm_bus_setsig(struct uart_softc *, int);
304 static int msm_bus_transmit(struct uart_softc *);
305 static void msm_bus_grab(struct uart_softc *);
306 static void msm_bus_ungrab(struct uart_softc *);
308 static kobj_method_t msm_methods[] = {
309 KOBJMETHOD(uart_probe, msm_bus_probe),
310 KOBJMETHOD(uart_attach, msm_bus_attach),
311 KOBJMETHOD(uart_flush, msm_bus_flush),
312 KOBJMETHOD(uart_getsig, msm_bus_getsig),
313 KOBJMETHOD(uart_ioctl, msm_bus_ioctl),
314 KOBJMETHOD(uart_ipend, msm_bus_ipend),
315 KOBJMETHOD(uart_param, msm_bus_param),
316 KOBJMETHOD(uart_receive, msm_bus_receive),
317 KOBJMETHOD(uart_setsig, msm_bus_setsig),
318 KOBJMETHOD(uart_transmit, msm_bus_transmit),
319 KOBJMETHOD(uart_grab, msm_bus_grab),
320 KOBJMETHOD(uart_ungrab, msm_bus_ungrab),
325 msm_bus_probe(struct uart_softc *sc)
328 sc->sc_txfifosz = 64;
329 sc->sc_rxfifosz = 64;
331 device_set_desc(sc->sc_dev, "Qualcomm HSUART");
337 msm_bus_attach(struct uart_softc *sc)
339 struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
340 struct uart_bas *bas = &sc->sc_bas;
345 /* Set TX_READY, TXLEV, RXLEV, RXSTALE */
346 u->ier = UART_DM_IMR_ENABLED;
348 /* Configure Interrupt Mask register IMR */
349 uart_setreg(bas, UART_DM_IMR, u->ier);
355 * Write the current transmit buffer to the TX FIFO.
358 msm_bus_transmit(struct uart_softc *sc)
360 struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
361 struct uart_bas *bas = &sc->sc_bas;
364 uart_lock(sc->sc_hwmtx);
366 /* Write some data */
367 for (i = 0; i < sc->sc_txdatasz; i++) {
369 msm_putc(bas, sc->sc_txbuf[i]);
373 /* TX FIFO is empty now, enable TX_READY interrupt */
374 u->ier |= UART_DM_TX_READY;
375 SETREG(bas, UART_DM_IMR, u->ier);
379 * Inform upper layer that it is transmitting data to hardware,
380 * this will be cleared when TXIDLE interrupt occurs.
383 uart_unlock(sc->sc_hwmtx);
389 msm_bus_setsig(struct uart_softc *sc, int sig)
396 msm_bus_receive(struct uart_softc *sc)
398 struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
399 struct uart_bas *bas;
403 uart_lock(sc->sc_hwmtx);
405 /* Initialize Receive Path and interrupt */
406 SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
407 SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);
408 u->ier |= UART_DM_RXLEV;
409 SETREG(bas, UART_DM_IMR, u->ier);
411 /* Loop over until we are full, or no data is available */
412 while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {
413 if (uart_rx_full(sc)) {
414 /* No space left in input buffer */
415 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
420 c = uart_getreg(bas, UART_DM_RF(0));
426 uart_unlock(sc->sc_hwmtx);
432 msm_bus_param(struct uart_softc *sc, int baudrate, int databits,
433 int stopbits, int parity)
437 if (sc->sc_bas.rclk == 0)
438 sc->sc_bas.rclk = DEF_CLK;
440 KASSERT(sc->sc_bas.rclk != 0, ("msm_init: Invalid rclk"));
442 uart_lock(sc->sc_hwmtx);
443 error = msm_uart_param(&sc->sc_bas, baudrate, databits, stopbits,
445 uart_unlock(sc->sc_hwmtx);
451 msm_bus_ipend(struct uart_softc *sc)
453 struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
454 struct uart_bas *bas = &sc->sc_bas;
458 uart_lock(sc->sc_hwmtx);
461 isr = GETREG(bas, UART_DM_MISR);
465 /* Uart RX starting, notify upper layer */
466 if (isr & UART_DM_RXLEV) {
467 u->ier &= ~UART_DM_RXLEV;
468 SETREG(bas, UART_DM_IMR, u->ier);
470 ipend |= SER_INT_RXREADY;
473 /* Stale RX interrupt */
474 if (isr & UART_DM_RXSTALE) {
475 /* Disable and reset it */
476 SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_DISABLE);
477 SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
479 ipend |= SER_INT_RXREADY;
482 /* TX READY interrupt */
483 if (isr & UART_DM_TX_READY) {
485 SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);
487 /* Disable TX_READY */
488 u->ier &= ~UART_DM_TX_READY;
489 SETREG(bas, UART_DM_IMR, u->ier);
492 if (sc->sc_txbusy != 0)
493 ipend |= SER_INT_TXIDLE;
496 if (isr & UART_DM_TXLEV) {
497 /* TX FIFO is empty */
498 u->ier &= ~UART_DM_TXLEV;
499 SETREG(bas, UART_DM_IMR, u->ier);
502 if (sc->sc_txbusy != 0)
503 ipend |= SER_INT_TXIDLE;
506 uart_unlock(sc->sc_hwmtx);
511 msm_bus_flush(struct uart_softc *sc, int what)
518 msm_bus_getsig(struct uart_softc *sc)
525 msm_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
532 msm_bus_grab(struct uart_softc *sc)
534 struct uart_bas *bas = &sc->sc_bas;
537 * XXX: Turn off all interrupts to enter polling mode. Leave the
538 * saved mask alone. We'll restore whatever it was in ungrab.
540 uart_lock(sc->sc_hwmtx);
541 SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
542 SETREG(bas, UART_DM_IMR, 0);
544 uart_unlock(sc->sc_hwmtx);
548 msm_bus_ungrab(struct uart_softc *sc)
550 struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
551 struct uart_bas *bas = &sc->sc_bas;
554 * Restore previous interrupt mask
556 uart_lock(sc->sc_hwmtx);
557 SETREG(bas, UART_DM_IMR, u->ier);
559 uart_unlock(sc->sc_hwmtx);
562 static struct uart_class uart_msm_class = {
565 sizeof(struct msm_uart_softc),
566 .uc_ops = &uart_msm_ops,
571 static struct ofw_compat_data compat_data[] = {
572 {"qcom,msm-uartdm", (uintptr_t)&uart_msm_class},
573 {NULL, (uintptr_t)NULL},
575 UART_FDT_CLASS_AND_DEVICE(compat_data);