2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/uart/uart.h>
47 #include <dev/uart/uart_cpu.h>
49 #include <dev/uart/uart_cpu_fdt.h>
51 #include <dev/uart/uart_bus.h>
52 #include <dev/uart/uart_dev_ns8250.h>
53 #include <dev/uart/uart_ppstypes.h>
55 #include <dev/ic/ns16550.h>
59 #define DEFAULT_RCLK 1843200
61 static int broken_txfifo = 0;
62 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
63 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
64 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
67 * Clear pending interrupts. THRE is cleared by reading IIR. Data
68 * that may have been received gets lost here.
71 ns8250_clrint(struct uart_bas *bas)
75 iir = uart_getreg(bas, REG_IIR);
76 while ((iir & IIR_NOPEND) == 0) {
79 lsr = uart_getreg(bas, REG_LSR);
80 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
81 (void)uart_getreg(bas, REG_DATA);
82 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
83 (void)uart_getreg(bas, REG_DATA);
84 else if (iir == IIR_MLSC)
85 (void)uart_getreg(bas, REG_MSR);
87 iir = uart_getreg(bas, REG_IIR);
92 ns8250_delay(struct uart_bas *bas)
97 lcr = uart_getreg(bas, REG_LCR);
98 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
100 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
102 uart_setreg(bas, REG_LCR, lcr);
105 /* 1/10th the time to transmit 1 character (estimate). */
107 return (16000000 * divisor / bas->rclk);
108 return (16000 * divisor / (bas->rclk / 1000));
112 ns8250_divisor(int rclk, int baudrate)
114 int actual_baud, divisor;
120 divisor = (rclk / (baudrate << 3) + 1) >> 1;
121 if (divisor == 0 || divisor >= 65536)
123 actual_baud = rclk / (divisor << 4);
125 /* 10 times error in percent: */
126 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
128 /* 3.0% maximum error tolerance: */
129 if (error < -30 || error > 30)
136 ns8250_drain(struct uart_bas *bas, int what)
140 delay = ns8250_delay(bas);
142 if (what & UART_DRAIN_TRANSMITTER) {
144 * Pick an arbitrary high limit to avoid getting stuck in
145 * an infinite loop when the hardware is broken. Make the
146 * limit high enough to handle large FIFOs.
149 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
152 /* printf("ns8250: transmitter appears stuck... "); */
157 if (what & UART_DRAIN_RECEIVER) {
159 * Pick an arbitrary high limit to avoid getting stuck in
160 * an infinite loop when the hardware is broken. Make the
161 * limit high enough to handle large FIFOs and integrated
162 * UARTs. The HP rx2600 for example has 3 UARTs on the
163 * management board that tend to get a lot of data send
164 * to it when the UART is first activated.
167 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
168 (void)uart_getreg(bas, REG_DATA);
173 /* printf("ns8250: receiver appears broken... "); */
182 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
183 * drained. WARNING: this function clobbers the FIFO setting!
186 ns8250_flush(struct uart_bas *bas, int what)
191 if (what & UART_FLUSH_TRANSMITTER)
193 if (what & UART_FLUSH_RECEIVER)
195 uart_setreg(bas, REG_FCR, fcr);
200 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
209 else if (databits == 7)
211 else if (databits == 6)
221 divisor = ns8250_divisor(bas->rclk, baudrate);
224 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
226 uart_setreg(bas, REG_DLL, divisor & 0xff);
227 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
231 /* Set LCR and clear DLAB. */
232 uart_setreg(bas, REG_LCR, lcr);
238 * Low-level UART interface.
240 static int ns8250_probe(struct uart_bas *bas);
241 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
242 static void ns8250_term(struct uart_bas *bas);
243 static void ns8250_putc(struct uart_bas *bas, int);
244 static int ns8250_rxready(struct uart_bas *bas);
245 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
247 struct uart_ops uart_ns8250_ops = {
248 .probe = ns8250_probe,
252 .rxready = ns8250_rxready,
257 ns8250_probe(struct uart_bas *bas)
261 /* Check known 0 bits that don't depend on DLAB. */
262 val = uart_getreg(bas, REG_IIR);
266 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
267 * chip, but otherwise doesn't seem to have a function. In
268 * other words, uart(4) works regardless. Ignore that bit so
269 * the probe succeeds.
271 val = uart_getreg(bas, REG_MCR);
279 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
285 bas->rclk = DEFAULT_RCLK;
286 ns8250_param(bas, baudrate, databits, stopbits, parity);
288 /* Disable all interrupt sources. */
290 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
291 * UARTs split the receive time-out interrupt bit out separately as
292 * 0x10. This gets handled by ier_mask and ier_rxbits below.
294 ier = uart_getreg(bas, REG_IER) & 0xe0;
295 uart_setreg(bas, REG_IER, ier);
298 /* Disable the FIFO (if present). */
299 uart_setreg(bas, REG_FCR, 0);
303 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
310 ns8250_term(struct uart_bas *bas)
313 /* Clear RTS & DTR. */
314 uart_setreg(bas, REG_MCR, MCR_IE);
319 ns8250_putc(struct uart_bas *bas, int c)
324 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
326 uart_setreg(bas, REG_DATA, c);
329 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
334 ns8250_rxready(struct uart_bas *bas)
337 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
341 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
347 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
353 c = uart_getreg(bas, REG_DATA);
360 static kobj_method_t ns8250_methods[] = {
361 KOBJMETHOD(uart_attach, ns8250_bus_attach),
362 KOBJMETHOD(uart_detach, ns8250_bus_detach),
363 KOBJMETHOD(uart_flush, ns8250_bus_flush),
364 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
365 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
366 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
367 KOBJMETHOD(uart_param, ns8250_bus_param),
368 KOBJMETHOD(uart_probe, ns8250_bus_probe),
369 KOBJMETHOD(uart_receive, ns8250_bus_receive),
370 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
371 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
372 KOBJMETHOD(uart_grab, ns8250_bus_grab),
373 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
377 struct uart_class uart_ns8250_class = {
380 sizeof(struct ns8250_softc),
381 .uc_ops = &uart_ns8250_ops,
383 .uc_rclk = DEFAULT_RCLK
387 static struct ofw_compat_data compat_data[] = {
388 {"ns16550", (uintptr_t)&uart_ns8250_class},
389 {NULL, (uintptr_t)NULL},
391 UART_FDT_CLASS_AND_DEVICE(compat_data);
394 /* Use token-pasting to form SER_ and MSR_ named constants. */
395 #define SER(sig) SER_##sig
396 #define SERD(sig) SER_D##sig
397 #define MSR(sig) MSR_##sig
398 #define MSRD(sig) MSR_D##sig
401 * Detect signal changes using software delta detection. The previous state of
402 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
403 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
404 * new state of both the signal and the delta bits.
406 #define SIGCHGSW(var, msr, sig) \
407 if ((msr) & MSR(sig)) { \
408 if ((var & SER(sig)) == 0) \
409 var |= SERD(sig) | SER(sig); \
411 if ((var & SER(sig)) != 0) \
412 var = SERD(sig) | (var & ~SER(sig)); \
416 * Detect signal changes using the hardware msr delta bits. This is currently
417 * used only when PPS timing information is being captured using the "narrow
418 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
419 * by time the interrupt handler is invoked. The hardware will latch the fact
420 * that it changed in the delta bits.
422 #define SIGCHGHW(var, msr, sig) \
423 if ((msr) & MSRD(sig)) { \
424 if (((msr) & MSR(sig)) != 0) \
425 var |= SERD(sig) | SER(sig); \
427 var = SERD(sig) | (var & ~SER(sig)); \
431 ns8250_bus_attach(struct uart_softc *sc)
433 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
434 struct uart_bas *bas;
441 ns8250->busy_detect = 0;
445 * Check whether uart requires to read USR reg when IIR_BUSY and
448 node = ofw_bus_get_node(sc->sc_dev);
449 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
450 ns8250->busy_detect = 1;
451 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
457 ns8250->mcr = uart_getreg(bas, REG_MCR);
458 ns8250->fcr = FCR_ENABLE;
459 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
461 if (UART_FLAGS_FCR_RX_LOW(ivar))
462 ns8250->fcr |= FCR_RX_LOW;
463 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
464 ns8250->fcr |= FCR_RX_MEDL;
465 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
466 ns8250->fcr |= FCR_RX_HIGH;
468 ns8250->fcr |= FCR_RX_MEDH;
470 ns8250->fcr |= FCR_RX_MEDH;
474 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
476 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
478 /* Get IER RX interrupt bits */
479 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
480 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
482 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
484 uart_setreg(bas, REG_FCR, ns8250->fcr);
486 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
488 if (ns8250->mcr & MCR_DTR)
489 sc->sc_hwsig |= SER_DTR;
490 if (ns8250->mcr & MCR_RTS)
491 sc->sc_hwsig |= SER_RTS;
492 ns8250_bus_getsig(sc);
495 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
496 ns8250->ier |= ns8250->ier_rxbits;
497 uart_setreg(bas, REG_IER, ns8250->ier);
501 * Timing of the H/W access was changed with r253161 of uart_core.c
502 * It has been observed that an ITE IT8513E would signal a break
503 * condition with pretty much every character it received, unless
504 * it had enough time to settle between ns8250_bus_attach() and
505 * ns8250_bus_ipend() -- which it accidentally had before r253161.
506 * It's not understood why the UART chip behaves this way and it
507 * could very well be that the DELAY make the H/W work in the same
508 * accidental manner as before. More analysis is warranted, but
509 * at least now we fixed a known regression.
516 ns8250_bus_detach(struct uart_softc *sc)
518 struct ns8250_softc *ns8250;
519 struct uart_bas *bas;
522 ns8250 = (struct ns8250_softc *)sc;
524 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
525 uart_setreg(bas, REG_IER, ier);
532 ns8250_bus_flush(struct uart_softc *sc, int what)
534 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
535 struct uart_bas *bas;
539 uart_lock(sc->sc_hwmtx);
540 if (sc->sc_rxfifosz > 1) {
541 ns8250_flush(bas, what);
542 uart_setreg(bas, REG_FCR, ns8250->fcr);
546 error = ns8250_drain(bas, what);
547 uart_unlock(sc->sc_hwmtx);
552 ns8250_bus_getsig(struct uart_softc *sc)
558 * The delta bits are reputed to be broken on some hardware, so use
559 * software delta detection by default. Use the hardware delta bits
560 * when capturing PPS pulses which are too narrow for software detection
561 * to see the edges. Hardware delta for RI doesn't work like the
562 * others, so always use software for it. Other threads may be changing
563 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully
564 * update without other changes happening. Note that the SIGCHGxx()
565 * macros carefully preserve the delta bits when we have to loop several
566 * times and a signal transitions between iterations.
571 uart_lock(sc->sc_hwmtx);
572 msr = uart_getreg(&sc->sc_bas, REG_MSR);
573 uart_unlock(sc->sc_hwmtx);
574 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
575 SIGCHGHW(sig, msr, DSR);
576 SIGCHGHW(sig, msr, CTS);
577 SIGCHGHW(sig, msr, DCD);
579 SIGCHGSW(sig, msr, DSR);
580 SIGCHGSW(sig, msr, CTS);
581 SIGCHGSW(sig, msr, DCD);
583 SIGCHGSW(sig, msr, RI);
584 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
589 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
591 struct uart_bas *bas;
592 int baudrate, divisor, error;
597 uart_lock(sc->sc_hwmtx);
599 case UART_IOCTL_BREAK:
600 lcr = uart_getreg(bas, REG_LCR);
605 uart_setreg(bas, REG_LCR, lcr);
608 case UART_IOCTL_IFLOW:
609 lcr = uart_getreg(bas, REG_LCR);
611 uart_setreg(bas, REG_LCR, 0xbf);
613 efr = uart_getreg(bas, REG_EFR);
618 uart_setreg(bas, REG_EFR, efr);
620 uart_setreg(bas, REG_LCR, lcr);
623 case UART_IOCTL_OFLOW:
624 lcr = uart_getreg(bas, REG_LCR);
626 uart_setreg(bas, REG_LCR, 0xbf);
628 efr = uart_getreg(bas, REG_EFR);
633 uart_setreg(bas, REG_EFR, efr);
635 uart_setreg(bas, REG_LCR, lcr);
638 case UART_IOCTL_BAUD:
639 lcr = uart_getreg(bas, REG_LCR);
640 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
642 divisor = uart_getreg(bas, REG_DLL) |
643 (uart_getreg(bas, REG_DLH) << 8);
645 uart_setreg(bas, REG_LCR, lcr);
647 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
649 *(int*)data = baudrate;
657 uart_unlock(sc->sc_hwmtx);
662 ns8250_bus_ipend(struct uart_softc *sc)
664 struct uart_bas *bas;
665 struct ns8250_softc *ns8250;
669 ns8250 = (struct ns8250_softc *)sc;
671 uart_lock(sc->sc_hwmtx);
672 iir = uart_getreg(bas, REG_IIR);
674 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
675 (void)uart_getreg(bas, DW_REG_USR);
676 uart_unlock(sc->sc_hwmtx);
679 if (iir & IIR_NOPEND) {
680 uart_unlock(sc->sc_hwmtx);
684 if (iir & IIR_RXRDY) {
685 lsr = uart_getreg(bas, REG_LSR);
687 ipend |= SER_INT_OVERRUN;
689 ipend |= SER_INT_BREAK;
691 ipend |= SER_INT_RXREADY;
693 if (iir & IIR_TXRDY) {
694 ipend |= SER_INT_TXIDLE;
695 uart_setreg(bas, REG_IER, ns8250->ier);
697 ipend |= SER_INT_SIGCHG;
701 uart_unlock(sc->sc_hwmtx);
706 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
707 int stopbits, int parity)
709 struct ns8250_softc *ns8250;
710 struct uart_bas *bas;
713 ns8250 = (struct ns8250_softc*)sc;
715 uart_lock(sc->sc_hwmtx);
717 * When using DW UART with BUSY detection it is necessary to wait
718 * until all serial transfers are finished before manipulating the
719 * line control. LCR will not be affected when UART is busy.
721 if (ns8250->busy_detect != 0) {
723 * Pick an arbitrary high limit to avoid getting stuck in
724 * an infinite loop in case when the hardware is broken.
727 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
732 /* UART appears to be stuck */
733 uart_unlock(sc->sc_hwmtx);
738 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
739 uart_unlock(sc->sc_hwmtx);
744 ns8250_bus_probe(struct uart_softc *sc)
746 struct ns8250_softc *ns8250;
747 struct uart_bas *bas;
748 int count, delay, error, limit;
749 uint8_t lsr, mcr, ier;
751 ns8250 = (struct ns8250_softc *)sc;
754 error = ns8250_probe(bas);
759 if (sc->sc_sysdev == NULL) {
760 /* By using ns8250_init() we also set DTR and RTS. */
761 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
763 mcr |= MCR_DTR | MCR_RTS;
765 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
770 * Set loopback mode. This avoids having garbage on the wire and
771 * also allows us send and receive data. We set DTR and RTS to
772 * avoid the possibility that automatic flow-control prevents
773 * any data from being sent.
775 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
779 * Enable FIFOs. And check that the UART has them. If not, we're
780 * done. Since this is the first time we enable the FIFOs, we reset
783 uart_setreg(bas, REG_FCR, FCR_ENABLE);
785 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
787 * NS16450 or INS8250. We don't bother to differentiate
788 * between them. They're too old to be interesting.
790 uart_setreg(bas, REG_MCR, mcr);
792 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
793 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
797 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
801 delay = ns8250_delay(bas);
803 /* We have FIFOs. Drain the transmitter and receiver. */
804 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
806 uart_setreg(bas, REG_MCR, mcr);
807 uart_setreg(bas, REG_FCR, 0);
813 * We should have a sufficiently clean "pipe" to determine the
814 * size of the FIFOs. We send as much characters as is reasonable
815 * and wait for the overflow bit in the LSR register to be
816 * asserted, counting the characters as we send them. Based on
817 * that count we know the FIFO size.
820 uart_setreg(bas, REG_DATA, 0);
827 * LSR bits are cleared upon read, so we must accumulate
828 * them to be able to test LSR_OE below.
830 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
834 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
835 uart_setreg(bas, REG_IER, ier);
836 uart_setreg(bas, REG_MCR, mcr);
837 uart_setreg(bas, REG_FCR, 0);
842 } while ((lsr & LSR_OE) == 0 && count < 130);
845 uart_setreg(bas, REG_MCR, mcr);
848 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
851 if (count >= 14 && count <= 16) {
852 sc->sc_rxfifosz = 16;
853 device_set_desc(sc->sc_dev, "16550 or compatible");
854 } else if (count >= 28 && count <= 32) {
855 sc->sc_rxfifosz = 32;
856 device_set_desc(sc->sc_dev, "16650 or compatible");
857 } else if (count >= 56 && count <= 64) {
858 sc->sc_rxfifosz = 64;
859 device_set_desc(sc->sc_dev, "16750 or compatible");
860 } else if (count >= 112 && count <= 128) {
861 sc->sc_rxfifosz = 128;
862 device_set_desc(sc->sc_dev, "16950 or compatible");
864 sc->sc_rxfifosz = 16;
865 device_set_desc(sc->sc_dev,
866 "Non-standard ns8250 class UART with FIFOs");
870 * Force the Tx FIFO size to 16 bytes for now. We don't program the
871 * Tx trigger. Also, we assume that all data has been sent when the
874 sc->sc_txfifosz = 16;
878 * XXX there are some issues related to hardware flow control and
879 * it's likely that uart(4) is the cause. This basicly needs more
880 * investigation, but we avoid using for hardware flow control
883 /* 16650s or higher have automatic flow control. */
884 if (sc->sc_rxfifosz > 16) {
894 ns8250_bus_receive(struct uart_softc *sc)
896 struct uart_bas *bas;
901 uart_lock(sc->sc_hwmtx);
902 lsr = uart_getreg(bas, REG_LSR);
903 while (lsr & LSR_RXRDY) {
904 if (uart_rx_full(sc)) {
905 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
908 xc = uart_getreg(bas, REG_DATA);
910 xc |= UART_STAT_FRAMERR;
912 xc |= UART_STAT_PARERR;
914 lsr = uart_getreg(bas, REG_LSR);
916 /* Discard everything left in the Rx FIFO. */
917 while (lsr & LSR_RXRDY) {
918 (void)uart_getreg(bas, REG_DATA);
920 lsr = uart_getreg(bas, REG_LSR);
922 uart_unlock(sc->sc_hwmtx);
927 ns8250_bus_setsig(struct uart_softc *sc, int sig)
929 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
930 struct uart_bas *bas;
937 if (sig & SER_DDTR) {
938 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
940 if (sig & SER_DRTS) {
941 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
943 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
944 uart_lock(sc->sc_hwmtx);
945 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
947 ns8250->mcr |= MCR_DTR;
949 ns8250->mcr |= MCR_RTS;
950 uart_setreg(bas, REG_MCR, ns8250->mcr);
952 uart_unlock(sc->sc_hwmtx);
957 ns8250_bus_transmit(struct uart_softc *sc)
959 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
960 struct uart_bas *bas;
964 uart_lock(sc->sc_hwmtx);
965 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
967 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
969 for (i = 0; i < sc->sc_txdatasz; i++) {
970 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
974 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
977 uart_unlock(sc->sc_hwmtx);
979 uart_sched_softih(sc, SER_INT_TXIDLE);
984 ns8250_bus_grab(struct uart_softc *sc)
986 struct uart_bas *bas = &sc->sc_bas;
989 * turn off all interrupts to enter polling mode. Leave the
990 * saved mask alone. We'll restore whatever it was in ungrab.
991 * All pending interupt signals are reset when IER is set to 0.
993 uart_lock(sc->sc_hwmtx);
994 uart_setreg(bas, REG_IER, 0);
996 uart_unlock(sc->sc_hwmtx);
1000 ns8250_bus_ungrab(struct uart_softc *sc)
1002 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1003 struct uart_bas *bas = &sc->sc_bas;
1006 * Restore previous interrupt mask
1008 uart_lock(sc->sc_hwmtx);
1009 uart_setreg(bas, REG_IER, ns8250->ier);
1011 uart_unlock(sc->sc_hwmtx);