1 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
36 * Effort sponsored in part by the Defense Advanced Research Projects
37 * Agency (DARPA) and Air Force Research Laboratory, Air Force
38 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
48 #include "opt_ubsec.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
59 #include <sys/mutex.h>
60 #include <sys/sysctl.h>
61 #include <sys/endian.h>
66 #include <machine/bus.h>
67 #include <machine/resource.h>
71 #include <crypto/sha1.h>
72 #include <opencrypto/cryptodev.h>
73 #include <opencrypto/cryptosoft.h>
75 #include <sys/random.h>
78 #include "cryptodev_if.h"
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pcireg.h>
83 /* grr, #defines for gratuitous incompatibility in queue.h */
84 #define SIMPLEQ_HEAD STAILQ_HEAD
85 #define SIMPLEQ_ENTRY STAILQ_ENTRY
86 #define SIMPLEQ_INIT STAILQ_INIT
87 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
88 #define SIMPLEQ_EMPTY STAILQ_EMPTY
89 #define SIMPLEQ_FIRST STAILQ_FIRST
90 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
91 #define SIMPLEQ_FOREACH STAILQ_FOREACH
92 /* ditto for endian.h */
93 #define letoh16(x) le16toh(x)
94 #define letoh32(x) le32toh(x)
97 #include <dev/rndtest/rndtest.h>
99 #include <dev/ubsec/ubsecreg.h>
100 #include <dev/ubsec/ubsecvar.h>
103 * Prototypes and count for the pci_device structure
105 static int ubsec_probe(device_t);
106 static int ubsec_attach(device_t);
107 static int ubsec_detach(device_t);
108 static int ubsec_suspend(device_t);
109 static int ubsec_resume(device_t);
110 static int ubsec_shutdown(device_t);
112 static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
113 static int ubsec_freesession(device_t, u_int64_t);
114 static int ubsec_process(device_t, struct cryptop *, int);
115 static int ubsec_kprocess(device_t, struct cryptkop *, int);
117 static device_method_t ubsec_methods[] = {
118 /* Device interface */
119 DEVMETHOD(device_probe, ubsec_probe),
120 DEVMETHOD(device_attach, ubsec_attach),
121 DEVMETHOD(device_detach, ubsec_detach),
122 DEVMETHOD(device_suspend, ubsec_suspend),
123 DEVMETHOD(device_resume, ubsec_resume),
124 DEVMETHOD(device_shutdown, ubsec_shutdown),
126 /* crypto device methods */
127 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
128 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
129 DEVMETHOD(cryptodev_process, ubsec_process),
130 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess),
134 static driver_t ubsec_driver = {
137 sizeof (struct ubsec_softc)
139 static devclass_t ubsec_devclass;
141 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
142 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
144 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
147 static void ubsec_intr(void *);
148 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
149 static void ubsec_feed(struct ubsec_softc *);
150 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
151 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
152 static int ubsec_feed2(struct ubsec_softc *);
153 static void ubsec_rng(void *);
154 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
155 struct ubsec_dma_alloc *, int);
156 #define ubsec_dma_sync(_dma, _flags) \
157 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
158 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
159 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
161 static void ubsec_reset_board(struct ubsec_softc *sc);
162 static void ubsec_init_board(struct ubsec_softc *sc);
163 static void ubsec_init_pciregs(device_t dev);
164 static void ubsec_totalreset(struct ubsec_softc *sc);
166 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
168 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
169 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
170 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
171 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
172 static int ubsec_ksigbits(struct crparam *);
173 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
174 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
176 static SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0,
177 "Broadcom driver parameters");
180 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
181 static void ubsec_dump_mcr(struct ubsec_mcr *);
182 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
184 static int ubsec_debug = 0;
185 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
186 0, "control debugging msgs");
189 #define READ_REG(sc,r) \
190 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
192 #define WRITE_REG(sc,reg,val) \
193 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
195 #define SWAP32(x) (x) = htole32(ntohl((x)))
196 #define HTOLE32(x) (x) = htole32(x)
198 struct ubsec_stats ubsecstats;
199 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
200 ubsec_stats, "driver statistics");
203 ubsec_probe(device_t dev)
205 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
206 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
207 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
208 return (BUS_PROBE_DEFAULT);
209 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
210 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
211 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
212 return (BUS_PROBE_DEFAULT);
213 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
214 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
221 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825
223 return (BUS_PROBE_DEFAULT);
228 ubsec_partname(struct ubsec_softc *sc)
230 /* XXX sprintf numbers when not decoded */
231 switch (pci_get_vendor(sc->sc_dev)) {
232 case PCI_VENDOR_BROADCOM:
233 switch (pci_get_device(sc->sc_dev)) {
234 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
235 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
236 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
237 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
238 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
239 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
240 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
241 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825";
243 return "Broadcom unknown-part";
244 case PCI_VENDOR_BLUESTEEL:
245 switch (pci_get_device(sc->sc_dev)) {
246 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
248 return "Bluesteel unknown-part";
250 switch (pci_get_device(sc->sc_dev)) {
251 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
252 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
254 return "Sun unknown-part";
256 return "Unknown-vendor unknown-part";
260 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
262 random_harvest(buf, count, count*NBBY/2, RANDOM_PURE_UBSEC);
266 ubsec_attach(device_t dev)
268 struct ubsec_softc *sc = device_get_softc(dev);
269 struct ubsec_dma *dmap;
273 bzero(sc, sizeof (*sc));
276 SIMPLEQ_INIT(&sc->sc_queue);
277 SIMPLEQ_INIT(&sc->sc_qchip);
278 SIMPLEQ_INIT(&sc->sc_queue2);
279 SIMPLEQ_INIT(&sc->sc_qchip2);
280 SIMPLEQ_INIT(&sc->sc_q2free);
282 /* XXX handle power management */
284 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
286 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
287 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
290 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
291 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
292 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
293 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
295 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
296 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
297 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
298 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
300 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
301 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
302 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
303 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
304 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) ||
305 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
306 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
307 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
308 /* NB: the 5821/5822 defines some additional status bits */
309 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
310 BS_STAT_MCR2_ALLEMPTY;
311 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
312 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
315 pci_enable_busmaster(dev);
318 * Setup memory-mapping of PCI registers.
321 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
323 if (sc->sc_sr == NULL) {
324 device_printf(dev, "cannot map register space\n");
327 sc->sc_st = rman_get_bustag(sc->sc_sr);
328 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
331 * Arrange interrupt line.
334 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
335 RF_SHAREABLE|RF_ACTIVE);
336 if (sc->sc_irq == NULL) {
337 device_printf(dev, "could not map interrupt\n");
341 * NB: Network code assumes we are blocked with splimp()
342 * so make sure the IRQ is mapped appropriately.
344 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
345 NULL, ubsec_intr, sc, &sc->sc_ih)) {
346 device_printf(dev, "could not establish interrupt\n");
350 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
351 if (sc->sc_cid < 0) {
352 device_printf(dev, "could not get crypto driver id\n");
357 * Setup DMA descriptor area.
359 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
360 1, 0, /* alignment, bounds */
361 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
362 BUS_SPACE_MAXADDR, /* highaddr */
363 NULL, NULL, /* filter, filterarg */
364 0x3ffff, /* maxsize */
365 UBS_MAX_SCATTER, /* nsegments */
366 0xffff, /* maxsegsize */
367 BUS_DMA_ALLOCNOW, /* flags */
368 NULL, NULL, /* lockfunc, lockarg */
370 device_printf(dev, "cannot allocate DMA tag\n");
373 SIMPLEQ_INIT(&sc->sc_freequeue);
375 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
378 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
381 device_printf(dev, "cannot allocate queue buffers\n");
385 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
386 &dmap->d_alloc, 0)) {
387 device_printf(dev, "cannot allocate dma buffers\n");
391 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
394 sc->sc_queuea[i] = q;
396 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
398 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
399 "mcr1 operations", MTX_DEF);
400 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
401 "mcr1 free q", MTX_DEF);
403 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
405 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
406 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
407 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
408 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
411 * Reset Broadcom chip
413 ubsec_reset_board(sc);
416 * Init Broadcom specific PCI settings
418 ubsec_init_pciregs(dev);
423 ubsec_init_board(sc);
426 if (sc->sc_flags & UBS_FLAGS_RNG) {
427 sc->sc_statmask |= BS_STAT_MCR2_DONE;
429 sc->sc_rndtest = rndtest_attach(dev);
431 sc->sc_harvest = rndtest_harvest;
433 sc->sc_harvest = default_harvest;
435 sc->sc_harvest = default_harvest;
438 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
439 &sc->sc_rng.rng_q.q_mcr, 0))
442 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
443 &sc->sc_rng.rng_q.q_ctx, 0)) {
444 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
448 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
449 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
450 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
456 sc->sc_rnghz = hz / 100;
459 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
460 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
464 #endif /* UBSEC_NO_RNG */
465 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
466 "mcr2 operations", MTX_DEF);
468 if (sc->sc_flags & UBS_FLAGS_KEY) {
469 sc->sc_statmask |= BS_STAT_MCR2_DONE;
471 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
473 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
478 crypto_unregister_all(sc->sc_cid);
480 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
482 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
484 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
490 * Detach a device that successfully probed.
493 ubsec_detach(device_t dev)
495 struct ubsec_softc *sc = device_get_softc(dev);
497 /* XXX wait/abort active ops */
499 /* disable interrupts */
500 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
501 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
503 callout_stop(&sc->sc_rngto);
505 crypto_unregister_all(sc->sc_cid);
509 rndtest_detach(sc->sc_rndtest);
512 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
515 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
516 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
517 ubsec_dma_free(sc, &q->q_dma->d_alloc);
520 mtx_destroy(&sc->sc_mcr1lock);
521 mtx_destroy(&sc->sc_freeqlock);
523 if (sc->sc_flags & UBS_FLAGS_RNG) {
524 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
525 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
526 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
528 #endif /* UBSEC_NO_RNG */
529 mtx_destroy(&sc->sc_mcr2lock);
531 bus_generic_detach(dev);
532 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
535 bus_dma_tag_destroy(sc->sc_dmat);
536 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
542 * Stop all chip i/o so that the kernel's probe routines don't
543 * get confused by errant DMAs when rebooting.
546 ubsec_shutdown(device_t dev)
549 ubsec_stop(device_get_softc(dev));
555 * Device suspend routine.
558 ubsec_suspend(device_t dev)
560 struct ubsec_softc *sc = device_get_softc(dev);
563 /* XXX stop the device and save PCI settings */
565 sc->sc_suspended = 1;
571 ubsec_resume(device_t dev)
573 struct ubsec_softc *sc = device_get_softc(dev);
576 /* XXX retore PCI settings and start the device */
578 sc->sc_suspended = 0;
583 * UBSEC Interrupt routine
586 ubsec_intr(void *arg)
588 struct ubsec_softc *sc = arg;
589 volatile u_int32_t stat;
591 struct ubsec_dma *dmap;
594 stat = READ_REG(sc, BS_STAT);
595 stat &= sc->sc_statmask;
599 WRITE_REG(sc, BS_STAT, stat); /* IACK */
602 * Check to see if we have any packets waiting for us
604 if ((stat & BS_STAT_MCR1_DONE)) {
605 mtx_lock(&sc->sc_mcr1lock);
606 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
607 q = SIMPLEQ_FIRST(&sc->sc_qchip);
610 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
613 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
615 npkts = q->q_nstacked_mcrs;
616 sc->sc_nqchip -= 1+npkts;
618 * search for further sc_qchip ubsec_q's that share
619 * the same MCR, and complete them too, they must be
622 for (i = 0; i < npkts; i++) {
623 if(q->q_stacked_mcr[i]) {
624 ubsec_callback(sc, q->q_stacked_mcr[i]);
629 ubsec_callback(sc, q);
632 * Don't send any more packet to chip if there has been
635 if (!(stat & BS_STAT_DMAERR))
637 mtx_unlock(&sc->sc_mcr1lock);
641 * Check to see if we have any key setups/rng's waiting for us
643 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
644 (stat & BS_STAT_MCR2_DONE)) {
646 struct ubsec_mcr *mcr;
648 mtx_lock(&sc->sc_mcr2lock);
649 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
650 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
652 ubsec_dma_sync(&q2->q_mcr,
653 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
657 ubsec_dma_sync(&q2->q_mcr,
658 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
661 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
662 ubsec_callback2(sc, q2);
664 * Don't send any more packet to chip if there has been
667 if (!(stat & BS_STAT_DMAERR))
670 mtx_unlock(&sc->sc_mcr2lock);
674 * Check to see if we got any DMA Error
676 if (stat & BS_STAT_DMAERR) {
679 volatile u_int32_t a = READ_REG(sc, BS_ERR);
681 printf("dmaerr %s@%08x\n",
682 (a & BS_ERR_READ) ? "read" : "write",
685 #endif /* UBSEC_DEBUG */
686 ubsecstats.hst_dmaerr++;
687 mtx_lock(&sc->sc_mcr1lock);
688 ubsec_totalreset(sc);
690 mtx_unlock(&sc->sc_mcr1lock);
693 if (sc->sc_needwakeup) { /* XXX check high watermark */
696 mtx_lock(&sc->sc_freeqlock);
697 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
700 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
702 #endif /* UBSEC_DEBUG */
703 sc->sc_needwakeup &= ~wakeup;
704 mtx_unlock(&sc->sc_freeqlock);
705 crypto_unblock(sc->sc_cid, wakeup);
710 * ubsec_feed() - aggregate and post requests to chip
713 ubsec_feed(struct ubsec_softc *sc)
715 struct ubsec_q *q, *q2;
721 * Decide how many ops to combine in a single MCR. We cannot
722 * aggregate more than UBS_MAX_AGGR because this is the number
723 * of slots defined in the data structure. Note that
724 * aggregation only happens if ops are marked batch'able.
725 * Aggregating ops reduces the number of interrupts to the host
726 * but also (potentially) increases the latency for processing
727 * completed ops as we only get an interrupt when all aggregated
728 * ops have completed.
730 if (sc->sc_nqueue == 0)
732 if (sc->sc_nqueue > 1) {
734 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
736 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
742 * Check device status before going any further.
744 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
745 if (stat & BS_STAT_DMAERR) {
746 ubsec_totalreset(sc);
747 ubsecstats.hst_dmaerr++;
749 ubsecstats.hst_mcr1full++;
752 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
753 ubsecstats.hst_maxqueue = sc->sc_nqueue;
754 if (npkts > UBS_MAX_AGGR)
755 npkts = UBS_MAX_AGGR;
756 if (npkts < 2) /* special case 1 op */
759 ubsecstats.hst_totbatch += npkts-1;
762 printf("merging %d records\n", npkts);
763 #endif /* UBSEC_DEBUG */
765 q = SIMPLEQ_FIRST(&sc->sc_queue);
766 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
769 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
770 if (q->q_dst_map != NULL)
771 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
773 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
775 for (i = 0; i < q->q_nstacked_mcrs; i++) {
776 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
777 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
778 BUS_DMASYNC_PREWRITE);
779 if (q2->q_dst_map != NULL)
780 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
781 BUS_DMASYNC_PREREAD);
782 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
785 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
786 sizeof(struct ubsec_mcr_add));
787 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
788 q->q_stacked_mcr[i] = q2;
790 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
791 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
792 sc->sc_nqchip += npkts;
793 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
794 ubsecstats.hst_maxqchip = sc->sc_nqchip;
795 ubsec_dma_sync(&q->q_dma->d_alloc,
796 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
797 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
798 offsetof(struct ubsec_dmachunk, d_mcr));
801 q = SIMPLEQ_FIRST(&sc->sc_queue);
803 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
804 if (q->q_dst_map != NULL)
805 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
806 ubsec_dma_sync(&q->q_dma->d_alloc,
807 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
809 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
810 offsetof(struct ubsec_dmachunk, d_mcr));
813 printf("feed1: q->chip %p %08x stat %08x\n",
814 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
816 #endif /* UBSEC_DEBUG */
817 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
819 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
821 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
822 ubsecstats.hst_maxqchip = sc->sc_nqchip;
827 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
830 /* Go ahead and compute key in ubsec's byte order */
831 if (algo == CRYPTO_DES_CBC) {
832 bcopy(key, &ses->ses_deskey[0], 8);
833 bcopy(key, &ses->ses_deskey[2], 8);
834 bcopy(key, &ses->ses_deskey[4], 8);
836 bcopy(key, ses->ses_deskey, 24);
838 SWAP32(ses->ses_deskey[0]);
839 SWAP32(ses->ses_deskey[1]);
840 SWAP32(ses->ses_deskey[2]);
841 SWAP32(ses->ses_deskey[3]);
842 SWAP32(ses->ses_deskey[4]);
843 SWAP32(ses->ses_deskey[5]);
847 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
853 for (i = 0; i < klen; i++)
854 key[i] ^= HMAC_IPAD_VAL;
856 if (algo == CRYPTO_MD5_HMAC) {
858 MD5Update(&md5ctx, key, klen);
859 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
860 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
863 SHA1Update(&sha1ctx, key, klen);
864 SHA1Update(&sha1ctx, hmac_ipad_buffer,
865 SHA1_HMAC_BLOCK_LEN - klen);
866 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
869 for (i = 0; i < klen; i++)
870 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
872 if (algo == CRYPTO_MD5_HMAC) {
874 MD5Update(&md5ctx, key, klen);
875 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
876 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
879 SHA1Update(&sha1ctx, key, klen);
880 SHA1Update(&sha1ctx, hmac_opad_buffer,
881 SHA1_HMAC_BLOCK_LEN - klen);
882 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
885 for (i = 0; i < klen; i++)
886 key[i] ^= HMAC_OPAD_VAL;
890 * Allocate a new 'session' and return an encoded session id. 'sidp'
891 * contains our registration id, and should contain an encoded session
892 * id on successful allocation.
895 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
897 struct ubsec_softc *sc = device_get_softc(dev);
898 struct cryptoini *c, *encini = NULL, *macini = NULL;
899 struct ubsec_session *ses = NULL;
902 if (sidp == NULL || cri == NULL || sc == NULL)
905 for (c = cri; c != NULL; c = c->cri_next) {
906 if (c->cri_alg == CRYPTO_MD5_HMAC ||
907 c->cri_alg == CRYPTO_SHA1_HMAC) {
911 } else if (c->cri_alg == CRYPTO_DES_CBC ||
912 c->cri_alg == CRYPTO_3DES_CBC) {
919 if (encini == NULL && macini == NULL)
922 if (sc->sc_sessions == NULL) {
923 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
924 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
928 sc->sc_nsessions = 1;
930 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
931 if (sc->sc_sessions[sesn].ses_used == 0) {
932 ses = &sc->sc_sessions[sesn];
938 sesn = sc->sc_nsessions;
939 ses = (struct ubsec_session *)malloc((sesn + 1) *
940 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
943 bcopy(sc->sc_sessions, ses, sesn *
944 sizeof(struct ubsec_session));
945 bzero(sc->sc_sessions, sesn *
946 sizeof(struct ubsec_session));
947 free(sc->sc_sessions, M_DEVBUF);
948 sc->sc_sessions = ses;
949 ses = &sc->sc_sessions[sesn];
953 bzero(ses, sizeof(struct ubsec_session));
957 /* get an IV, network byte order */
958 /* XXX may read fewer than requested */
959 read_random(ses->ses_iv, sizeof(ses->ses_iv));
961 if (encini->cri_key != NULL) {
962 ubsec_setup_enckey(ses, encini->cri_alg,
968 ses->ses_mlen = macini->cri_mlen;
969 if (ses->ses_mlen == 0) {
970 if (macini->cri_alg == CRYPTO_MD5_HMAC)
971 ses->ses_mlen = MD5_HASH_LEN;
973 ses->ses_mlen = SHA1_HASH_LEN;
976 if (macini->cri_key != NULL) {
977 ubsec_setup_mackey(ses, macini->cri_alg,
978 macini->cri_key, macini->cri_klen / 8);
982 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
987 * Deallocate a session.
990 ubsec_freesession(device_t dev, u_int64_t tid)
992 struct ubsec_softc *sc = device_get_softc(dev);
994 u_int32_t sid = CRYPTO_SESID2LID(tid);
999 session = UBSEC_SESSION(sid);
1000 if (session < sc->sc_nsessions) {
1001 bzero(&sc->sc_sessions[session],
1002 sizeof(sc->sc_sessions[session]));
1011 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1013 struct ubsec_operand *op = arg;
1015 KASSERT(nsegs <= UBS_MAX_SCATTER,
1016 ("Too many DMA segments returned when mapping operand"));
1019 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1020 (u_int) mapsize, nsegs, error);
1024 op->mapsize = mapsize;
1026 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1030 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1032 struct ubsec_softc *sc = device_get_softc(dev);
1033 struct ubsec_q *q = NULL;
1034 int err = 0, i, j, nicealign;
1035 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1036 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1037 int sskip, dskip, stheend, dtheend;
1039 struct ubsec_session *ses;
1040 struct ubsec_pktctx ctx;
1041 struct ubsec_dma *dmap = NULL;
1043 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1044 ubsecstats.hst_invalid++;
1047 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1048 ubsecstats.hst_badsession++;
1052 mtx_lock(&sc->sc_freeqlock);
1053 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1054 ubsecstats.hst_queuefull++;
1055 sc->sc_needwakeup |= CRYPTO_SYMQ;
1056 mtx_unlock(&sc->sc_freeqlock);
1059 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1060 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1061 mtx_unlock(&sc->sc_freeqlock);
1063 dmap = q->q_dma; /* Save dma pointer */
1064 bzero(q, sizeof(struct ubsec_q));
1065 bzero(&ctx, sizeof(ctx));
1067 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1069 ses = &sc->sc_sessions[q->q_sesn];
1071 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1072 q->q_src_m = (struct mbuf *)crp->crp_buf;
1073 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1074 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1075 q->q_src_io = (struct uio *)crp->crp_buf;
1076 q->q_dst_io = (struct uio *)crp->crp_buf;
1078 ubsecstats.hst_badflags++;
1080 goto errout; /* XXX we don't handle contiguous blocks! */
1083 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1085 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1086 dmap->d_dma->d_mcr.mcr_flags = 0;
1089 crd1 = crp->crp_desc;
1091 ubsecstats.hst_nodesc++;
1095 crd2 = crd1->crd_next;
1098 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1099 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1102 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1103 crd1->crd_alg == CRYPTO_3DES_CBC) {
1107 ubsecstats.hst_badalg++;
1112 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1113 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1114 (crd2->crd_alg == CRYPTO_DES_CBC ||
1115 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1116 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1119 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1120 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1121 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1122 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1123 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1128 * We cannot order the ubsec as requested
1130 ubsecstats.hst_badalg++;
1137 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1138 ubsec_setup_enckey(ses, enccrd->crd_alg,
1142 encoffset = enccrd->crd_skip;
1143 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1145 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1146 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1148 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1149 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1151 ctx.pc_iv[0] = ses->ses_iv[0];
1152 ctx.pc_iv[1] = ses->ses_iv[1];
1155 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1156 crypto_copyback(crp->crp_flags, crp->crp_buf,
1157 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1160 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1162 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1163 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1165 crypto_copydata(crp->crp_flags, crp->crp_buf,
1166 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1170 ctx.pc_deskey[0] = ses->ses_deskey[0];
1171 ctx.pc_deskey[1] = ses->ses_deskey[1];
1172 ctx.pc_deskey[2] = ses->ses_deskey[2];
1173 ctx.pc_deskey[3] = ses->ses_deskey[3];
1174 ctx.pc_deskey[4] = ses->ses_deskey[4];
1175 ctx.pc_deskey[5] = ses->ses_deskey[5];
1176 SWAP32(ctx.pc_iv[0]);
1177 SWAP32(ctx.pc_iv[1]);
1181 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1182 ubsec_setup_mackey(ses, maccrd->crd_alg,
1183 maccrd->crd_key, maccrd->crd_klen / 8);
1186 macoffset = maccrd->crd_skip;
1188 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1189 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1191 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1193 for (i = 0; i < 5; i++) {
1194 ctx.pc_hminner[i] = ses->ses_hminner[i];
1195 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1197 HTOLE32(ctx.pc_hminner[i]);
1198 HTOLE32(ctx.pc_hmouter[i]);
1202 if (enccrd && maccrd) {
1204 * ubsec cannot handle packets where the end of encryption
1205 * and authentication are not the same, or where the
1206 * encrypted part begins before the authenticated part.
1208 if ((encoffset + enccrd->crd_len) !=
1209 (macoffset + maccrd->crd_len)) {
1210 ubsecstats.hst_lenmismatch++;
1214 if (enccrd->crd_skip < maccrd->crd_skip) {
1215 ubsecstats.hst_skipmismatch++;
1219 sskip = maccrd->crd_skip;
1220 cpskip = dskip = enccrd->crd_skip;
1221 stheend = maccrd->crd_len;
1222 dtheend = enccrd->crd_len;
1223 coffset = enccrd->crd_skip - maccrd->crd_skip;
1224 cpoffset = cpskip + dtheend;
1227 printf("mac: skip %d, len %d, inject %d\n",
1228 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1229 printf("enc: skip %d, len %d, inject %d\n",
1230 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1231 printf("src: skip %d, len %d\n", sskip, stheend);
1232 printf("dst: skip %d, len %d\n", dskip, dtheend);
1233 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1234 coffset, stheend, cpskip, cpoffset);
1238 cpskip = dskip = sskip = macoffset + encoffset;
1239 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1240 cpoffset = cpskip + dtheend;
1243 ctx.pc_offset = htole16(coffset >> 2);
1245 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1246 ubsecstats.hst_nomap++;
1250 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1251 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1252 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1253 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1254 q->q_src_map = NULL;
1255 ubsecstats.hst_noload++;
1259 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1260 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1261 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1262 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1263 q->q_src_map = NULL;
1264 ubsecstats.hst_noload++;
1269 nicealign = ubsec_dmamap_aligned(&q->q_src);
1271 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1275 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1277 for (i = j = 0; i < q->q_src_nsegs; i++) {
1278 struct ubsec_pktbuf *pb;
1279 bus_size_t packl = q->q_src_segs[i].ds_len;
1280 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1282 if (sskip >= packl) {
1291 if (packl > 0xfffc) {
1297 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1299 pb = &dmap->d_dma->d_sbuf[j - 1];
1301 pb->pb_addr = htole32(packp);
1304 if (packl > stheend) {
1305 pb->pb_len = htole32(stheend);
1308 pb->pb_len = htole32(packl);
1312 pb->pb_len = htole32(packl);
1314 if ((i + 1) == q->q_src_nsegs)
1317 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1318 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1322 if (enccrd == NULL && maccrd != NULL) {
1323 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1324 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1325 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1326 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1329 printf("opkt: %x %x %x\n",
1330 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1331 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1332 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1335 if (crp->crp_flags & CRYPTO_F_IOV) {
1337 ubsecstats.hst_iovmisaligned++;
1341 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1343 ubsecstats.hst_nomap++;
1347 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1348 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1349 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1350 q->q_dst_map = NULL;
1351 ubsecstats.hst_noload++;
1355 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1357 q->q_dst = q->q_src;
1360 struct mbuf *m, *top, **mp;
1362 ubsecstats.hst_unaligned++;
1363 totlen = q->q_src_mapsize;
1364 if (totlen >= MINCLSIZE) {
1365 m = m_getcl(M_NOWAIT, MT_DATA,
1366 q->q_src_m->m_flags & M_PKTHDR);
1368 } else if (q->q_src_m->m_flags & M_PKTHDR) {
1369 m = m_gethdr(M_NOWAIT, MT_DATA);
1372 m = m_get(M_NOWAIT, MT_DATA);
1375 if (m && q->q_src_m->m_flags & M_PKTHDR &&
1376 !m_dup_pkthdr(m, q->q_src_m, M_NOWAIT)) {
1381 ubsecstats.hst_nombuf++;
1382 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1385 m->m_len = len = min(totlen, len);
1390 while (totlen > 0) {
1391 if (totlen >= MINCLSIZE) {
1392 m = m_getcl(M_NOWAIT,
1396 m = m_get(M_NOWAIT, MT_DATA);
1401 ubsecstats.hst_nombuf++;
1402 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1405 m->m_len = len = min(totlen, len);
1411 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1413 if (bus_dmamap_create(sc->sc_dmat,
1414 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1415 ubsecstats.hst_nomap++;
1419 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1420 q->q_dst_map, q->q_dst_m,
1421 ubsec_op_cb, &q->q_dst,
1422 BUS_DMA_NOWAIT) != 0) {
1423 bus_dmamap_destroy(sc->sc_dmat,
1425 q->q_dst_map = NULL;
1426 ubsecstats.hst_noload++;
1432 ubsecstats.hst_badflags++;
1439 printf("dst skip: %d\n", dskip);
1441 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1442 struct ubsec_pktbuf *pb;
1443 bus_size_t packl = q->q_dst_segs[i].ds_len;
1444 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1446 if (dskip >= packl) {
1455 if (packl > 0xfffc) {
1461 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1463 pb = &dmap->d_dma->d_dbuf[j - 1];
1465 pb->pb_addr = htole32(packp);
1468 if (packl > dtheend) {
1469 pb->pb_len = htole32(dtheend);
1472 pb->pb_len = htole32(packl);
1476 pb->pb_len = htole32(packl);
1478 if ((i + 1) == q->q_dst_nsegs) {
1480 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1481 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1485 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1486 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1491 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1492 offsetof(struct ubsec_dmachunk, d_ctx));
1494 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1495 struct ubsec_pktctx_long *ctxl;
1497 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1498 offsetof(struct ubsec_dmachunk, d_ctx));
1500 /* transform small context into long context */
1501 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1502 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1503 ctxl->pc_flags = ctx.pc_flags;
1504 ctxl->pc_offset = ctx.pc_offset;
1505 for (i = 0; i < 6; i++)
1506 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1507 for (i = 0; i < 5; i++)
1508 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1509 for (i = 0; i < 5; i++)
1510 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1511 ctxl->pc_iv[0] = ctx.pc_iv[0];
1512 ctxl->pc_iv[1] = ctx.pc_iv[1];
1514 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1515 offsetof(struct ubsec_dmachunk, d_ctx),
1516 sizeof(struct ubsec_pktctx));
1518 mtx_lock(&sc->sc_mcr1lock);
1519 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1521 ubsecstats.hst_ipackets++;
1522 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1523 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1525 mtx_unlock(&sc->sc_mcr1lock);
1530 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1531 m_freem(q->q_dst_m);
1533 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1534 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1535 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1537 if (q->q_src_map != NULL) {
1538 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1539 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1542 if (q != NULL || err == ERESTART) {
1543 mtx_lock(&sc->sc_freeqlock);
1545 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1546 if (err == ERESTART)
1547 sc->sc_needwakeup |= CRYPTO_SYMQ;
1548 mtx_unlock(&sc->sc_freeqlock);
1550 if (err != ERESTART) {
1551 crp->crp_etype = err;
1558 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1560 struct cryptop *crp = (struct cryptop *)q->q_crp;
1561 struct cryptodesc *crd;
1562 struct ubsec_dma *dmap = q->q_dma;
1564 ubsecstats.hst_opackets++;
1565 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1567 ubsec_dma_sync(&dmap->d_alloc,
1568 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1569 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1570 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1571 BUS_DMASYNC_POSTREAD);
1572 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1573 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1575 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1576 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1577 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1579 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1580 m_freem(q->q_src_m);
1581 crp->crp_buf = (caddr_t)q->q_dst_m;
1584 /* copy out IV for future use */
1585 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1586 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1587 if (crd->crd_alg != CRYPTO_DES_CBC &&
1588 crd->crd_alg != CRYPTO_3DES_CBC)
1590 crypto_copydata(crp->crp_flags, crp->crp_buf,
1591 crd->crd_skip + crd->crd_len - 8, 8,
1592 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1597 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1598 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1599 crd->crd_alg != CRYPTO_SHA1_HMAC)
1601 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1602 sc->sc_sessions[q->q_sesn].ses_mlen,
1603 (caddr_t)dmap->d_dma->d_macbuf);
1606 mtx_lock(&sc->sc_freeqlock);
1607 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1608 mtx_unlock(&sc->sc_freeqlock);
1613 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1615 int i, j, dlen, slen;
1619 sptr = srcm->m_data;
1621 dptr = dstm->m_data;
1625 for (i = 0; i < min(slen, dlen); i++) {
1626 if (j < hoffset || j >= toffset)
1633 srcm = srcm->m_next;
1636 sptr = srcm->m_data;
1640 dstm = dstm->m_next;
1643 dptr = dstm->m_data;
1650 * feed the key generator, must be called at splimp() or higher.
1653 ubsec_feed2(struct ubsec_softc *sc)
1657 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1658 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1660 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1662 ubsec_dma_sync(&q->q_mcr,
1663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1664 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1666 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1667 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1669 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1675 * Callback for handling random numbers
1678 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1680 struct cryptkop *krp;
1681 struct ubsec_ctx_keyop *ctx;
1683 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1684 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1686 switch (q->q_type) {
1687 #ifndef UBSEC_NO_RNG
1688 case UBS_CTXOP_RNGBYPASS: {
1689 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1691 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1692 (*sc->sc_harvest)(sc->sc_rndtest,
1693 rng->rng_buf.dma_vaddr,
1694 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1696 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1700 case UBS_CTXOP_MODEXP: {
1701 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1705 rlen = (me->me_modbits + 7) / 8;
1706 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1708 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1709 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1710 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1711 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1714 krp->krp_status = E2BIG;
1716 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1717 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1718 (krp->krp_param[krp->krp_iparams].crp_nbits
1720 bcopy(me->me_C.dma_vaddr,
1721 krp->krp_param[krp->krp_iparams].crp_p,
1722 (me->me_modbits + 7) / 8);
1724 ubsec_kshift_l(me->me_shiftbits,
1725 me->me_C.dma_vaddr, me->me_normbits,
1726 krp->krp_param[krp->krp_iparams].crp_p,
1727 krp->krp_param[krp->krp_iparams].crp_nbits);
1732 /* bzero all potentially sensitive data */
1733 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1734 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1735 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1736 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1738 /* Can't free here, so put us on the free list. */
1739 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1742 case UBS_CTXOP_RSAPRIV: {
1743 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1747 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1748 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1750 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1751 bcopy(rp->rpr_msgout.dma_vaddr,
1752 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1756 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1757 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1758 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1760 /* Can't free here, so put us on the free list. */
1761 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1765 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1766 letoh16(ctx->ctx_op));
1771 #ifndef UBSEC_NO_RNG
1773 ubsec_rng(void *vsc)
1775 struct ubsec_softc *sc = vsc;
1776 struct ubsec_q2_rng *rng = &sc->sc_rng;
1777 struct ubsec_mcr *mcr;
1778 struct ubsec_ctx_rngbypass *ctx;
1780 mtx_lock(&sc->sc_mcr2lock);
1781 if (rng->rng_used) {
1782 mtx_unlock(&sc->sc_mcr2lock);
1786 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1790 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1792 mcr->mcr_pkts = htole16(1);
1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1795 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1796 mcr->mcr_ipktbuf.pb_len = 0;
1797 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1798 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1799 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1801 mcr->mcr_opktbuf.pb_next = 0;
1803 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1804 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1805 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1807 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1809 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1812 ubsecstats.hst_rng++;
1813 mtx_unlock(&sc->sc_mcr2lock);
1819 * Something weird happened, generate our own call back.
1822 mtx_unlock(&sc->sc_mcr2lock);
1823 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1825 #endif /* UBSEC_NO_RNG */
1828 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1830 bus_addr_t *paddr = (bus_addr_t*) arg;
1831 *paddr = segs->ds_addr;
1836 struct ubsec_softc *sc,
1838 struct ubsec_dma_alloc *dma,
1844 /* XXX could specify sc_dmat as parent but that just adds overhead */
1845 r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1846 1, 0, /* alignment, bounds */
1847 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1848 BUS_SPACE_MAXADDR, /* highaddr */
1849 NULL, NULL, /* filter, filterarg */
1852 size, /* maxsegsize */
1853 BUS_DMA_ALLOCNOW, /* flags */
1854 NULL, NULL, /* lockfunc, lockarg */
1857 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1858 "bus_dma_tag_create failed; error %u\n", r);
1862 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1864 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1865 "bus_dmamap_create failed; error %u\n", r);
1869 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1870 BUS_DMA_NOWAIT, &dma->dma_map);
1872 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1873 "bus_dmammem_alloc failed; size %ju, error %u\n",
1878 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1882 mapflags | BUS_DMA_NOWAIT);
1884 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1885 "bus_dmamap_load failed; error %u\n", r);
1889 dma->dma_size = size;
1893 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1895 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1897 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1898 bus_dma_tag_destroy(dma->dma_tag);
1900 dma->dma_map = NULL;
1901 dma->dma_tag = NULL;
1906 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1908 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1909 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1910 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1911 bus_dma_tag_destroy(dma->dma_tag);
1915 * Resets the board. Values in the regesters are left as is
1916 * from the reset (i.e. initial values are assigned elsewhere).
1919 ubsec_reset_board(struct ubsec_softc *sc)
1921 volatile u_int32_t ctrl;
1923 ctrl = READ_REG(sc, BS_CTRL);
1924 ctrl |= BS_CTRL_RESET;
1925 WRITE_REG(sc, BS_CTRL, ctrl);
1928 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1934 * Init Broadcom registers
1937 ubsec_init_board(struct ubsec_softc *sc)
1941 ctrl = READ_REG(sc, BS_CTRL);
1942 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1943 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1945 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1946 ctrl |= BS_CTRL_MCR2INT;
1948 ctrl &= ~BS_CTRL_MCR2INT;
1950 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1951 ctrl &= ~BS_CTRL_SWNORM;
1953 WRITE_REG(sc, BS_CTRL, ctrl);
1957 * Init Broadcom PCI registers
1960 ubsec_init_pciregs(device_t dev)
1965 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1966 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1967 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1968 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1969 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1970 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1974 * This will set the cache line size to 1, this will
1975 * force the BCM58xx chip just to do burst read/writes.
1976 * Cache line read/writes are to slow
1978 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1982 * Clean up after a chip crash.
1983 * It is assumed that the caller in splimp()
1986 ubsec_cleanchip(struct ubsec_softc *sc)
1990 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1991 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1992 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
1993 ubsec_free_q(sc, q);
2000 * It is assumed that the caller is within splimp().
2003 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2006 struct cryptop *crp;
2010 npkts = q->q_nstacked_mcrs;
2012 for (i = 0; i < npkts; i++) {
2013 if(q->q_stacked_mcr[i]) {
2014 q2 = q->q_stacked_mcr[i];
2016 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2017 m_freem(q2->q_dst_m);
2019 crp = (struct cryptop *)q2->q_crp;
2021 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2023 crp->crp_etype = EFAULT;
2033 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2034 m_freem(q->q_dst_m);
2036 crp = (struct cryptop *)q->q_crp;
2038 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2040 crp->crp_etype = EFAULT;
2046 * Routine to reset the chip and clean up.
2047 * It is assumed that the caller is in splimp()
2050 ubsec_totalreset(struct ubsec_softc *sc)
2052 ubsec_reset_board(sc);
2053 ubsec_init_board(sc);
2054 ubsec_cleanchip(sc);
2058 ubsec_dmamap_aligned(struct ubsec_operand *op)
2062 for (i = 0; i < op->nsegs; i++) {
2063 if (op->segs[i].ds_addr & 3)
2065 if ((i != (op->nsegs - 1)) &&
2066 (op->segs[i].ds_len & 3))
2073 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2075 switch (q->q_type) {
2076 case UBS_CTXOP_MODEXP: {
2077 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2079 ubsec_dma_free(sc, &me->me_q.q_mcr);
2080 ubsec_dma_free(sc, &me->me_q.q_ctx);
2081 ubsec_dma_free(sc, &me->me_M);
2082 ubsec_dma_free(sc, &me->me_E);
2083 ubsec_dma_free(sc, &me->me_C);
2084 ubsec_dma_free(sc, &me->me_epb);
2088 case UBS_CTXOP_RSAPRIV: {
2089 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2091 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2092 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2093 ubsec_dma_free(sc, &rp->rpr_msgin);
2094 ubsec_dma_free(sc, &rp->rpr_msgout);
2099 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2105 ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint)
2107 struct ubsec_softc *sc = device_get_softc(dev);
2110 if (krp == NULL || krp->krp_callback == NULL)
2113 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2116 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2117 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2121 switch (krp->krp_op) {
2123 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2124 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2126 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2128 case CRK_MOD_EXP_CRT:
2129 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2131 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2133 krp->krp_status = EOPNOTSUPP;
2137 return (0); /* silence compiler */
2141 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2144 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2146 struct ubsec_q2_modexp *me;
2147 struct ubsec_mcr *mcr;
2148 struct ubsec_ctx_modexp *ctx;
2149 struct ubsec_pktbuf *epb;
2151 u_int nbits, normbits, mbits, shiftbits, ebits;
2153 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2158 bzero(me, sizeof *me);
2160 me->me_q.q_type = UBS_CTXOP_MODEXP;
2162 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2165 else if (nbits <= 768)
2167 else if (nbits <= 1024)
2169 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2171 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2178 shiftbits = normbits - nbits;
2180 me->me_modbits = nbits;
2181 me->me_shiftbits = shiftbits;
2182 me->me_normbits = normbits;
2184 /* Sanity check: result bits must be >= true modulus bits. */
2185 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2190 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2191 &me->me_q.q_mcr, 0)) {
2195 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2197 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2198 &me->me_q.q_ctx, 0)) {
2203 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2204 if (mbits > nbits) {
2208 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2212 ubsec_kshift_r(shiftbits,
2213 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2214 me->me_M.dma_vaddr, normbits);
2216 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2220 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2222 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2223 if (ebits > nbits) {
2227 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2231 ubsec_kshift_r(shiftbits,
2232 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2233 me->me_E.dma_vaddr, normbits);
2235 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2240 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2241 epb->pb_addr = htole32(me->me_E.dma_paddr);
2243 epb->pb_len = htole32(normbits / 8);
2252 mcr->mcr_pkts = htole16(1);
2254 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2255 mcr->mcr_reserved = 0;
2256 mcr->mcr_pktlen = 0;
2258 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2259 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2260 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2262 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2263 mcr->mcr_opktbuf.pb_next = 0;
2264 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2267 /* Misaligned output buffer will hang the chip. */
2268 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2269 panic("%s: modexp invalid addr 0x%x\n",
2270 device_get_nameunit(sc->sc_dev),
2271 letoh32(mcr->mcr_opktbuf.pb_addr));
2272 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2273 panic("%s: modexp invalid len 0x%x\n",
2274 device_get_nameunit(sc->sc_dev),
2275 letoh32(mcr->mcr_opktbuf.pb_len));
2278 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2279 bzero(ctx, sizeof(*ctx));
2280 ubsec_kshift_r(shiftbits,
2281 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2282 ctx->me_N, normbits);
2283 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2284 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2285 ctx->me_E_len = htole16(nbits);
2286 ctx->me_N_len = htole16(nbits);
2290 ubsec_dump_mcr(mcr);
2291 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2296 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2299 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2300 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2301 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2302 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2304 /* Enqueue and we're done... */
2305 mtx_lock(&sc->sc_mcr2lock);
2306 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2308 ubsecstats.hst_modexp++;
2309 mtx_unlock(&sc->sc_mcr2lock);
2315 if (me->me_q.q_mcr.dma_map != NULL)
2316 ubsec_dma_free(sc, &me->me_q.q_mcr);
2317 if (me->me_q.q_ctx.dma_map != NULL) {
2318 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2319 ubsec_dma_free(sc, &me->me_q.q_ctx);
2321 if (me->me_M.dma_map != NULL) {
2322 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2323 ubsec_dma_free(sc, &me->me_M);
2325 if (me->me_E.dma_map != NULL) {
2326 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2327 ubsec_dma_free(sc, &me->me_E);
2329 if (me->me_C.dma_map != NULL) {
2330 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2331 ubsec_dma_free(sc, &me->me_C);
2333 if (me->me_epb.dma_map != NULL)
2334 ubsec_dma_free(sc, &me->me_epb);
2337 krp->krp_status = err;
2343 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2346 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2348 struct ubsec_q2_modexp *me;
2349 struct ubsec_mcr *mcr;
2350 struct ubsec_ctx_modexp *ctx;
2351 struct ubsec_pktbuf *epb;
2353 u_int nbits, normbits, mbits, shiftbits, ebits;
2355 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2360 bzero(me, sizeof *me);
2362 me->me_q.q_type = UBS_CTXOP_MODEXP;
2364 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2367 else if (nbits <= 768)
2369 else if (nbits <= 1024)
2371 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2373 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2380 shiftbits = normbits - nbits;
2383 me->me_modbits = nbits;
2384 me->me_shiftbits = shiftbits;
2385 me->me_normbits = normbits;
2387 /* Sanity check: result bits must be >= true modulus bits. */
2388 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2393 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2394 &me->me_q.q_mcr, 0)) {
2398 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2400 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2401 &me->me_q.q_ctx, 0)) {
2406 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2407 if (mbits > nbits) {
2411 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2415 bzero(me->me_M.dma_vaddr, normbits / 8);
2416 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2417 me->me_M.dma_vaddr, (mbits + 7) / 8);
2419 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2423 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2425 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2426 if (ebits > nbits) {
2430 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2434 bzero(me->me_E.dma_vaddr, normbits / 8);
2435 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2436 me->me_E.dma_vaddr, (ebits + 7) / 8);
2438 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2443 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2444 epb->pb_addr = htole32(me->me_E.dma_paddr);
2446 epb->pb_len = htole32((ebits + 7) / 8);
2455 mcr->mcr_pkts = htole16(1);
2457 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2458 mcr->mcr_reserved = 0;
2459 mcr->mcr_pktlen = 0;
2461 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2462 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2463 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2465 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2466 mcr->mcr_opktbuf.pb_next = 0;
2467 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2470 /* Misaligned output buffer will hang the chip. */
2471 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2472 panic("%s: modexp invalid addr 0x%x\n",
2473 device_get_nameunit(sc->sc_dev),
2474 letoh32(mcr->mcr_opktbuf.pb_addr));
2475 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2476 panic("%s: modexp invalid len 0x%x\n",
2477 device_get_nameunit(sc->sc_dev),
2478 letoh32(mcr->mcr_opktbuf.pb_len));
2481 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2482 bzero(ctx, sizeof(*ctx));
2483 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2485 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2486 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2487 ctx->me_E_len = htole16(ebits);
2488 ctx->me_N_len = htole16(nbits);
2492 ubsec_dump_mcr(mcr);
2493 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2498 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2501 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2502 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2503 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2504 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2506 /* Enqueue and we're done... */
2507 mtx_lock(&sc->sc_mcr2lock);
2508 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2510 mtx_unlock(&sc->sc_mcr2lock);
2516 if (me->me_q.q_mcr.dma_map != NULL)
2517 ubsec_dma_free(sc, &me->me_q.q_mcr);
2518 if (me->me_q.q_ctx.dma_map != NULL) {
2519 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2520 ubsec_dma_free(sc, &me->me_q.q_ctx);
2522 if (me->me_M.dma_map != NULL) {
2523 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2524 ubsec_dma_free(sc, &me->me_M);
2526 if (me->me_E.dma_map != NULL) {
2527 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2528 ubsec_dma_free(sc, &me->me_E);
2530 if (me->me_C.dma_map != NULL) {
2531 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2532 ubsec_dma_free(sc, &me->me_C);
2534 if (me->me_epb.dma_map != NULL)
2535 ubsec_dma_free(sc, &me->me_epb);
2538 krp->krp_status = err;
2544 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2546 struct ubsec_q2_rsapriv *rp = NULL;
2547 struct ubsec_mcr *mcr;
2548 struct ubsec_ctx_rsapriv *ctx;
2550 u_int padlen, msglen;
2552 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2553 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2554 if (msglen > padlen)
2559 else if (padlen <= 384)
2561 else if (padlen <= 512)
2563 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2565 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2572 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2577 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2582 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2587 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2590 bzero(rp, sizeof *rp);
2592 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2594 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2595 &rp->rpr_q.q_mcr, 0)) {
2599 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2601 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2602 &rp->rpr_q.q_ctx, 0)) {
2606 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2607 bzero(ctx, sizeof *ctx);
2610 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2611 &ctx->rpr_buf[0 * (padlen / 8)],
2612 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2615 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2616 &ctx->rpr_buf[1 * (padlen / 8)],
2617 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2620 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2621 &ctx->rpr_buf[2 * (padlen / 8)],
2622 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2625 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2626 &ctx->rpr_buf[3 * (padlen / 8)],
2627 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2630 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2631 &ctx->rpr_buf[4 * (padlen / 8)],
2632 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2634 msglen = padlen * 2;
2636 /* Copy in input message (aligned buffer/length). */
2637 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2638 /* Is this likely? */
2642 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2646 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2647 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2648 rp->rpr_msgin.dma_vaddr,
2649 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2651 /* Prepare space for output message (aligned buffer/length). */
2652 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2653 /* Is this likely? */
2657 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2661 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2663 mcr->mcr_pkts = htole16(1);
2665 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2666 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2667 mcr->mcr_ipktbuf.pb_next = 0;
2668 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2669 mcr->mcr_reserved = 0;
2670 mcr->mcr_pktlen = htole16(msglen);
2671 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2672 mcr->mcr_opktbuf.pb_next = 0;
2673 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2676 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2677 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2678 device_get_nameunit(sc->sc_dev),
2679 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2681 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2682 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2683 device_get_nameunit(sc->sc_dev),
2684 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2688 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2689 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2690 ctx->rpr_q_len = htole16(padlen);
2691 ctx->rpr_p_len = htole16(padlen);
2694 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2697 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2698 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2700 /* Enqueue and we're done... */
2701 mtx_lock(&sc->sc_mcr2lock);
2702 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2704 ubsecstats.hst_modexpcrt++;
2705 mtx_unlock(&sc->sc_mcr2lock);
2710 if (rp->rpr_q.q_mcr.dma_map != NULL)
2711 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2712 if (rp->rpr_msgin.dma_map != NULL) {
2713 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2714 ubsec_dma_free(sc, &rp->rpr_msgin);
2716 if (rp->rpr_msgout.dma_map != NULL) {
2717 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2718 ubsec_dma_free(sc, &rp->rpr_msgout);
2722 krp->krp_status = err;
2729 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2731 printf("addr 0x%x (0x%x) next 0x%x\n",
2732 pb->pb_addr, pb->pb_len, pb->pb_next);
2736 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2738 printf("CTX (0x%x):\n", c->ctx_len);
2739 switch (letoh16(c->ctx_op)) {
2740 case UBS_CTXOP_RNGBYPASS:
2741 case UBS_CTXOP_RNGSHA1:
2743 case UBS_CTXOP_MODEXP:
2745 struct ubsec_ctx_modexp *cx = (void *)c;
2748 printf(" Elen %u, Nlen %u\n",
2749 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2750 len = (cx->me_N_len + 7)/8;
2751 for (i = 0; i < len; i++)
2752 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2757 printf("unknown context: %x\n", c->ctx_op);
2759 printf("END CTX\n");
2763 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2765 volatile struct ubsec_mcr_add *ma;
2769 printf(" pkts: %u, flags 0x%x\n",
2770 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2771 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2772 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2773 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2774 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2775 letoh16(ma->mcr_reserved));
2776 printf(" %d: ipkt ", i);
2777 ubsec_dump_pb(&ma->mcr_ipktbuf);
2778 printf(" %d: opkt ", i);
2779 ubsec_dump_pb(&ma->mcr_opktbuf);
2782 printf("END MCR\n");
2784 #endif /* UBSEC_DEBUG */
2787 * Return the number of significant bits of a big number.
2790 ubsec_ksigbits(struct crparam *cr)
2792 u_int plen = (cr->crp_nbits + 7) / 8;
2793 int i, sig = plen * 8;
2794 u_int8_t c, *p = cr->crp_p;
2796 for (i = plen - 1; i >= 0; i--) {
2799 while ((c & 0x80) == 0) {
2813 u_int8_t *src, u_int srcbits,
2814 u_int8_t *dst, u_int dstbits)
2819 slen = (srcbits + 7) / 8;
2820 dlen = (dstbits + 7) / 8;
2822 for (i = 0; i < slen; i++)
2824 for (i = 0; i < dlen - slen; i++)
2832 dst[di--] = dst[si--];
2839 for (i = dlen - 1; i > 0; i--)
2840 dst[i] = (dst[i] << n) |
2841 (dst[i - 1] >> (8 - n));
2842 dst[0] = dst[0] << n;
2849 u_int8_t *src, u_int srcbits,
2850 u_int8_t *dst, u_int dstbits)
2852 int slen, dlen, i, n;
2854 slen = (srcbits + 7) / 8;
2855 dlen = (dstbits + 7) / 8;
2858 for (i = 0; i < slen; i++)
2859 dst[i] = src[i + n];
2860 for (i = 0; i < dlen - slen; i++)
2865 for (i = 0; i < (dlen - 1); i++)
2866 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2867 dst[dlen - 1] = dst[dlen - 1] >> n;