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33 #ifndef VXGE_HAL_RING_H
34 #define VXGE_HAL_RING_H
38 typedef u8 vxge_hal_ring_block_t[VXGE_OS_HOST_PAGE_SIZE];
40 #define VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_OS_HOST_PAGE_SIZE-8)
41 #define VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET (VXGE_OS_HOST_PAGE_SIZE-16)
44 * struct __hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
45 * @dma_addr: DMA (mapped) address of _this_ descriptor.
46 * @dma_handle: DMA handle used to map the descriptor onto device.
47 * @dma_offset: Descriptor's offset in the memory block. HAL allocates
48 * descriptors in memory blocks of %VXGE_OS_HOST_PAGE_SIZE
49 * bytes. Each memblock is contiguous DMA-able memory. Each
50 * memblock contains 1 or more 4KB RxD blocks visible to the
52 * @dma_object: DMA address and handle of the memory block that contains
53 * the descriptor. This member is used only in the "checked"
54 * version of the HAL (to enforce certain assertions);
55 * otherwise it gets compiled out.
56 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
57 * @db_bytes: Number of doorbell bytes to be posted for this Rxd. This includes
58 * next RxD block pointers
60 * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
61 * information associated with the descriptor. Note that ULD can ask HAL
62 * to allocate additional per-descriptor space for its own (ULD-specific)
65 typedef struct __hal_ring_rxd_priv_t {
69 #if defined(VXGE_DEBUG_ASSERT)
70 vxge_hal_mempool_dma_t *dma_object;
72 #if defined(VXGE_OS_MEMORY_CHECK)
76 } __hal_ring_rxd_priv_t;
80 * struct __hal_ring_t - Ring channel.
81 * @channel: Channel "base" of this ring, the common part of all HAL
83 * @mempool: Memory pool, the pool from which descriptors get allocated.
84 * (See vxge_hal_mm.h).
85 * @config: Ring configuration, part of device configuration
86 * (see vxge_hal_device_config_t {}).
87 * @ring_length: Length of the ring
88 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
89 * as per X3100 User Guide.
90 * @indicate_max_pkts: Maximum number of packets processed within a single
91 * interrupt. Can be used to limit the time spent inside hw interrupt.
92 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per X3100 spec,
93 * 1-buffer mode descriptor is 32 byte long, etc.
94 * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
95 * data (e.g., DMA handle for Solaris)
96 * @per_rxd_space: Per rxd space requested by ULD
97 * @rxds_per_block: Number of descriptors per hardware-defined RxD
98 * block. Depends on the (1-, 3-, 5-) buffer mode.
99 * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
100 * usage. Not to confuse with @rxd_priv_size.
101 * @rxd_mem_avail: Available RxD memory
102 * @db_byte_count: Number of doorbell bytes to be posted
103 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
104 * Used in conjunction with @indicate_max_pkts.
105 * @active_sw_lros: List of Software LRO sessions in progess
106 * @active_sw_lro_count: Number of Software LRO sessions in progess
107 * @free_sw_lros: List of Software LRO sessions free
108 * @free_sw_lro_count: Number of Software LRO sessions free
109 * @sw_lro_lock: LRO session lists' lock
110 * @callback: Channel completion callback. HAL invokes the callback when there
111 * are new completions on that channel. In many implementations
112 * the @callback executes in the hw interrupt context.
113 * @rxd_init: Channel's descriptor-initialize callback.
114 * See vxge_hal_ring_rxd_init_f {}.
115 * If not NULL, HAL invokes the callback when opening the ring.
116 * @rxd_term: Channel's descriptor-terminate callback. If not NULL,
117 * HAL invokes the callback when closing the corresponding channel.
118 * See also vxge_hal_channel_rxd_term_f {}.
119 * @stats: Statistics for ring
122 * Note: The structure is cache line aligned to better utilize
123 * CPU cache performance.
125 typedef struct __hal_ring_t {
126 __hal_channel_t channel;
127 vxge_hal_mempool_t *mempool;
128 vxge_hal_ring_config_t *config;
131 u32 indicate_max_pkts;
136 u32 rxdblock_priv_size;
140 vxge_hal_ring_callback_f callback;
141 vxge_hal_ring_rxd_init_f rxd_init;
142 vxge_hal_ring_rxd_term_f rxd_term;
143 vxge_hal_vpath_stats_sw_ring_info_t *stats;
144 } __vxge_os_attr_cacheline_aligned __hal_ring_t;
146 #define VXGE_HAL_RING_ULD_PRIV(ring, rxdh) \
147 ring->channel.dtr_arr[ \
148 ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].uld_priv
150 #define VXGE_HAL_RING_HAL_PRIV(ring, rxdh) \
151 ((__hal_ring_rxd_priv_t *)(ring->channel.dtr_arr[ \
152 ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].hal_priv))
154 #define VXGE_HAL_RING_POST_DOORBELL(vph, ringh) \
156 if (((__hal_ring_t *)(ringh))->config->post_mode == \
157 VXGE_HAL_RING_POST_MODE_DOORBELL) { \
158 vxge_hal_ring_rxd_post_post_db(vph); \
162 #define VXGE_HAL_RING_RXD_INDEX(rxdp) \
163 (u32)((vxge_hal_ring_rxd_5_t *)rxdp)->host_control
165 /* ========================== RING PRIVATE API ============================ */
168 __hal_ring_first_block_address_get(
169 vxge_hal_ring_h ringh);
173 vxge_hal_vpath_h vpath_handle,
174 vxge_hal_ring_attr_t *attr);
178 vxge_hal_ring_h ringh,
179 vxge_hal_reopen_e reopen);
183 vxge_hal_ring_h ringh);
187 vxge_hal_vpath_h vpath_handle);
190 vxge_hal_ring_initial_replenish(
192 vxge_hal_reopen_e reopen);
195 __hal_ring_frame_length_set(
196 __hal_virtualpath_t *vpath,
201 #endif /* VXGE_HAL_RING_H */