2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
51 #include <sys/sysctl.h>
52 #include <machine/bus.h>
55 #include <sys/syslog.h>
57 #include <sys/signalvar.h>
60 #include <machine/asmacros.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/md_var.h>
64 #include <machine/pcb.h>
65 #include <machine/psl.h>
66 #include <machine/resource.h>
67 #include <machine/specialreg.h>
68 #include <machine/segments.h>
69 #include <machine/ucontext.h>
71 #include <machine/intr_machdep.h>
73 #include <xen/xen-os.h>
74 #include <xen/hypervisor.h>
78 #include <isa/isavar.h>
81 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
82 #define CPU_ENABLE_SSE
86 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
89 #if defined(__GNUCLIKE_ASM) && !defined(lint)
91 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
92 #define fnclex() __asm __volatile("fnclex")
93 #define fninit() __asm __volatile("fninit")
94 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
95 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
96 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
97 #define fp_divide_by_0() __asm __volatile( \
98 "fldz; fld1; fdiv %st,%st(1); fnop")
99 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr)))
100 #ifdef CPU_ENABLE_SSE
101 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
102 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
103 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
104 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
107 xrstor(char *addr, uint64_t mask)
113 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
117 xsave(char *addr, uint64_t mask)
123 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
128 xsaveopt(char *addr, uint64_t mask)
134 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
138 #else /* !(__GNUCLIKE_ASM && !lint) */
140 void fldcw(u_short cw);
143 void fnsave(caddr_t addr);
144 void fnstcw(caddr_t addr);
145 void fnstsw(caddr_t addr);
146 void fp_divide_by_0(void);
147 void frstor(caddr_t addr);
148 #ifdef CPU_ENABLE_SSE
149 void fxsave(caddr_t addr);
150 void fxrstor(caddr_t addr);
151 void ldmxcsr(u_int csr);
152 void stmxcsr(u_int *csr);
153 void xrstor(char *addr, uint64_t mask);
154 void xsave(char *addr, uint64_t mask);
155 void xsaveopt(char *addr, uint64_t mask);
158 #endif /* __GNUCLIKE_ASM && !lint */
161 #define start_emulating() (HYPERVISOR_fpu_taskswitch(1))
162 #define stop_emulating() (HYPERVISOR_fpu_taskswitch(0))
164 #define start_emulating() load_cr0(rcr0() | CR0_TS)
165 #define stop_emulating() clts()
168 #ifdef CPU_ENABLE_SSE
169 #define GET_FPU_CW(thread) \
171 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
172 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
173 #define GET_FPU_SW(thread) \
175 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
176 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
177 #define SET_FPU_CW(savefpu, value) do { \
179 (savefpu)->sv_xmm.sv_env.en_cw = (value); \
181 (savefpu)->sv_87.sv_env.en_cw = (value); \
183 #else /* CPU_ENABLE_SSE */
184 #define GET_FPU_CW(thread) \
185 (thread->td_pcb->pcb_save->sv_87.sv_env.en_cw)
186 #define GET_FPU_SW(thread) \
187 (thread->td_pcb->pcb_save->sv_87.sv_env.en_sw)
188 #define SET_FPU_CW(savefpu, value) \
189 (savefpu)->sv_87.sv_env.en_cw = (value)
190 #endif /* CPU_ENABLE_SSE */
192 #ifdef CPU_ENABLE_SSE
193 CTASSERT(sizeof(union savefpu) == 512);
194 CTASSERT(sizeof(struct xstate_hdr) == 64);
195 CTASSERT(sizeof(struct savefpu_ymm) == 832);
198 * This requirement is to make it easier for asm code to calculate
199 * offset of the fpu save area from the pcb address. FPU save area
200 * must be 64-byte aligned.
202 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
205 * Ensure the copy of XCR0 saved in a core is contained in the padding
208 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) &&
209 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm));
211 static void fpu_clean_state(void);
214 static void fpusave(union savefpu *);
215 static void fpurstor(union savefpu *);
219 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
220 &hw_float, 0, "Floating point instructions executed in hardware");
222 #ifdef CPU_ENABLE_SSE
226 static uma_zone_t fpu_save_area_zone;
227 static union savefpu *npx_initialstate;
229 #ifdef CPU_ENABLE_SSE
230 struct xsave_area_elm_descr {
235 static int use_xsaveopt;
238 static volatile u_int npx_traps_while_probing;
240 alias_for_inthand_t probetrap;
244 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
245 " __XSTRING(CNAME(probetrap)) ": \n\
247 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
253 * Determine if an FPU is present and how to use it.
258 struct gate_descriptor save_idt_npxtrap;
259 u_short control, status;
262 * Modern CPUs all have an FPU that uses the INT16 interface
263 * and provide a simple way to verify that, so handle the
264 * common case right away.
266 if (cpu_feature & CPUID_FPU) {
271 save_idt_npxtrap = idt[IDT_MF];
272 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
273 GSEL(GCODE_SEL, SEL_KPL));
276 * Don't trap while we're probing.
281 * Finish resetting the coprocessor, if any. If there is an error
282 * pending, then we may get a bogus IRQ13, but npx_intr() will handle
283 * it OK. Bogus halts have never been observed, but we enabled
284 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
289 * Don't use fwait here because it might hang.
290 * Don't use fnop here because it usually hangs if there is no FPU.
292 DELAY(1000); /* wait for any IRQ13 */
294 if (npx_traps_while_probing != 0)
295 printf("fninit caused %u bogus npx trap(s)\n",
296 npx_traps_while_probing);
299 * Check for a status of mostly zero.
303 if ((status & 0xb8ff) == 0) {
305 * Good, now check for a proper control word.
309 if ((control & 0x1f3f) == 0x033f) {
311 * We have an npx, now divide by 0 to see if exception
314 control &= ~(1 << 2); /* enable divide by 0 trap */
316 #ifdef FPU_ERROR_BROKEN
318 * FPU error signal doesn't work on some CPU
324 npx_traps_while_probing = 0;
326 if (npx_traps_while_probing != 0) {
328 * Good, exception 16 works.
334 "FPU does not use exception 16 for error reporting\n");
340 * Probe failed. Floating point simply won't work.
341 * Notify user and disable FPU/MMX/SSE instruction execution.
343 printf("WARNING: no FPU!\n");
344 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
345 "n" (CR0_EM | CR0_MP) : "ax");
348 idt[IDT_MF] = save_idt_npxtrap;
352 #ifdef CPU_ENABLE_SSE
354 * Enable XSAVE if supported and allowed by user.
355 * Calculate the xsave_mask.
361 uint64_t xsave_mask_user;
363 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
365 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
370 cpuid_count(0xd, 0x0, cp);
371 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
372 if ((cp[0] & xsave_mask) != xsave_mask)
373 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
374 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
375 xsave_mask_user = xsave_mask;
376 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user);
377 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
378 xsave_mask &= xsave_mask_user;
379 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
380 xsave_mask &= ~XFEATURE_AVX512;
381 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
382 xsave_mask &= ~XFEATURE_MPX;
384 cpuid_count(0xd, 0x1, cp);
385 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0)
391 * Calculate the fpu save area size.
396 #ifdef CPU_ENABLE_SSE
400 cpuid_count(0xd, 0x0, cp);
401 cpu_max_ext_state_size = cp[1];
404 * Reload the cpu_feature2, since we enabled OSXSAVE.
407 cpu_feature2 = cp[2];
410 cpu_max_ext_state_size = sizeof(union savefpu);
414 * Initialize floating point unit.
419 static union savefpu dummy;
421 #ifdef CPU_ENABLE_SSE
429 #ifdef CPU_ENABLE_SSE
434 #ifdef CPU_ENABLE_SSE
436 load_cr4(rcr4() | CR4_XSAVE);
437 load_xcr(XCR0, xsave_mask);
442 * XCR0 shall be set up before CPU can report the save area size.
448 * fninit has the same h/w bugs as fnsave. Use the detoxified
449 * fnsave to throw away any junk in the fpu. fpusave() initializes
452 * It is too early for critical_enter() to work on AP.
454 saveintr = intr_disable();
456 #ifdef CPU_ENABLE_SSE
462 control = __INITIAL_NPXCW__;
464 #ifdef CPU_ENABLE_SSE
466 mxcsr = __INITIAL_MXCSR__;
471 intr_restore(saveintr);
475 * On the boot CPU we generate a clean state that is used to
476 * initialize the floating point unit when it is first used by a
480 npxinitstate(void *arg __unused)
483 #ifdef CPU_ENABLE_SSE
484 int cp[4], i, max_ext_n;
490 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
492 saveintr = intr_disable();
495 fpusave(npx_initialstate);
496 #ifdef CPU_ENABLE_SSE
498 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask)
500 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask;
502 cpu_mxcsr_mask = 0xFFBF;
505 * The fninit instruction does not modify XMM
506 * registers or x87 registers (MM/ST). The fpusave
507 * call dumped the garbage contained in the registers
508 * after reset to the initial state saved. Clear XMM
509 * and x87 registers file image to make the startup
510 * program state and signal handler XMM/x87 register
511 * content predictable.
513 bzero(npx_initialstate->sv_xmm.sv_fp,
514 sizeof(npx_initialstate->sv_xmm.sv_fp));
515 bzero(npx_initialstate->sv_xmm.sv_xmm,
516 sizeof(npx_initialstate->sv_xmm.sv_xmm));
519 bzero(npx_initialstate->sv_87.sv_ac,
520 sizeof(npx_initialstate->sv_87.sv_ac));
522 #ifdef CPU_ENABLE_SSE
524 * Create a table describing the layout of the CPU Extended
528 if (xsave_mask >> 32 != 0)
529 max_ext_n = fls(xsave_mask >> 32) + 32;
531 max_ext_n = fls(xsave_mask);
532 xsave_area_desc = malloc(max_ext_n * sizeof(struct
533 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
535 xsave_area_desc[0].offset = 0;
536 xsave_area_desc[0].size = 160;
538 xsave_area_desc[1].offset = 160;
539 xsave_area_desc[1].size = 288 - 160;
541 for (i = 2; i < max_ext_n; i++) {
542 cpuid_count(0xd, i, cp);
543 xsave_area_desc[i].offset = cp[1];
544 xsave_area_desc[i].size = cp[0];
549 fpu_save_area_zone = uma_zcreate("FPU_save_area",
550 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
551 XSAVE_AREA_ALIGN - 1, 0);
554 intr_restore(saveintr);
556 SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);
559 * Free coprocessor (if we have it).
567 if (curthread == PCPU_GET(fpcurthread)) {
569 fpusave(curpcb->pcb_save);
571 PCPU_SET(fpcurthread, NULL);
576 u_int masked_exceptions;
578 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
580 * Log exceptions that would have trapped with the old
581 * control word (overflow, divide by 0, and invalid operand).
583 if (masked_exceptions & 0x0d)
585 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
586 td->td_proc->p_pid, td->td_proc->p_comm,
597 return (_MC_FPFMT_NODEV);
598 #ifdef CPU_ENABLE_SSE
600 return (_MC_FPFMT_XMM);
602 return (_MC_FPFMT_387);
606 * The following mechanism is used to ensure that the FPE_... value
607 * that is passed as a trapcode to the signal handler of the user
608 * process does not have more than one bit set.
610 * Multiple bits may be set if the user process modifies the control
611 * word while a status word bit is already set. While this is a sign
612 * of bad coding, we have no choise than to narrow them down to one
613 * bit, since we must not send a trapcode that is not exactly one of
616 * The mechanism has a static table with 127 entries. Each combination
617 * of the 7 FPU status word exception bits directly translates to a
618 * position in this table, where a single FPE_... value is stored.
619 * This FPE_... value stored there is considered the "most important"
620 * of the exception bits and will be sent as the signal code. The
621 * precedence of the bits is based upon Intel Document "Numerical
622 * Applications", Chapter "Special Computational Situations".
624 * The macro to choose one of these values does these steps: 1) Throw
625 * away status word bits that cannot be masked. 2) Throw away the bits
626 * currently masked in the control word, assuming the user isn't
627 * interested in them anymore. 3) Reinsert status word bit 7 (stack
628 * fault) if it is set, which cannot be masked but must be presered.
629 * 4) Use the remaining bits to point into the trapcode table.
631 * The 6 maskable bits in order of their preference, as stated in the
632 * above referenced Intel manual:
633 * 1 Invalid operation (FP_X_INV)
636 * 1c Operand of unsupported format
638 * 2 QNaN operand (not an exception, irrelavant here)
639 * 3 Any other invalid-operation not mentioned above or zero divide
640 * (FP_X_INV, FP_X_DZ)
641 * 4 Denormal operand (FP_X_DNML)
642 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
643 * 6 Inexact result (FP_X_IMP)
645 static char fpetable[128] = {
647 FPE_FLTINV, /* 1 - INV */
648 FPE_FLTUND, /* 2 - DNML */
649 FPE_FLTINV, /* 3 - INV | DNML */
650 FPE_FLTDIV, /* 4 - DZ */
651 FPE_FLTINV, /* 5 - INV | DZ */
652 FPE_FLTDIV, /* 6 - DNML | DZ */
653 FPE_FLTINV, /* 7 - INV | DNML | DZ */
654 FPE_FLTOVF, /* 8 - OFL */
655 FPE_FLTINV, /* 9 - INV | OFL */
656 FPE_FLTUND, /* A - DNML | OFL */
657 FPE_FLTINV, /* B - INV | DNML | OFL */
658 FPE_FLTDIV, /* C - DZ | OFL */
659 FPE_FLTINV, /* D - INV | DZ | OFL */
660 FPE_FLTDIV, /* E - DNML | DZ | OFL */
661 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
662 FPE_FLTUND, /* 10 - UFL */
663 FPE_FLTINV, /* 11 - INV | UFL */
664 FPE_FLTUND, /* 12 - DNML | UFL */
665 FPE_FLTINV, /* 13 - INV | DNML | UFL */
666 FPE_FLTDIV, /* 14 - DZ | UFL */
667 FPE_FLTINV, /* 15 - INV | DZ | UFL */
668 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
669 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
670 FPE_FLTOVF, /* 18 - OFL | UFL */
671 FPE_FLTINV, /* 19 - INV | OFL | UFL */
672 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
673 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
674 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
675 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
676 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
677 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
678 FPE_FLTRES, /* 20 - IMP */
679 FPE_FLTINV, /* 21 - INV | IMP */
680 FPE_FLTUND, /* 22 - DNML | IMP */
681 FPE_FLTINV, /* 23 - INV | DNML | IMP */
682 FPE_FLTDIV, /* 24 - DZ | IMP */
683 FPE_FLTINV, /* 25 - INV | DZ | IMP */
684 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
685 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
686 FPE_FLTOVF, /* 28 - OFL | IMP */
687 FPE_FLTINV, /* 29 - INV | OFL | IMP */
688 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
689 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
690 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
691 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
692 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
693 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
694 FPE_FLTUND, /* 30 - UFL | IMP */
695 FPE_FLTINV, /* 31 - INV | UFL | IMP */
696 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
697 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
698 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
699 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
700 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
701 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
702 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
703 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
704 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
705 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
706 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
707 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
708 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
709 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
710 FPE_FLTSUB, /* 40 - STK */
711 FPE_FLTSUB, /* 41 - INV | STK */
712 FPE_FLTUND, /* 42 - DNML | STK */
713 FPE_FLTSUB, /* 43 - INV | DNML | STK */
714 FPE_FLTDIV, /* 44 - DZ | STK */
715 FPE_FLTSUB, /* 45 - INV | DZ | STK */
716 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
717 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
718 FPE_FLTOVF, /* 48 - OFL | STK */
719 FPE_FLTSUB, /* 49 - INV | OFL | STK */
720 FPE_FLTUND, /* 4A - DNML | OFL | STK */
721 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
722 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
723 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
724 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
725 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
726 FPE_FLTUND, /* 50 - UFL | STK */
727 FPE_FLTSUB, /* 51 - INV | UFL | STK */
728 FPE_FLTUND, /* 52 - DNML | UFL | STK */
729 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
730 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
731 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
732 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
733 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
734 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
735 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
736 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
737 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
738 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
739 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
740 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
741 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
742 FPE_FLTRES, /* 60 - IMP | STK */
743 FPE_FLTSUB, /* 61 - INV | IMP | STK */
744 FPE_FLTUND, /* 62 - DNML | IMP | STK */
745 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
746 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
747 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
748 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
749 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
750 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
751 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
752 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
753 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
754 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
755 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
756 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
757 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
758 FPE_FLTUND, /* 70 - UFL | IMP | STK */
759 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
760 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
761 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
762 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
763 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
764 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
765 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
766 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
767 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
768 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
769 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
770 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
771 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
772 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
773 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
777 * Read the FP status and control words, then generate si_code value
778 * for SIGFPE. The error code chosen will be one of the
779 * FPE_... macros. It will be sent as the second argument to old
780 * BSD-style signal handlers and as "siginfo_t->si_code" (second
781 * argument) to SA_SIGINFO signal handlers.
783 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
784 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
785 * usermode code which understands the FPU hardware enough to enable
786 * the exceptions, can also handle clearing the exception state in the
787 * handler. The only consequence of not clearing the exception is the
788 * rethrow of the SIGFPE on return from the signal handler and
789 * reexecution of the corresponding instruction.
791 * For XMM traps, the exceptions were never cleared.
796 u_short control, status;
800 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n",
801 PCPU_GET(fpcurthread), curthread, hw_float);
802 panic("npxtrap from nowhere");
807 * Interrupt handling (for another interrupt) may have pushed the
808 * state to memory. Fetch the relevant parts of the state from
811 if (PCPU_GET(fpcurthread) != curthread) {
812 control = GET_FPU_CW(curthread);
813 status = GET_FPU_SW(curthread);
819 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
822 #ifdef CPU_ENABLE_SSE
830 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n",
831 PCPU_GET(fpcurthread), curthread, hw_float);
832 panic("npxtrap from nowhere");
835 if (PCPU_GET(fpcurthread) != curthread)
836 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr;
840 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
845 * Implement device not available (DNA) exception
847 * It would be better to switch FP context here (if curthread != fpcurthread)
848 * and not necessarily for every context switch, but it is too hard to
849 * access foreign pcb's.
852 static int err_count = 0;
861 if (PCPU_GET(fpcurthread) == curthread) {
862 printf("npxdna: fpcurthread == curthread %d times\n",
868 if (PCPU_GET(fpcurthread) != NULL) {
869 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
870 PCPU_GET(fpcurthread),
871 PCPU_GET(fpcurthread)->td_proc->p_pid,
872 curthread, curthread->td_proc->p_pid);
877 * Record new context early in case frstor causes a trap.
879 PCPU_SET(fpcurthread, curthread);
881 #ifdef CPU_ENABLE_SSE
886 if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) {
888 * This is the first time this thread has used the FPU or
889 * the PCB doesn't contain a clean FPU state. Explicitly
890 * load an initial state.
892 * We prefer to restore the state from the actual save
893 * area in PCB instead of directly loading from
894 * npx_initialstate, to ignite the XSAVEOPT
897 bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
898 fpurstor(curpcb->pcb_save);
899 if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
900 fldcw(curpcb->pcb_initial_npxcw);
901 curpcb->pcb_flags |= PCB_NPXINITDONE;
902 if (PCB_USER_FPU(curpcb))
903 curpcb->pcb_flags |= PCB_NPXUSERINITDONE;
905 fpurstor(curpcb->pcb_save);
913 * Wrapper for fpusave() called from context switch routines.
915 * npxsave() must be called with interrupts disabled, so that it clears
916 * fpcurthread atomically with saving the state. We require callers to do the
917 * disabling, since most callers need to disable interrupts anyway to call
918 * npxsave() atomically with checking fpcurthread.
926 #ifdef CPU_ENABLE_SSE
928 xsaveopt((char *)addr, xsave_mask);
933 PCPU_SET(fpcurthread, NULL);
937 * Unconditionally save the current co-processor state across suspend and
941 npxsuspend(union savefpu *addr)
947 if (PCPU_GET(fpcurthread) == NULL) {
948 bcopy(npx_initialstate, addr, cpu_max_ext_state_size);
958 npxresume(union savefpu *addr)
978 * Discard pending exceptions in the !cpu_fxsr case so that unmasked
979 * ones don't cause a panic on the next frstor.
981 #ifdef CPU_ENABLE_SSE
986 td = PCPU_GET(fpcurthread);
987 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
989 PCPU_SET(fpcurthread, NULL);
990 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
995 * Get the user state of the FPU into pcb->pcb_user_save without
996 * dropping ownership (if possible). It returns the FPU ownership
1000 npxgetregs(struct thread *td)
1003 #ifdef CPU_ENABLE_SSE
1004 uint64_t *xstate_bv, bit;
1011 return (_MC_FPOWNED_NONE);
1014 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
1015 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb),
1016 cpu_max_ext_state_size);
1017 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw);
1019 return (_MC_FPOWNED_PCB);
1022 if (td == PCPU_GET(fpcurthread)) {
1023 fpusave(get_pcb_user_save_pcb(pcb));
1024 #ifdef CPU_ENABLE_SSE
1028 * fnsave initializes the FPU and destroys whatever
1029 * context it contains. Make sure the FPU owner
1030 * starts with a clean state next time.
1033 owned = _MC_FPOWNED_FPU;
1035 owned = _MC_FPOWNED_PCB;
1038 #ifdef CPU_ENABLE_SSE
1041 * Handle partially saved state.
1043 sa = (char *)get_pcb_user_save_pcb(pcb);
1044 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) +
1045 offsetof(struct xstate_hdr, xstate_bv));
1046 if (xsave_mask >> 32 != 0)
1047 max_ext_n = fls(xsave_mask >> 32) + 32;
1049 max_ext_n = fls(xsave_mask);
1050 for (i = 0; i < max_ext_n; i++) {
1052 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
1054 bcopy((char *)npx_initialstate +
1055 xsave_area_desc[i].offset,
1056 sa + xsave_area_desc[i].offset,
1057 xsave_area_desc[i].size);
1066 npxuserinited(struct thread *td)
1071 if (PCB_USER_FPU(pcb))
1072 pcb->pcb_flags |= PCB_NPXINITDONE;
1073 pcb->pcb_flags |= PCB_NPXUSERINITDONE;
1076 #ifdef CPU_ENABLE_SSE
1078 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
1080 struct xstate_hdr *hdr, *ehdr;
1081 size_t len, max_len;
1084 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
1085 if (xfpustate == NULL)
1088 return (EOPNOTSUPP);
1090 len = xfpustate_size;
1091 if (len < sizeof(struct xstate_hdr))
1093 max_len = cpu_max_ext_state_size - sizeof(union savefpu);
1097 ehdr = (struct xstate_hdr *)xfpustate;
1098 bv = ehdr->xstate_bv;
1103 if (bv & ~xsave_mask)
1106 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
1108 hdr->xstate_bv = bv;
1109 bcopy(xfpustate + sizeof(struct xstate_hdr),
1110 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
1117 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
1118 size_t xfpustate_size)
1121 #ifdef CPU_ENABLE_SSE
1130 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
1131 #ifdef CPU_ENABLE_SSE
1132 error = npxsetxstate(td, xfpustate, xfpustate_size);
1139 fnclex(); /* As in npxdrop(). */
1140 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1141 fpurstor(get_pcb_user_save_td(td));
1143 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
1146 #ifdef CPU_ENABLE_SSE
1147 error = npxsetxstate(td, xfpustate, xfpustate_size);
1151 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1159 union savefpu *addr;
1162 #ifdef CPU_ENABLE_SSE
1164 xsave((char *)addr, xsave_mask);
1172 #ifdef CPU_ENABLE_SSE
1174 * On AuthenticAMD processors, the fxrstor instruction does not restore
1175 * the x87's stored last instruction pointer, last data pointer, and last
1176 * opcode values, except in the rare case in which the exception summary
1177 * (ES) bit in the x87 status word is set to 1.
1179 * In order to avoid leaking this information across processes, we clean
1180 * these values by performing a dummy load before executing fxrstor().
1183 fpu_clean_state(void)
1185 static float dummy_variable = 0.0;
1189 * Clear the ES bit in the x87 status word if it is currently
1190 * set, in order to avoid causing a fault in the upcoming load.
1197 * Load the dummy variable into the x87 stack. This mangles
1198 * the x87 stack, but we don't care since we're about to call
1201 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1203 #endif /* CPU_ENABLE_SSE */
1207 union savefpu *addr;
1210 #ifdef CPU_ENABLE_SSE
1212 xrstor((char *)addr, xsave_mask);
1222 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1224 static struct isa_pnp_id npxisa_ids[] = {
1225 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1230 npxisa_probe(device_t dev)
1233 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
1240 npxisa_attach(device_t dev)
1245 static device_method_t npxisa_methods[] = {
1246 /* Device interface */
1247 DEVMETHOD(device_probe, npxisa_probe),
1248 DEVMETHOD(device_attach, npxisa_attach),
1249 DEVMETHOD(device_detach, bus_generic_detach),
1250 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1251 DEVMETHOD(device_suspend, bus_generic_suspend),
1252 DEVMETHOD(device_resume, bus_generic_resume),
1257 static driver_t npxisa_driver = {
1263 static devclass_t npxisa_devclass;
1265 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
1267 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
1269 #endif /* DEV_ISA */
1271 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
1272 "Kernel contexts for FPU state");
1274 #define FPU_KERN_CTX_NPXINITDONE 0x01
1275 #define FPU_KERN_CTX_DUMMY 0x02
1277 struct fpu_kern_ctx {
1278 union savefpu *prev;
1283 struct fpu_kern_ctx *
1284 fpu_kern_alloc_ctx(u_int flags)
1286 struct fpu_kern_ctx *res;
1289 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
1290 cpu_max_ext_state_size;
1291 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
1292 M_NOWAIT : M_WAITOK) | M_ZERO);
1297 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
1300 /* XXXKIB clear the memory ? */
1301 free(ctx, M_FPUKERN_CTX);
1304 static union savefpu *
1305 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
1309 p = (vm_offset_t)&ctx->hwstate1;
1310 p = roundup2(p, XSAVE_AREA_ALIGN);
1311 return ((union savefpu *)p);
1315 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
1319 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1320 ctx->flags = FPU_KERN_CTX_DUMMY;
1324 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1325 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1327 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
1328 ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
1330 ctx->prev = pcb->pcb_save;
1331 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1332 pcb->pcb_flags |= PCB_KERNNPX;
1333 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1338 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1342 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1346 if (curthread == PCPU_GET(fpcurthread))
1349 pcb->pcb_save = ctx->prev;
1350 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1351 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0)
1352 pcb->pcb_flags |= PCB_NPXINITDONE;
1354 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1355 pcb->pcb_flags &= ~PCB_KERNNPX;
1357 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
1358 pcb->pcb_flags |= PCB_NPXINITDONE;
1360 pcb->pcb_flags &= ~PCB_NPXINITDONE;
1361 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1367 fpu_kern_thread(u_int flags)
1370 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1371 ("Only kthread may use fpu_kern_thread"));
1372 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1373 ("mangled pcb_save"));
1374 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1376 curpcb->pcb_flags |= PCB_KERNNPX;
1381 is_fpu_kern_thread(u_int flags)
1384 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1386 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0);
1390 * FPU save area alloc/free/init utility routines
1393 fpu_save_area_alloc(void)
1396 return (uma_zalloc(fpu_save_area_zone, 0));
1400 fpu_save_area_free(union savefpu *fsa)
1403 uma_zfree(fpu_save_area_zone, fsa);
1407 fpu_save_area_reset(union savefpu *fsa)
1410 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size);