2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/page.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/if_vlan.h>
39 #include <linux/vmalloc.h>
40 #include <linux/moduleparam.h>
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
55 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
60 static int inline_thold __read_mostly = MAX_INLINE;
62 module_param_named(inline_thold, inline_thold, uint, 0444);
63 MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
65 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
66 struct mlx4_en_tx_ring **pring, u32 size,
67 u16 stride, int node, int queue_idx)
69 struct mlx4_en_dev *mdev = priv->mdev;
70 struct mlx4_en_tx_ring *ring;
75 ring = kzalloc_node(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL, node);
77 ring = kzalloc(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL);
79 en_err(priv, "Failed allocating TX ring\n");
84 /* Create DMA descriptor TAG */
85 if ((err = -bus_dma_tag_create(
86 bus_get_dma_tag(mdev->pdev->dev.bsddev),
87 1, /* any alignment */
89 BUS_SPACE_MAXADDR, /* lowaddr */
90 BUS_SPACE_MAXADDR, /* highaddr */
91 NULL, NULL, /* filter, filterarg */
92 MLX4_EN_TX_MAX_PAYLOAD_SIZE, /* maxsize */
93 MLX4_EN_TX_MAX_MBUF_FRAGS, /* nsegments */
94 MLX4_EN_TX_MAX_MBUF_SIZE, /* maxsegsize */
96 NULL, NULL, /* lockfunc, lockfuncarg */
101 ring->size_mask = size - 1;
102 ring->stride = stride;
103 ring->inline_thold = MAX(MIN_PKT_LEN, MIN(inline_thold, MAX_INLINE));
104 mtx_init(&ring->tx_lock.m, "mlx4 tx", NULL, MTX_DEF);
105 mtx_init(&ring->comp_lock.m, "mlx4 comp", NULL, MTX_DEF);
107 /* Allocate the buf ring */
108 ring->br = buf_ring_alloc(MLX4_EN_DEF_TX_QUEUE_SIZE, M_DEVBUF,
109 M_WAITOK, &ring->tx_lock.m);
110 if (ring->br == NULL) {
111 en_err(priv, "Failed allocating tx_info ring\n");
113 goto err_free_dma_tag;
116 tmp = size * sizeof(struct mlx4_en_tx_info);
117 ring->tx_info = kzalloc_node(tmp, GFP_KERNEL, node);
118 if (!ring->tx_info) {
119 ring->tx_info = kzalloc(tmp, GFP_KERNEL);
120 if (!ring->tx_info) {
126 /* Create DMA descriptor MAPs */
127 for (x = 0; x != size; x++) {
128 err = -bus_dmamap_create(ring->dma_tag, 0,
129 &ring->tx_info[x].dma_map);
132 bus_dmamap_destroy(ring->dma_tag,
133 ring->tx_info[x].dma_map);
139 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
142 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
144 /* Allocate HW buffers on provided NUMA node */
145 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
148 en_err(priv, "Failed allocating hwq resources\n");
152 err = mlx4_en_map_buffer(&ring->wqres.buf);
154 en_err(priv, "Failed to map TX buffer\n");
158 ring->buf = ring->wqres.buf.direct.buf;
160 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
161 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
162 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
164 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
167 en_err(priv, "failed reserving qp for TX ring\n");
171 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
173 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
176 ring->qp.event = mlx4_en_sqp_event;
178 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
180 en_dbg(DRV, priv, "working without blueflame (%d)", err);
181 ring->bf.uar = &mdev->priv_uar;
182 ring->bf.uar->map = mdev->uar_map;
183 ring->bf_enabled = false;
185 ring->bf_enabled = true;
186 ring->queue_index = queue_idx;
187 if (queue_idx < priv->num_tx_rings_p_up )
188 CPU_SET(queue_idx, &ring->affinity_mask);
194 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
196 mlx4_en_unmap_buffer(&ring->wqres.buf);
198 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
200 for (x = 0; x != size; x++)
201 bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
203 vfree(ring->tx_info);
205 buf_ring_free(ring->br, M_DEVBUF);
207 bus_dma_tag_destroy(ring->dma_tag);
213 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
214 struct mlx4_en_tx_ring **pring)
216 struct mlx4_en_dev *mdev = priv->mdev;
217 struct mlx4_en_tx_ring *ring = *pring;
219 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
221 buf_ring_free(ring->br, M_DEVBUF);
222 if (ring->bf_enabled)
223 mlx4_bf_free(mdev->dev, &ring->bf);
224 mlx4_qp_remove(mdev->dev, &ring->qp);
225 mlx4_qp_free(mdev->dev, &ring->qp);
226 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
227 mlx4_en_unmap_buffer(&ring->wqres.buf);
228 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
229 for (x = 0; x != ring->size; x++)
230 bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
231 vfree(ring->tx_info);
232 mtx_destroy(&ring->tx_lock.m);
233 mtx_destroy(&ring->comp_lock.m);
234 bus_dma_tag_destroy(ring->dma_tag);
239 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
240 struct mlx4_en_tx_ring *ring,
241 int cq, int user_prio)
243 struct mlx4_en_dev *mdev = priv->mdev;
248 ring->cons = 0xffffffff;
249 ring->last_nr_txbb = 1;
252 memset(ring->buf, 0, ring->buf_size);
254 ring->qp_state = MLX4_QP_STATE_RST;
255 ring->doorbell_qpn = ring->qp.qpn << 8;
257 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
258 ring->cqn, user_prio, &ring->context);
259 if (ring->bf_enabled)
260 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
262 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
263 &ring->qp, &ring->qp_state);
267 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
268 struct mlx4_en_tx_ring *ring)
270 struct mlx4_en_dev *mdev = priv->mdev;
272 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
273 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
276 static volatile struct mlx4_wqe_data_seg *
277 mlx4_en_store_inline_lso_data(volatile struct mlx4_wqe_data_seg *dseg,
278 struct mbuf *mb, int len, __be32 owner_bit)
280 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
282 /* copy data into place */
283 m_copydata(mb, 0, len, inl + 4);
284 dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
289 mlx4_en_store_inline_lso_header(volatile struct mlx4_wqe_data_seg *dseg,
290 int len, __be32 owner_bit)
295 mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
296 struct mlx4_en_tx_ring *ring, u32 index, u8 owner)
298 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
299 struct mlx4_en_tx_desc *tx_desc = (struct mlx4_en_tx_desc *)
300 (ring->buf + (index * TXBB_SIZE));
301 volatile __be32 *ptr = (__be32 *)tx_desc;
302 const __be32 stamp = cpu_to_be32(STAMP_VAL |
303 ((u32)owner << STAMP_SHIFT));
306 /* Stamp the freed descriptor */
307 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
314 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
315 struct mlx4_en_tx_ring *ring, u32 index)
317 struct mlx4_en_tx_info *tx_info;
320 tx_info = &ring->tx_info[index];
326 bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
327 BUS_DMASYNC_POSTWRITE);
328 bus_dmamap_unload(ring->dma_tag, tx_info->dma_map);
332 return (tx_info->nr_txbb);
335 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
337 struct mlx4_en_priv *priv = netdev_priv(dev);
340 /* Skip last polled descriptor */
341 ring->cons += ring->last_nr_txbb;
342 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
343 ring->cons, ring->prod);
345 if ((u32) (ring->prod - ring->cons) > ring->size) {
346 en_warn(priv, "Tx consumer passed producer!\n");
350 while (ring->cons != ring->prod) {
351 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
352 ring->cons & ring->size_mask);
353 ring->cons += ring->last_nr_txbb;
358 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
364 mlx4_en_tx_ring_is_full(struct mlx4_en_tx_ring *ring)
367 wqs = ring->size - (ring->prod - ring->cons);
368 return (wqs < (HEADROOM + (2 * MLX4_EN_TX_WQE_MAX_WQEBBS)));
371 static int mlx4_en_process_tx_cq(struct net_device *dev,
372 struct mlx4_en_cq *cq)
374 struct mlx4_en_priv *priv = netdev_priv(dev);
375 struct mlx4_cq *mcq = &cq->mcq;
376 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
377 struct mlx4_cqe *cqe;
379 u16 new_index, ring_index, stamp_index;
380 u32 txbbs_skipped = 0;
382 u32 cons_index = mcq->cons_index;
384 u32 size_mask = ring->size_mask;
385 struct mlx4_cqe *buf = cq->buf;
386 int factor = priv->cqe_factor;
391 index = cons_index & size_mask;
392 cqe = &buf[(index << factor) + factor];
393 ring_index = ring->cons & size_mask;
394 stamp_index = ring_index;
396 /* Process all completed CQEs */
397 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
398 cons_index & size)) {
400 * make sure we read the CQE after we read the
405 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
406 MLX4_CQE_OPCODE_ERROR)) {
407 en_err(priv, "CQE completed in error - vendor syndrom: 0x%x syndrom: 0x%x\n",
408 ((struct mlx4_err_cqe *)cqe)->
410 ((struct mlx4_err_cqe *)cqe)->syndrome);
413 /* Skip over last polled CQE */
414 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
417 txbbs_skipped += ring->last_nr_txbb;
418 ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
419 /* free next descriptor */
420 ring->last_nr_txbb = mlx4_en_free_tx_desc(
421 priv, ring, ring_index);
422 mlx4_en_stamp_wqe(priv, ring, stamp_index,
423 !!((ring->cons + txbbs_stamp) &
425 stamp_index = ring_index;
426 txbbs_stamp = txbbs_skipped;
427 } while (ring_index != new_index);
430 index = cons_index & size_mask;
431 cqe = &buf[(index << factor) + factor];
436 * To prevent CQ overflow we first update CQ consumer and only then
439 mcq->cons_index = cons_index;
442 ring->cons += txbbs_skipped;
444 /* Wakeup Tx queue if it was stopped and ring is not full */
445 if (unlikely(ring->blocked) && !mlx4_en_tx_ring_is_full(ring)) {
447 if (atomic_fetchadd_int(&priv->blocked, -1) == 1)
448 atomic_clear_int(&dev->if_drv_flags ,IFF_DRV_OACTIVE);
450 priv->port_stats.wake_queue++;
455 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
457 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
458 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
459 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
461 if (!spin_trylock(&ring->comp_lock))
463 mlx4_en_process_tx_cq(cq->dev, cq);
464 mod_timer(&cq->timer, jiffies + 1);
465 spin_unlock(&ring->comp_lock);
468 void mlx4_en_poll_tx_cq(unsigned long data)
470 struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
471 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
472 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
475 INC_PERF_COUNTER(priv->pstats.tx_poll);
477 if (!spin_trylock(&ring->comp_lock)) {
478 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
481 mlx4_en_process_tx_cq(cq->dev, cq);
482 inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
484 /* If there are still packets in flight and the timer has not already
485 * been scheduled by the Tx routine then schedule it here to guarantee
486 * completion processing of these packets */
487 if (inflight && priv->port_up)
488 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
490 spin_unlock(&ring->comp_lock);
493 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
495 struct mlx4_en_cq *cq = priv->tx_cq[tx_ind];
496 struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
498 /* If we don't have a pending timer, set one up to catch our recent
499 post in case the interface becomes idle */
500 if (!timer_pending(&cq->timer))
501 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
503 /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
504 if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
505 if (spin_trylock(&ring->comp_lock)) {
506 mlx4_en_process_tx_cq(priv->dev, cq);
507 spin_unlock(&ring->comp_lock);
512 mlx4_en_get_inline_hdr_size(struct mlx4_en_tx_ring *ring, struct mbuf *mb)
516 /* only copy from first fragment, if possible */
517 retval = MIN(ring->inline_thold, mb->m_len);
519 /* check for too little data */
520 if (unlikely(retval < MIN_PKT_LEN))
521 retval = MIN(ring->inline_thold, mb->m_pkthdr.len);
526 mlx4_en_get_header_size(struct mbuf *mb)
528 struct ether_vlan_header *eh;
531 int ip_hlen, tcp_hlen;
536 eh = mtod(mb, struct ether_vlan_header *);
537 if (mb->m_len < ETHER_HDR_LEN)
539 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
540 eth_type = ntohs(eh->evl_proto);
541 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
543 eth_type = ntohs(eh->evl_encap_proto);
544 eth_hdr_len = ETHER_HDR_LEN;
546 if (mb->m_len < eth_hdr_len)
550 ip = (struct ip *)(mb->m_data + eth_hdr_len);
551 if (mb->m_len < eth_hdr_len + sizeof(*ip))
553 if (ip->ip_p != IPPROTO_TCP)
555 ip_hlen = ip->ip_hl << 2;
556 eth_hdr_len += ip_hlen;
559 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
560 if (mb->m_len < eth_hdr_len + sizeof(*ip6))
562 if (ip6->ip6_nxt != IPPROTO_TCP)
564 eth_hdr_len += sizeof(*ip6);
569 if (mb->m_len < eth_hdr_len + sizeof(*th))
571 th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
572 tcp_hlen = th->th_off << 2;
573 eth_hdr_len += tcp_hlen;
574 if (mb->m_len < eth_hdr_len)
576 return (eth_hdr_len);
579 static volatile struct mlx4_wqe_data_seg *
580 mlx4_en_store_inline_data(volatile struct mlx4_wqe_data_seg *dseg,
581 struct mbuf *mb, int len, __be32 owner_bit)
583 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
584 const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
586 if (unlikely(len < MIN_PKT_LEN)) {
587 m_copydata(mb, 0, len, inl + 4);
588 memset(inl + 4 + len, 0, MIN_PKT_LEN - len);
589 dseg += DIV_ROUND_UP(4 + MIN_PKT_LEN, DS_SIZE_ALIGNMENT);
590 } else if (len <= spc) {
591 m_copydata(mb, 0, len, inl + 4);
592 dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
594 m_copydata(mb, 0, spc, inl + 4);
595 m_copydata(mb, spc, len - spc, inl + 8 + spc);
596 dseg += DIV_ROUND_UP(8 + len, DS_SIZE_ALIGNMENT);
602 mlx4_en_store_inline_header(volatile struct mlx4_wqe_data_seg *dseg,
603 int len, __be32 owner_bit)
605 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
606 const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
608 if (unlikely(len < MIN_PKT_LEN)) {
609 *(volatile uint32_t *)inl =
610 SET_BYTE_COUNT((1 << 31) | MIN_PKT_LEN);
611 } else if (len <= spc) {
612 *(volatile uint32_t *)inl =
613 SET_BYTE_COUNT((1 << 31) | len);
615 *(volatile uint32_t *)(inl + 4 + spc) =
616 SET_BYTE_COUNT((1 << 31) | (len - spc));
618 *(volatile uint32_t *)inl =
619 SET_BYTE_COUNT((1 << 31) | spc);
623 static unsigned long hashrandom;
624 static void hashrandom_init(void *arg)
626 hashrandom = random();
628 SYSINIT(hashrandom_init, SI_SUB_KLD, SI_ORDER_SECOND, &hashrandom_init, NULL);
630 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
632 struct mlx4_en_priv *priv = netdev_priv(dev);
633 u32 rings_p_up = priv->num_tx_rings_p_up;
637 #if (MLX4_EN_NUM_UP > 1)
638 /* Obtain VLAN information if present */
639 if (mb->m_flags & M_VLANTAG) {
640 u32 vlan_tag = mb->m_pkthdr.ether_vtag;
641 up = (vlan_tag >> 13) % MLX4_EN_NUM_UP;
644 queue_index = mlx4_en_hashmbuf(MLX4_F_HASHL3 | MLX4_F_HASHL4, mb, hashrandom);
646 return ((queue_index % rings_p_up) + (up * rings_p_up));
649 static void mlx4_bf_copy(void __iomem *dst, volatile unsigned long *src, unsigned bytecnt)
651 __iowrite64_copy(dst, __DEVOLATILE(void *, src), bytecnt / 8);
654 static u64 mlx4_en_mac_to_u64(u8 *addr)
659 for (i = 0; i < ETHER_ADDR_LEN; i++) {
666 static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp)
669 DS_FACT = TXBB_SIZE / DS_SIZE_ALIGNMENT,
670 CTRL_FLAGS = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
671 MLX4_WQE_CTRL_SOLICITED),
673 bus_dma_segment_t segs[MLX4_EN_TX_MAX_MBUF_FRAGS];
674 volatile struct mlx4_wqe_data_seg *dseg;
675 volatile struct mlx4_wqe_data_seg *dseg_inline;
676 volatile struct mlx4_en_tx_desc *tx_desc;
677 struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
678 struct ifnet *ifp = priv->dev;
679 struct mlx4_en_tx_info *tx_info;
680 struct mbuf *mb = *mbp;
693 if (unlikely(!priv->port_up)) {
698 /* check if TX ring is full */
699 if (unlikely(mlx4_en_tx_ring_is_full(ring))) {
700 /* every full native Tx ring stops queue */
701 if (ring->blocked == 0)
702 atomic_add_int(&priv->blocked, 1);
703 /* Set HW-queue-is-full flag */
704 atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
705 priv->port_stats.queue_stopped++;
707 priv->port_stats.queue_stopped++;
708 ring->queue_stopped++;
710 /* Use interrupts to find out when queue opened */
711 mlx4_en_arm_cq(priv, priv->tx_cq[tx_ind]);
715 /* sanity check we are not wrapping around */
716 KASSERT(((~ring->prod) & ring->size_mask) >=
717 (MLX4_EN_TX_WQE_MAX_WQEBBS - 1), ("Wrapping around TX ring"));
719 /* Track current inflight packets for performance analysis */
720 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
721 (u32) (ring->prod - ring->cons - 1));
723 /* Track current mbuf packet header length */
724 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, mb->m_pkthdr.len);
726 /* Grab an index and try to transmit packet */
727 owner_bit = (ring->prod & ring->size) ?
728 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0;
729 index = ring->prod & ring->size_mask;
730 tx_desc = (volatile struct mlx4_en_tx_desc *)
731 (ring->buf + index * TXBB_SIZE);
732 tx_info = &ring->tx_info[index];
733 dseg = &tx_desc->data;
735 /* send a copy of the frame to the BPF listener, if any */
736 if (ifp != NULL && ifp->if_bpf != NULL)
737 ETHER_BPF_MTAP(ifp, mb);
739 /* get default flags */
740 tx_desc->ctrl.srcrb_flags = CTRL_FLAGS;
742 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
743 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
745 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP |
746 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
747 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM);
750 if (likely(tx_desc->ctrl.srcrb_flags != CTRL_FLAGS)) {
751 priv->port_stats.tx_chksum_offload++;
755 /* check for VLAN tag */
756 if (mb->m_flags & M_VLANTAG) {
757 tx_desc->ctrl.vlan_tag = cpu_to_be16(mb->m_pkthdr.ether_vtag);
758 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN;
760 tx_desc->ctrl.vlan_tag = 0;
761 tx_desc->ctrl.ins_vlan = 0;
764 /* clear immediate field */
765 tx_desc->ctrl.imm = 0;
767 /* Handle LSO (TSO) packets */
768 if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
770 u32 mss = mb->m_pkthdr.tso_segsz;
773 opcode = cpu_to_be32(MLX4_OPCODE_LSO | MLX4_WQE_CTRL_RR) |
775 ihs = mlx4_en_get_header_size(mb);
776 if (unlikely(ihs > MAX_INLINE)) {
777 ring->oversized_packets++;
781 tx_desc->lso.mss_hdr_size = cpu_to_be32((mss << 16) | ihs);
782 payload_len = mb->m_pkthdr.len - ihs;
783 if (unlikely(payload_len == 0))
786 num_pkts = DIV_ROUND_UP(payload_len, mss);
787 ring->bytes += payload_len + (num_pkts * ihs);
788 ring->packets += num_pkts;
789 priv->port_stats.tso_packets++;
790 /* store pointer to inline header */
792 /* copy data inline */
793 dseg = mlx4_en_store_inline_lso_data(dseg,
796 opcode = cpu_to_be32(MLX4_OPCODE_SEND) |
798 ihs = mlx4_en_get_inline_hdr_size(ring, mb);
799 ring->bytes += max_t (unsigned int,
800 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
802 /* store pointer to inline header */
804 /* copy data inline */
805 dseg = mlx4_en_store_inline_data(dseg,
810 /* trim off empty mbufs */
811 while (mb->m_len == 0) {
813 /* check if all data has been inlined */
820 err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
821 mb, segs, &nr_segs, BUS_DMA_NOWAIT);
822 if (unlikely(err == EFBIG)) {
823 /* Too many mbuf fragments */
824 m = m_defrag(mb, M_NOWAIT);
826 ring->oversized_packets++;
831 err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
832 mb, segs, &nr_segs, BUS_DMA_NOWAIT);
835 if (unlikely(err != 0)) {
836 ring->oversized_packets++;
839 /* make sure all mbuf data is written to RAM */
840 bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
841 BUS_DMASYNC_PREWRITE);
844 /* compute number of DS needed */
845 ds_cnt = (dseg - ((volatile struct mlx4_wqe_data_seg *)tx_desc)) + nr_segs;
848 * Check if the next request can wrap around and fill the end
849 * of the current request with zero immediate data:
851 pad = DIV_ROUND_UP(ds_cnt, DS_FACT);
852 pad = (~(ring->prod + pad)) & ring->size_mask;
854 if (unlikely(pad < (MLX4_EN_TX_WQE_MAX_WQEBBS - 1))) {
856 * Compute the least number of DS blocks we need to
857 * pad in order to achieve a TX ring wraparound:
859 pad = (DS_FACT * (pad + 1));
862 * The hardware will automatically jump to the next
863 * TXBB. No need for padding.
868 /* compute total number of DS blocks */
871 * When modifying this code, please ensure that the following
872 * computation is always less than or equal to 0x3F:
874 * ((MLX4_EN_TX_WQE_MAX_WQEBBS - 1) * DS_FACT) +
875 * (MLX4_EN_TX_WQE_MAX_WQEBBS * DS_FACT)
877 * Else the "ds_cnt" variable can become too big.
879 tx_desc->ctrl.fence_size = (ds_cnt & 0x3f);
881 /* store pointer to mbuf */
883 tx_info->nr_txbb = DIV_ROUND_UP(ds_cnt, DS_FACT);
884 bf_size = ds_cnt * DS_SIZE_ALIGNMENT;
885 bf_prod = ring->prod;
887 /* compute end of "dseg" array */
888 dseg += nr_segs + pad;
890 /* pad using zero immediate dseg */
896 dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0);
899 /* fill segment list */
901 if (unlikely(segs[nr_segs].ds_len == 0)) {
906 dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0);
909 dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr);
910 dseg->lkey = cpu_to_be32(priv->mdev->mr.key);
912 dseg->byte_count = SET_BYTE_COUNT((uint32_t)segs[nr_segs].ds_len);
918 /* write owner bits in reverse order */
919 if ((opcode & cpu_to_be32(0x1F)) == cpu_to_be32(MLX4_OPCODE_LSO))
920 mlx4_en_store_inline_lso_header(dseg_inline, ihs, owner_bit);
922 mlx4_en_store_inline_header(dseg_inline, ihs, owner_bit);
924 if (unlikely(priv->validate_loopback)) {
925 /* Copy dst mac address to wqe */
926 struct ether_header *ethh;
930 ethh = mtod(mb, struct ether_header *);
931 mac = mlx4_en_mac_to_u64(ethh->ether_dhost);
933 mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16);
934 mac_l = (u32) (mac & 0xffffffff);
935 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h);
936 tx_desc->ctrl.imm = cpu_to_be32(mac_l);
940 /* update producer counter */
941 ring->prod += tx_info->nr_txbb;
943 if (ring->bf_enabled && bf_size <= MAX_BF &&
944 (tx_desc->ctrl.ins_vlan != MLX4_WQE_CTRL_INS_VLAN)) {
946 /* store doorbell number */
947 *(volatile __be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
949 /* or in producer number for this WQE */
950 opcode |= cpu_to_be32((bf_prod & 0xffff) << 8);
953 * Ensure the new descriptor hits memory before
954 * setting ownership of this descriptor to HW:
957 tx_desc->ctrl.owner_opcode = opcode;
959 mlx4_bf_copy(((u8 *)ring->bf.reg) + ring->bf.offset,
960 (volatile unsigned long *) &tx_desc->ctrl, bf_size);
962 ring->bf.offset ^= ring->bf.buf_size;
965 * Ensure the new descriptor hits memory before
966 * setting ownership of this descriptor to HW:
969 tx_desc->ctrl.owner_opcode = opcode;
971 writel(cpu_to_be32(ring->doorbell_qpn),
972 ((u8 *)ring->bf.uar->map) + MLX4_SEND_DOORBELL);
983 mlx4_en_transmit_locked(struct ifnet *dev, int tx_ind, struct mbuf *m)
985 struct mlx4_en_priv *priv = netdev_priv(dev);
986 struct mlx4_en_tx_ring *ring;
988 int enqueued, err = 0;
990 ring = priv->tx_ring[tx_ind];
991 if ((dev->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
992 IFF_DRV_RUNNING || priv->port_up == 0) {
994 err = drbr_enqueue(dev, ring->br, m);
1001 * If we can't insert mbuf into drbr, try to xmit anyway.
1002 * We keep the error we got so we could return that after xmit.
1004 err = drbr_enqueue(dev, ring->br, m);
1006 /* Process the queue */
1007 while ((next = drbr_peek(dev, ring->br)) != NULL) {
1008 if (mlx4_en_xmit(priv, tx_ind, &next) != 0) {
1010 drbr_advance(dev, ring->br);
1012 drbr_putback(dev, ring->br, next);
1016 drbr_advance(dev, ring->br);
1018 if ((dev->if_drv_flags & IFF_DRV_RUNNING) == 0)
1023 ring->watchdog_time = ticks;
1029 mlx4_en_tx_que(void *context, int pending)
1031 struct mlx4_en_tx_ring *ring;
1032 struct mlx4_en_priv *priv;
1033 struct net_device *dev;
1034 struct mlx4_en_cq *cq;
1038 priv = dev->if_softc;
1040 ring = priv->tx_ring[tx_ind];
1041 if (dev->if_drv_flags & IFF_DRV_RUNNING) {
1042 mlx4_en_xmit_poll(priv, tx_ind);
1043 spin_lock(&ring->tx_lock);
1044 if (!drbr_empty(dev, ring->br))
1045 mlx4_en_transmit_locked(dev, tx_ind, NULL);
1046 spin_unlock(&ring->tx_lock);
1051 mlx4_en_transmit(struct ifnet *dev, struct mbuf *m)
1053 struct mlx4_en_priv *priv = netdev_priv(dev);
1054 struct mlx4_en_tx_ring *ring;
1055 struct mlx4_en_cq *cq;
1058 /* Compute which queue to use */
1059 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
1060 i = m->m_pkthdr.flowid % priv->tx_ring_num;
1063 i = mlx4_en_select_queue(dev, m);
1066 ring = priv->tx_ring[i];
1067 if (spin_trylock(&ring->tx_lock)) {
1068 err = mlx4_en_transmit_locked(dev, i, m);
1069 spin_unlock(&ring->tx_lock);
1071 mlx4_en_xmit_poll(priv, i);
1073 err = drbr_enqueue(dev, ring->br, m);
1074 cq = priv->tx_cq[i];
1075 taskqueue_enqueue(cq->tq, &cq->cq_task);
1082 * Flush ring buffers.
1085 mlx4_en_qflush(struct ifnet *dev)
1087 struct mlx4_en_priv *priv = netdev_priv(dev);
1088 struct mlx4_en_tx_ring *ring;
1091 for (int i = 0; i < priv->tx_ring_num; i++) {
1092 ring = priv->tx_ring[i];
1093 spin_lock(&ring->tx_lock);
1094 while ((m = buf_ring_dequeue_sc(ring->br)) != NULL)
1096 spin_unlock(&ring->tx_lock);