2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/kobject.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/if_ether.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
49 #include <linux/mlx4/device.h>
50 #include <linux/mlx4/qp.h>
51 #include <linux/mlx4/cq.h>
52 #include <linux/mlx4/srq.h>
53 #include <linux/mlx4/doorbell.h>
54 #include <linux/mlx4/cmd.h>
56 #include <netinet/tcp_lro.h>
59 #include "mlx4_stats.h"
61 #define DRV_NAME "mlx4_en"
63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
70 #define MLX4_EN_PAGE_SHIFT 12
71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
72 #define DEF_RX_RINGS 16
73 #define MAX_RX_RINGS 128
74 #define MIN_RX_RINGS 4
76 #define HEADROOM (2048 / TXBB_SIZE + 1)
77 #define STAMP_STRIDE 64
78 #define STAMP_DWORDS (STAMP_STRIDE / 4)
79 #define STAMP_SHIFT 31
80 #define STAMP_VAL 0x7fffffff
81 #define STATS_DELAY (HZ / 4)
82 #define SERVICE_TASK_DELAY (HZ / 4)
83 #define MAX_NUM_OF_FS_RULES 256
85 #define MLX4_EN_FILTER_HASH_SHIFT 4
86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88 #ifdef CONFIG_NET_RX_BUSY_POLL
89 #define LL_EXTENDED_STATS
92 /* vlan valid range */
93 #define VLAN_MIN_VALUE 1
94 #define VLAN_MAX_VALUE 4094
97 * OS related constants and tunables
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE)
103 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
105 enum mlx4_en_alloc_type {
106 MLX4_EN_ALLOC_NEW = 0,
107 MLX4_EN_ALLOC_REPLACEMENT = 1,
110 /* Maximum ring sizes */
111 #define MLX4_EN_DEF_TX_QUEUE_SIZE 4096
113 /* Minimum packet number till arming the CQ */
114 #define MLX4_EN_MIN_RX_ARM 2048
115 #define MLX4_EN_MIN_TX_ARM 2048
117 /* Maximum ring sizes */
118 #define MLX4_EN_MAX_TX_SIZE 8192
119 #define MLX4_EN_MAX_RX_SIZE 8192
121 /* Minimum ring sizes */
122 #define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE)
123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
125 #define MLX4_EN_SMALL_PKT_SIZE 64
127 #define MLX4_EN_MAX_TX_RING_P_UP 32
128 #define MLX4_EN_NUM_UP 1
130 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
133 #define MLX4_EN_DEF_TX_RING_SIZE 1024
134 #define MLX4_EN_DEF_RX_RING_SIZE 1024
136 /* Target number of bytes to coalesce with interrupt moderation */
137 #define MLX4_EN_RX_COAL_TARGET 0x20000
138 #define MLX4_EN_RX_COAL_TIME 0x10
140 #define MLX4_EN_TX_COAL_PKTS 64
141 #define MLX4_EN_TX_COAL_TIME 64
143 #define MLX4_EN_RX_RATE_LOW 400000
144 #define MLX4_EN_RX_COAL_TIME_LOW 0
145 #define MLX4_EN_RX_RATE_HIGH 450000
146 #define MLX4_EN_RX_COAL_TIME_HIGH 128
147 #define MLX4_EN_RX_SIZE_THRESH 1024
148 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
149 #define MLX4_EN_SAMPLE_INTERVAL 0
150 #define MLX4_EN_AVG_PKT_SMALL 256
152 #define MLX4_EN_AUTO_CONF 0xffff
154 #define MLX4_EN_DEF_RX_PAUSE 1
155 #define MLX4_EN_DEF_TX_PAUSE 1
157 /* Interval between successive polls in the Tx routine when polling is used
158 instead of interrupts (in per-core Tx rings) - should be power of 2 */
159 #define MLX4_EN_TX_POLL_MODER 16
160 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
162 #define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD)
163 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
164 #define HEADER_COPY_SIZE (128)
165 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN)
167 #define MLX4_EN_MIN_MTU 46
168 #define ETH_BCAST 0xffffffffffffULL
170 #define MLX4_EN_LOOPBACK_RETRIES 5
171 #define MLX4_EN_LOOPBACK_TIMEOUT 100
173 #ifdef MLX4_EN_PERF_STAT
174 /* Number of samples to 'average' */
176 #define AVG_FACTOR 1024
178 #define INC_PERF_COUNTER(cnt) (++(cnt))
179 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
180 #define AVG_PERF_COUNTER(cnt, sample) \
181 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
182 #define GET_PERF_COUNTER(cnt) (cnt)
183 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
187 #define INC_PERF_COUNTER(cnt) do {} while (0)
188 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
189 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
190 #define GET_PERF_COUNTER(cnt) (0)
191 #define GET_AVG_PERF_COUNTER(cnt) (0)
192 #endif /* MLX4_EN_PERF_STAT */
207 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
208 #define XNOR(x, y) (!(x) == !(y))
209 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
211 struct mlx4_en_tx_info {
212 bus_dmamap_t dma_map;
219 #define MLX4_EN_BIT_DESC_OWN 0x80000000
220 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
221 #define MLX4_EN_MEMTYPE_PAD 0x100
222 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
225 struct mlx4_en_tx_desc {
226 struct mlx4_wqe_ctrl_seg ctrl;
228 struct mlx4_wqe_data_seg data; /* at least one data segment */
229 struct mlx4_wqe_lso_seg lso;
230 struct mlx4_wqe_inline_seg inl;
234 #define MLX4_EN_USE_SRQ 0x01000000
236 #define MLX4_EN_RX_BUDGET 64
238 #define MLX4_EN_TX_MAX_DESC_SIZE 512 /* bytes */
239 #define MLX4_EN_TX_MAX_MBUF_SIZE 65536 /* bytes */
240 #define MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536 /* bytes */
241 #define MLX4_EN_TX_MAX_MBUF_FRAGS \
242 ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
243 #define MLX4_EN_TX_WQE_MAX_WQEBBS \
244 (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */
246 #define MLX4_EN_CX3_LOW_ID 0x1000
247 #define MLX4_EN_CX3_HIGH_ID 0x1005
249 struct mlx4_en_tx_ring {
251 bus_dma_tag_t dma_tag;
252 struct mlx4_hwq_resources wqres;
253 u32 size ; /* number of TXBBs */
256 u16 cqn; /* index of port CQ associated with this ring */
264 struct mlx4_en_tx_info *tx_info;
266 cpuset_t affinity_mask;
270 struct mlx4_qp_context context;
272 enum mlx4_qp_state qp_state;
273 struct mlx4_srq dummy;
275 unsigned long packets;
276 unsigned long tx_csum;
277 unsigned long queue_stopped;
278 unsigned long oversized_packets;
279 unsigned long wake_queue;
282 int hwtstamp_tx_type;
283 spinlock_t comp_lock;
288 struct mlx4_en_rx_desc {
289 /* actual number of entries depends on rx ring stride */
290 struct mlx4_wqe_data_seg data[0];
293 struct mlx4_en_rx_mbuf {
294 bus_dmamap_t dma_map;
298 struct mlx4_en_rx_spare {
299 bus_dmamap_t dma_map;
304 struct mlx4_en_rx_ring {
305 struct mlx4_hwq_resources wqres;
306 bus_dma_tag_t dma_tag;
307 struct mlx4_en_rx_spare spare;
308 u32 size ; /* number of Rx descs*/
313 u16 cqn; /* index of port CQ associated with this ring */
324 struct mlx4_en_rx_mbuf *mbuf;
325 unsigned long errors;
327 unsigned long packets;
328 #ifdef LL_EXTENDED_STATS
329 unsigned long yields;
330 unsigned long misses;
331 unsigned long cleaned;
333 unsigned long csum_ok;
334 unsigned long csum_none;
335 int hwtstamp_rx_filter;
340 static inline int mlx4_en_can_lro(__be16 status)
342 const __be16 status_all = cpu_to_be16(
343 MLX4_CQE_STATUS_IPV4 |
344 MLX4_CQE_STATUS_IPV4F |
345 MLX4_CQE_STATUS_IPV6 |
346 MLX4_CQE_STATUS_IPV4OPT |
347 MLX4_CQE_STATUS_TCP |
348 MLX4_CQE_STATUS_UDP |
349 MLX4_CQE_STATUS_IPOK);
350 const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
351 MLX4_CQE_STATUS_IPV4 |
352 MLX4_CQE_STATUS_IPOK |
353 MLX4_CQE_STATUS_TCP);
354 const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
355 MLX4_CQE_STATUS_IPV6 |
356 MLX4_CQE_STATUS_IPOK |
357 MLX4_CQE_STATUS_TCP);
359 status &= status_all;
360 return (status == status_ipv4_ipok_tcp ||
361 status == status_ipv6_ipok_tcp);
366 struct mlx4_hwq_resources wqres;
369 struct net_device *dev;
370 /* Per-core Tx cq processing support */
371 struct timer_list timer;
378 struct mlx4_cqe *buf;
380 struct taskqueue *tq;
381 #define MLX4_EN_OPCODE_ERROR 0x1e
384 u32 curr_poll_rx_cpu_id;
386 #ifdef CONFIG_NET_RX_BUSY_POLL
388 #define MLX4_EN_CQ_STATEIDLE 0
389 #define MLX4_EN_CQ_STATENAPI 1 /* NAPI owns this CQ */
390 #define MLX4_EN_CQ_STATEPOLL 2 /* poll owns this CQ */
391 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATENAPI | MLX4_EN_CQ_STATEPOLL)
392 #define MLX4_EN_CQ_STATENAPI_YIELD 4 /* NAPI yielded this CQ */
393 #define MLX4_EN_CQ_STATEPOLL_YIELD 8 /* poll yielded this CQ */
394 #define CQ_YIELD (MLX4_EN_CQ_STATENAPI_YIELD | MLX4_EN_CQ_STATEPOLL_YIELD)
395 #define CQ_USER_PEND (MLX4_EN_CQ_STATEPOLL | MLX4_EN_CQ_STATEPOLL_YIELD)
396 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
397 #endif /* CONFIG_NET_RX_BUSY_POLL */
400 struct mlx4_en_port_profile {
413 struct mlx4_en_profile {
420 u8 num_tx_rings_p_up;
421 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
425 struct mlx4_dev *dev;
426 struct pci_dev *pdev;
427 struct mutex state_lock;
428 struct net_device *pndev[MLX4_MAX_PORTS + 1];
431 struct mlx4_en_profile profile;
433 struct workqueue_struct *workqueue;
434 struct device *dma_device;
435 void __iomem *uar_map;
436 struct mlx4_uar priv_uar;
440 u8 mac_removed[MLX4_MAX_PORTS + 1];
441 unsigned long last_overflow_check;
442 unsigned long overflow_period;
446 struct mlx4_en_rss_map {
448 struct mlx4_qp qps[MAX_RX_RINGS];
449 enum mlx4_qp_state state[MAX_RX_RINGS];
450 struct mlx4_qp indir_qp;
451 enum mlx4_qp_state indir_state;
454 struct mlx4_en_port_state {
461 enum mlx4_en_mclist_act {
467 struct mlx4_en_mc_list {
468 struct list_head list;
469 enum mlx4_en_mclist_act action;
474 #ifdef CONFIG_MLX4_EN_DCB
475 /* Minimal TC BW - setting to 0 will block traffic */
476 #define MLX4_EN_BW_MIN 1
477 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
479 #define MLX4_EN_TC_ETS 7
485 MLX4_EN_FLAG_PROMISC = (1 << 0),
486 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
487 /* whether we need to enable hardware loopback by putting dmac
490 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
491 /* whether we need to drop packets that hardware loopback-ed */
492 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
493 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
494 #ifdef CONFIG_MLX4_EN_DCB
495 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5)
499 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
500 #define MLX4_EN_MAC_HASH_IDX 5
504 struct mlx4_dev *dev;
509 struct mlx4_en_priv {
510 struct mlx4_en_dev *mdev;
511 struct mlx4_en_port_profile *prof;
512 struct net_device *dev;
513 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
514 struct mlx4_en_port_state port_state;
515 spinlock_t stats_lock;
516 /* To allow rules removal while port is going down */
517 struct list_head ethtool_list;
519 unsigned long last_moder_packets[MAX_RX_RINGS];
520 unsigned long last_moder_tx_packets;
521 unsigned long last_moder_bytes[MAX_RX_RINGS];
522 unsigned long last_moder_jiffies;
523 int last_moder_time[MAX_RX_RINGS];
533 u32 adaptive_rx_coal;
536 u32 validate_loopback;
538 struct mlx4_hwq_resources res;
546 unsigned char current_mac[ETH_ALEN + 2];
553 struct mlx4_en_rss_map rss_map;
555 u8 num_tx_rings_p_up;
563 struct mlx4_en_tx_ring **tx_ring;
564 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
565 struct mlx4_en_cq **tx_cq;
566 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
567 struct mlx4_qp drop_qp;
568 struct work_struct rx_mode_task;
569 struct work_struct watchdog_task;
570 struct work_struct linkstate_task;
571 struct delayed_work stats_task;
572 struct delayed_work service_task;
573 struct mlx4_en_perf_stats pstats;
574 struct mlx4_en_pkt_stats pkstats;
575 struct mlx4_en_flow_stats flowstats[MLX4_NUM_PRIORITIES];
576 struct mlx4_en_port_stats port_stats;
577 struct mlx4_en_vport_stats vport_stats;
578 struct mlx4_en_vf_stats vf_stats;
579 DECLARE_BITMAP(stats_bitmap, NUM_ALL_STATS);
580 struct list_head mc_list;
581 struct list_head curr_list;
583 struct mlx4_en_stat_out_mbox hw_stats;
587 struct dentry *dev_root;
589 eventhandler_tag vlan_attach;
590 eventhandler_tag vlan_detach;
591 struct callout watchdog_timer;
592 struct ifmedia media;
593 volatile int blocked;
594 struct sysctl_oid *sysctl;
595 struct sysctl_ctx_list conf_ctx;
596 struct sysctl_ctx_list stat_ctx;
597 #define MLX4_EN_MAC_HASH_IDX 5
598 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
600 #ifdef CONFIG_MLX4_EN_DCB
602 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
605 #ifdef CONFIG_RFS_ACCEL
606 spinlock_t filters_lock;
608 struct list_head filters;
609 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
611 struct en_port *vf_ports[MLX4_MAX_NUM_VF];
612 unsigned long last_ifq_jiffies;
613 u64 if_counters_rx_errors;
614 u64 if_counters_rx_no_buffer;
618 MLX4_EN_WOL_MAGIC = (1ULL << 61),
619 MLX4_EN_WOL_ENABLED = (1ULL << 62),
622 struct mlx4_mac_entry {
623 struct hlist_node hlist;
624 unsigned char mac[ETH_ALEN + 2];
628 #ifdef CONFIG_NET_RX_BUSY_POLL
629 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
631 spin_lock_init(&cq->poll_lock);
632 cq->state = MLX4_EN_CQ_STATEIDLE;
635 /* called from the device poll rutine to get ownership of a cq */
636 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
639 spin_lock(&cq->poll_lock);
640 if (cq->state & MLX4_CQ_LOCKED) {
641 WARN_ON(cq->state & MLX4_EN_CQ_STATENAPI);
642 cq->state |= MLX4_EN_CQ_STATENAPI_YIELD;
645 /* we don't care if someone yielded */
646 cq->state = MLX4_EN_CQ_STATENAPI;
647 spin_unlock(&cq->poll_lock);
651 /* returns true is someone tried to get the cq while napi had it */
652 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
655 spin_lock(&cq->poll_lock);
656 WARN_ON(cq->state & (MLX4_EN_CQ_STATEPOLL |
657 MLX4_EN_CQ_STATENAPI_YIELD));
659 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD)
661 cq->state = MLX4_EN_CQ_STATEIDLE;
662 spin_unlock(&cq->poll_lock);
666 /* called from mlx4_en_low_latency_poll() */
667 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
670 spin_lock_bh(&cq->poll_lock);
671 if ((cq->state & MLX4_CQ_LOCKED)) {
672 struct net_device *dev = cq->dev;
673 struct mlx4_en_priv *priv = netdev_priv(dev);
674 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
676 cq->state |= MLX4_EN_CQ_STATEPOLL_YIELD;
678 #ifdef LL_EXTENDED_STATS
682 /* preserve yield marks */
683 cq->state |= MLX4_EN_CQ_STATEPOLL;
684 spin_unlock_bh(&cq->poll_lock);
688 /* returns true if someone tried to get the cq while it was locked */
689 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
692 spin_lock_bh(&cq->poll_lock);
693 WARN_ON(cq->state & (MLX4_EN_CQ_STATENAPI));
695 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD)
697 cq->state = MLX4_EN_CQ_STATEIDLE;
698 spin_unlock_bh(&cq->poll_lock);
702 /* true if a socket is polling, even if it did not get the lock */
703 static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
705 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
706 return cq->state & CQ_USER_PEND;
709 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
713 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
718 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
723 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
728 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
733 static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
737 #endif /* CONFIG_NET_RX_BUSY_POLL */
739 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
741 void mlx4_en_destroy_netdev(struct net_device *dev);
742 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
743 struct mlx4_en_port_profile *prof);
745 int mlx4_en_start_port(struct net_device *dev);
746 void mlx4_en_stop_port(struct net_device *dev);
748 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
749 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
751 int mlx4_en_pre_config(struct mlx4_en_priv *priv);
752 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
753 int entries, int ring, enum cq_type mode, int node);
754 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
755 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
757 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
758 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
759 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
761 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
762 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb);
764 int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m);
765 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
766 struct mlx4_en_tx_ring **pring,
767 u32 size, u16 stride, int node, int queue_idx);
768 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
769 struct mlx4_en_tx_ring **pring);
770 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
771 struct mlx4_en_tx_ring *ring,
772 int cq, int user_prio);
773 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
774 struct mlx4_en_tx_ring *ring);
775 void mlx4_en_qflush(struct ifnet *dev);
777 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
778 struct mlx4_en_rx_ring **pring,
780 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
781 struct mlx4_en_rx_ring **pring,
782 u32 size, u16 stride);
783 void mlx4_en_tx_que(void *context, int pending);
784 void mlx4_en_rx_que(void *context, int pending);
785 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
786 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
787 struct mlx4_en_rx_ring *ring);
788 int mlx4_en_process_rx_cq(struct net_device *dev,
789 struct mlx4_en_cq *cq,
791 void mlx4_en_poll_tx_cq(unsigned long data);
792 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
793 int is_tx, int rss, int qpn, int cqn, int user_prio,
794 struct mlx4_qp_context *context);
795 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
796 int mlx4_en_map_buffer(struct mlx4_buf *buf);
797 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
798 void mlx4_en_calc_rx_buf(struct net_device *dev);
800 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
801 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
802 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
803 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
804 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
805 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
807 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
808 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
810 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
811 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
812 int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port);
813 void mlx4_en_create_debug_files(struct mlx4_en_priv *priv);
814 void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv);
815 int mlx4_en_register_debugfs(void);
816 void mlx4_en_unregister_debugfs(void);
818 #ifdef CONFIG_MLX4_EN_DCB
819 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
820 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
823 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
825 #ifdef CONFIG_RFS_ACCEL
826 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
827 struct mlx4_en_rx_ring *rx_ring);
830 #define MLX4_EN_NUM_SELF_TEST 5
831 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
832 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
835 * Functions for time stamping
837 #define SKBTX_HW_TSTAMP (1 << 0)
838 #define SKBTX_IN_PROGRESS (1 << 2)
840 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
842 /* Functions for caching and restoring statistics */
843 int mlx4_en_get_sset_count(struct net_device *dev, int sset);
844 void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv,
850 extern const struct ethtool_ops mlx4_en_ethtool_ops;
853 * Defines for link speed - needed by selftest
855 #define MLX4_EN_LINK_SPEED_1G 1000
856 #define MLX4_EN_LINK_SPEED_10G 10000
857 #define MLX4_EN_LINK_SPEED_40G 40000
860 NETIF_MSG_DRV = 0x0001,
861 NETIF_MSG_PROBE = 0x0002,
862 NETIF_MSG_LINK = 0x0004,
863 NETIF_MSG_TIMER = 0x0008,
864 NETIF_MSG_IFDOWN = 0x0010,
865 NETIF_MSG_IFUP = 0x0020,
866 NETIF_MSG_RX_ERR = 0x0040,
867 NETIF_MSG_TX_ERR = 0x0080,
868 NETIF_MSG_TX_QUEUED = 0x0100,
869 NETIF_MSG_INTR = 0x0200,
870 NETIF_MSG_TX_DONE = 0x0400,
871 NETIF_MSG_RX_STATUS = 0x0800,
872 NETIF_MSG_PKTDATA = 0x1000,
873 NETIF_MSG_HW = 0x2000,
874 NETIF_MSG_WOL = 0x4000,
879 * printk / logging functions
882 #define en_print(level, priv, format, arg...) \
884 if ((priv)->registered) \
885 printk(level "%s: %s: " format, DRV_NAME, \
886 (priv->dev)->if_xname, ## arg); \
888 printk(level "%s: %s: Port %d: " format, \
889 DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
890 (priv)->port, ## arg); \
894 #define en_dbg(mlevel, priv, format, arg...) \
896 if (NETIF_MSG_##mlevel & priv->msg_enable) \
897 en_print(KERN_DEBUG, priv, format, ##arg); \
899 #define en_warn(priv, format, arg...) \
900 en_print(KERN_WARNING, priv, format, ##arg)
901 #define en_err(priv, format, arg...) \
902 en_print(KERN_ERR, priv, format, ##arg)
903 #define en_info(priv, format, arg...) \
904 en_print(KERN_INFO, priv, format, ## arg)
906 #define mlx4_err(mdev, format, arg...) \
907 pr_err("%s %s: " format, DRV_NAME, \
908 dev_name(&mdev->pdev->dev), ##arg)
909 #define mlx4_info(mdev, format, arg...) \
910 pr_info("%s %s: " format, DRV_NAME, \
911 dev_name(&mdev->pdev->dev), ##arg)
912 #define mlx4_warn(mdev, format, arg...) \
913 pr_warning("%s %s: " format, DRV_NAME, \
914 dev_name(&mdev->pdev->dev), ##arg)