2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/module.h>
36 #include <linux/err.h>
38 #include <linux/mlx4/cmd.h>
39 #include <linux/moduleparam.h>
41 #include "mlx4_stats.h"
44 int mlx4_set_4k_mtu = -1;
45 module_param_named(set_4k_mtu, mlx4_set_4k_mtu, int, 0444);
46 MODULE_PARM_DESC(set_4k_mtu,
47 "(Obsolete) attempt to set 4K MTU to all ConnectX ports");
50 #define MLX4_MAC_VALID (1ull << 63)
52 #define MLX4_VLAN_VALID (1u << 31)
53 #define MLX4_VLAN_MASK 0xfff
55 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
59 mutex_init(&table->mutex);
60 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
61 table->entries[i] = 0;
64 table->max = 1 << dev->caps.log_num_macs;
68 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
72 mutex_init(&table->mutex);
73 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
74 table->entries[i] = 0;
77 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
81 static int validate_index(struct mlx4_dev *dev,
82 struct mlx4_mac_table *table, int index)
86 if (index < 0 || index >= table->max || !table->refs[index]) {
87 mlx4_warn(dev, "No valid Mac entry for the given index\n");
93 static int find_index(struct mlx4_dev *dev,
94 struct mlx4_mac_table *table, u64 mac)
98 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
99 if ((mac & MLX4_MAC_MASK) ==
100 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
107 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
110 struct mlx4_cmd_mailbox *mailbox;
114 mailbox = mlx4_alloc_cmd_mailbox(dev);
116 return PTR_ERR(mailbox);
118 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
120 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
122 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
123 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
125 mlx4_free_cmd_mailbox(dev, mailbox);
129 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
131 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
132 struct mlx4_mac_table *table = &info->mac_table;
136 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
137 (unsigned long long) mac, port);
139 mutex_lock(&table->mutex);
140 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
141 if (free < 0 && !table->refs[i]) {
146 if ((mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) &&
148 /* MAC already registered, Must not have duplicates */
155 mlx4_dbg(dev, "Free MAC index is %d\n", free);
157 if (table->total == table->max) {
158 /* No free mac entries */
163 /* Register new MAC */
164 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
166 err = mlx4_set_port_mac_table(dev, port, table->entries);
168 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
169 (unsigned long long) mac);
170 table->entries[free] = 0;
173 table->refs[free] = 1;
178 mutex_unlock(&table->mutex);
181 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
183 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
188 if (mlx4_is_mfunc(dev)) {
189 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
190 err = mlx4_cmd_imm(dev, mac, &out_param,
191 ((u32) port) << 8 | (u32) RES_MAC,
192 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
193 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
195 if (err && err == -EINVAL && mlx4_is_slave(dev)) {
196 /* retry using old REG_MAC format */
197 set_param_l(&out_param, port);
198 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
199 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
200 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
202 dev->flags |= MLX4_FLAG_OLD_REG_MAC;
207 return get_param_l(&out_param);
209 return __mlx4_register_mac(dev, port, mac);
211 EXPORT_SYMBOL_GPL(mlx4_register_mac);
213 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
215 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
216 (port - 1) * (1 << dev->caps.log_num_macs);
218 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
220 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
222 struct mlx4_port_info *info;
223 struct mlx4_mac_table *table;
226 if (port < 1 || port > dev->caps.num_ports) {
227 mlx4_warn(dev, "invalid port number (%d), aborting...\n", port);
230 info = &mlx4_priv(dev)->port[port];
231 table = &info->mac_table;
232 mutex_lock(&table->mutex);
234 index = find_index(dev, table, mac);
236 if (validate_index(dev, table, index))
239 if (--table->refs[index]) {
240 mlx4_dbg(dev, "Have more references for index %d,"
241 "no need to modify mac table\n", index);
245 table->entries[index] = 0;
246 mlx4_set_port_mac_table(dev, port, table->entries);
249 mutex_unlock(&table->mutex);
251 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
253 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
257 if (mlx4_is_mfunc(dev)) {
258 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
259 (void) mlx4_cmd_imm(dev, mac, &out_param,
260 ((u32) port) << 8 | (u32) RES_MAC,
261 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
262 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
264 /* use old unregister mac format */
265 set_param_l(&out_param, port);
266 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
267 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
268 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
272 __mlx4_unregister_mac(dev, port, mac);
275 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
277 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
279 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
280 struct mlx4_mac_table *table = &info->mac_table;
281 int index = qpn - info->base_qpn;
284 /* CX1 doesn't support multi-functions */
285 mutex_lock(&table->mutex);
287 err = validate_index(dev, table, index);
291 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
293 err = mlx4_set_port_mac_table(dev, port, table->entries);
295 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
296 (unsigned long long) new_mac);
297 table->entries[index] = 0;
300 mutex_unlock(&table->mutex);
303 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
305 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
308 struct mlx4_cmd_mailbox *mailbox;
312 mailbox = mlx4_alloc_cmd_mailbox(dev);
314 return PTR_ERR(mailbox);
316 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
317 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
318 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
319 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
321 mlx4_free_cmd_mailbox(dev, mailbox);
326 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
328 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
331 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
332 if (table->refs[i] &&
333 (vid == (MLX4_VLAN_MASK &
334 be32_to_cpu(table->entries[i])))) {
335 /* VLAN already registered, increase reference count */
343 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
345 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
348 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
352 mutex_lock(&table->mutex);
354 if (table->total == table->max) {
355 /* No free vlan entries */
360 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
361 if (free < 0 && (table->refs[i] == 0)) {
366 if (table->refs[i] &&
367 (vlan == (MLX4_VLAN_MASK &
368 be32_to_cpu(table->entries[i])))) {
369 /* Vlan already registered, increase references count */
381 /* Register new VLAN */
382 table->refs[free] = 1;
383 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
385 err = mlx4_set_port_vlan_table(dev, port, table->entries);
387 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
388 table->refs[free] = 0;
389 table->entries[free] = 0;
396 mutex_unlock(&table->mutex);
400 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
408 if (mlx4_is_mfunc(dev)) {
409 err = mlx4_cmd_imm(dev, vlan, &out_param,
410 ((u32) port) << 8 | (u32) RES_VLAN,
411 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
412 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
414 *index = get_param_l(&out_param);
418 return __mlx4_register_vlan(dev, port, vlan, index);
420 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
422 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
424 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
427 mutex_lock(&table->mutex);
428 if (mlx4_find_cached_vlan(dev, port, vlan, &index)) {
429 mlx4_warn(dev, "vlan 0x%x is not in the vlan table\n", vlan);
433 if (index < MLX4_VLAN_REGULAR) {
434 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
438 if (--table->refs[index]) {
439 mlx4_dbg(dev, "Have %d more references for index %d, "
440 "no need to modify vlan table\n", table->refs[index],
444 table->entries[index] = 0;
445 mlx4_set_port_vlan_table(dev, port, table->entries);
448 mutex_unlock(&table->mutex);
451 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
455 if (mlx4_is_mfunc(dev)) {
456 (void) mlx4_cmd_imm(dev, vlan, &out_param,
457 ((u32) port) << 8 | (u32) RES_VLAN,
458 RES_OP_RESERVE_AND_MAP,
459 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
463 __mlx4_unregister_vlan(dev, port, vlan);
465 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
467 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
469 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
473 inmailbox = mlx4_alloc_cmd_mailbox(dev);
474 if (IS_ERR(inmailbox))
475 return PTR_ERR(inmailbox);
477 outmailbox = mlx4_alloc_cmd_mailbox(dev);
478 if (IS_ERR(outmailbox)) {
479 mlx4_free_cmd_mailbox(dev, inmailbox);
480 return PTR_ERR(outmailbox);
483 inbuf = inmailbox->buf;
484 outbuf = outmailbox->buf;
485 memset(inbuf, 0, 256);
486 memset(outbuf, 0, 256);
491 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
492 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
494 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
495 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
498 *caps = *(__be32 *) (outbuf + 84);
499 mlx4_free_cmd_mailbox(dev, inmailbox);
500 mlx4_free_cmd_mailbox(dev, outmailbox);
503 static struct mlx4_roce_gid_entry zgid_entry;
505 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave)
508 return MLX4_ROCE_PF_GIDS;
509 if (slave <= ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) % dev->num_vfs))
510 return ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / dev->num_vfs) + 1;
511 return (MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / dev->num_vfs;
514 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave)
519 gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
524 if (slave <= gids % vfs)
525 return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave - 1);
527 return MLX4_ROCE_PF_GIDS + (gids % vfs) + ((gids / vfs) * (slave - 1));
530 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
531 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
533 struct mlx4_priv *priv = mlx4_priv(dev);
534 struct mlx4_port_info *port_info;
535 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
536 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
537 struct mlx4_set_port_rqp_calc_context *qpn_context;
538 struct mlx4_set_port_general_context *gen_context;
539 struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1;
540 int reset_qkey_viols;
552 __be32 slave_cap_mask;
555 port = in_mod & 0xff;
556 in_modifier = (in_mod >> 8) & 0xff;
558 port_info = &priv->port[port];
563 /* Slaves cannot perform SET_PORT operations except changing MTU */
565 if (slave != dev->caps.function &&
566 in_modifier != MLX4_SET_PORT_GENERAL &&
567 in_modifier != MLX4_SET_PORT_GID_TABLE) {
568 mlx4_warn(dev, "denying SET_PORT for slave:%d,"
569 "port %d, config_select 0x%x\n",
570 slave, port, in_modifier);
573 switch (in_modifier) {
574 case MLX4_SET_PORT_RQP_CALC:
575 qpn_context = inbox->buf;
576 qpn_context->base_qpn =
577 cpu_to_be32(port_info->base_qpn);
578 qpn_context->n_mac = 0x7;
579 promisc = be32_to_cpu(qpn_context->promisc) >>
580 SET_PORT_PROMISC_SHIFT;
581 qpn_context->promisc = cpu_to_be32(
582 promisc << SET_PORT_PROMISC_SHIFT |
583 port_info->base_qpn);
584 promisc = be32_to_cpu(qpn_context->mcast) >>
585 SET_PORT_MC_PROMISC_SHIFT;
586 qpn_context->mcast = cpu_to_be32(
587 promisc << SET_PORT_MC_PROMISC_SHIFT |
588 port_info->base_qpn);
590 case MLX4_SET_PORT_GENERAL:
591 gen_context = inbox->buf;
592 /* Mtu is configured as the max MTU among all the
593 * the functions on the port. */
594 mtu = be16_to_cpu(gen_context->mtu);
595 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
596 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
597 prev_mtu = slave_st->mtu[port];
598 slave_st->mtu[port] = mtu;
599 if (mtu > master->max_mtu[port])
600 master->max_mtu[port] = mtu;
601 if (mtu < prev_mtu && prev_mtu ==
602 master->max_mtu[port]) {
603 slave_st->mtu[port] = mtu;
604 master->max_mtu[port] = mtu;
605 for (i = 0; i < dev->num_slaves; i++) {
606 master->max_mtu[port] =
607 max(master->max_mtu[port],
608 master->slave_state[i].mtu[port]);
612 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
614 case MLX4_SET_PORT_GID_TABLE:
615 /* change to MULTIPLE entries: number of guest's gids
616 * need a FOR-loop here over number of gids the guest has.
617 * 1. Check no duplicates in gids passed by slave
619 num_gids = mlx4_get_slave_num_gids(dev, slave);
620 base = mlx4_get_base_gid_ix(dev, slave);
621 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
622 for (i = 0; i < num_gids; gid_entry_mbox++, i++) {
623 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
626 gid_entry_mb1 = gid_entry_mbox + 1;
627 for (j = i + 1; j < num_gids; gid_entry_mb1++, j++) {
628 if (!memcmp(gid_entry_mb1->raw,
629 zgid_entry.raw, sizeof(zgid_entry)))
631 if (!memcmp(gid_entry_mb1->raw, gid_entry_mbox->raw,
632 sizeof(gid_entry_mbox->raw))) {
633 /* found duplicate */
639 /* 2. Check that do not have duplicates in OTHER
640 * entries in the port GID table
642 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
643 if (i >= base && i < base + num_gids)
644 continue; /* don't compare to slave's current gids */
645 gid_entry_tbl = &priv->roce_gids[port - 1][i];
646 if (!memcmp(gid_entry_tbl->raw, zgid_entry.raw, sizeof(zgid_entry)))
648 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
649 for (j = 0; j < num_gids; gid_entry_mbox++, j++) {
650 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
653 if (!memcmp(gid_entry_mbox->raw, gid_entry_tbl->raw,
654 sizeof(gid_entry_tbl->raw))) {
655 /* found duplicate */
656 mlx4_warn(dev, "requested gid entry for slave:%d "
657 "is a duplicate of gid at index %d\n",
664 /* insert slave GIDs with memcpy, starting at slave's base index */
665 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
666 for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++)
667 memcpy(priv->roce_gids[port - 1][offset].raw, gid_entry_mbox->raw, 16);
669 /* Now, copy roce port gids table to current mailbox for passing to FW */
670 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
671 for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
672 memcpy(gid_entry_mbox->raw, priv->roce_gids[port - 1][i].raw, 16);
676 return mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
677 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
681 /* For IB, we only consider:
682 * - The capability mask, which is set to the aggregate of all
683 * slave function capabilities
684 * - The QKey violatin counter - reset according to each request.
687 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
688 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
689 new_cap_mask = ((__be32 *) inbox->buf)[2];
691 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
692 new_cap_mask = ((__be32 *) inbox->buf)[1];
695 /* slave may not set the IS_SM capability for the port */
696 if (slave != mlx4_master_func_num(dev) &&
697 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
700 /* No DEV_MGMT in multifunc mode */
701 if (mlx4_is_mfunc(dev) &&
702 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
707 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
708 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
709 for (i = 0; i < dev->num_slaves; i++)
711 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
713 /* only clear mailbox for guests. Master may be setting
714 * MTU or PKEY table size
716 if (slave != dev->caps.function)
717 memset(inbox->buf, 0, 256);
718 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
719 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
720 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
722 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
723 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
726 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
727 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
729 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
734 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
735 struct mlx4_vhcr *vhcr,
736 struct mlx4_cmd_mailbox *inbox,
737 struct mlx4_cmd_mailbox *outbox,
738 struct mlx4_cmd_info *cmd)
740 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
741 vhcr->op_modifier, inbox);
744 /* bit locations for set port command with zero op modifier */
746 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
747 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
748 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
749 MLX4_CHANGE_PORT_VL_CAP = 21,
750 MLX4_CHANGE_PORT_MTU_CAP = 22,
753 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
755 struct mlx4_cmd_mailbox *mailbox;
756 int err = -EINVAL, vl_cap, pkey_tbl_flag = 0;
759 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_NONE)
762 mailbox = mlx4_alloc_cmd_mailbox(dev);
764 return PTR_ERR(mailbox);
766 memset(mailbox->buf, 0, 256);
768 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
769 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
770 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1,
771 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
774 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
776 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
778 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
781 /* IB VL CAP enum isn't used by the firmware, just numerical values */
782 for (vl_cap = dev->caps.vl_cap[port];
783 vl_cap >= 1; vl_cap >>= 1) {
784 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
785 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
786 (1 << MLX4_CHANGE_PORT_VL_CAP) |
787 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
788 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
789 (vl_cap << MLX4_SET_PORT_VL_CAP));
790 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
791 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
797 mlx4_free_cmd_mailbox(dev, mailbox);
801 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
802 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
804 struct mlx4_cmd_mailbox *mailbox;
805 struct mlx4_set_port_general_context *context;
809 mailbox = mlx4_alloc_cmd_mailbox(dev);
811 return PTR_ERR(mailbox);
812 context = mailbox->buf;
813 memset(context, 0, sizeof *context);
815 context->flags = SET_PORT_GEN_ALL_VALID;
816 context->mtu = cpu_to_be16(mtu);
817 context->pptx = (pptx * (!pfctx)) << 7;
818 context->pfctx = pfctx;
819 context->pprx = (pprx * (!pfcrx)) << 7;
820 context->pfcrx = pfcrx;
822 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
823 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
824 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
826 mlx4_free_cmd_mailbox(dev, mailbox);
829 EXPORT_SYMBOL(mlx4_SET_PORT_general);
831 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
834 struct mlx4_cmd_mailbox *mailbox;
835 struct mlx4_set_port_rqp_calc_context *context;
838 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
839 MCAST_DIRECT : MCAST_DEFAULT;
841 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
844 mailbox = mlx4_alloc_cmd_mailbox(dev);
846 return PTR_ERR(mailbox);
847 context = mailbox->buf;
848 memset(context, 0, sizeof *context);
850 context->base_qpn = cpu_to_be32(base_qpn);
851 context->n_mac = dev->caps.log_num_macs;
852 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
854 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
856 context->intra_no_vlan = 0;
857 context->no_vlan = MLX4_NO_VLAN_IDX;
858 context->intra_vlan_miss = 0;
859 context->vlan_miss = MLX4_VLAN_MISS_IDX;
861 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
862 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
863 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
865 mlx4_free_cmd_mailbox(dev, mailbox);
868 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
870 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
872 struct mlx4_cmd_mailbox *mailbox;
873 struct mlx4_set_port_prio2tc_context *context;
878 mailbox = mlx4_alloc_cmd_mailbox(dev);
880 return PTR_ERR(mailbox);
881 context = mailbox->buf;
882 memset(context, 0, sizeof *context);
884 for (i = 0; i < MLX4_NUM_UP; i += 2)
885 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
887 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
888 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
889 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
891 mlx4_free_cmd_mailbox(dev, mailbox);
894 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
896 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
897 u8 *pg, u16 *ratelimit)
899 struct mlx4_cmd_mailbox *mailbox;
900 struct mlx4_set_port_scheduler_context *context;
905 mailbox = mlx4_alloc_cmd_mailbox(dev);
907 return PTR_ERR(mailbox);
908 context = mailbox->buf;
909 memset(context, 0, sizeof *context);
911 for (i = 0; i < MLX4_NUM_TC; i++) {
912 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
914 if (ratelimit && ratelimit[i]) {
915 if (ratelimit[i] <= MLX4_MAX_100M_UNITS_VAL) {
918 htons(MLX4_RATELIMIT_100M_UNITS);
922 htons(MLX4_RATELIMIT_1G_UNITS);
924 tc->max_bw_value = htons(r);
926 tc->max_bw_value = htons(MLX4_RATELIMIT_DEFAULT);
927 tc->max_bw_units = htons(MLX4_RATELIMIT_1G_UNITS);
930 tc->pg = htons(pg[i]);
931 tc->bw_precentage = htons(tc_tx_bw[i]);
934 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
935 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
936 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
938 mlx4_free_cmd_mailbox(dev, mailbox);
941 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
943 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
944 struct mlx4_vhcr *vhcr,
945 struct mlx4_cmd_mailbox *inbox,
946 struct mlx4_cmd_mailbox *outbox,
947 struct mlx4_cmd_info *cmd)
954 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
955 u64 mac, u64 clear, u8 mode)
957 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
958 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
961 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
963 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd)
974 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
975 struct mlx4_vhcr *vhcr,
976 struct mlx4_cmd_mailbox *inbox,
977 struct mlx4_cmd_mailbox *outbox,
978 struct mlx4_cmd_info *cmd)
983 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, unsigned long *stats_bitmap)
987 bitmap_zero(stats_bitmap, NUM_ALL_STATS);
989 if (mlx4_is_slave(dev)) {
990 last_i = dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN ?
991 NUM_PKT_STATS + NUM_FLOW_STATS : NUM_PKT_STATS;
993 bitmap_set(stats_bitmap, last_i, NUM_PKT_STATS);
994 last_i = NUM_PKT_STATS;
996 if (dev->caps.flags2 &
997 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
998 bitmap_set(stats_bitmap, last_i, NUM_FLOW_STATS);
999 last_i += NUM_FLOW_STATS;
1003 if (mlx4_is_slave(dev))
1004 bitmap_set(stats_bitmap, last_i, NUM_VF_STATS);
1005 last_i += NUM_VF_STATS;
1007 if (mlx4_is_master(dev))
1008 bitmap_set(stats_bitmap, last_i, NUM_VPORT_STATS);
1009 last_i += NUM_VPORT_STATS;
1011 bitmap_set(stats_bitmap, last_i, NUM_PORT_STATS);
1013 EXPORT_SYMBOL(mlx4_set_stats_bitmap);
1015 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id)
1017 struct mlx4_priv *priv = mlx4_priv(dev);
1018 int i, found_ix = -1;
1019 int vf_gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1021 if (!mlx4_is_mfunc(dev))
1024 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
1025 if (!memcmp(priv->roce_gids[port - 1][i].raw, gid, 16)) {
1031 if (found_ix >= 0) {
1032 if (found_ix < MLX4_ROCE_PF_GIDS)
1034 else if (found_ix < MLX4_ROCE_PF_GIDS + (vf_gids % dev->num_vfs) *
1035 (vf_gids / dev->num_vfs + 1))
1036 *slave_id = ((found_ix - MLX4_ROCE_PF_GIDS) /
1037 (vf_gids / dev->num_vfs + 1)) + 1;
1040 ((found_ix - MLX4_ROCE_PF_GIDS -
1041 ((vf_gids % dev->num_vfs) * ((vf_gids / dev->num_vfs + 1)))) /
1042 (vf_gids / dev->num_vfs)) + vf_gids % dev->num_vfs + 1;
1045 return (found_ix >= 0) ? 0 : -EINVAL;
1047 EXPORT_SYMBOL(mlx4_get_slave_from_roce_gid);
1049 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid)
1051 struct mlx4_priv *priv = mlx4_priv(dev);
1053 if (!mlx4_is_master(dev))
1056 memcpy(gid, priv->roce_gids[port - 1][slave_id].raw, 16);
1059 EXPORT_SYMBOL(mlx4_get_roce_gid_from_slave);
1061 /* Cable Module Info */
1062 #define MODULE_INFO_MAX_READ 48
1064 #define I2C_ADDR_LOW 0x50
1065 #define I2C_ADDR_HIGH 0x51
1066 #define I2C_PAGE_SIZE 256
1068 /* Module Info Data */
1069 struct mlx4_cable_info {
1072 __be16 dev_mem_address;
1075 __be32 reserved2[2];
1076 u8 data[MODULE_INFO_MAX_READ];
1079 enum cable_info_err {
1080 CABLE_INF_INV_PORT = 0x1,
1081 CABLE_INF_OP_NOSUP = 0x2,
1082 CABLE_INF_NOT_CONN = 0x3,
1083 CABLE_INF_NO_EEPRM = 0x4,
1084 CABLE_INF_PAGE_ERR = 0x5,
1085 CABLE_INF_INV_ADDR = 0x6,
1086 CABLE_INF_I2C_ADDR = 0x7,
1087 CABLE_INF_QSFP_VIO = 0x8,
1088 CABLE_INF_I2C_BUSY = 0x9,
1091 #define MAD_STATUS_2_CABLE_ERR(mad_status) ((mad_status >> 8) & 0xFF)
1094 static inline const char *cable_info_mad_err_str(u16 mad_status)
1096 u8 err = MAD_STATUS_2_CABLE_ERR(mad_status);
1099 case CABLE_INF_INV_PORT:
1100 return "invalid port selected";
1101 case CABLE_INF_OP_NOSUP:
1102 return "operation not supported for this port (the port is of type CX4 or internal)";
1103 case CABLE_INF_NOT_CONN:
1104 return "cable is not connected";
1105 case CABLE_INF_NO_EEPRM:
1106 return "the connected cable has no EPROM (passive copper cable)";
1107 case CABLE_INF_PAGE_ERR:
1108 return "page number is greater than 15";
1109 case CABLE_INF_INV_ADDR:
1110 return "invalid device_address or size (that is, size equals 0 or address+size is greater than 256)";
1111 case CABLE_INF_I2C_ADDR:
1112 return "invalid I2C slave address";
1113 case CABLE_INF_QSFP_VIO:
1114 return "at least one cable violates the QSFP specification and ignores the modsel signal";
1115 case CABLE_INF_I2C_BUSY:
1116 return "I2C bus is constantly busy";
1118 return "Unknown Error";
1123 * mlx4_get_module_info - Read cable module eeprom data
1125 * @port: port number.
1126 * @offset: byte offset in eeprom to start reading data from.
1127 * @size: num of bytes to read.
1128 * @data: output buffer to put the requested data into.
1130 * Reads cable module eeprom data, puts the outcome data into
1131 * data pointer paramer.
1132 * Returns num of read bytes on success or a negative error
1135 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, u16 offset,
1138 struct mlx4_cmd_mailbox *inbox, *outbox;
1139 struct mlx4_mad_ifc *inmad, *outmad;
1140 struct mlx4_cable_info *cable_info;
1144 if (size > MODULE_INFO_MAX_READ)
1145 size = MODULE_INFO_MAX_READ;
1147 inbox = mlx4_alloc_cmd_mailbox(dev);
1148 if (IS_ERR(inbox)) {
1150 "mlx4_alloc_cmd_mailbox returned with error(%lx)", PTR_ERR(inbox));
1151 return PTR_ERR(inbox);
1154 outbox = mlx4_alloc_cmd_mailbox(dev);
1155 if (IS_ERR(outbox)) {
1156 mlx4_free_cmd_mailbox(dev, inbox);
1158 "mlx4_alloc_cmd_mailbox returned with error(%lx)", PTR_ERR(outbox));
1159 return PTR_ERR(outbox);
1162 inmad = (struct mlx4_mad_ifc *)(inbox->buf);
1163 outmad = (struct mlx4_mad_ifc *)(outbox->buf);
1165 inmad->method = 0x1; /* Get */
1166 inmad->class_version = 0x1;
1167 inmad->mgmt_class = 0x1;
1168 inmad->base_version = 0x1;
1169 inmad->attr_id = cpu_to_be16(0xFF60); /* Module Info */
1171 if (offset < I2C_PAGE_SIZE && offset + size > I2C_PAGE_SIZE)
1172 /* Cross pages reads are not allowed
1173 * read until offset 256 in low page
1175 size -= offset + size - I2C_PAGE_SIZE;
1177 i2c_addr = I2C_ADDR_LOW;
1178 if (offset >= I2C_PAGE_SIZE) {
1179 /* Reset offset to high page */
1180 i2c_addr = I2C_ADDR_HIGH;
1181 offset -= I2C_PAGE_SIZE;
1184 cable_info = (struct mlx4_cable_info *)inmad->data;
1185 cable_info->dev_mem_address = cpu_to_be16(offset);
1186 cable_info->page_num = 0;
1187 cable_info->i2c_addr = i2c_addr;
1188 cable_info->size = cpu_to_be16(size);
1190 ret = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
1191 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1195 if (be16_to_cpu(outmad->status)) {
1196 /* Mad returned with bad status */
1197 ret = be16_to_cpu(outmad->status);
1199 mlx4_warn(dev, "MLX4_CMD_MAD_IFC Get Module info attr(%x) "
1200 "port(%d) i2c_addr(%x) offset(%d) size(%d): Response "
1201 "Mad Status(%x) - %s\n", 0xFF60, port, i2c_addr, offset,
1202 size, ret, cable_info_mad_err_str(ret));
1204 if (i2c_addr == I2C_ADDR_HIGH &&
1205 MAD_STATUS_2_CABLE_ERR(ret) == CABLE_INF_I2C_ADDR)
1206 /* Some SFP cables do not support i2c slave
1207 * address 0x51 (high page), abort silently.
1214 cable_info = (struct mlx4_cable_info *)outmad->data;
1215 memcpy(data, cable_info->data, size);
1218 mlx4_free_cmd_mailbox(dev, inbox);
1219 mlx4_free_cmd_mailbox(dev, outbox);
1222 EXPORT_SYMBOL(mlx4_get_module_info);