2 * Copyright (c) 2013 The FreeBSD Foundation
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #if defined(__amd64__) /* || defined(__ia64__) */
41 #include <sys/param.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/memdesc.h>
47 #include <sys/module.h>
49 #include <sys/rwlock.h>
51 #include <sys/taskqueue.h>
53 #include <machine/bus.h>
54 #include <contrib/dev/acpica/include/acpi.h>
55 #include <contrib/dev/acpica/include/accommon.h>
56 #include <dev/acpica/acpivar.h>
58 #include <vm/vm_extern.h>
59 #include <vm/vm_kern.h>
60 #include <vm/vm_object.h>
61 #include <vm/vm_page.h>
62 #include <vm/vm_pager.h>
63 #include <vm/vm_map.h>
64 #include <x86/include/busdma_impl.h>
65 #include <x86/iommu/intel_reg.h>
66 #include <x86/iommu/busdma_dmar.h>
67 #include <x86/iommu/intel_dmar.h>
68 #include <dev/pci/pcivar.h>
74 #define DMAR_FAULT_IRQ_RID 0
75 #define DMAR_QI_IRQ_RID 1
76 #define DMAR_REG_RID 2
78 static devclass_t dmar_devclass;
79 static device_t *dmar_devs;
80 static int dmar_devcnt;
82 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
85 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
87 ACPI_TABLE_DMAR *dmartbl;
88 ACPI_DMAR_HEADER *dmarh;
92 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
93 if (ACPI_FAILURE(status))
95 ptr = (char *)dmartbl + sizeof(*dmartbl);
96 ptrend = (char *)dmartbl + dmartbl->Header.Length;
100 dmarh = (ACPI_DMAR_HEADER *)ptr;
101 if (dmarh->Length <= 0) {
102 printf("dmar_identify: corrupted DMAR table, l %d\n",
106 ptr += dmarh->Length;
107 if (!iter(dmarh, arg))
112 struct find_iter_args {
114 ACPI_DMAR_HARDWARE_UNIT *res;
118 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
120 struct find_iter_args *fia;
122 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
127 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
134 static ACPI_DMAR_HARDWARE_UNIT *
135 dmar_find_by_index(int idx)
137 struct find_iter_args fia;
141 dmar_iterate_tbl(dmar_find_iter, &fia);
146 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
149 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
154 static int dmar_enable = 0;
156 dmar_identify(driver_t *driver, device_t parent)
158 ACPI_TABLE_DMAR *dmartbl;
159 ACPI_DMAR_HARDWARE_UNIT *dmarh;
163 if (acpi_disabled("dmar"))
165 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
169 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
171 TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose);
172 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
173 if (ACPI_FAILURE(status))
175 haw = dmartbl->Width + 1;
176 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
177 dmar_high = BUS_SPACE_MAXADDR;
179 dmar_high = 1ULL << (haw + 1);
181 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
182 (unsigned)dmartbl->Flags,
183 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
186 dmar_iterate_tbl(dmar_count_iter, NULL);
187 if (dmar_devcnt == 0)
189 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
191 for (i = 0; i < dmar_devcnt; i++) {
192 dmarh = dmar_find_by_index(i);
194 printf("dmar_identify: cannot find HWUNIT %d\n", i);
197 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
198 if (dmar_devs[i] == NULL) {
199 printf("dmar_identify: cannot create instance %d\n", i);
202 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
203 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
206 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
207 i, (uintmax_t)dmarh->Address, error);
208 device_delete_child(parent, dmar_devs[i]);
215 dmar_probe(device_t dev)
218 if (acpi_get_handle(dev) != NULL)
220 device_set_desc(dev, "DMA remap");
221 return (BUS_PROBE_NOWILDCARD);
225 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
227 struct dmar_msi_data *dmd;
229 dmd = &unit->intrs[idx];
232 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
233 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
234 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
235 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
241 dmar_release_resources(device_t dev, struct dmar_unit *unit)
245 dmar_fini_busdma(unit);
247 dmar_fini_fault_log(unit);
248 for (i = 0; i < DMAR_INTR_TOTAL; i++)
249 dmar_release_intr(dev, unit, i);
250 if (unit->regs != NULL) {
251 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
253 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
257 if (unit->domids != NULL) {
258 delete_unrhdr(unit->domids);
261 if (unit->ctx_obj != NULL) {
262 vm_object_deallocate(unit->ctx_obj);
263 unit->ctx_obj = NULL;
268 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
271 struct dmar_msi_data *dmd;
276 dmd = &unit->intrs[idx];
277 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
278 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
280 device_printf(dev, "cannot allocate %s interrupt, %d\n",
284 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
287 device_printf(dev, "cannot set %s interrupt resource, %d\n",
291 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
292 &dmd->irq_rid, RF_ACTIVE);
293 if (dmd->irq_res == NULL) {
295 "cannot allocate resource for %s interrupt\n", dmd->name);
299 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
300 dmd->handler, NULL, unit, &dmd->intr_handle);
302 device_printf(dev, "cannot setup %s interrupt, %d\n",
306 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, dmd->name);
307 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
309 device_printf(dev, "cannot map %s interrupt, %d\n",
313 dmar_write4(unit, dmd->msi_data_reg, msi_data);
314 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
315 /* Only for xAPIC mode */
316 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
320 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
322 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
324 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
326 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
334 dmar_remap_intr(device_t dev, device_t child, u_int irq)
336 struct dmar_unit *unit;
337 struct dmar_msi_data *dmd;
342 unit = device_get_softc(dev);
343 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
344 dmd = &unit->intrs[i];
345 if (irq == dmd->irq) {
346 error = PCIB_MAP_MSI(device_get_parent(
347 device_get_parent(dev)),
348 dev, irq, &msi_addr, &msi_data);
352 (dmd->disable_intr)(unit);
353 dmar_write4(unit, dmd->msi_data_reg, msi_data);
354 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
355 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
356 (dmd->enable_intr)(unit);
366 dmar_print_caps(device_t dev, struct dmar_unit *unit,
367 ACPI_DMAR_HARDWARE_UNIT *dmaru)
369 uint32_t caphi, ecaphi;
371 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
372 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
373 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
374 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
375 caphi = unit->hw_cap >> 32;
376 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
377 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
378 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
379 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
380 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
381 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
382 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
383 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
384 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
386 ecaphi = unit->hw_ecap >> 32;
387 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
388 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
389 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
390 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
391 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
392 DMAR_ECAP_IRO(unit->hw_ecap));
396 dmar_attach(device_t dev)
398 struct dmar_unit *unit;
399 ACPI_DMAR_HARDWARE_UNIT *dmaru;
402 unit = device_get_softc(dev);
404 unit->unit = device_get_unit(dev);
405 dmaru = dmar_find_by_index(unit->unit);
408 unit->segment = dmaru->Segment;
409 unit->base = dmaru->Address;
410 unit->reg_rid = DMAR_REG_RID;
411 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
412 &unit->reg_rid, RF_ACTIVE);
413 if (unit->regs == NULL) {
414 device_printf(dev, "cannot allocate register window\n");
417 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
418 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
419 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
421 dmar_print_caps(dev, unit, dmaru);
422 dmar_quirks_post_ident(unit);
424 for (i = 0; i < DMAR_INTR_TOTAL; i++)
425 unit->intrs[i].irq = -1;
427 unit->intrs[DMAR_INTR_FAULT].name = "fault";
428 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
429 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
430 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
431 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
432 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
433 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
434 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
435 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
437 dmar_release_resources(dev, unit);
440 if (DMAR_HAS_QI(unit)) {
441 unit->intrs[DMAR_INTR_QI].name = "qi";
442 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
443 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
444 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
445 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
446 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
447 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
448 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
449 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
451 dmar_release_resources(dev, unit);
456 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
457 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
461 * 9.2 "Context Entry":
462 * When Caching Mode (CM) field is reported as Set, the
463 * domain-id value of zero is architecturally reserved.
464 * Software must not use domain-id value of zero
467 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
468 alloc_unr_specific(unit->domids, 0);
470 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
471 DMAR_CTX_CNT), 0, 0, NULL);
474 * Allocate and load the root entry table pointer. Enable the
475 * address translation after the required invalidations are
478 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
480 error = dmar_load_root_entry_ptr(unit);
483 dmar_release_resources(dev, unit);
486 error = dmar_inv_ctx_glob(unit);
489 dmar_release_resources(dev, unit);
492 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
493 error = dmar_inv_iotlb_glob(unit);
496 dmar_release_resources(dev, unit);
502 error = dmar_init_fault_log(unit);
504 dmar_release_resources(dev, unit);
507 error = dmar_init_qi(unit);
509 dmar_release_resources(dev, unit);
512 error = dmar_init_busdma(unit);
514 dmar_release_resources(dev, unit);
520 error = dmar_enable_translation(unit);
523 dmar_release_resources(dev, unit);
533 dmar_detach(device_t dev)
540 dmar_suspend(device_t dev)
547 dmar_resume(device_t dev)
554 static device_method_t dmar_methods[] = {
555 DEVMETHOD(device_identify, dmar_identify),
556 DEVMETHOD(device_probe, dmar_probe),
557 DEVMETHOD(device_attach, dmar_attach),
558 DEVMETHOD(device_detach, dmar_detach),
559 DEVMETHOD(device_suspend, dmar_suspend),
560 DEVMETHOD(device_resume, dmar_resume),
562 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
567 static driver_t dmar_driver = {
570 sizeof(struct dmar_unit),
573 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
574 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
577 dmar_print_path(device_t dev, const char *banner, int busno, int depth,
578 const ACPI_DMAR_PCI_PATH *path)
582 device_printf(dev, "%s [%d, ", banner, busno);
583 for (i = 0; i < depth; i++) {
586 printf("(%d, %d)", path[i].Device, path[i].Function);
592 dmar_dev_depth(device_t child)
594 devclass_t pci_class;
598 pci_class = devclass_find("pci");
599 for (depth = 1; ; depth++) {
600 bus = device_get_parent(child);
601 pcib = device_get_parent(bus);
602 if (device_get_devclass(device_get_parent(pcib)) !=
610 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth)
612 devclass_t pci_class;
615 pci_class = devclass_find("pci");
616 for (depth--; depth != -1; depth--) {
617 path[depth].Device = pci_get_slot(child);
618 path[depth].Function = pci_get_function(child);
619 bus = device_get_parent(child);
620 pcib = device_get_parent(bus);
621 if (device_get_devclass(device_get_parent(pcib)) !=
623 /* reached a host bridge */
624 *busno = pcib_get_bus(bus);
629 panic("wrong depth");
633 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
634 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
635 enum AcpiDmarScopeType scope_type)
639 if (busno1 != busno2)
641 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
646 for (i = 0; i < depth; i++) {
647 if (path1[i].Device != path2[i].Device ||
648 path1[i].Function != path2[i].Function)
655 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev,
656 int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
658 ACPI_DMAR_PCI_PATH *path;
661 if (devscope->Length < sizeof(*devscope)) {
662 printf("dmar_find: corrupted DMAR table, dl %d\n",
666 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
667 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
669 path_len = devscope->Length - sizeof(*devscope);
670 if (path_len % 2 != 0) {
671 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n",
676 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
678 printf("dmar_find: corrupted DMAR table, dl %d\n",
682 if (dmar_match_verbose)
683 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path);
685 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
686 dev_path, dev_path_len, devscope->EntryType));
690 dmar_find(device_t dev)
693 ACPI_DMAR_HARDWARE_UNIT *dmarh;
694 ACPI_DMAR_DEVICE_SCOPE *devscope;
696 int i, match, dev_domain, dev_busno, dev_path_len;
699 dev_domain = pci_get_domain(dev);
700 dev_path_len = dmar_dev_depth(dev);
701 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
702 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
703 if (dmar_match_verbose)
704 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path);
706 for (i = 0; i < dmar_devcnt; i++) {
707 if (dmar_devs[i] == NULL)
709 dmarh = dmar_find_by_index(i);
712 if (dmarh->Segment != dev_domain)
714 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
715 dmar_dev = dmar_devs[i];
716 if (dmar_match_verbose) {
718 "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n",
719 dev_domain, pci_get_bus(dev),
721 pci_get_function(dev),
722 ((struct dmar_unit *)device_get_softc(
727 ptr = (char *)dmarh + sizeof(*dmarh);
728 ptrend = (char *)dmarh + dmarh->Header.Length;
732 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
733 ptr += devscope->Length;
734 if (dmar_match_verbose) {
736 "pci%d:%d:%d:%d matching dmar%d\n",
737 dev_domain, pci_get_bus(dev),
739 pci_get_function(dev),
740 ((struct dmar_unit *)device_get_softc(
741 dmar_devs[i]))->unit);
743 match = dmar_match_devscope(devscope, dev, dev_busno,
744 dev_path, dev_path_len);
745 if (dmar_match_verbose) {
747 printf("table error\n");
749 printf("not matched\n");
755 else if (match == 1) {
756 dmar_dev = dmar_devs[i];
763 return (device_get_softc(dmar_dev));
766 struct rmrr_iter_args {
767 struct dmar_ctx *ctx;
771 ACPI_DMAR_PCI_PATH *dev_path;
773 struct dmar_map_entries_tailq *rmrr_entries;
777 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
779 struct rmrr_iter_args *ria;
780 ACPI_DMAR_RESERVED_MEMORY *resmem;
781 ACPI_DMAR_DEVICE_SCOPE *devscope;
782 struct dmar_map_entry *entry;
786 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
790 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
791 if (dmar_match_verbose) {
792 printf("RMRR [%jx,%jx] segment %d\n",
793 (uintmax_t)resmem->BaseAddress,
794 (uintmax_t)resmem->EndAddress,
797 if (resmem->Segment != ria->dev_domain)
800 ptr = (char *)resmem + sizeof(*resmem);
801 ptrend = (char *)resmem + resmem->Header.Length;
805 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
806 ptr += devscope->Length;
807 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno,
808 ria->dev_path, ria->dev_path_len);
810 if (dmar_match_verbose)
812 entry = dmar_gas_alloc_entry(ria->ctx, DMAR_PGF_WAITOK);
813 entry->start = resmem->BaseAddress;
814 /* The RMRR entry end address is inclusive. */
815 entry->end = resmem->EndAddress;
816 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
818 } else if (dmar_match_verbose) {
819 printf("not matched, err %d\n", match);
827 dmar_ctx_parse_rmrr(struct dmar_ctx *ctx, device_t dev,
828 struct dmar_map_entries_tailq *rmrr_entries)
830 struct rmrr_iter_args ria;
832 ria.dev_domain = pci_get_domain(dev);
833 ria.dev_path_len = dmar_dev_depth(dev);
834 ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len];
835 dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len);
837 if (dmar_match_verbose) {
838 device_printf(dev, "parsing RMRR entries for ");
839 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len,
845 ria.dev_path = dev_path;
846 ria.rmrr_entries = rmrr_entries;
847 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
850 struct inst_rmrr_iter_args {
851 struct dmar_unit *dmar;
855 dmar_path_dev(int segment, int path_len, int busno,
856 const ACPI_DMAR_PCI_PATH *path)
858 devclass_t pci_class;
859 device_t bus, pcib, dev;
862 pci_class = devclass_find("pci");
864 for (i = 0; i < path_len; i++, path++) {
865 dev = pci_find_dbsf(segment, busno, path->Device,
869 if (i != path_len - 1) {
870 bus = device_get_parent(dev);
871 pcib = device_get_parent(bus);
872 if (device_get_devclass(device_get_parent(pcib)) !=
876 busno = pcib_get_bus(dev);
882 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
884 const ACPI_DMAR_RESERVED_MEMORY *resmem;
885 const ACPI_DMAR_DEVICE_SCOPE *devscope;
886 struct inst_rmrr_iter_args *iria;
887 const char *ptr, *ptrend;
888 struct dmar_unit *dev_dmar;
891 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
895 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
896 if (resmem->Segment != iria->dmar->segment)
898 if (dmar_match_verbose) {
899 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
900 (uintmax_t)resmem->BaseAddress,
901 (uintmax_t)resmem->EndAddress);
904 ptr = (const char *)resmem + sizeof(*resmem);
905 ptrend = (const char *)resmem + resmem->Header.Length;
909 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
910 ptr += devscope->Length;
912 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
914 if (dmar_match_verbose) {
915 dmar_print_path(iria->dmar->dev, "RMRR scope",
916 devscope->Bus, (devscope->Length -
917 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
918 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
920 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
921 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
922 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
924 if (dmar_match_verbose)
925 printf("null dev\n");
928 dev_dmar = dmar_find(dev);
929 if (dev_dmar != iria->dmar) {
930 if (dmar_match_verbose) {
931 printf("dmar%d matched, skipping\n",
936 if (dmar_match_verbose)
937 printf("matched, instantiating RMRR context\n");
938 dmar_instantiate_ctx(iria->dmar, dev, true);
946 * Pre-create all contexts for the DMAR which have RMRR entries.
949 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
951 struct inst_rmrr_iter_args iria;
954 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
959 if (dmar_match_verbose)
960 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit);
961 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
963 if (!LIST_EMPTY(&dmar->contexts)) {
964 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
965 ("dmar%d: RMRR not handled but translation is already enabled",
967 error = dmar_enable_translation(dmar);
969 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
975 #include <ddb/db_lex.h>
978 dmar_print_ctx_entry(const struct dmar_map_entry *entry)
980 struct dmar_map_entry *l, *r;
983 " start %jx end %jx free_after %jx free_down %jx flags %x ",
984 entry->start, entry->end, entry->free_after, entry->free_down,
987 l = RB_LEFT(entry, rb_entry);
991 db_printf("%jx ", l->start);
993 r = RB_RIGHT(entry, rb_entry);
997 db_printf("%jx", r->start);
1002 dmar_print_ctx(struct dmar_ctx *ctx, bool show_mappings)
1004 struct dmar_map_entry *entry;
1007 " @%p pci%d:%d:%d dom %d mgaw %d agaw %d pglvl %d end %jx\n"
1008 " refs %d flags %x pgobj %p map_ents %u loads %lu unloads %lu\n",
1009 ctx, pci_get_bus(ctx->ctx_tag.owner),
1010 pci_get_slot(ctx->ctx_tag.owner),
1011 pci_get_function(ctx->ctx_tag.owner), ctx->domain, ctx->mgaw,
1012 ctx->agaw, ctx->pglvl, (uintmax_t)ctx->end, ctx->refs,
1013 ctx->flags, ctx->pgtbl_obj, ctx->entries_cnt, ctx->loads,
1017 db_printf(" mapped:\n");
1018 RB_FOREACH(entry, dmar_gas_entries_tree, &ctx->rb_root) {
1019 dmar_print_ctx_entry(entry);
1025 db_printf(" unloading:\n");
1026 TAILQ_FOREACH(entry, &ctx->unload_entries, dmamap_link) {
1027 dmar_print_ctx_entry(entry);
1033 DB_FUNC(dmar_ctx, db_dmar_print_ctx, db_show_table, CS_OWN, NULL)
1035 struct dmar_unit *unit;
1036 struct dmar_ctx *ctx;
1037 bool show_mappings, valid;
1038 int domain, bus, device, function, i, t;
1044 t = db_read_token();
1046 t = db_read_token();
1048 db_printf("Bad modifier\n");
1053 show_mappings = strchr(db_tok_string, 'm') != NULL;
1054 t = db_read_token();
1056 show_mappings = false;
1059 domain = db_tok_number;
1060 t = db_read_token();
1062 bus = db_tok_number;
1063 t = db_read_token();
1065 device = db_tok_number;
1066 t = db_read_token();
1068 function = db_tok_number;
1077 db_printf("usage: show dmar_ctx [/m] "
1078 "<domain> <bus> <device> <func>\n");
1081 for (i = 0; i < dmar_devcnt; i++) {
1082 unit = device_get_softc(dmar_devs[i]);
1083 LIST_FOREACH(ctx, &unit->contexts, link) {
1084 if (domain == unit->segment &&
1085 bus == pci_get_bus(ctx->ctx_tag.owner) &&
1086 device == pci_get_slot(ctx->ctx_tag.owner) &&
1087 function == pci_get_function(ctx->ctx_tag.owner)) {
1088 dmar_print_ctx(ctx, show_mappings);
1097 dmar_print_one(int idx, bool show_ctxs, bool show_mappings)
1099 struct dmar_unit *unit;
1100 struct dmar_ctx *ctx;
1103 unit = device_get_softc(dmar_devs[idx]);
1104 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1105 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1106 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1107 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1108 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1109 dmar_read4(unit, DMAR_GSTS_REG),
1110 dmar_read4(unit, DMAR_FSTS_REG),
1111 dmar_read4(unit, DMAR_FECTL_REG));
1112 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1113 dmar_read4(unit, DMAR_FEDATA_REG),
1114 dmar_read4(unit, DMAR_FEADDR_REG),
1115 dmar_read4(unit, DMAR_FEUADDR_REG));
1116 db_printf("primary fault log:\n");
1117 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1118 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1119 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1120 (uintmax_t)dmar_read8(unit, frir),
1121 (uintmax_t)dmar_read8(unit, frir + 8));
1123 if (DMAR_HAS_QI(unit)) {
1124 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1125 dmar_read4(unit, DMAR_IEDATA_REG),
1126 dmar_read4(unit, DMAR_IEADDR_REG),
1127 dmar_read4(unit, DMAR_IEUADDR_REG));
1128 if (unit->qi_enabled) {
1129 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1131 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1132 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1133 (uintmax_t)unit->inv_queue,
1134 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1135 (uintmax_t)unit->inv_queue_size,
1136 dmar_read4(unit, DMAR_IQH_REG),
1137 dmar_read4(unit, DMAR_IQT_REG),
1138 unit->inv_queue_avail,
1139 dmar_read4(unit, DMAR_ICS_REG),
1140 dmar_read4(unit, DMAR_IECTL_REG),
1141 unit->inv_waitd_seq_hw,
1142 &unit->inv_waitd_seq_hw,
1143 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1144 unit->inv_waitd_seq,
1145 unit->inv_waitd_gen);
1147 db_printf("qi is disabled\n");
1151 db_printf("contexts:\n");
1152 LIST_FOREACH(ctx, &unit->contexts, link) {
1153 dmar_print_ctx(ctx, show_mappings);
1160 DB_SHOW_COMMAND(dmar, db_dmar_print)
1162 bool show_ctxs, show_mappings;
1164 show_ctxs = strchr(modif, 'c') != NULL;
1165 show_mappings = strchr(modif, 'm') != NULL;
1167 db_printf("usage: show dmar [/c] [/m] index\n");
1170 dmar_print_one((int)addr, show_ctxs, show_mappings);
1173 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1176 bool show_ctxs, show_mappings;
1178 show_ctxs = strchr(modif, 'c') != NULL;
1179 show_mappings = strchr(modif, 'm') != NULL;
1181 for (i = 0; i < dmar_devcnt; i++) {
1182 dmar_print_one(i, show_ctxs, show_mappings);