sys/arm/arm/identcpu.c

   1 /*      $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1995 Mark Brinicombe.
   5  * Copyright (c) 1995 Brini.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Brini.
  19  * 4. The name of the company nor the name of the author may be used to
  20  *    endorse or promote products derived from this software without specific
  21  *    prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * RiscBSD kernel project
  36  *
  37  * cpu.c
  38  *
  39  * Probing and configuration for the master CPU
  40  *
  41  * Created      : 10/10/95
  42  */
  43
  44 #include <sys/cdefs.h>
  45 __FBSDID("$FreeBSD$");
  46 #include <sys/systm.h>
  47 #include <sys/param.h>
  48 #include <sys/malloc.h>
  49 #include <sys/time.h>
  50 #include <sys/proc.h>
  51 #include <sys/conf.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <machine/cpu.h>
  55
  56 #include <machine/cpuconf.h>
  57
  58 char machine[] = "arm";
  59
  60 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  61         machine, 0, "Machine class");
  62 enum cpu_class {
  63         CPU_CLASS_NONE,
  64         CPU_CLASS_ARM2,
  65         CPU_CLASS_ARM2AS,
  66         CPU_CLASS_ARM3,
  67         CPU_CLASS_ARM6,
  68         CPU_CLASS_ARM7,
  69         CPU_CLASS_ARM7TDMI,
  70         CPU_CLASS_ARM8,
  71         CPU_CLASS_ARM9TDMI,
  72         CPU_CLASS_ARM9ES,
  73         CPU_CLASS_ARM9EJS,
  74         CPU_CLASS_ARM10E,
  75         CPU_CLASS_ARM10EJ,
  76         CPU_CLASS_SA1,
  77         CPU_CLASS_XSCALE,
  78         CPU_CLASS_ARM11J,
  79         CPU_CLASS_MARVELL
  80 };
  81
  82 static const char * const generic_steppings[16] = {
  83         "rev 0",        "rev 1",        "rev 2",        "rev 3",
  84         "rev 4",        "rev 5",        "rev 6",        "rev 7",
  85         "rev 8",        "rev 9",        "rev 10",       "rev 11",
  86         "rev 12",       "rev 13",       "rev 14",       "rev 15",
  87 };
  88
  89 static const char * const sa110_steppings[16] = {
  90         "rev 0",        "step J",       "step K",       "step S",
  91         "step T",       "rev 5",        "rev 6",        "rev 7",
  92         "rev 8",        "rev 9",        "rev 10",       "rev 11",
  93         "rev 12",       "rev 13",       "rev 14",       "rev 15",
  94 };
  95
  96 static const char * const sa1100_steppings[16] = {
  97         "rev 0",        "step B",       "step C",       "rev 3",
  98         "rev 4",        "rev 5",        "rev 6",        "rev 7",
  99         "step D",       "step E",       "rev 10"        "step G",
 100         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 101 };
 102
 103 static const char * const sa1110_steppings[16] = {
 104         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 105         "step B-0",     "step B-1",     "step B-2",     "step B-3",
 106         "step B-4",     "step B-5",     "rev 10",       "rev 11",
 107         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 108 };
 109
 110 static const char * const ixp12x0_steppings[16] = {
 111         "(IXP1200 step A)",             "(IXP1200 step B)",
 112         "rev 2",                        "(IXP1200 step C)",
 113         "(IXP1200 step D)",             "(IXP1240/1250 step A)",
 114         "(IXP1240 step B)",             "(IXP1250 step B)",
 115         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 116         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 117 };
 118
 119 static const char * const xscale_steppings[16] = {
 120         "step A-0",     "step A-1",     "step B-0",     "step C-0",
 121         "step D-0",     "rev 5",        "rev 6",        "rev 7",
 122         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 123         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 124 };
 125
 126 static const char * const i80219_steppings[16] = {
 127         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 128         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 129         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 130         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 131 };
 132
 133 static const char * const i80321_steppings[16] = {
 134         "step A-0",     "step B-0",     "rev 2",        "rev 3",
 135         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 136         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 137         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 138 };
 139
 140 static const char * const i81342_steppings[16] = {
 141         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 142         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 143         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 144         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 145 };
 146
 147 /* Steppings for PXA2[15]0 */
 148 static const char * const pxa2x0_steppings[16] = {
 149         "step A-0",     "step A-1",     "step B-0",     "step B-1",
 150         "step B-2",     "step C-0",     "rev 6",        "rev 7",
 151         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 152         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 153 };
 154
 155 /* Steppings for PXA255/26x.
 156  * rev 5: PXA26x B0, rev 6: PXA255 A0
 157  */
 158 static const char * const pxa255_steppings[16] = {
 159         "rev 0",        "rev 1",        "rev 2",        "step A-0",
 160         "rev 4",        "step B-0",     "step A-0",     "rev 7",
 161         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 162         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 163 };
 164
 165 /* Stepping for PXA27x */
 166 static const char * const pxa27x_steppings[16] = {
 167         "step A-0",     "step A-1",     "step B-0",     "step B-1",
 168         "step C-0",     "rev 5",        "rev 6",        "rev 7",
 169         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 170         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 171 };
 172
 173 static const char * const ixp425_steppings[16] = {
 174         "step 0 (A0)",  "rev 1 (ARMv5TE)", "rev 2",     "rev 3",
 175         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 176         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 177         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 178 };
 179
 180 struct cpuidtab {
 181         u_int32_t       cpuid;
 182         enum            cpu_class cpu_class;
 183         const char      *cpu_name;
 184         const char * const *cpu_steppings;
 185 };
 186
 187 const struct cpuidtab cpuids[] = {
 188         { CPU_ID_ARM2,          CPU_CLASS_ARM2,         "ARM2",
 189           generic_steppings },
 190         { CPU_ID_ARM250,        CPU_CLASS_ARM2AS,       "ARM250",
 191           generic_steppings },
 192
 193         { CPU_ID_ARM3,          CPU_CLASS_ARM3,         "ARM3",
 194           generic_steppings },
 195
 196         { CPU_ID_ARM600,        CPU_CLASS_ARM6,         "ARM600",
 197           generic_steppings },
 198         { CPU_ID_ARM610,        CPU_CLASS_ARM6,         "ARM610",
 199           generic_steppings },
 200         { CPU_ID_ARM620,        CPU_CLASS_ARM6,         "ARM620",
 201           generic_steppings },
 202
 203         { CPU_ID_ARM700,        CPU_CLASS_ARM7,         "ARM700",
 204           generic_steppings },
 205         { CPU_ID_ARM710,        CPU_CLASS_ARM7,         "ARM710",
 206           generic_steppings },
 207         { CPU_ID_ARM7500,       CPU_CLASS_ARM7,         "ARM7500",
 208           generic_steppings },
 209         { CPU_ID_ARM710A,       CPU_CLASS_ARM7,         "ARM710a",
 210           generic_steppings },
 211         { CPU_ID_ARM7500FE,     CPU_CLASS_ARM7,         "ARM7500FE",
 212           generic_steppings },
 213         { CPU_ID_ARM710T,       CPU_CLASS_ARM7TDMI,     "ARM710T",
 214           generic_steppings },
 215         { CPU_ID_ARM720T,       CPU_CLASS_ARM7TDMI,     "ARM720T",
 216           generic_steppings },
 217         { CPU_ID_ARM740T8K,     CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
 218           generic_steppings },
 219         { CPU_ID_ARM740T4K,     CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
 220           generic_steppings },
 221
 222         { CPU_ID_ARM810,        CPU_CLASS_ARM8,         "ARM810",
 223           generic_steppings },
 224
 225         { CPU_ID_ARM920T,       CPU_CLASS_ARM9TDMI,     "ARM920T",
 226           generic_steppings },
 227         { CPU_ID_ARM920T_ALT,   CPU_CLASS_ARM9TDMI,     "ARM920T",
 228           generic_steppings },
 229         { CPU_ID_ARM922T,       CPU_CLASS_ARM9TDMI,     "ARM922T",
 230           generic_steppings },
 231         { CPU_ID_ARM926EJS,     CPU_CLASS_ARM9EJS,      "ARM926EJ-S",
 232           generic_steppings },
 233         { CPU_ID_ARM940T,       CPU_CLASS_ARM9TDMI,     "ARM940T",
 234           generic_steppings },
 235         { CPU_ID_ARM946ES,      CPU_CLASS_ARM9ES,       "ARM946E-S",
 236           generic_steppings },
 237         { CPU_ID_ARM966ES,      CPU_CLASS_ARM9ES,       "ARM966E-S",
 238           generic_steppings },
 239         { CPU_ID_ARM966ESR1,    CPU_CLASS_ARM9ES,       "ARM966E-S",
 240           generic_steppings },
 241         { CPU_ID_TI925T,        CPU_CLASS_ARM9TDMI,     "TI ARM925T",
 242           generic_steppings },
 243
 244         { CPU_ID_ARM1020E,      CPU_CLASS_ARM10E,       "ARM1020E",
 245           generic_steppings },
 246         { CPU_ID_ARM1022ES,     CPU_CLASS_ARM10E,       "ARM1022E-S",
 247           generic_steppings },
 248         { CPU_ID_ARM1026EJS,    CPU_CLASS_ARM10EJ,      "ARM1026EJ-S",
 249           generic_steppings },
 250
 251         { CPU_ID_SA110,         CPU_CLASS_SA1,          "SA-110",
 252           sa110_steppings },
 253         { CPU_ID_SA1100,        CPU_CLASS_SA1,          "SA-1100",
 254           sa1100_steppings },
 255         { CPU_ID_SA1110,        CPU_CLASS_SA1,          "SA-1110",
 256           sa1110_steppings },
 257
 258         { CPU_ID_IXP1200,       CPU_CLASS_SA1,          "IXP1200",
 259           ixp12x0_steppings },
 260
 261         { CPU_ID_80200,         CPU_CLASS_XSCALE,       "i80200",
 262           xscale_steppings },
 263
 264         { CPU_ID_80321_400,     CPU_CLASS_XSCALE,       "i80321 400MHz",
 265           i80321_steppings },
 266         { CPU_ID_80321_600,     CPU_CLASS_XSCALE,       "i80321 600MHz",
 267           i80321_steppings },
 268         { CPU_ID_80321_400_B0,  CPU_CLASS_XSCALE,       "i80321 400MHz",
 269           i80321_steppings },
 270         { CPU_ID_80321_600_B0,  CPU_CLASS_XSCALE,       "i80321 600MHz",
 271           i80321_steppings },
 272
 273         { CPU_ID_81342,         CPU_CLASS_XSCALE,       "i81342",
 274           i81342_steppings },
 275
 276         { CPU_ID_80219_400,     CPU_CLASS_XSCALE,       "i80219 400MHz",
 277           i80219_steppings },
 278         { CPU_ID_80219_600,     CPU_CLASS_XSCALE,       "i80219 600MHz",
 279           i80219_steppings },
 280
 281         { CPU_ID_PXA27X,        CPU_CLASS_XSCALE,       "PXA27x",
 282           pxa27x_steppings },
 283         { CPU_ID_PXA250A,       CPU_CLASS_XSCALE,       "PXA250",
 284           pxa2x0_steppings },
 285         { CPU_ID_PXA210A,       CPU_CLASS_XSCALE,       "PXA210",
 286           pxa2x0_steppings },
 287         { CPU_ID_PXA250B,       CPU_CLASS_XSCALE,       "PXA250",
 288           pxa2x0_steppings },
 289         { CPU_ID_PXA210B,       CPU_CLASS_XSCALE,       "PXA210",
 290           pxa2x0_steppings },
 291         { CPU_ID_PXA250C,       CPU_CLASS_XSCALE,       "PXA255",
 292           pxa255_steppings },
 293         { CPU_ID_PXA210C,       CPU_CLASS_XSCALE,       "PXA210",
 294           pxa2x0_steppings },
 295
 296         { CPU_ID_IXP425_533,    CPU_CLASS_XSCALE,       "IXP425 533MHz",
 297           ixp425_steppings },
 298         { CPU_ID_IXP425_400,    CPU_CLASS_XSCALE,       "IXP425 400MHz",
 299           ixp425_steppings },
 300         { CPU_ID_IXP425_266,    CPU_CLASS_XSCALE,       "IXP425 266MHz",
 301           ixp425_steppings },
 302
 303         /* XXX ixp435 steppings? */
 304         { CPU_ID_IXP435,        CPU_CLASS_XSCALE,       "IXP435",
 305           ixp425_steppings },
 306
 307         { CPU_ID_ARM1136JS,     CPU_CLASS_ARM11J,       "ARM1136J-S",
 308           generic_steppings },
 309         { CPU_ID_ARM1136JSR1,   CPU_CLASS_ARM11J,       "ARM1136J-S R1",
 310           generic_steppings },
 311
 312         { CPU_ID_MV88FR131,     CPU_CLASS_MARVELL,      "Feroceon 88FR131",
 313           generic_steppings },
 314
 315         { CPU_ID_MV88FR571_VD,  CPU_CLASS_MARVELL,      "Feroceon 88FR571-VD",
 316           generic_steppings },
 317
 318         { CPU_ID_MV88FR571_41,  CPU_CLASS_MARVELL,      "Early Feroceon 88FR571",
 319           generic_steppings },
 320
 321         { 0, CPU_CLASS_NONE, NULL, NULL }
 322 };
 323
 324 struct cpu_classtab {
 325         const char      *class_name;
 326         const char      *class_option;
 327 };
 328
 329 const struct cpu_classtab cpu_classes[] = {
 330         { "unknown",    NULL },                 /* CPU_CLASS_NONE */
 331         { "ARM2",       "CPU_ARM2" },           /* CPU_CLASS_ARM2 */
 332         { "ARM2as",     "CPU_ARM250" },         /* CPU_CLASS_ARM2AS */
 333         { "ARM3",       "CPU_ARM3" },           /* CPU_CLASS_ARM3 */
 334         { "ARM6",       "CPU_ARM6" },           /* CPU_CLASS_ARM6 */
 335         { "ARM7",       "CPU_ARM7" },           /* CPU_CLASS_ARM7 */
 336         { "ARM7TDMI",   "CPU_ARM7TDMI" },       /* CPU_CLASS_ARM7TDMI */
 337         { "ARM8",       "CPU_ARM8" },           /* CPU_CLASS_ARM8 */
 338         { "ARM9TDMI",   "CPU_ARM9TDMI" },       /* CPU_CLASS_ARM9TDMI */
 339         { "ARM9E-S",    "CPU_ARM9E" },          /* CPU_CLASS_ARM9ES */
 340         { "ARM9EJ-S",   "CPU_ARM9E" },          /* CPU_CLASS_ARM9EJS */
 341         { "ARM10E",     "CPU_ARM10" },          /* CPU_CLASS_ARM10E */
 342         { "ARM10EJ",    "CPU_ARM10" },          /* CPU_CLASS_ARM10EJ */
 343         { "SA-1",       "CPU_SA110" },          /* CPU_CLASS_SA1 */
 344         { "XScale",     "CPU_XSCALE_..." },     /* CPU_CLASS_XSCALE */
 345         { "ARM11J",     "CPU_ARM11" },          /* CPU_CLASS_ARM11J */
 346 };
 347
 348 /*
 349  * Report the type of the specified arm processor. This uses the generic and
 350  * arm specific information in the cpu structure to identify the processor.
 351  * The remaining fields in the cpu structure are filled in appropriately.
 352  */
 353
 354 static const char * const wtnames[] = {
 355         "write-through",
 356         "write-back",
 357         "write-back",
 358         "**unknown 3**",
 359         "**unknown 4**",
 360         "write-back-locking",           /* XXX XScale-specific? */
 361         "write-back-locking-A",
 362         "write-back-locking-B",
 363         "**unknown 8**",
 364         "**unknown 9**",
 365         "**unknown 10**",
 366         "**unknown 11**",
 367         "**unknown 12**",
 368         "**unknown 13**",
 369         "write-back-locking-C",
 370         "**unknown 15**",
 371 };
 372
 373
 374 extern int ctrl;
 375 void
 376 identify_arm_cpu(void)
 377 {
 378         u_int cpuid;
 379         enum cpu_class cpu_class = CPU_CLASS_NONE;
 380         int i;
 381
 382         cpuid = cpu_id();
 383
 384         if (cpuid == 0) {
 385                 printf("Processor failed probe - no CPU ID\n");
 386                 return;
 387         }
 388
 389         for (i = 0; cpuids[i].cpuid != 0; i++)
 390                 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) {
 391                         cpu_class = cpuids[i].cpu_class;
 392                         printf("CPU: %s %s (%s core)\n",
 393                             cpuids[i].cpu_name,
 394                             cpuids[i].cpu_steppings[cpuid &
 395                             CPU_ID_REVISION_MASK],
 396                             cpu_classes[cpu_class].class_name);
 397                         break;
 398                 }
 399         if (cpuids[i].cpuid == 0)
 400                 printf("unknown CPU (ID = 0x%x)\n", cpuid);
 401
 402         printf(" ");
 403         switch (cpu_class) {
 404         case CPU_CLASS_ARM6:
 405         case CPU_CLASS_ARM7:
 406         case CPU_CLASS_ARM7TDMI:
 407         case CPU_CLASS_ARM8:
 408                 if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
 409                         printf(" IDC disabled");
 410                 else
 411                         printf(" IDC enabled");
 412                 break;
 413         case CPU_CLASS_ARM9TDMI:
 414         case CPU_CLASS_ARM9ES:
 415         case CPU_CLASS_ARM9EJS:
 416         case CPU_CLASS_ARM10E:
 417         case CPU_CLASS_ARM10EJ:
 418         case CPU_CLASS_SA1:
 419         case CPU_CLASS_XSCALE:
 420         case CPU_CLASS_ARM11J:
 421                 if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0)
 422                         printf(" DC disabled");
 423                 else
 424                         printf(" DC enabled");
 425                 if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0)
 426                         printf(" IC disabled");
 427                 else
 428                         printf(" IC enabled");
 429 #ifdef CPU_XSCALE_81342
 430                 if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0)
 431                         printf(" L2 disabled");
 432                 else
 433                         printf(" L2 enabled");
 434 #endif
 435                 break;
 436         default:
 437                 break;
 438         }
 439         if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0)
 440                 printf(" WB disabled");
 441         else
 442                 printf(" WB enabled");
 443
 444         if (ctrl & CPU_CONTROL_LABT_ENABLE)
 445                 printf(" LABT");
 446         else
 447                 printf(" EABT");
 448
 449         if (ctrl & CPU_CONTROL_BPRD_ENABLE)
 450                 printf(" branch prediction enabled");
 451
 452         printf("\n");
 453         /* Print cache info. */
 454         if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
 455                 return;
 456
 457         if (arm_pcache_unified) {
 458                 printf("  %dKB/%dB %d-way %s unified cache\n",
 459                     arm_pdcache_size / 1024,
 460                     arm_pdcache_line_size, arm_pdcache_ways,
 461                     wtnames[arm_pcache_type]);
 462         } else {
 463                 printf("  %dKB/%dB %d-way Instruction cache\n",
 464                     arm_picache_size / 1024,
 465                     arm_picache_line_size, arm_picache_ways);
 466                 printf("  %dKB/%dB %d-way %s Data cache\n",
 467                     arm_pdcache_size / 1024,
 468                     arm_pdcache_line_size, arm_pdcache_ways,
 469                     wtnames[arm_pcache_type]);
 470         }
 471 }
 472