1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
80 * 3. All advertising materials mentioning features or use of this software
81 * must display the following acknowledgement:
82 * This product includes software developed by the NetBSD
83 * Foundation, Inc. and its contributors.
84 * 4. Neither the name of The NetBSD Foundation nor the names of its
85 * contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
98 * POSSIBILITY OF SUCH DAMAGE.
102 * Copyright (c) 1994-1998 Mark Brinicombe.
103 * Copyright (c) 1994 Brini.
104 * All rights reserved.
106 * This code is derived from software written for Brini by Mark Brinicombe
108 * Redistribution and use in source and binary forms, with or without
109 * modification, are permitted provided that the following conditions
111 * 1. Redistributions of source code must retain the above copyright
112 * notice, this list of conditions and the following disclaimer.
113 * 2. Redistributions in binary form must reproduce the above copyright
114 * notice, this list of conditions and the following disclaimer in the
115 * documentation and/or other materials provided with the distribution.
116 * 3. All advertising materials mentioning features or use of this software
117 * must display the following acknowledgement:
118 * This product includes software developed by Mark Brinicombe.
119 * 4. The name of the author may not be used to endorse or promote products
120 * derived from this software without specific prior written permission.
122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
132 * RiscBSD kernel project
136 * Machine dependant vm stuff
142 * Special compilation symbols
143 * PMAP_DEBUG - Build in pmap_debug_level code
145 /* Include header files */
149 #include <sys/cdefs.h>
150 __FBSDID("$FreeBSD$");
151 #include <sys/param.h>
152 #include <sys/systm.h>
153 #include <sys/kernel.h>
155 #include <sys/proc.h>
156 #include <sys/malloc.h>
157 #include <sys/msgbuf.h>
158 #include <sys/vmmeter.h>
159 #include <sys/mman.h>
161 #include <sys/sched.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
172 #include <sys/lock.h>
173 #include <sys/mutex.h>
174 #include <machine/md_var.h>
175 #include <machine/vmparam.h>
176 #include <machine/cpu.h>
177 #include <machine/cpufunc.h>
178 #include <machine/pcb.h>
181 #define PDEBUG(_lev_,_stat_) \
182 if (pmap_debug_level >= (_lev_)) \
184 #define dprintf printf
186 int pmap_debug_level = 0;
188 #else /* PMAP_DEBUG */
189 #define PDEBUG(_lev_,_stat_) /* Nothing */
190 #define dprintf(x, arg...)
191 #define PMAP_INLINE __inline
192 #endif /* PMAP_DEBUG */
194 extern struct pv_addr systempage;
196 * Internal function prototypes
198 static void pmap_free_pv_entry (pv_entry_t);
199 static pv_entry_t pmap_get_pv_entry(void);
201 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
202 vm_prot_t, boolean_t, int);
203 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
204 static void pmap_alloc_l1(pmap_t);
205 static void pmap_free_l1(pmap_t);
206 static void pmap_use_l1(pmap_t);
208 static int pmap_clearbit(struct vm_page *, u_int);
210 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
211 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
212 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
213 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
215 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
217 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
218 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
219 vm_offset_t pmap_curmaxkvaddr;
220 vm_paddr_t kernel_l1pa;
223 vm_offset_t kernel_vm_end = 0;
225 struct pmap kernel_pmap_store;
227 static pt_entry_t *csrc_pte, *cdst_pte;
228 static vm_offset_t csrcp, cdstp;
229 static struct mtx cmtx;
231 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
233 * These routines are called when the CPU type is identified to set up
234 * the PTE prototypes, cache modes, etc.
236 * The variables are always here, just in case LKMs need to reference
237 * them (though, they shouldn't).
240 pt_entry_t pte_l1_s_cache_mode;
241 pt_entry_t pte_l1_s_cache_mode_pt;
242 pt_entry_t pte_l1_s_cache_mask;
244 pt_entry_t pte_l2_l_cache_mode;
245 pt_entry_t pte_l2_l_cache_mode_pt;
246 pt_entry_t pte_l2_l_cache_mask;
248 pt_entry_t pte_l2_s_cache_mode;
249 pt_entry_t pte_l2_s_cache_mode_pt;
250 pt_entry_t pte_l2_s_cache_mask;
252 pt_entry_t pte_l2_s_prot_u;
253 pt_entry_t pte_l2_s_prot_w;
254 pt_entry_t pte_l2_s_prot_mask;
256 pt_entry_t pte_l1_s_proto;
257 pt_entry_t pte_l1_c_proto;
258 pt_entry_t pte_l2_s_proto;
260 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
261 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
263 * Which pmap is currently 'live' in the cache
265 * XXXSCW: Fix for SMP ...
267 union pmap_cache_state *pmap_cache_state;
269 struct msgbuf *msgbufp = 0;
274 static caddr_t crashdumpmap;
276 extern void bcopy_page(vm_offset_t, vm_offset_t);
277 extern void bzero_page(vm_offset_t);
279 extern vm_offset_t alloc_firstaddr;
284 * Metadata for L1 translation tables.
287 /* Entry on the L1 Table list */
288 SLIST_ENTRY(l1_ttable) l1_link;
290 /* Entry on the L1 Least Recently Used list */
291 TAILQ_ENTRY(l1_ttable) l1_lru;
293 /* Track how many domains are allocated from this L1 */
294 volatile u_int l1_domain_use_count;
297 * A free-list of domain numbers for this L1.
298 * We avoid using ffs() and a bitmap to track domains since ffs()
301 u_int8_t l1_domain_first;
302 u_int8_t l1_domain_free[PMAP_DOMAINS];
304 /* Physical address of this L1 page table */
305 vm_paddr_t l1_physaddr;
307 /* KVA of this L1 page table */
312 * Convert a virtual address into its L1 table index. That is, the
313 * index used to locate the L2 descriptor table pointer in an L1 table.
314 * This is basically used to index l1->l1_kva[].
316 * Each L2 descriptor table represents 1MB of VA space.
318 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
321 * L1 Page Tables are tracked using a Least Recently Used list.
322 * - New L1s are allocated from the HEAD.
323 * - Freed L1s are added to the TAIl.
324 * - Recently accessed L1s (where an 'access' is some change to one of
325 * the userland pmaps which owns this L1) are moved to the TAIL.
327 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
329 * A list of all L1 tables
331 static SLIST_HEAD(, l1_ttable) l1_list;
332 static struct mtx l1_lru_lock;
335 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
337 * This is normally 16MB worth L2 page descriptors for any given pmap.
338 * Reference counts are maintained for L2 descriptors so they can be
342 /* The number of L2 page descriptors allocated to this l2_dtable */
345 /* List of L2 page descriptors */
347 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
348 vm_paddr_t l2b_phys; /* Physical address of same */
349 u_short l2b_l1idx; /* This L2 table's L1 index */
350 u_short l2b_occupancy; /* How many active descriptors */
351 } l2_bucket[L2_BUCKET_SIZE];
354 /* pmap_kenter_internal flags */
355 #define KENTER_CACHE 0x1
356 #define KENTER_USER 0x2
359 * Given an L1 table index, calculate the corresponding l2_dtable index
360 * and bucket index within the l2_dtable.
362 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
364 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
367 * Given a virtual address, this macro returns the
368 * virtual address required to drop into the next L2 bucket.
370 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
375 #define pmap_alloc_l2_dtable() \
376 (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE)
377 #define pmap_free_l2_dtable(l2) \
378 uma_zfree(l2table_zone, l2)
381 * We try to map the page tables write-through, if possible. However, not
382 * all CPUs have a write-through cache mode, so on those we have to sync
383 * the cache when we frob page tables.
385 * We try to evaluate this at compile time, if possible. However, it's
386 * not always possible to do that, hence this run-time var.
388 int pmap_needs_pte_sync;
391 * Macro to determine if a mapping might be resident in the
392 * instruction cache and/or TLB
394 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
397 * Macro to determine if a mapping might be resident in the
398 * data cache and/or TLB
400 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
402 #ifndef PMAP_SHPGPERPROC
403 #define PMAP_SHPGPERPROC 200
406 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
407 curproc->p_vmspace->vm_map.pmap == (pm))
408 static uma_zone_t pvzone = NULL;
410 static uma_zone_t l2table_zone;
411 static vm_offset_t pmap_kernel_l2dtable_kva;
412 static vm_offset_t pmap_kernel_l2ptp_kva;
413 static vm_paddr_t pmap_kernel_l2ptp_phys;
414 static struct vm_object pvzone_obj;
415 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
418 * This list exists for the benefit of pmap_map_chunk(). It keeps track
419 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
420 * find them as necessary.
422 * Note that the data on this list MUST remain valid after initarm() returns,
423 * as pmap_bootstrap() uses it to contruct L2 table metadata.
425 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
428 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
433 l1->l1_domain_use_count = 0;
434 l1->l1_domain_first = 0;
436 for (i = 0; i < PMAP_DOMAINS; i++)
437 l1->l1_domain_free[i] = i + 1;
440 * Copy the kernel's L1 entries to each new L1.
442 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
443 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
445 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
446 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
447 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
448 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
452 kernel_pt_lookup(vm_paddr_t pa)
456 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
463 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
465 pmap_pte_init_generic(void)
468 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
469 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
471 pte_l2_l_cache_mode = L2_B|L2_C;
472 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
474 pte_l2_s_cache_mode = L2_B|L2_C;
475 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
478 * If we have a write-through cache, set B and C. If
479 * we have a write-back cache, then we assume setting
480 * only C will make those pages write-through.
482 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
483 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
484 pte_l2_l_cache_mode_pt = L2_B|L2_C;
485 pte_l2_s_cache_mode_pt = L2_B|L2_C;
487 pte_l1_s_cache_mode_pt = L1_S_C;
488 pte_l2_l_cache_mode_pt = L2_C;
489 pte_l2_s_cache_mode_pt = L2_C;
492 pte_l2_s_prot_u = L2_S_PROT_U_generic;
493 pte_l2_s_prot_w = L2_S_PROT_W_generic;
494 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
496 pte_l1_s_proto = L1_S_PROTO_generic;
497 pte_l1_c_proto = L1_C_PROTO_generic;
498 pte_l2_s_proto = L2_S_PROTO_generic;
500 pmap_copy_page_func = pmap_copy_page_generic;
501 pmap_zero_page_func = pmap_zero_page_generic;
504 #if defined(CPU_ARM8)
506 pmap_pte_init_arm8(void)
510 * ARM8 is compatible with generic, but we need to use
511 * the page tables uncached.
513 pmap_pte_init_generic();
515 pte_l1_s_cache_mode_pt = 0;
516 pte_l2_l_cache_mode_pt = 0;
517 pte_l2_s_cache_mode_pt = 0;
519 #endif /* CPU_ARM8 */
521 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
523 pmap_pte_init_arm9(void)
527 * ARM9 is compatible with generic, but we want to use
528 * write-through caching for now.
530 pmap_pte_init_generic();
532 pte_l1_s_cache_mode = L1_S_C;
533 pte_l2_l_cache_mode = L2_C;
534 pte_l2_s_cache_mode = L2_C;
536 pte_l1_s_cache_mode_pt = L1_S_C;
537 pte_l2_l_cache_mode_pt = L2_C;
538 pte_l2_s_cache_mode_pt = L2_C;
540 #endif /* CPU_ARM9 */
541 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
543 #if defined(CPU_ARM10)
545 pmap_pte_init_arm10(void)
549 * ARM10 is compatible with generic, but we want to use
550 * write-through caching for now.
552 pmap_pte_init_generic();
554 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
555 pte_l2_l_cache_mode = L2_B | L2_C;
556 pte_l2_s_cache_mode = L2_B | L2_C;
558 pte_l1_s_cache_mode_pt = L1_S_C;
559 pte_l2_l_cache_mode_pt = L2_C;
560 pte_l2_s_cache_mode_pt = L2_C;
563 #endif /* CPU_ARM10 */
567 pmap_pte_init_sa1(void)
571 * The StrongARM SA-1 cache does not have a write-through
572 * mode. So, do the generic initialization, then reset
573 * the page table cache mode to B=1,C=1, and note that
574 * the PTEs need to be sync'd.
576 pmap_pte_init_generic();
578 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
579 pte_l2_l_cache_mode_pt = L2_B|L2_C;
580 pte_l2_s_cache_mode_pt = L2_B|L2_C;
582 pmap_needs_pte_sync = 1;
584 #endif /* ARM_MMU_SA1 == 1*/
586 #if ARM_MMU_XSCALE == 1
587 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
588 static u_int xscale_use_minidata;
592 pmap_pte_init_xscale(void)
595 int write_through = 0;
597 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
598 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
600 pte_l2_l_cache_mode = L2_B|L2_C;
601 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
603 pte_l2_s_cache_mode = L2_B|L2_C;
604 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
606 pte_l1_s_cache_mode_pt = L1_S_C;
607 pte_l2_l_cache_mode_pt = L2_C;
608 pte_l2_s_cache_mode_pt = L2_C;
609 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
611 * The XScale core has an enhanced mode where writes that
612 * miss the cache cause a cache line to be allocated. This
613 * is significantly faster than the traditional, write-through
614 * behavior of this case.
616 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
617 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
618 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
619 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
620 #ifdef XSCALE_CACHE_WRITE_THROUGH
622 * Some versions of the XScale core have various bugs in
623 * their cache units, the work-around for which is to run
624 * the cache in write-through mode. Unfortunately, this
625 * has a major (negative) impact on performance. So, we
626 * go ahead and run fast-and-loose, in the hopes that we
627 * don't line up the planets in a way that will trip the
630 * However, we give you the option to be slow-but-correct.
633 #elif defined(XSCALE_CACHE_WRITE_BACK)
634 /* force write back cache mode */
636 #elif defined(CPU_XSCALE_PXA2X0)
638 * Intel PXA2[15]0 processors are known to have a bug in
639 * write-back cache on revision 4 and earlier (stepping
640 * A[01] and B[012]). Fixed for C0 and later.
646 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
648 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
649 if ((id & CPU_ID_REVISION_MASK) < 5) {
650 /* write through for stepping A0-1 and B0-2 */
655 #endif /* XSCALE_CACHE_WRITE_THROUGH */
658 pte_l1_s_cache_mode = L1_S_C;
659 pte_l2_l_cache_mode = L2_C;
660 pte_l2_s_cache_mode = L2_C;
664 xscale_use_minidata = 1;
667 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
668 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
669 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
671 pte_l1_s_proto = L1_S_PROTO_xscale;
672 pte_l1_c_proto = L1_C_PROTO_xscale;
673 pte_l2_s_proto = L2_S_PROTO_xscale;
675 #ifdef CPU_XSCALE_CORE3
676 pmap_copy_page_func = pmap_copy_page_generic;
677 pmap_zero_page_func = pmap_zero_page_generic;
678 xscale_use_minidata = 0;
679 /* Make sure it is L2-cachable */
680 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
681 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
682 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
683 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
684 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
685 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
688 pmap_copy_page_func = pmap_copy_page_xscale;
689 pmap_zero_page_func = pmap_zero_page_xscale;
693 * Disable ECC protection of page table access, for now.
695 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
696 auxctl &= ~XSCALE_AUXCTL_P;
697 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
701 * xscale_setup_minidata:
703 * Set up the mini-data cache clean area. We require the
704 * caller to allocate the right amount of physically and
705 * virtually contiguous space.
707 extern vm_offset_t xscale_minidata_clean_addr;
708 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
710 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
712 pd_entry_t *pde = (pd_entry_t *) l1pt;
717 xscale_minidata_clean_addr = va;
719 /* Round it to page size. */
720 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
723 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
724 pte = (pt_entry_t *) kernel_pt_lookup(
725 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
727 panic("xscale_setup_minidata: can't find L2 table for "
728 "VA 0x%08x", (u_int32_t) va);
729 pte[l2pte_index(va)] =
730 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
731 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
735 * Configure the mini-data cache for write-back with
736 * read/write-allocate.
738 * NOTE: In order to reconfigure the mini-data cache, we must
739 * make sure it contains no valid data! In order to do that,
740 * we must issue a global data cache invalidate command!
742 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
743 * THIS IS VERY IMPORTANT!
746 /* Invalidate data and mini-data. */
747 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
748 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
749 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
750 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
755 * Allocate an L1 translation table for the specified pmap.
756 * This is called at pmap creation time.
759 pmap_alloc_l1(pmap_t pm)
761 struct l1_ttable *l1;
765 * Remove the L1 at the head of the LRU list
767 mtx_lock(&l1_lru_lock);
768 l1 = TAILQ_FIRST(&l1_lru_list);
769 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
772 * Pick the first available domain number, and update
773 * the link to the next number.
775 domain = l1->l1_domain_first;
776 l1->l1_domain_first = l1->l1_domain_free[domain];
779 * If there are still free domain numbers in this L1,
780 * put it back on the TAIL of the LRU list.
782 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
783 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
785 mtx_unlock(&l1_lru_lock);
788 * Fix up the relevant bits in the pmap structure
791 pm->pm_domain = domain + 1;
795 * Free an L1 translation table.
796 * This is called at pmap destruction time.
799 pmap_free_l1(pmap_t pm)
801 struct l1_ttable *l1 = pm->pm_l1;
803 mtx_lock(&l1_lru_lock);
806 * If this L1 is currently on the LRU list, remove it.
808 if (l1->l1_domain_use_count < PMAP_DOMAINS)
809 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
812 * Free up the domain number which was allocated to the pmap
814 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
815 l1->l1_domain_first = pm->pm_domain - 1;
816 l1->l1_domain_use_count--;
819 * The L1 now must have at least 1 free domain, so add
820 * it back to the LRU list. If the use count is zero,
821 * put it at the head of the list, otherwise it goes
824 if (l1->l1_domain_use_count == 0) {
825 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
827 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
829 mtx_unlock(&l1_lru_lock);
832 static PMAP_INLINE void
833 pmap_use_l1(pmap_t pm)
835 struct l1_ttable *l1;
838 * Do nothing if we're in interrupt context.
839 * Access to an L1 by the kernel pmap must not affect
842 if (pm == pmap_kernel())
848 * If the L1 is not currently on the LRU list, just return
850 if (l1->l1_domain_use_count == PMAP_DOMAINS)
853 mtx_lock(&l1_lru_lock);
856 * Check the use count again, now that we've acquired the lock
858 if (l1->l1_domain_use_count == PMAP_DOMAINS) {
859 mtx_unlock(&l1_lru_lock);
864 * Move the L1 to the back of the LRU list
866 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
867 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
869 mtx_unlock(&l1_lru_lock);
874 * Returns a pointer to the L2 bucket associated with the specified pmap
875 * and VA, or NULL if no L2 bucket exists for the address.
877 static PMAP_INLINE struct l2_bucket *
878 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
880 struct l2_dtable *l2;
881 struct l2_bucket *l2b;
886 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
887 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
894 * Returns a pointer to the L2 bucket associated with the specified pmap
897 * If no L2 bucket exists, perform the necessary allocations to put an L2
898 * bucket/page table in place.
900 * Note that if a new L2 bucket/page was allocated, the caller *must*
901 * increment the bucket occupancy counter appropriately *before*
902 * releasing the pmap's lock to ensure no other thread or cpu deallocates
903 * the bucket/page in the meantime.
905 static struct l2_bucket *
906 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
908 struct l2_dtable *l2;
909 struct l2_bucket *l2b;
914 PMAP_ASSERT_LOCKED(pm);
915 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
916 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
918 * No mapping at this address, as there is
919 * no entry in the L1 table.
920 * Need to allocate a new l2_dtable.
924 vm_page_unlock_queues();
925 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
926 vm_page_lock_queues();
930 vm_page_lock_queues();
932 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
934 vm_page_unlock_queues();
935 uma_zfree(l2table_zone, l2);
936 vm_page_lock_queues();
938 l2 = pm->pm_l2[L2_IDX(l1idx)];
942 * Someone already allocated the l2_dtable while
943 * we were doing the same.
946 bzero(l2, sizeof(*l2));
948 * Link it into the parent pmap
950 pm->pm_l2[L2_IDX(l1idx)] = l2;
954 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
957 * Fetch pointer to the L2 page table associated with the address.
959 if (l2b->l2b_kva == NULL) {
963 * No L2 page table has been allocated. Chances are, this
964 * is because we just allocated the l2_dtable, above.
968 vm_page_unlock_queues();
969 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE);
970 vm_page_lock_queues();
972 if (l2b->l2b_kva != 0) {
973 /* We lost the race. */
975 vm_page_unlock_queues();
976 uma_zfree(l2zone, ptep);
977 vm_page_lock_queues();
979 if (l2b->l2b_kva == 0)
983 l2b->l2b_phys = vtophys(ptep);
986 * Oops, no more L2 page tables available at this
987 * time. We may need to deallocate the l2_dtable
988 * if we allocated a new one above.
990 if (l2->l2_occupancy == 0) {
991 pm->pm_l2[L2_IDX(l1idx)] = NULL;
992 pmap_free_l2_dtable(l2);
999 l2b->l2b_l1idx = l1idx;
1005 static PMAP_INLINE void
1006 #ifndef PMAP_INCLUDE_PTE_SYNC
1007 pmap_free_l2_ptp(pt_entry_t *l2)
1009 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
1012 #ifdef PMAP_INCLUDE_PTE_SYNC
1014 * Note: With a write-back cache, we may need to sync this
1015 * L2 table before re-using it.
1016 * This is because it may have belonged to a non-current
1017 * pmap, in which case the cache syncs would have been
1018 * skipped when the pages were being unmapped. If the
1019 * L2 table were then to be immediately re-allocated to
1020 * the *current* pmap, it may well contain stale mappings
1021 * which have not yet been cleared by a cache write-back
1022 * and so would still be visible to the mmu.
1025 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1027 uma_zfree(l2zone, l2);
1030 * One or more mappings in the specified L2 descriptor table have just been
1033 * Garbage collect the metadata and descriptor table itself if necessary.
1035 * The pmap lock must be acquired when this is called (not necessary
1036 * for the kernel pmap).
1039 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1041 struct l2_dtable *l2;
1042 pd_entry_t *pl1pd, l1pd;
1048 * Update the bucket's reference count according to how many
1049 * PTEs the caller has just invalidated.
1051 l2b->l2b_occupancy -= count;
1056 * Level 2 page tables allocated to the kernel pmap are never freed
1057 * as that would require checking all Level 1 page tables and
1058 * removing any references to the Level 2 page table. See also the
1059 * comment elsewhere about never freeing bootstrap L2 descriptors.
1061 * We make do with just invalidating the mapping in the L2 table.
1063 * This isn't really a big deal in practice and, in fact, leads
1064 * to a performance win over time as we don't need to continually
1067 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1071 * There are no more valid mappings in this level 2 page table.
1072 * Go ahead and NULL-out the pointer in the bucket, then
1073 * free the page table.
1075 l1idx = l2b->l2b_l1idx;
1076 ptep = l2b->l2b_kva;
1077 l2b->l2b_kva = NULL;
1079 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1082 * If the L1 slot matches the pmap's domain
1083 * number, then invalidate it.
1085 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1086 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1092 * Release the L2 descriptor table back to the pool cache.
1094 #ifndef PMAP_INCLUDE_PTE_SYNC
1095 pmap_free_l2_ptp(ptep);
1097 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1101 * Update the reference count in the associated l2_dtable
1103 l2 = pm->pm_l2[L2_IDX(l1idx)];
1104 if (--l2->l2_occupancy > 0)
1108 * There are no more valid mappings in any of the Level 1
1109 * slots managed by this l2_dtable. Go ahead and NULL-out
1110 * the pointer in the parent pmap and free the l2_dtable.
1112 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1113 pmap_free_l2_dtable(l2);
1117 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1121 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1123 #ifndef PMAP_INCLUDE_PTE_SYNC
1124 struct l2_bucket *l2b;
1125 pt_entry_t *ptep, pte;
1126 #ifdef ARM_USE_SMALL_ALLOC
1129 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1132 * The mappings for these page tables were initially made using
1133 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1134 * mode will not be right for page table mappings. To avoid
1135 * polluting the pmap_kenter() code with a special case for
1136 * page tables, we simply fix up the cache-mode here if it's not
1139 #ifdef ARM_USE_SMALL_ALLOC
1140 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1141 if (!l1pte_section_p(*pde)) {
1143 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1144 ptep = &l2b->l2b_kva[l2pte_index(va)];
1147 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1149 * Page tables must have the cache-mode set to
1152 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1154 cpu_tlb_flushD_SE(va);
1157 #ifdef ARM_USE_SMALL_ALLOC
1161 memset(mem, 0, L2_TABLE_SIZE_REAL);
1162 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1167 * A bunch of routines to conditionally flush the caches/TLB depending
1168 * on whether the specified pmap actually needs to be flushed at any
1171 static PMAP_INLINE void
1172 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1175 if (pmap_is_current(pm))
1176 cpu_tlb_flushID_SE(va);
1179 static PMAP_INLINE void
1180 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1183 if (pmap_is_current(pm))
1184 cpu_tlb_flushD_SE(va);
1187 static PMAP_INLINE void
1188 pmap_tlb_flushID(pmap_t pm)
1191 if (pmap_is_current(pm))
1194 static PMAP_INLINE void
1195 pmap_tlb_flushD(pmap_t pm)
1198 if (pmap_is_current(pm))
1202 static PMAP_INLINE void
1203 pmap_l2cache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1209 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1212 CTR4(KTR_PMAP, "pmap_l2cache_wbinv_range: pmap %p is_kernel %d "
1213 "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest);
1214 if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep))
1215 cpu_l2cache_wbinv_range(va, rest);
1220 rest = MIN(PAGE_SIZE, len);
1224 static PMAP_INLINE void
1225 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1228 if (pmap_is_current(pm)) {
1229 cpu_idcache_wbinv_range(va, len);
1230 pmap_l2cache_wbinv_range(pm, va, len);
1234 static PMAP_INLINE void
1235 pmap_l2cache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1241 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1244 CTR4(KTR_PMAP, "pmap_l2cache_wb_range: pmap %p is_kernel %d "
1245 "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest);
1246 if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep))
1247 cpu_l2cache_wb_range(va, rest);
1252 rest = MIN(PAGE_SIZE, len);
1256 static PMAP_INLINE void
1257 pmap_l2cache_inv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1263 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1266 CTR4(KTR_PMAP, "pmap_l2cache_wb_range: pmap %p is_kernel %d "
1267 "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest);
1268 if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep))
1269 cpu_l2cache_inv_range(va, rest);
1274 rest = MIN(PAGE_SIZE, len);
1278 static PMAP_INLINE void
1279 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1283 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1284 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1285 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1287 if (pmap_is_current(pm)) {
1290 cpu_dcache_inv_range(va, len);
1291 pmap_l2cache_inv_range(pm, va, len);
1294 cpu_dcache_wbinv_range(va, len);
1295 pmap_l2cache_wbinv_range(pm, va, len);
1297 } else if (!rd_only) {
1298 cpu_dcache_wb_range(va, len);
1299 pmap_l2cache_wb_range(pm, va, len);
1304 static PMAP_INLINE void
1305 pmap_idcache_wbinv_all(pmap_t pm)
1308 if (pmap_is_current(pm)) {
1309 cpu_idcache_wbinv_all();
1310 cpu_l2cache_wbinv_all();
1314 static PMAP_INLINE void
1315 pmap_dcache_wbinv_all(pmap_t pm)
1318 if (pmap_is_current(pm)) {
1319 cpu_dcache_wbinv_all();
1320 cpu_l2cache_wbinv_all();
1327 * Make sure the pte is written out to RAM.
1328 * We need to do this for one of two cases:
1329 * - We're dealing with the kernel pmap
1330 * - There is no pmap active in the cache/tlb.
1331 * - The specified pmap is 'active' in the cache/tlb.
1333 #ifdef PMAP_INCLUDE_PTE_SYNC
1334 #define PTE_SYNC_CURRENT(pm, ptep) \
1336 if (PMAP_NEEDS_PTE_SYNC && \
1337 pmap_is_current(pm)) \
1339 } while (/*CONSTCOND*/0)
1341 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1345 * cacheable == -1 means we must make the entry uncacheable, 1 means
1348 static __inline void
1349 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1351 struct l2_bucket *l2b;
1352 pt_entry_t *ptep, pte;
1354 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1355 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1357 if (cacheable == 1) {
1358 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1359 if (l2pte_valid(pte)) {
1360 if (PV_BEEN_EXECD(pv->pv_flags)) {
1361 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1362 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1363 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1367 pte = *ptep &~ L2_S_CACHE_MASK;
1368 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1370 if (PV_BEEN_EXECD(pv->pv_flags)) {
1371 pmap_idcache_wbinv_range(pv->pv_pmap,
1372 pv->pv_va, PAGE_SIZE);
1373 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1374 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1375 pmap_dcache_wb_range(pv->pv_pmap,
1376 pv->pv_va, PAGE_SIZE, TRUE,
1377 (pv->pv_flags & PVF_WRITE) == 0);
1378 pmap_tlb_flushD_SE(pv->pv_pmap,
1384 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1388 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1391 int writable = 0, kwritable = 0, uwritable = 0;
1392 int entries = 0, kentries = 0, uentries = 0;
1393 struct pv_entry *pv;
1395 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1397 /* the cache gets written back/invalidated on context switch.
1398 * therefore, if a user page shares an entry in the same page or
1399 * with the kernel map and at least one is writable, then the
1400 * cache entry must be set write-through.
1403 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1404 /* generate a count of the pv_entry uses */
1405 if (pv->pv_flags & PVF_WRITE) {
1406 if (pv->pv_pmap == pmap_kernel())
1408 else if (pv->pv_pmap == pm)
1412 if (pv->pv_pmap == pmap_kernel())
1415 if (pv->pv_pmap == pm)
1421 * check if the user duplicate mapping has
1424 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1428 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1429 /* check for user uncachable conditions - order is important */
1430 if (pm != pmap_kernel() &&
1431 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1433 if ((uentries > 1 && uwritable) || uwritable > 1) {
1435 /* user duplicate mapping */
1436 if (pv->pv_pmap != pmap_kernel())
1437 pv->pv_flags |= PVF_MWC;
1439 if (!(pv->pv_flags & PVF_NC)) {
1440 pv->pv_flags |= PVF_NC;
1441 pmap_set_cache_entry(pv, pm, va, -1);
1444 } else /* no longer a duplicate user */
1445 pv->pv_flags &= ~PVF_MWC;
1449 * check for kernel uncachable conditions
1450 * kernel writable or kernel readable with writable user entry
1452 if ((kwritable && entries) ||
1454 ((kwritable != writable) && kentries &&
1455 (pv->pv_pmap == pmap_kernel() ||
1456 (pv->pv_flags & PVF_WRITE) ||
1457 (pv->pv_flags & PVF_MWC)))) {
1459 if (!(pv->pv_flags & PVF_NC)) {
1460 pv->pv_flags |= PVF_NC;
1461 pmap_set_cache_entry(pv, pm, va, -1);
1466 /* kernel and user are cachable */
1467 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1468 (pv->pv_flags & PVF_NC)) {
1470 pv->pv_flags &= ~PVF_NC;
1471 pmap_set_cache_entry(pv, pm, va, 1);
1474 /* user is no longer sharable and writable */
1475 if (pm != pmap_kernel() &&
1476 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) &&
1477 !pmwc && (pv->pv_flags & PVF_NC)) {
1479 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1480 pmap_set_cache_entry(pv, pm, va, 1);
1484 if ((kwritable == 0) && (writable == 0)) {
1485 pg->md.pvh_attrs &= ~PVF_MOD;
1486 vm_page_flag_clear(pg, PG_WRITEABLE);
1492 * Modify pte bits for all ptes corresponding to the given physical address.
1493 * We use `maskbits' rather than `clearbits' because we're always passing
1494 * constants and the latter would require an extra inversion at run-time.
1497 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1499 struct l2_bucket *l2b;
1500 struct pv_entry *pv;
1501 pt_entry_t *ptep, npte, opte;
1507 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1509 if (maskbits & PVF_WRITE)
1510 maskbits |= PVF_MOD;
1512 * Clear saved attributes (modify, reference)
1514 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1516 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1521 * Loop over all current mappings setting/clearing as appropos
1523 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1526 oflags = pv->pv_flags;
1528 if (!(oflags & maskbits)) {
1529 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1530 /* It is safe to re-enable cacheing here. */
1532 l2b = pmap_get_l2_bucket(pm, va);
1533 ptep = &l2b->l2b_kva[l2pte_index(va)];
1534 *ptep |= pte_l2_s_cache_mode;
1537 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1542 pv->pv_flags &= ~maskbits;
1546 l2b = pmap_get_l2_bucket(pm, va);
1548 ptep = &l2b->l2b_kva[l2pte_index(va)];
1549 npte = opte = *ptep;
1551 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1552 if ((pv->pv_flags & PVF_NC)) {
1554 * Entry is not cacheable:
1556 * Don't turn caching on again if this is a
1557 * modified emulation. This would be
1558 * inconsitent with the settings created by
1559 * pmap_fix_cache(). Otherwise, it's safe
1560 * to re-enable cacheing.
1562 * There's no need to call pmap_fix_cache()
1563 * here: all pages are losing their write
1566 if (maskbits & PVF_WRITE) {
1567 npte |= pte_l2_s_cache_mode;
1568 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1571 if (opte & L2_S_PROT_W) {
1574 * Entry is writable/cacheable: check if pmap
1575 * is current if it is flush it, otherwise it
1576 * won't be in the cache
1578 if (PV_BEEN_EXECD(oflags))
1579 pmap_idcache_wbinv_range(pm, pv->pv_va,
1582 if (PV_BEEN_REFD(oflags))
1583 pmap_dcache_wb_range(pm, pv->pv_va,
1585 (maskbits & PVF_REF) ? TRUE : FALSE,
1589 /* make the pte read only */
1590 npte &= ~L2_S_PROT_W;
1593 if (maskbits & PVF_REF) {
1594 if ((pv->pv_flags & PVF_NC) == 0 &&
1595 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1597 * Check npte here; we may have already
1598 * done the wbinv above, and the validity
1599 * of the PTE is the same for opte and
1602 if (npte & L2_S_PROT_W) {
1603 if (PV_BEEN_EXECD(oflags))
1604 pmap_idcache_wbinv_range(pm,
1605 pv->pv_va, PAGE_SIZE);
1607 if (PV_BEEN_REFD(oflags))
1608 pmap_dcache_wb_range(pm,
1609 pv->pv_va, PAGE_SIZE,
1612 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1613 /* XXXJRT need idcache_inv_range */
1614 if (PV_BEEN_EXECD(oflags))
1615 pmap_idcache_wbinv_range(pm,
1616 pv->pv_va, PAGE_SIZE);
1618 if (PV_BEEN_REFD(oflags))
1619 pmap_dcache_wb_range(pm,
1620 pv->pv_va, PAGE_SIZE,
1626 * Make the PTE invalid so that we will take a
1627 * page fault the next time the mapping is
1630 npte &= ~L2_TYPE_MASK;
1631 npte |= L2_TYPE_INV;
1638 /* Flush the TLB entry if a current pmap. */
1639 if (PV_BEEN_EXECD(oflags))
1640 pmap_tlb_flushID_SE(pm, pv->pv_va);
1642 if (PV_BEEN_REFD(oflags))
1643 pmap_tlb_flushD_SE(pm, pv->pv_va);
1650 if (maskbits & PVF_WRITE)
1651 vm_page_flag_clear(pg, PG_WRITEABLE);
1656 * main pv_entry manipulation functions:
1657 * pmap_enter_pv: enter a mapping onto a vm_page list
1658 * pmap_remove_pv: remove a mappiing from a vm_page list
1660 * NOTE: pmap_enter_pv expects to lock the pvh itself
1661 * pmap_remove_pv expects te caller to lock the pvh before calling
1665 * pmap_enter_pv: enter a mapping onto a vm_page lst
1667 * => caller should hold the proper lock on pmap_main_lock
1668 * => caller should have pmap locked
1669 * => we will gain the lock on the vm_page and allocate the new pv_entry
1670 * => caller should adjust ptp's wire_count before calling
1671 * => caller should not adjust pmap's wire_count
1674 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1675 vm_offset_t va, u_int flags)
1680 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1682 if (pg->md.pv_kva) {
1683 /* PMAP_ASSERT_LOCKED(pmap_kernel()); */
1684 pve->pv_pmap = pmap_kernel();
1685 pve->pv_va = pg->md.pv_kva;
1686 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1689 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1690 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1691 if ((km = PMAP_OWNED(pmap_kernel())))
1692 PMAP_UNLOCK(pmap_kernel());
1693 vm_page_unlock_queues();
1694 if ((pve = pmap_get_pv_entry()) == NULL)
1695 panic("pmap_kenter_internal: no pv entries");
1696 vm_page_lock_queues();
1698 PMAP_LOCK(pmap_kernel());
1701 PMAP_ASSERT_LOCKED(pm);
1704 pve->pv_flags = flags;
1706 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1707 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1708 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1709 if (pve->pv_flags & PVF_WIRED)
1710 ++pm->pm_stats.wired_count;
1711 vm_page_flag_set(pg, PG_REFERENCED);
1716 * pmap_find_pv: Find a pv entry
1718 * => caller should hold lock on vm_page
1720 static PMAP_INLINE struct pv_entry *
1721 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1723 struct pv_entry *pv;
1725 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1726 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1727 if (pm == pv->pv_pmap && va == pv->pv_va)
1733 * vector_page_setprot:
1735 * Manipulate the protection of the vector page.
1738 vector_page_setprot(int prot)
1740 struct l2_bucket *l2b;
1743 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1745 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1747 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1749 cpu_tlb_flushD_SE(vector_page);
1754 * pmap_remove_pv: try to remove a mapping from a pv_list
1756 * => caller should hold proper lock on pmap_main_lock
1757 * => pmap should be locked
1758 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1759 * => caller should adjust ptp's wire_count and free PTP if needed
1760 * => caller should NOT adjust pmap's wire_count
1761 * => we return the removed pve
1765 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1768 struct pv_entry *pv;
1769 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1770 PMAP_ASSERT_LOCKED(pm);
1771 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1772 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1773 if (pve->pv_flags & PVF_WIRED)
1774 --pm->pm_stats.wired_count;
1775 if (pg->md.pvh_attrs & PVF_MOD)
1777 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1778 pg->md.pvh_attrs &= ~PVF_REF;
1780 vm_page_flag_set(pg, PG_REFERENCED);
1781 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1782 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1783 pmap_fix_cache(pg, pm, 0);
1784 else if (pve->pv_flags & PVF_WRITE) {
1785 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1786 if (pve->pv_flags & PVF_WRITE)
1789 pg->md.pvh_attrs &= ~PVF_MOD;
1790 vm_page_flag_clear(pg, PG_WRITEABLE);
1793 pv = TAILQ_FIRST(&pg->md.pv_list);
1794 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1795 TAILQ_NEXT(pv, pv_list) == NULL) {
1796 pg->md.pv_kva = pv->pv_va;
1797 /* a recursive pmap_nuke_pv */
1798 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1799 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1800 if (pv->pv_flags & PVF_WIRED)
1801 --pm->pm_stats.wired_count;
1802 pg->md.pvh_attrs &= ~PVF_REF;
1803 pg->md.pvh_attrs &= ~PVF_MOD;
1804 vm_page_flag_clear(pg, PG_WRITEABLE);
1805 pmap_free_pv_entry(pv);
1809 static struct pv_entry *
1810 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1812 struct pv_entry *pve;
1814 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1815 pve = TAILQ_FIRST(&pg->md.pv_list);
1818 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1819 pmap_nuke_pv(pg, pm, pve);
1822 pve = TAILQ_NEXT(pve, pv_list);
1825 if (pve == NULL && pg->md.pv_kva == va)
1828 return(pve); /* return removed pve */
1832 * pmap_modify_pv: Update pv flags
1834 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1835 * => caller should NOT adjust pmap's wire_count
1836 * => we return the old flags
1838 * Modify a physical-virtual mapping in the pv table
1841 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1842 u_int clr_mask, u_int set_mask)
1844 struct pv_entry *npv;
1845 u_int flags, oflags;
1847 PMAP_ASSERT_LOCKED(pm);
1848 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1849 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1853 * There is at least one VA mapping this page.
1856 if (clr_mask & (PVF_REF | PVF_MOD))
1857 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1859 oflags = npv->pv_flags;
1860 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1862 if ((flags ^ oflags) & PVF_WIRED) {
1863 if (flags & PVF_WIRED)
1864 ++pm->pm_stats.wired_count;
1866 --pm->pm_stats.wired_count;
1869 if ((flags ^ oflags) & PVF_WRITE)
1870 pmap_fix_cache(pg, pm, 0);
1875 /* Function to set the debug level of the pmap code */
1878 pmap_debug(int level)
1880 pmap_debug_level = level;
1881 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1883 #endif /* PMAP_DEBUG */
1886 pmap_pinit0(struct pmap *pmap)
1888 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1890 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1891 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1892 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1893 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1894 PMAP_LOCK_INIT(pmap);
1898 * Initialize a vm_page's machine-dependent fields.
1901 pmap_page_init(vm_page_t m)
1904 TAILQ_INIT(&m->md.pv_list);
1908 * Initialize the pmap module.
1909 * Called by vm_init, to initialize any structures that the pmap
1910 * system needs to map virtual memory.
1915 int shpgperproc = PMAP_SHPGPERPROC;
1917 PDEBUG(1, printf("pmap_init: phys_start = %08x\n"));
1920 * init the pv free list
1922 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1923 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1925 * Now it is safe to enable pv_table recording.
1927 PDEBUG(1, printf("pmap_init: done!\n"));
1929 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1931 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1932 pv_entry_high_water = 9 * (pv_entry_max / 10);
1933 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1934 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1935 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1936 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1937 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1939 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1944 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1946 struct l2_dtable *l2;
1947 struct l2_bucket *l2b;
1948 pd_entry_t *pl1pd, l1pd;
1949 pt_entry_t *ptep, pte;
1955 vm_page_lock_queues();
1959 * If there is no l2_dtable for this address, then the process
1960 * has no business accessing it.
1962 * Note: This will catch userland processes trying to access
1965 l2 = pm->pm_l2[L2_IDX(l1idx)];
1970 * Likewise if there is no L2 descriptor table
1972 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1973 if (l2b->l2b_kva == NULL)
1977 * Check the PTE itself.
1979 ptep = &l2b->l2b_kva[l2pte_index(va)];
1985 * Catch a userland access to the vector page mapped at 0x0
1987 if (user && (pte & L2_S_PROT_U) == 0)
1989 if (va == vector_page)
1994 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1996 * This looks like a good candidate for "page modified"
1999 struct pv_entry *pv;
2002 /* Extract the physical address of the page */
2003 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2006 /* Get the current flags for this page. */
2008 pv = pmap_find_pv(pg, pm, va);
2014 * Do the flags say this page is writable? If not then it
2015 * is a genuine write fault. If yes then the write fault is
2016 * our fault as we did not reflect the write access in the
2017 * PTE. Now we know a write has occurred we can correct this
2018 * and also set the modified bit
2020 if ((pv->pv_flags & PVF_WRITE) == 0) {
2024 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
2026 pv->pv_flags |= PVF_REF | PVF_MOD;
2029 * Re-enable write permissions for the page. No need to call
2030 * pmap_fix_cache(), since this is just a
2031 * modified-emulation fault, and the PVF_WRITE bit isn't
2032 * changing. We've already set the cacheable bits based on
2033 * the assumption that we can write to this page.
2035 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
2039 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
2041 * This looks like a good candidate for "page referenced"
2044 struct pv_entry *pv;
2047 /* Extract the physical address of the page */
2048 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
2050 /* Get the current flags for this page. */
2052 pv = pmap_find_pv(pg, pm, va);
2056 pg->md.pvh_attrs |= PVF_REF;
2057 pv->pv_flags |= PVF_REF;
2060 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2066 * We know there is a valid mapping here, so simply
2067 * fix up the L1 if necessary.
2069 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2070 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2071 if (*pl1pd != l1pd) {
2079 * There are bugs in the rev K SA110. This is a check for one
2082 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2083 curcpu()->ci_arm_cpurev < 3) {
2084 /* Always current pmap */
2085 if (l2pte_valid(pte)) {
2086 extern int kernel_debug;
2087 if (kernel_debug & 1) {
2088 struct proc *p = curlwp->l_proc;
2089 printf("prefetch_abort: page is already "
2090 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2091 printf("prefetch_abort: pc=%08lx proc=%p "
2092 "process=%s\n", va, p, p->p_comm);
2093 printf("prefetch_abort: far=%08x fs=%x\n",
2094 cpu_faultaddress(), cpu_faultstatus());
2097 if (kernel_debug & 2)
2103 #endif /* CPU_SA110 */
2107 * If 'rv == 0' at this point, it generally indicates that there is a
2108 * stale TLB entry for the faulting address. This happens when two or
2109 * more processes are sharing an L1. Since we don't flush the TLB on
2110 * a context switch between such processes, we can take domain faults
2111 * for mappings which exist at the same VA in both processes. EVEN IF
2112 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2115 * This is extremely likely to happen if pmap_enter() updated the L1
2116 * entry for a recently entered mapping. In this case, the TLB is
2117 * flushed for the new mapping, but there may still be TLB entries for
2118 * other mappings belonging to other processes in the 1MB range
2119 * covered by the L1 entry.
2121 * Since 'rv == 0', we know that the L1 already contains the correct
2122 * value, so the fault must be due to a stale TLB entry.
2124 * Since we always need to flush the TLB anyway in the case where we
2125 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2126 * stale TLB entries dynamically.
2128 * However, the above condition can ONLY happen if the current L1 is
2129 * being shared. If it happens when the L1 is unshared, it indicates
2130 * that other parts of the pmap are not doing their job WRT managing
2133 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2134 extern int last_fault_code;
2135 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2137 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2138 l2, l2b, ptep, pl1pd);
2139 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2140 pte, l1pd, last_fault_code);
2147 cpu_tlb_flushID_SE(va);
2153 vm_page_unlock_queues();
2161 struct l2_bucket *l2b;
2162 struct l1_ttable *l1;
2164 pt_entry_t *ptep, pte;
2165 vm_offset_t va, eva;
2168 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2170 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2172 for (loop = 0; loop < needed; loop++, l1++) {
2173 /* Allocate a L1 page table */
2174 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2175 0xffffffff, L1_TABLE_SIZE, 0);
2178 panic("Cannot allocate L1 KVM");
2180 eva = va + L1_TABLE_SIZE;
2181 pl1pt = (pd_entry_t *)va;
2184 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2185 ptep = &l2b->l2b_kva[l2pte_index(va)];
2187 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2190 cpu_tlb_flushD_SE(va);
2194 pmap_init_l1(l1, pl1pt);
2199 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2205 * This is used to stuff certain critical values into the PCB where they
2206 * can be accessed quickly from cpu_switch() et al.
2209 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2211 struct l2_bucket *l2b;
2213 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2214 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2215 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2217 if (vector_page < KERNBASE) {
2218 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2219 l2b = pmap_get_l2_bucket(pm, vector_page);
2220 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2221 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2223 pcb->pcb_pl1vec = NULL;
2227 pmap_activate(struct thread *td)
2232 pm = vmspace_pmap(td->td_proc->p_vmspace);
2236 pmap_set_pcb_pagedir(pm, pcb);
2238 if (td == curthread) {
2239 u_int cur_dacr, cur_ttb;
2241 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2242 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2244 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2246 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2247 cur_dacr == pcb->pcb_dacr) {
2249 * No need to switch address spaces.
2257 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2258 * to 'vector_page' in the incoming L1 table before switching
2259 * to it otherwise subsequent interrupts/exceptions (including
2260 * domain faults!) will jump into hyperspace.
2262 if (pcb->pcb_pl1vec) {
2264 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2266 * Don't need to PTE_SYNC() at this point since
2267 * cpu_setttb() is about to flush both the cache
2272 cpu_domains(pcb->pcb_dacr);
2273 cpu_setttb(pcb->pcb_pagedir);
2279 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2281 pd_entry_t *pdep, pde;
2282 pt_entry_t *ptep, pte;
2287 * Make sure the descriptor itself has the correct cache mode
2289 pdep = &kl1[L1_IDX(va)];
2292 if (l1pte_section_p(pde)) {
2293 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2294 *pdep = (pde & ~L1_S_CACHE_MASK) |
2295 pte_l1_s_cache_mode_pt;
2297 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2299 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2304 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2305 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2307 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2309 ptep = &ptep[l2pte_index(va)];
2311 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2312 *ptep = (pte & ~L2_S_CACHE_MASK) |
2313 pte_l2_s_cache_mode_pt;
2315 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2317 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2327 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2330 vm_offset_t va = *availp;
2331 struct l2_bucket *l2b;
2334 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2336 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2338 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2342 *availp = va + (PAGE_SIZE * pages);
2346 * Bootstrap the system enough to run with virtual memory.
2348 * On the arm this is called after mapping has already been enabled
2349 * and just syncs the pmap module with what has already been done.
2350 * [We can't call it easily with mapping off since the kernel is not
2351 * mapped with PA == VA, hence we would have to relocate every address
2352 * from the linked base (virtual) address "KERNBASE" to the actual
2353 * (physical) address starting relative to 0]
2355 #define PMAP_STATIC_L2_SIZE 16
2356 #ifdef ARM_USE_SMALL_ALLOC
2357 extern struct mtx smallalloc_mtx;
2361 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2363 static struct l1_ttable static_l1;
2364 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2365 struct l1_ttable *l1 = &static_l1;
2366 struct l2_dtable *l2;
2367 struct l2_bucket *l2b;
2369 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2374 int l1idx, l2idx, l2next = 0;
2376 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n",
2377 firstaddr, loadaddr));
2379 virtual_avail = firstaddr;
2380 kernel_pmap->pm_l1 = l1;
2381 kernel_l1pa = l1pt->pv_pa;
2384 * Scan the L1 translation table created by initarm() and create
2385 * the required metadata for all valid mappings found in it.
2387 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2388 pde = kernel_l1pt[l1idx];
2391 * We're only interested in Coarse mappings.
2392 * pmap_extract() can deal with section mappings without
2393 * recourse to checking L2 metadata.
2395 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2399 * Lookup the KVA of this L2 descriptor table
2401 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2402 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2405 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2406 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2410 * Fetch the associated L2 metadata structure.
2411 * Allocate a new one if necessary.
2413 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2414 if (l2next == PMAP_STATIC_L2_SIZE)
2415 panic("pmap_bootstrap: out of static L2s");
2416 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2417 &static_l2[l2next++];
2421 * One more L1 slot tracked...
2426 * Fill in the details of the L2 descriptor in the
2427 * appropriate bucket.
2429 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2430 l2b->l2b_kva = ptep;
2432 l2b->l2b_l1idx = l1idx;
2435 * Establish an initial occupancy count for this descriptor
2438 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2440 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2441 l2b->l2b_occupancy++;
2446 * Make sure the descriptor itself has the correct cache mode.
2447 * If not, fix it, but whine about the problem. Port-meisters
2448 * should consider this a clue to fix up their initarm()
2451 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2452 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2453 "L2 pte @ %p\n", ptep);
2459 * Ensure the primary (kernel) L1 has the correct cache mode for
2460 * a page table. Bitch if it is not correctly set.
2462 for (va = (vm_offset_t)kernel_l1pt;
2463 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2464 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2465 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2466 "primary L1 @ 0x%x\n", va);
2469 cpu_dcache_wbinv_all();
2470 cpu_l2cache_wbinv_all();
2474 PMAP_LOCK_INIT(kernel_pmap);
2475 kernel_pmap->pm_active = -1;
2476 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2477 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2480 * Reserve some special page table entries/VA space for temporary
2483 #define SYSMAP(c, p, v, n) \
2484 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2486 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2487 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2488 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2489 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2490 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2491 pmap_alloc_specials(&virtual_avail,
2492 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2493 &pmap_kernel_l2ptp_kva, NULL);
2495 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2496 pmap_alloc_specials(&virtual_avail,
2497 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2498 &pmap_kernel_l2dtable_kva, NULL);
2500 pmap_alloc_specials(&virtual_avail,
2501 1, (vm_offset_t*)&_tmppt, NULL);
2502 pmap_alloc_specials(&virtual_avail,
2503 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2504 SLIST_INIT(&l1_list);
2505 TAILQ_INIT(&l1_lru_list);
2506 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2507 pmap_init_l1(l1, kernel_l1pt);
2508 cpu_dcache_wbinv_all();
2509 cpu_l2cache_wbinv_all();
2511 virtual_avail = round_page(virtual_avail);
2512 virtual_end = lastaddr;
2513 kernel_vm_end = pmap_curmaxkvaddr;
2514 arm_nocache_startaddr = lastaddr;
2515 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2517 #ifdef ARM_USE_SMALL_ALLOC
2518 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2519 arm_init_smallalloc();
2521 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2524 /***************************************************
2525 * Pmap allocation/deallocation routines.
2526 ***************************************************/
2529 * Release any resources held by the given physical map.
2530 * Called when a pmap initialized by pmap_pinit is being released.
2531 * Should only be called if the map contains no valid mappings.
2534 pmap_release(pmap_t pmap)
2538 pmap_idcache_wbinv_all(pmap);
2539 cpu_l2cache_wbinv_all();
2540 pmap_tlb_flushID(pmap);
2542 if (vector_page < KERNBASE) {
2543 struct pcb *curpcb = PCPU_GET(curpcb);
2544 pcb = thread0.td_pcb;
2545 if (pmap_is_current(pmap)) {
2547 * Frob the L1 entry corresponding to the vector
2548 * page so that it contains the kernel pmap's domain
2549 * number. This will ensure pmap_remove() does not
2550 * pull the current vector page out from under us.
2553 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2554 cpu_domains(pcb->pcb_dacr);
2555 cpu_setttb(pcb->pcb_pagedir);
2558 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2560 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2561 * since this process has no remaining mappings of its own.
2563 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2564 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2565 curpcb->pcb_dacr = pcb->pcb_dacr;
2566 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2570 PMAP_LOCK_DESTROY(pmap);
2572 dprintf("pmap_release()\n");
2578 * Helper function for pmap_grow_l2_bucket()
2581 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2583 struct l2_bucket *l2b;
2588 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2591 pa = VM_PAGE_TO_PHYS(pg);
2596 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2598 ptep = &l2b->l2b_kva[l2pte_index(va)];
2599 *ptep = L2_S_PROTO | pa | cache_mode |
2600 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2606 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2607 * used by pmap_growkernel().
2609 static __inline struct l2_bucket *
2610 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2612 struct l2_dtable *l2;
2613 struct l2_bucket *l2b;
2614 struct l1_ttable *l1;
2621 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2623 * No mapping at this address, as there is
2624 * no entry in the L1 table.
2625 * Need to allocate a new l2_dtable.
2627 nva = pmap_kernel_l2dtable_kva;
2628 if ((nva & PAGE_MASK) == 0) {
2630 * Need to allocate a backing page
2632 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2636 l2 = (struct l2_dtable *)nva;
2637 nva += sizeof(struct l2_dtable);
2639 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2642 * The new l2_dtable straddles a page boundary.
2643 * Map in another page to cover it.
2645 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2649 pmap_kernel_l2dtable_kva = nva;
2652 * Link it into the parent pmap
2654 pm->pm_l2[L2_IDX(l1idx)] = l2;
2655 memset(l2, 0, sizeof(*l2));
2658 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2661 * Fetch pointer to the L2 page table associated with the address.
2663 if (l2b->l2b_kva == NULL) {
2667 * No L2 page table has been allocated. Chances are, this
2668 * is because we just allocated the l2_dtable, above.
2670 nva = pmap_kernel_l2ptp_kva;
2671 ptep = (pt_entry_t *)nva;
2672 if ((nva & PAGE_MASK) == 0) {
2674 * Need to allocate a backing page
2676 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2677 &pmap_kernel_l2ptp_phys))
2679 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2681 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2683 l2b->l2b_kva = ptep;
2684 l2b->l2b_l1idx = l1idx;
2685 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2687 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2688 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2691 /* Distribute new L1 entry to all other L1s */
2692 SLIST_FOREACH(l1, &l1_list, l1_link) {
2693 pl1pd = &l1->l1_kva[L1_IDX(va)];
2694 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2704 * grow the number of kernel page table entries, if needed
2707 pmap_growkernel(vm_offset_t addr)
2709 pmap_t kpm = pmap_kernel();
2711 if (addr <= pmap_curmaxkvaddr)
2712 return; /* we are OK */
2715 * whoops! we need to add kernel PTPs
2718 /* Map 1MB at a time */
2719 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2720 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2723 * flush out the cache, expensive but growkernel will happen so
2726 cpu_dcache_wbinv_all();
2727 cpu_l2cache_wbinv_all();
2730 kernel_vm_end = pmap_curmaxkvaddr;
2735 * Remove all pages from specified address space
2736 * this aids process exit speeds. Also, this code
2737 * is special cased for current process only, but
2738 * can have the more generic (and slightly slower)
2739 * mode enabled. This is much faster than pmap_remove
2740 * in the case of running down an entire address space.
2743 pmap_remove_pages(pmap_t pmap)
2745 struct pv_entry *pv, *npv;
2746 struct l2_bucket *l2b = NULL;
2750 vm_page_lock_queues();
2752 cpu_idcache_wbinv_all();
2753 cpu_l2cache_wbinv_all();
2754 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2755 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2756 /* Cannot remove wired or unmanaged pages now. */
2757 npv = TAILQ_NEXT(pv, pv_plist);
2760 pmap->pm_stats.resident_count--;
2761 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2762 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2763 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2764 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2765 #ifdef ARM_USE_SMALL_ALLOC
2766 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2768 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2772 npv = TAILQ_NEXT(pv, pv_plist);
2773 pmap_nuke_pv(m, pmap, pv);
2774 if (TAILQ_EMPTY(&m->md.pv_list))
2775 vm_page_flag_clear(m, PG_WRITEABLE);
2776 pmap_free_pv_entry(pv);
2777 pmap_free_l2_bucket(pmap, l2b, 1);
2779 vm_page_unlock_queues();
2786 /***************************************************
2787 * Low level mapping routines.....
2788 ***************************************************/
2790 #ifdef ARM_HAVE_SUPERSECTIONS
2791 /* Map a super section into the KVA. */
2794 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2796 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2797 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2798 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2799 struct l1_ttable *l1;
2800 vm_offset_t va0, va_end;
2802 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2803 ("Not a valid super section mapping"));
2804 if (flags & SECTION_CACHE)
2805 pd |= pte_l1_s_cache_mode;
2806 else if (flags & SECTION_PT)
2807 pd |= pte_l1_s_cache_mode_pt;
2808 va0 = va & L1_SUP_FRAME;
2809 va_end = va + L1_SUP_SIZE;
2810 SLIST_FOREACH(l1, &l1_list, l1_link) {
2812 for (; va < va_end; va += L1_S_SIZE) {
2813 l1->l1_kva[L1_IDX(va)] = pd;
2814 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2820 /* Map a section into the KVA. */
2823 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2825 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2826 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2827 struct l1_ttable *l1;
2829 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2830 ("Not a valid section mapping"));
2831 if (flags & SECTION_CACHE)
2832 pd |= pte_l1_s_cache_mode;
2833 else if (flags & SECTION_PT)
2834 pd |= pte_l1_s_cache_mode_pt;
2835 SLIST_FOREACH(l1, &l1_list, l1_link) {
2836 l1->l1_kva[L1_IDX(va)] = pd;
2837 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2842 * Make a temporary mapping for a physical address. This is only intended
2843 * to be used for panic dumps.
2846 pmap_kenter_temp(vm_paddr_t pa, int i)
2850 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2851 pmap_kenter(va, pa);
2852 return ((void *)crashdumpmap);
2856 * add a wired page to the kva
2857 * note that in order for the mapping to take effect -- you
2858 * should do a invltlb after doing the pmap_kenter...
2860 static PMAP_INLINE void
2861 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2863 struct l2_bucket *l2b;
2866 struct pv_entry *pve;
2869 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2870 (uint32_t) va, (uint32_t) pa));
2873 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2875 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2876 KASSERT(l2b != NULL, ("No L2 Bucket"));
2877 pte = &l2b->l2b_kva[l2pte_index(va)];
2879 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2880 (uint32_t) pte, opte, *pte));
2881 if (l2pte_valid(opte)) {
2885 l2b->l2b_occupancy++;
2887 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2888 VM_PROT_READ | VM_PROT_WRITE);
2889 if (flags & KENTER_CACHE)
2890 *pte |= pte_l2_s_cache_mode;
2891 if (flags & KENTER_USER)
2892 *pte |= L2_S_PROT_U;
2895 /* kernel direct mappings can be shared, so use a pv_entry
2896 * to ensure proper caching.
2898 * The pvzone is used to delay the recording of kernel
2899 * mappings until the VM is running.
2901 * This expects the physical memory to have vm_page_array entry.
2903 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa))) {
2904 vm_page_lock_queues();
2905 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva) {
2906 /* release vm_page lock for pv_entry UMA */
2907 vm_page_unlock_queues();
2908 if ((pve = pmap_get_pv_entry()) == NULL)
2909 panic("pmap_kenter_internal: no pv entries");
2910 vm_page_lock_queues();
2911 PMAP_LOCK(pmap_kernel());
2912 pmap_enter_pv(m, pve, pmap_kernel(), va,
2913 PVF_WRITE | PVF_UNMAN);
2914 pmap_fix_cache(m, pmap_kernel(), va);
2915 PMAP_UNLOCK(pmap_kernel());
2919 vm_page_unlock_queues();
2924 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2926 pmap_kenter_internal(va, pa, KENTER_CACHE);
2930 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2933 pmap_kenter_internal(va, pa, 0);
2937 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2940 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2942 * Call pmap_fault_fixup now, to make sure we'll have no exception
2943 * at the first use of the new address, or bad things will happen,
2944 * as we use one of these addresses in the exception handlers.
2946 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2950 * remove a page from the kernel pagetables
2953 pmap_kremove(vm_offset_t va)
2955 struct l2_bucket *l2b;
2956 pt_entry_t *pte, opte;
2957 struct pv_entry *pve;
2961 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2964 KASSERT(l2b != NULL, ("No L2 Bucket"));
2965 pte = &l2b->l2b_kva[l2pte_index(va)];
2967 if (l2pte_valid(opte)) {
2968 /* pa = vtophs(va) taken from pmap_extract() */
2969 switch (opte & L2_TYPE_MASK) {
2971 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2974 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2977 /* note: should never have to remove an allocation
2978 * before the pvzone is initialized.
2980 vm_page_lock_queues();
2981 PMAP_LOCK(pmap_kernel());
2982 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2983 (pve = pmap_remove_pv(m, pmap_kernel(), va)))
2984 pmap_free_pv_entry(pve);
2985 PMAP_UNLOCK(pmap_kernel());
2986 vm_page_unlock_queues();
2987 va = va & ~PAGE_MASK;
2988 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2989 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2990 cpu_tlb_flushD_SE(va);
2998 * Used to map a range of physical addresses into kernel
2999 * virtual address space.
3001 * The value passed in '*virt' is a suggested virtual address for
3002 * the mapping. Architectures which can support a direct-mapped
3003 * physical to virtual region can return the appropriate address
3004 * within that region, leaving '*virt' unchanged. Other
3005 * architectures should map the pages starting at '*virt' and
3006 * update '*virt' with the first usable address after the mapped
3010 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
3012 #ifdef ARM_USE_SMALL_ALLOC
3013 return (arm_ptovirt(start));
3015 vm_offset_t sva = *virt;
3016 vm_offset_t va = sva;
3018 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
3019 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
3022 while (start < end) {
3023 pmap_kenter(va, start);
3033 pmap_wb_page(vm_page_t m)
3035 struct pv_entry *pv;
3037 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3038 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
3039 (pv->pv_flags & PVF_WRITE) == 0);
3043 pmap_inv_page(vm_page_t m)
3045 struct pv_entry *pv;
3047 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3048 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
3051 * Add a list of wired pages to the kva
3052 * this routine is only used for temporary
3053 * kernel mappings that do not need to have
3054 * page modification or references recorded.
3055 * Note that old mappings are simply written
3056 * over. The page *must* be wired.
3059 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
3063 for (i = 0; i < count; i++) {
3065 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
3073 * this routine jerks page mappings from the
3074 * kernel -- it is meant only for temporary mappings.
3077 pmap_qremove(vm_offset_t va, int count)
3082 for (i = 0; i < count; i++) {
3085 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3094 * pmap_object_init_pt preloads the ptes for a given object
3095 * into the specified pmap. This eliminates the blast of soft
3096 * faults on process startup and immediately after an mmap.
3099 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3100 vm_pindex_t pindex, vm_size_t size)
3103 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3104 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3105 ("pmap_object_init_pt: non-device object"));
3110 * pmap_is_prefaultable:
3112 * Return whether or not the specified virtual address is elgible
3116 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3121 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3123 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3130 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3131 * Returns TRUE if the mapping exists, else FALSE.
3133 * NOTE: This function is only used by a couple of arm-specific modules.
3134 * It is not safe to take any pmap locks here, since we could be right
3135 * in the middle of debugging the pmap anyway...
3137 * It is possible for this routine to return FALSE even though a valid
3138 * mapping does exist. This is because we don't lock, so the metadata
3139 * state may be inconsistent.
3141 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3142 * a "section" mapping.
3145 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3147 struct l2_dtable *l2;
3148 pd_entry_t *pl1pd, l1pd;
3152 if (pm->pm_l1 == NULL)
3156 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3159 if (l1pte_section_p(l1pd)) {
3164 if (pm->pm_l2 == NULL)
3167 l2 = pm->pm_l2[L2_IDX(l1idx)];
3170 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3174 *ptp = &ptep[l2pte_index(va)];
3179 * Routine: pmap_remove_all
3181 * Removes this physical page from
3182 * all physical maps in which it resides.
3183 * Reflects back modify bits to the pager.
3186 * Original versions of this routine were very
3187 * inefficient because they iteratively called
3188 * pmap_remove (slow...)
3191 pmap_remove_all(vm_page_t m)
3195 struct l2_bucket *l2b;
3196 boolean_t flush = FALSE;
3200 #if defined(PMAP_DEBUG)
3202 * XXX This makes pmap_remove_all() illegal for non-managed pages!
3204 if (m->flags & PG_FICTITIOUS) {
3205 panic("pmap_remove_all: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m));
3209 if (TAILQ_EMPTY(&m->md.pv_list))
3211 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3212 pmap_remove_write(m);
3213 curpm = vmspace_pmap(curproc->p_vmspace);
3214 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3215 if (flush == FALSE && (pv->pv_pmap == curpm ||
3216 pv->pv_pmap == pmap_kernel()))
3219 PMAP_LOCK(pv->pv_pmap);
3221 * Cached contents were written-back in pmap_remove_write(),
3222 * but we still have to invalidate the cache entry to make
3223 * sure stale data are not retrieved when another page will be
3224 * mapped under this virtual address.
3226 if (pmap_is_current(pv->pv_pmap)) {
3227 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3228 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3231 if (pv->pv_flags & PVF_UNMAN) {
3232 /* remove the pv entry, but do not remove the mapping
3233 * and remember this is a kernel mapped page
3235 m->md.pv_kva = pv->pv_va;
3237 /* remove the mapping and pv entry */
3238 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3239 KASSERT(l2b != NULL, ("No l2 bucket"));
3240 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3242 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3243 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3244 if (pv->pv_flags & PVF_WIRED)
3245 pv->pv_pmap->pm_stats.wired_count--;
3246 pv->pv_pmap->pm_stats.resident_count--;
3247 flags |= pv->pv_flags;
3249 pmap_nuke_pv(m, pv->pv_pmap, pv);
3250 PMAP_UNLOCK(pv->pv_pmap);
3251 pmap_free_pv_entry(pv);
3255 if (PV_BEEN_EXECD(flags))
3256 pmap_tlb_flushID(curpm);
3258 pmap_tlb_flushD(curpm);
3260 vm_page_flag_clear(m, PG_WRITEABLE);
3265 * Set the physical protection on the
3266 * specified range of this map as requested.
3269 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3271 struct l2_bucket *l2b;
3272 pt_entry_t *ptep, pte;
3273 vm_offset_t next_bucket;
3277 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3278 pm, sva, eva, prot);
3280 if ((prot & VM_PROT_READ) == 0) {
3281 pmap_remove(pm, sva, eva);
3285 if (prot & VM_PROT_WRITE) {
3287 * If this is a read->write transition, just ignore it and let
3288 * vm_fault() take care of it later.
3293 vm_page_lock_queues();
3297 * OK, at this point, we know we're doing write-protect operation.
3298 * If the pmap is active, write-back the range.
3300 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3302 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3306 next_bucket = L2_NEXT_BUCKET(sva);
3307 if (next_bucket > eva)
3310 l2b = pmap_get_l2_bucket(pm, sva);
3316 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3318 while (sva < next_bucket) {
3319 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3323 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3324 pte &= ~L2_S_PROT_W;
3329 f = pmap_modify_pv(pg, pm, sva,
3333 f = PVF_REF | PVF_EXEC;
3339 if (PV_BEEN_EXECD(f))
3340 pmap_tlb_flushID_SE(pm, sva);
3342 if (PV_BEEN_REFD(f))
3343 pmap_tlb_flushD_SE(pm, sva);
3353 if (PV_BEEN_EXECD(flags))
3354 pmap_tlb_flushID(pm);
3356 if (PV_BEEN_REFD(flags))
3357 pmap_tlb_flushD(pm);
3359 vm_page_unlock_queues();
3366 * Insert the given physical page (p) at
3367 * the specified virtual address (v) in the
3368 * target physical map with the protection requested.
3370 * If specified, the page will be wired down, meaning
3371 * that the related pte can not be reclaimed.
3373 * NB: This is the only routine which MAY NOT lazy-evaluate
3374 * or lose information. That is, this routine must actually
3375 * insert this page into the given map NOW.
3379 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3380 vm_prot_t prot, boolean_t wired)
3383 vm_page_lock_queues();
3385 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3386 vm_page_unlock_queues();
3391 * The page queues and pmap must be locked.
3394 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3395 boolean_t wired, int flags)
3397 struct l2_bucket *l2b = NULL;
3398 struct vm_page *opg;
3399 struct pv_entry *pve = NULL;
3400 pt_entry_t *ptep, npte, opte;
3405 PMAP_ASSERT_LOCKED(pmap);
3406 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3407 if (va == vector_page) {
3408 pa = systempage.pv_pa;
3411 pa = VM_PAGE_TO_PHYS(m);
3413 if (prot & VM_PROT_WRITE)
3414 nflags |= PVF_WRITE;
3415 if (prot & VM_PROT_EXECUTE)
3418 nflags |= PVF_WIRED;
3419 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3420 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3422 if (pmap == pmap_kernel()) {
3423 l2b = pmap_get_l2_bucket(pmap, va);
3425 l2b = pmap_grow_l2_bucket(pmap, va);
3428 l2b = pmap_alloc_l2_bucket(pmap, va);
3430 if (flags & M_WAITOK) {
3432 vm_page_unlock_queues();
3434 vm_page_lock_queues();
3442 ptep = &l2b->l2b_kva[l2pte_index(va)];
3449 * There is already a mapping at this address.
3450 * If the physical address is different, lookup the
3453 if (l2pte_pa(opte) != pa)
3454 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3460 if ((prot & (VM_PROT_ALL)) ||
3461 (!m || m->md.pvh_attrs & PVF_REF)) {
3463 * - The access type indicates that we don't need
3464 * to do referenced emulation.
3466 * - The physical page has already been referenced
3467 * so no need to re-do referenced emulation here.
3473 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3474 (m->md.pvh_attrs & PVF_MOD))) {
3476 * This is a writable mapping, and the
3477 * page's mod state indicates it has
3478 * already been modified. Make it
3479 * writable from the outset.
3482 if (!(m->md.pvh_attrs & PVF_MOD))
3486 vm_page_flag_set(m, PG_REFERENCED);
3489 * Need to do page referenced emulation.
3491 npte |= L2_TYPE_INV;
3494 if (prot & VM_PROT_WRITE) {
3495 npte |= L2_S_PROT_W;
3497 vm_page_flag_set(m, PG_WRITEABLE);
3499 npte |= pte_l2_s_cache_mode;
3500 if (m && m == opg) {
3502 * We're changing the attrs of an existing mapping.
3504 oflags = pmap_modify_pv(m, pmap, va,
3505 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3506 PVF_MOD | PVF_REF, nflags);
3509 * We may need to flush the cache if we're
3512 if (pmap_is_current(pmap) &&
3513 (oflags & PVF_NC) == 0 &&
3514 (opte & L2_S_PROT_W) != 0 &&
3515 (prot & VM_PROT_WRITE) == 0) {
3516 cpu_dcache_wb_range(va, PAGE_SIZE);
3517 pmap_l2cache_wb_range(pmap, va, PAGE_SIZE);
3521 * New mapping, or changing the backing page
3522 * of an existing mapping.
3526 * Replacing an existing mapping with a new one.
3527 * It is part of our managed memory so we
3528 * must remove it from the PV list
3530 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3532 /* note for patch: the oflags/invalidation was moved
3533 * because PG_FICTITIOUS pages could free the pve
3535 oflags = pve->pv_flags;
3537 * If the old mapping was valid (ref/mod
3538 * emulation creates 'invalid' mappings
3539 * initially) then make sure to frob
3542 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3543 if (PV_BEEN_EXECD(oflags)) {
3544 pmap_idcache_wbinv_range(pmap, va,
3547 if (PV_BEEN_REFD(oflags)) {
3548 pmap_dcache_wb_range(pmap, va,
3550 (oflags & PVF_WRITE) == 0);
3554 /* free/allocate a pv_entry for UNMANAGED pages if
3555 * this physical page is not/is already mapped.
3558 if (m && ((m->flags & PG_FICTITIOUS) ||
3559 ((m->flags & PG_UNMANAGED) &&
3561 TAILQ_EMPTY(&m->md.pv_list)))) {
3562 pmap_free_pv_entry(pve);
3565 } else if (m && !(m->flags & PG_FICTITIOUS) &&
3566 (!(m->flags & PG_UNMANAGED) || m->md.pv_kva ||
3567 !TAILQ_EMPTY(&m->md.pv_list)))
3568 pve = pmap_get_pv_entry();
3569 } else if (m && !(m->flags & PG_FICTITIOUS) &&
3570 (!(m->flags & PG_UNMANAGED) || m->md.pv_kva ||
3571 !TAILQ_EMPTY(&m->md.pv_list)))
3572 pve = pmap_get_pv_entry();
3574 if (m && !(m->flags & PG_FICTITIOUS)) {
3575 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3576 ("pmap_enter: managed mapping within the clean submap"));
3577 if (m->flags & PG_UNMANAGED) {
3578 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3580 KASSERT(pve != NULL, ("No pv"));
3581 nflags |= PVF_UNMAN;
3582 pmap_enter_pv(m, pve, pmap, va, nflags);
3586 KASSERT(pve != NULL, ("No pv"));
3587 pmap_enter_pv(m, pve, pmap, va, nflags);
3592 * Make sure userland mappings get the right permissions
3594 if (pmap != pmap_kernel() && va != vector_page) {
3595 npte |= L2_S_PROT_U;
3599 * Keep the stats up to date
3602 l2b->l2b_occupancy++;
3603 pmap->pm_stats.resident_count++;
3608 * If this is just a wiring change, the two PTEs will be
3609 * identical, so there's no need to update the page table.
3612 boolean_t is_cached = pmap_is_current(pmap);
3617 * We only need to frob the cache/tlb if this pmap
3621 if (L1_IDX(va) != L1_IDX(vector_page) &&
3622 l2pte_valid(npte)) {
3624 * This mapping is likely to be accessed as
3625 * soon as we return to userland. Fix up the
3626 * L1 entry to avoid taking another
3627 * page/domain fault.
3629 pd_entry_t *pl1pd, l1pd;
3631 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3632 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3634 if (*pl1pd != l1pd) {
3641 if (PV_BEEN_EXECD(oflags))
3642 pmap_tlb_flushID_SE(pmap, va);
3643 else if (PV_BEEN_REFD(oflags))
3644 pmap_tlb_flushD_SE(pmap, va);
3648 pmap_fix_cache(m, pmap, va);
3653 * Maps a sequence of resident pages belonging to the same object.
3654 * The sequence begins with the given page m_start. This page is
3655 * mapped at the given virtual address start. Each subsequent page is
3656 * mapped at a virtual address that is offset from start by the same
3657 * amount as the page is offset from m_start within the object. The
3658 * last page in the sequence is the page with the largest offset from
3659 * m_start that can be mapped at a virtual address less than the given
3660 * virtual address end. Not every virtual page between start and end
3661 * is mapped; only those for which a resident page exists with the
3662 * corresponding offset from m_start are mapped.
3665 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3666 vm_page_t m_start, vm_prot_t prot)
3669 vm_pindex_t diff, psize;
3671 psize = atop(end - start);
3674 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3675 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3676 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3677 m = TAILQ_NEXT(m, listq);
3683 * this code makes some *MAJOR* assumptions:
3684 * 1. Current pmap & pmap exists.
3687 * 4. No page table pages.
3688 * but is *MUCH* faster than pmap_enter...
3692 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3696 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3702 * Routine: pmap_change_wiring
3703 * Function: Change the wiring attribute for a map/virtual-address
3705 * In/out conditions:
3706 * The mapping must already exist in the pmap.
3709 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3711 struct l2_bucket *l2b;
3712 pt_entry_t *ptep, pte;
3715 vm_page_lock_queues();
3717 l2b = pmap_get_l2_bucket(pmap, va);
3718 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3719 ptep = &l2b->l2b_kva[l2pte_index(va)];
3721 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3723 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
3724 vm_page_unlock_queues();
3730 * Copy the range specified by src_addr/len
3731 * from the source map to the range dst_addr/len
3732 * in the destination map.
3734 * This routine is only advisory and need not do anything.
3737 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3738 vm_size_t len, vm_offset_t src_addr)
3744 * Routine: pmap_extract
3746 * Extract the physical page address associated
3747 * with the given map/virtual_address pair.
3750 pmap_extract(pmap_t pm, vm_offset_t va)
3752 struct l2_dtable *l2;
3754 pt_entry_t *ptep, pte;
3760 l1pd = pm->pm_l1->l1_kva[l1idx];
3761 if (l1pte_section_p(l1pd)) {
3763 * These should only happen for pmap_kernel()
3765 KASSERT(pm == pmap_kernel(), ("huh"));
3766 /* XXX: what to do about the bits > 32 ? */
3767 if (l1pd & L1_S_SUPERSEC)
3768 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3770 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3773 * Note that we can't rely on the validity of the L1
3774 * descriptor as an indication that a mapping exists.
3775 * We have to look it up in the L2 dtable.
3777 l2 = pm->pm_l2[L2_IDX(l1idx)];
3780 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3785 ptep = &ptep[l2pte_index(va)];
3793 switch (pte & L2_TYPE_MASK) {
3795 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3799 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3809 * Atomically extract and hold the physical page with the given
3810 * pmap and virtual address pair if that mapping permits the given
3815 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3817 struct l2_dtable *l2;
3819 pt_entry_t *ptep, pte;
3825 vm_page_lock_queues();
3827 l1pd = pmap->pm_l1->l1_kva[l1idx];
3828 if (l1pte_section_p(l1pd)) {
3830 * These should only happen for pmap_kernel()
3832 KASSERT(pmap == pmap_kernel(), ("huh"));
3833 /* XXX: what to do about the bits > 32 ? */
3834 if (l1pd & L1_S_SUPERSEC)
3835 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3837 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3838 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3839 m = PHYS_TO_VM_PAGE(pa);
3845 * Note that we can't rely on the validity of the L1
3846 * descriptor as an indication that a mapping exists.
3847 * We have to look it up in the L2 dtable.
3849 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3852 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3854 vm_page_unlock_queues();
3858 ptep = &ptep[l2pte_index(va)];
3863 vm_page_unlock_queues();
3866 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3867 switch (pte & L2_TYPE_MASK) {
3869 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3873 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3876 m = PHYS_TO_VM_PAGE(pa);
3882 vm_page_unlock_queues();
3887 * Initialize a preallocated and zeroed pmap structure,
3888 * such as one in a vmspace structure.
3892 pmap_pinit(pmap_t pmap)
3894 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3896 PMAP_LOCK_INIT(pmap);
3897 pmap_alloc_l1(pmap);
3898 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3900 pmap->pm_active = 0;
3902 TAILQ_INIT(&pmap->pm_pvlist);
3903 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3904 pmap->pm_stats.resident_count = 1;
3905 if (vector_page < KERNBASE) {
3906 pmap_enter(pmap, vector_page,
3907 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3914 /***************************************************
3915 * page management routines.
3916 ***************************************************/
3920 pmap_free_pv_entry(pv_entry_t pv)
3923 uma_zfree(pvzone, pv);
3928 * get a new pv_entry, allocating a block from the system
3930 * the memory allocation is performed bypassing the malloc code
3931 * because of the possibility of allocations at interrupt time.
3934 pmap_get_pv_entry(void)
3936 pv_entry_t ret_value;
3939 if (pv_entry_count > pv_entry_high_water)
3940 pagedaemon_wakeup();
3941 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3946 * Remove the given range of addresses from the specified map.
3948 * It is assumed that the start and end are properly
3949 * rounded to the page size.
3951 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3953 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3955 struct l2_bucket *l2b;
3956 vm_offset_t next_bucket;
3959 u_int mappings, is_exec, is_refd;
3964 * we lock in the pmap => pv_head direction
3967 vm_page_lock_queues();
3972 * Do one L2 bucket's worth at a time.
3974 next_bucket = L2_NEXT_BUCKET(sva);
3975 if (next_bucket > eva)
3978 l2b = pmap_get_l2_bucket(pm, sva);
3984 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3987 while (sva < next_bucket) {
3996 * Nothing here, move along
4003 pm->pm_stats.resident_count--;
4009 * Update flags. In a number of circumstances,
4010 * we could cluster a lot of these and do a
4011 * number of sequential pages in one go.
4013 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
4014 struct pv_entry *pve;
4016 pve = pmap_remove_pv(pg, pm, sva);
4018 is_exec = PV_BEEN_EXECD(pve->pv_flags);
4019 is_refd = PV_BEEN_REFD(pve->pv_flags);
4020 pmap_free_pv_entry(pve);
4024 if (l2pte_valid(pte) && pmap_is_current(pm)) {
4025 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
4028 cpu_idcache_wbinv_range(sva,
4030 cpu_l2cache_wbinv_range(sva,
4032 cpu_tlb_flushID_SE(sva);
4033 } else if (is_refd) {
4034 cpu_dcache_wbinv_range(sva,
4036 cpu_l2cache_wbinv_range(sva,
4038 cpu_tlb_flushD_SE(sva);
4040 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
4041 /* flushall will also only get set for
4042 * for a current pmap
4044 cpu_idcache_wbinv_all();
4045 cpu_l2cache_wbinv_all();
4058 pmap_free_l2_bucket(pm, l2b, mappings);
4061 vm_page_unlock_queues();
4070 * Zero a given physical page by mapping it at a page hook point.
4071 * In doing the zero page op, the page we zero is mapped cachable, as with
4072 * StrongARM accesses to non-cached pages are non-burst making writing
4073 * _any_ bulk data very slow.
4075 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
4077 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4079 #ifdef ARM_USE_SMALL_ALLOC
4084 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4086 if (pg->md.pvh_list != NULL)
4087 panic("pmap_zero_page: page has mappings");
4090 if (_arm_bzero && size >= _min_bzero_size &&
4091 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4094 #ifdef ARM_USE_SMALL_ALLOC
4095 dstpg = (char *)arm_ptovirt(phys);
4096 if (off || size != PAGE_SIZE) {
4097 bzero(dstpg + off, size);
4098 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4099 cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size);
4101 bzero_page((vm_offset_t)dstpg);
4102 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4103 cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4109 * Hook in the page, zero it, invalidate the TLB as needed.
4111 * Note the temporary zero-page mapping must be a non-cached page in
4112 * order to work without corruption when write-allocate is enabled.
4114 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
4115 cpu_tlb_flushD_SE(cdstp);
4117 if (off || size != PAGE_SIZE)
4118 bzero((void *)(cdstp + off), size);
4125 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4127 #if ARM_MMU_XSCALE == 1
4129 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4131 #ifdef ARM_USE_SMALL_ALLOC
4135 if (_arm_bzero && size >= _min_bzero_size &&
4136 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4138 #ifdef ARM_USE_SMALL_ALLOC
4139 dstpg = (char *)arm_ptovirt(phys);
4140 if (off || size != PAGE_SIZE) {
4141 bzero(dstpg + off, size);
4142 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4144 bzero_page((vm_offset_t)dstpg);
4145 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4150 * Hook in the page, zero it, and purge the cache for that
4151 * zeroed page. Invalidate the TLB as needed.
4153 *cdst_pte = L2_S_PROTO | phys |
4154 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4155 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4157 cpu_tlb_flushD_SE(cdstp);
4159 if (off || size != PAGE_SIZE)
4160 bzero((void *)(cdstp + off), size);
4164 xscale_cache_clean_minidata();
4169 * Change the PTEs for the specified kernel mappings such that they
4170 * will use the mini data cache instead of the main data cache.
4173 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4175 struct l2_bucket *l2b;
4176 pt_entry_t *ptep, *sptep, pte;
4177 vm_offset_t next_bucket, eva;
4179 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4180 if (xscale_use_minidata == 0)
4187 next_bucket = L2_NEXT_BUCKET(va);
4188 if (next_bucket > eva)
4191 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4193 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4195 while (va < next_bucket) {
4197 if (!l2pte_minidata(pte)) {
4198 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4199 cpu_tlb_flushD_SE(va);
4200 *ptep = pte & ~L2_B;
4205 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4209 #endif /* ARM_MMU_XSCALE == 1 */
4212 * pmap_zero_page zeros the specified hardware page by mapping
4213 * the page into KVM and using bzero to clear its contents.
4216 pmap_zero_page(vm_page_t m)
4218 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4223 * pmap_zero_page_area zeros the specified hardware page by mapping
4224 * the page into KVM and using bzero to clear its contents.
4226 * off and size may not cover an area beyond a single hardware page.
4229 pmap_zero_page_area(vm_page_t m, int off, int size)
4232 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4237 * pmap_zero_page_idle zeros the specified hardware page by mapping
4238 * the page into KVM and using bzero to clear its contents. This
4239 * is intended to be called from the vm_pagezero process only and
4243 pmap_zero_page_idle(vm_page_t m)
4253 * This is a local function used to work out the best strategy to clean
4254 * a single page referenced by its entry in the PV table. It's used by
4255 * pmap_copy_page, pmap_zero page and maybe some others later on.
4257 * Its policy is effectively:
4258 * o If there are no mappings, we don't bother doing anything with the cache.
4259 * o If there is one mapping, we clean just that page.
4260 * o If there are multiple mappings, we clean the entire cache.
4262 * So that some functions can be further optimised, it returns 0 if it didn't
4263 * clean the entire cache, or 1 if it did.
4265 * XXX One bug in this routine is that if the pv_entry has a single page
4266 * mapped at 0x00000000 a whole cache clean will be performed rather than
4267 * just the 1 page. Since this should not occur in everyday use and if it does
4268 * it will just result in not the most efficient clean for the page.
4271 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4273 pmap_t pm, pm_to_clean = NULL;
4274 struct pv_entry *npv;
4275 u_int cache_needs_cleaning = 0;
4277 vm_offset_t page_to_clean = 0;
4280 /* nothing mapped in so nothing to flush */
4285 * Since we flush the cache each time we change to a different
4286 * user vmspace, we only need to flush the page if it is in the
4290 pm = vmspace_pmap(curproc->p_vmspace);
4294 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4295 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4296 flags |= npv->pv_flags;
4298 * The page is mapped non-cacheable in
4299 * this map. No need to flush the cache.
4301 if (npv->pv_flags & PVF_NC) {
4303 if (cache_needs_cleaning)
4304 panic("pmap_clean_page: "
4305 "cache inconsistency");
4308 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4310 if (cache_needs_cleaning) {
4314 page_to_clean = npv->pv_va;
4315 pm_to_clean = npv->pv_pmap;
4317 cache_needs_cleaning = 1;
4320 if (page_to_clean) {
4321 if (PV_BEEN_EXECD(flags))
4322 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4325 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4326 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4327 } else if (cache_needs_cleaning) {
4328 if (PV_BEEN_EXECD(flags))
4329 pmap_idcache_wbinv_all(pm);
4331 pmap_dcache_wbinv_all(pm);
4339 * pmap_copy_page copies the specified (machine independent)
4340 * page by mapping the page into virtual memory and using
4341 * bcopy to copy the page, one machine dependent page at a
4348 * Copy one physical page into another, by mapping the pages into
4349 * hook points. The same comment regarding cachability as in
4350 * pmap_zero_page also applies here.
4352 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4354 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4357 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4360 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4362 if (dst_pg->md.pvh_list != NULL)
4363 panic("pmap_copy_page: dst page has mappings");
4368 * Clean the source page. Hold the source page's lock for
4369 * the duration of the copy so that no other mappings can
4370 * be created while we have a potentially aliased mapping.
4374 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4377 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4380 * Map the pages into the page hook points, copy them, and purge
4381 * the cache for the appropriate page. Invalidate the TLB
4385 *csrc_pte = L2_S_PROTO | src |
4386 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4388 *cdst_pte = L2_S_PROTO | dst |
4389 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4391 cpu_tlb_flushD_SE(csrcp);
4392 cpu_tlb_flushD_SE(cdstp);
4394 bcopy_page(csrcp, cdstp);
4396 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4397 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4398 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4399 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4401 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4403 #if ARM_MMU_XSCALE == 1
4405 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4408 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4409 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4412 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4414 if (dst_pg->md.pvh_list != NULL)
4415 panic("pmap_copy_page: dst page has mappings");
4420 * Clean the source page. Hold the source page's lock for
4421 * the duration of the copy so that no other mappings can
4422 * be created while we have a potentially aliased mapping.
4426 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4429 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4432 * Map the pages into the page hook points, copy them, and purge
4433 * the cache for the appropriate page. Invalidate the TLB
4437 *csrc_pte = L2_S_PROTO | src |
4438 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4439 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4441 *cdst_pte = L2_S_PROTO | dst |
4442 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4443 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4445 cpu_tlb_flushD_SE(csrcp);
4446 cpu_tlb_flushD_SE(cdstp);
4448 bcopy_page(csrcp, cdstp);
4450 xscale_cache_clean_minidata();
4452 #endif /* ARM_MMU_XSCALE == 1 */
4455 pmap_copy_page(vm_page_t src, vm_page_t dst)
4457 #ifdef ARM_USE_SMALL_ALLOC
4458 vm_offset_t srcpg, dstpg;
4461 cpu_dcache_wbinv_all();
4462 cpu_l2cache_wbinv_all();
4463 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4464 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4465 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4467 #ifdef ARM_USE_SMALL_ALLOC
4468 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4469 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4470 bcopy_page(srcpg, dstpg);
4471 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4472 cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE);
4474 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4482 * this routine returns true if a physical page resides
4483 * in the given pmap.
4486 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4491 if (m->flags & PG_FICTITIOUS)
4495 * Not found, check current mappings returning immediately
4497 for (pv = TAILQ_FIRST(&m->md.pv_list);
4499 pv = TAILQ_NEXT(pv, pv_list)) {
4500 if (pv->pv_pmap == pmap) {
4511 * pmap_page_wired_mappings:
4513 * Return the number of managed mappings to the given physical page
4517 pmap_page_wired_mappings(vm_page_t m)
4523 if ((m->flags & PG_FICTITIOUS) != 0)
4525 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4526 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4527 if ((pv->pv_flags & PVF_WIRED) != 0)
4533 * pmap_ts_referenced:
4535 * Return the count of reference bits for a page, clearing all of them.
4538 pmap_ts_referenced(vm_page_t m)
4541 if (m->flags & PG_FICTITIOUS)
4543 return (pmap_clearbit(m, PVF_REF));
4548 pmap_is_modified(vm_page_t m)
4551 if (m->md.pvh_attrs & PVF_MOD)
4559 * Clear the modify bits on the specified physical page.
4562 pmap_clear_modify(vm_page_t m)
4565 if (m->md.pvh_attrs & PVF_MOD)
4566 pmap_clearbit(m, PVF_MOD);
4571 * pmap_clear_reference:
4573 * Clear the reference bit on the specified physical page.
4576 pmap_clear_reference(vm_page_t m)
4579 if (m->md.pvh_attrs & PVF_REF)
4580 pmap_clearbit(m, PVF_REF);
4585 * Clear the write and modified bits in each of the given page's mappings.
4588 pmap_remove_write(vm_page_t m)
4591 if (m->flags & PG_WRITEABLE)
4592 pmap_clearbit(m, PVF_WRITE);
4597 * perform the pmap work for mincore
4600 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4602 printf("pmap_mincore()\n");
4609 * Increase the starting virtual address of the given mapping if a
4610 * different alignment might result in more superpage mappings.
4613 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4614 vm_offset_t *addr, vm_size_t size)
4620 * Map a set of physical memory pages into the kernel virtual
4621 * address space. Return a pointer to where it is mapped. This
4622 * routine is intended to be used for mapping device memory,
4626 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4628 vm_offset_t va, tmpva, offset;
4630 offset = pa & PAGE_MASK;
4631 size = roundup(size, PAGE_SIZE);
4635 va = kmem_alloc_nofault(kernel_map, size);
4637 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4638 for (tmpva = va; size > 0;) {
4639 pmap_kenter_internal(tmpva, pa, 0);
4645 return ((void *)(va + offset));
4648 #define BOOTSTRAP_DEBUG
4653 * Create a single section mapping.
4656 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4657 int prot, int cache)
4659 pd_entry_t *pde = (pd_entry_t *) l1pt;
4662 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4671 fl = pte_l1_s_cache_mode;
4675 fl = pte_l1_s_cache_mode_pt;
4679 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4680 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4681 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4688 * Link the L2 page table specified by l2pv.pv_pa into the L1
4689 * page table at the slot for "va".
4692 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4694 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4695 u_int slot = va >> L1_S_SHIFT;
4697 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4699 #ifdef VERBOSE_INIT_ARM
4700 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4703 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4705 PTE_SYNC(&pde[slot]);
4707 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4715 * Create a single page mapping.
4718 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4721 pd_entry_t *pde = (pd_entry_t *) l1pt;
4725 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4734 fl = pte_l2_s_cache_mode;
4738 fl = pte_l2_s_cache_mode_pt;
4742 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4743 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4745 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4748 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4750 pte[l2pte_index(va)] =
4751 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4752 PTE_SYNC(&pte[l2pte_index(va)]);
4758 * Map a chunk of memory using the most efficient mappings
4759 * possible (section. large page, small page) into the
4760 * provided L1 and L2 tables at the specified virtual address.
4763 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4764 vm_size_t size, int prot, int cache)
4766 pd_entry_t *pde = (pd_entry_t *) l1pt;
4767 pt_entry_t *pte, f1, f2s, f2l;
4771 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4774 panic("pmap_map_chunk: no L1 table provided");
4776 #ifdef VERBOSE_INIT_ARM
4777 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4778 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4790 f1 = pte_l1_s_cache_mode;
4791 f2l = pte_l2_l_cache_mode;
4792 f2s = pte_l2_s_cache_mode;
4796 f1 = pte_l1_s_cache_mode_pt;
4797 f2l = pte_l2_l_cache_mode_pt;
4798 f2s = pte_l2_s_cache_mode_pt;
4805 /* See if we can use a section mapping. */
4806 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4807 #ifdef VERBOSE_INIT_ARM
4810 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4811 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4812 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4813 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4821 * Ok, we're going to use an L2 table. Make sure
4822 * one is actually in the corresponding L1 slot
4823 * for the current VA.
4825 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4826 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4828 pte = (pt_entry_t *) kernel_pt_lookup(
4829 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4831 panic("pmap_map_chunk: can't find L2 table for VA"
4833 /* See if we can use a L2 large page mapping. */
4834 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4835 #ifdef VERBOSE_INIT_ARM
4838 for (i = 0; i < 16; i++) {
4839 pte[l2pte_index(va) + i] =
4841 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4842 PTE_SYNC(&pte[l2pte_index(va) + i]);
4850 /* Use a small page mapping. */
4851 #ifdef VERBOSE_INIT_ARM
4854 pte[l2pte_index(va)] =
4855 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4856 PTE_SYNC(&pte[l2pte_index(va)]);
4861 #ifdef VERBOSE_INIT_ARM
4868 /********************** Static device map routines ***************************/
4870 static const struct pmap_devmap *pmap_devmap_table;
4873 * Register the devmap table. This is provided in case early console
4874 * initialization needs to register mappings created by bootstrap code
4875 * before pmap_devmap_bootstrap() is called.
4878 pmap_devmap_register(const struct pmap_devmap *table)
4881 pmap_devmap_table = table;
4885 * Map all of the static regions in the devmap table, and remember
4886 * the devmap table so other parts of the kernel can look up entries
4890 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4894 pmap_devmap_table = table;
4896 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4897 #ifdef VERBOSE_INIT_ARM
4898 printf("devmap: %08x -> %08x @ %08x\n",
4899 pmap_devmap_table[i].pd_pa,
4900 pmap_devmap_table[i].pd_pa +
4901 pmap_devmap_table[i].pd_size - 1,
4902 pmap_devmap_table[i].pd_va);
4904 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4905 pmap_devmap_table[i].pd_pa,
4906 pmap_devmap_table[i].pd_size,
4907 pmap_devmap_table[i].pd_prot,
4908 pmap_devmap_table[i].pd_cache);
4912 const struct pmap_devmap *
4913 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4917 if (pmap_devmap_table == NULL)
4920 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4921 if (pa >= pmap_devmap_table[i].pd_pa &&
4922 pa + size <= pmap_devmap_table[i].pd_pa +
4923 pmap_devmap_table[i].pd_size)
4924 return (&pmap_devmap_table[i]);
4930 const struct pmap_devmap *
4931 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4935 if (pmap_devmap_table == NULL)
4938 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4939 if (va >= pmap_devmap_table[i].pd_va &&
4940 va + size <= pmap_devmap_table[i].pd_va +
4941 pmap_devmap_table[i].pd_size)
4942 return (&pmap_devmap_table[i]);