sys/dev/age/if_age.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/endian.h>
  37 #include <sys/kernel.h>
  38 #include <sys/malloc.h>
  39 #include <sys/mbuf.h>
  40 #include <sys/rman.h>
  41 #include <sys/module.h>
  42 #include <sys/queue.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <net/bpf.h>
  49 #include <net/if.h>
  50 #include <net/if_arp.h>
  51 #include <net/ethernet.h>
  52 #include <net/if_dl.h>
  53 #include <net/if_media.h>
  54 #include <net/if_types.h>
  55 #include <net/if_vlan_var.h>
  56
  57 #include <netinet/in.h>
  58 #include <netinet/in_systm.h>
  59 #include <netinet/ip.h>
  60 #include <netinet/tcp.h>
  61
  62 #include <dev/mii/mii.h>
  63 #include <dev/mii/miivar.h>
  64
  65 #include <dev/pci/pcireg.h>
  66 #include <dev/pci/pcivar.h>
  67
  68 #include <machine/bus.h>
  69 #include <machine/in_cksum.h>
  70
  71 #include <dev/age/if_agereg.h>
  72 #include <dev/age/if_agevar.h>
  73
  74 /* "device miibus" required.  See GENERIC if you get errors here. */
  75 #include "miibus_if.h"
  76
  77 #ifndef IFCAP_VLAN_HWTSO
  78 #define IFCAP_VLAN_HWTSO        0
  79 #endif
  80 #define AGE_CSUM_FEATURES       (CSUM_TCP | CSUM_UDP)
  81
  82 MODULE_DEPEND(age, pci, 1, 1, 1);
  83 MODULE_DEPEND(age, ether, 1, 1, 1);
  84 MODULE_DEPEND(age, miibus, 1, 1, 1);
  85
  86 /* Tunables. */
  87 static int msi_disable = 0;
  88 static int msix_disable = 0;
  89 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
  90 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
  91
  92 /*
  93  * Devices supported by this driver.
  94  */
  95 static struct age_dev {
  96         uint16_t        age_vendorid;
  97         uint16_t        age_deviceid;
  98         const char      *age_name;
  99 } age_devs[] = {
 100         { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
 101             "Attansic Technology Corp, L1 Gigabit Ethernet" },
 102 };
 103
 104 static int age_miibus_readreg(device_t, int, int);
 105 static int age_miibus_writereg(device_t, int, int, int);
 106 static void age_miibus_statchg(device_t);
 107 static void age_mediastatus(struct ifnet *, struct ifmediareq *);
 108 static int age_mediachange(struct ifnet *);
 109 static int age_probe(device_t);
 110 static void age_get_macaddr(struct age_softc *);
 111 static void age_phy_reset(struct age_softc *);
 112 static int age_attach(device_t);
 113 static int age_detach(device_t);
 114 static void age_sysctl_node(struct age_softc *);
 115 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 116 static int age_check_boundary(struct age_softc *);
 117 static int age_dma_alloc(struct age_softc *);
 118 static void age_dma_free(struct age_softc *);
 119 static int age_shutdown(device_t);
 120 static void age_setwol(struct age_softc *);
 121 static int age_suspend(device_t);
 122 static int age_resume(device_t);
 123 static int age_encap(struct age_softc *, struct mbuf **);
 124 static void age_tx_task(void *, int);
 125 static void age_start(struct ifnet *);
 126 static void age_watchdog(struct age_softc *);
 127 static int age_ioctl(struct ifnet *, u_long, caddr_t);
 128 static void age_mac_config(struct age_softc *);
 129 static void age_link_task(void *, int);
 130 static void age_stats_update(struct age_softc *);
 131 static int age_intr(void *);
 132 static void age_int_task(void *, int);
 133 static void age_txintr(struct age_softc *, int);
 134 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
 135 static int age_rxintr(struct age_softc *, int, int);
 136 static void age_tick(void *);
 137 static void age_reset(struct age_softc *);
 138 static void age_init(void *);
 139 static void age_init_locked(struct age_softc *);
 140 static void age_stop(struct age_softc *);
 141 static void age_stop_txmac(struct age_softc *);
 142 static void age_stop_rxmac(struct age_softc *);
 143 static void age_init_tx_ring(struct age_softc *);
 144 static int age_init_rx_ring(struct age_softc *);
 145 static void age_init_rr_ring(struct age_softc *);
 146 static void age_init_cmb_block(struct age_softc *);
 147 static void age_init_smb_block(struct age_softc *);
 148 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
 149 static void age_rxvlan(struct age_softc *);
 150 static void age_rxfilter(struct age_softc *);
 151 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
 152 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
 153 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
 154 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
 155
 156
 157 static device_method_t age_methods[] = {
 158         /* Device interface. */
 159         DEVMETHOD(device_probe,         age_probe),
 160         DEVMETHOD(device_attach,        age_attach),
 161         DEVMETHOD(device_detach,        age_detach),
 162         DEVMETHOD(device_shutdown,      age_shutdown),
 163         DEVMETHOD(device_suspend,       age_suspend),
 164         DEVMETHOD(device_resume,        age_resume),
 165
 166         /* MII interface. */
 167         DEVMETHOD(miibus_readreg,       age_miibus_readreg),
 168         DEVMETHOD(miibus_writereg,      age_miibus_writereg),
 169         DEVMETHOD(miibus_statchg,       age_miibus_statchg),
 170
 171         { NULL, NULL }
 172 };
 173
 174 static driver_t age_driver = {
 175         "age",
 176         age_methods,
 177         sizeof(struct age_softc)
 178 };
 179
 180 static devclass_t age_devclass;
 181
 182 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0);
 183 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0);
 184
 185 static struct resource_spec age_res_spec_mem[] = {
 186         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 187         { -1,                   0,              0 }
 188 };
 189
 190 static struct resource_spec age_irq_spec_legacy[] = {
 191         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 192         { -1,                   0,              0 }
 193 };
 194
 195 static struct resource_spec age_irq_spec_msi[] = {
 196         { SYS_RES_IRQ,          1,              RF_ACTIVE },
 197         { -1,                   0,              0 }
 198 };
 199
 200 static struct resource_spec age_irq_spec_msix[] = {
 201         { SYS_RES_IRQ,          1,              RF_ACTIVE },
 202         { -1,                   0,              0 }
 203 };
 204
 205 /*
 206  *      Read a PHY register on the MII of the L1.
 207  */
 208 static int
 209 age_miibus_readreg(device_t dev, int phy, int reg)
 210 {
 211         struct age_softc *sc;
 212         uint32_t v;
 213         int i;
 214
 215         sc = device_get_softc(dev);
 216         if (phy != sc->age_phyaddr)
 217                 return (0);
 218
 219         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
 220             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 221         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 222                 DELAY(1);
 223                 v = CSR_READ_4(sc, AGE_MDIO);
 224                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 225                         break;
 226         }
 227
 228         if (i == 0) {
 229                 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
 230                 return (0);
 231         }
 232
 233         return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
 234 }
 235
 236 /*
 237  *      Write a PHY register on the MII of the L1.
 238  */
 239 static int
 240 age_miibus_writereg(device_t dev, int phy, int reg, int val)
 241 {
 242         struct age_softc *sc;
 243         uint32_t v;
 244         int i;
 245
 246         sc = device_get_softc(dev);
 247         if (phy != sc->age_phyaddr)
 248                 return (0);
 249
 250         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
 251             (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
 252             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 253         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 254                 DELAY(1);
 255                 v = CSR_READ_4(sc, AGE_MDIO);
 256                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 257                         break;
 258         }
 259
 260         if (i == 0)
 261                 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
 262
 263         return (0);
 264 }
 265
 266 /*
 267  *      Callback from MII layer when media changes.
 268  */
 269 static void
 270 age_miibus_statchg(device_t dev)
 271 {
 272         struct age_softc *sc;
 273
 274         sc = device_get_softc(dev);
 275         taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
 276 }
 277
 278 /*
 279  *      Get the current interface media status.
 280  */
 281 static void
 282 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 283 {
 284         struct age_softc *sc;
 285         struct mii_data *mii;
 286
 287         sc = ifp->if_softc;
 288         AGE_LOCK(sc);
 289         mii = device_get_softc(sc->age_miibus);
 290
 291         mii_pollstat(mii);
 292         AGE_UNLOCK(sc);
 293         ifmr->ifm_status = mii->mii_media_status;
 294         ifmr->ifm_active = mii->mii_media_active;
 295 }
 296
 297 /*
 298  *      Set hardware to newly-selected media.
 299  */
 300 static int
 301 age_mediachange(struct ifnet *ifp)
 302 {
 303         struct age_softc *sc;
 304         struct mii_data *mii;
 305         struct mii_softc *miisc;
 306         int error;
 307
 308         sc = ifp->if_softc;
 309         AGE_LOCK(sc);
 310         mii = device_get_softc(sc->age_miibus);
 311         if (mii->mii_instance != 0) {
 312                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 313                         mii_phy_reset(miisc);
 314         }
 315         error = mii_mediachg(mii);
 316         AGE_UNLOCK(sc);
 317
 318         return (error);
 319 }
 320
 321 static int
 322 age_probe(device_t dev)
 323 {
 324         struct age_dev *sp;
 325         int i;
 326         uint16_t vendor, devid;
 327
 328         vendor = pci_get_vendor(dev);
 329         devid = pci_get_device(dev);
 330         sp = age_devs;
 331         for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]);
 332             i++, sp++) {
 333                 if (vendor == sp->age_vendorid &&
 334                     devid == sp->age_deviceid) {
 335                         device_set_desc(dev, sp->age_name);
 336                         return (BUS_PROBE_DEFAULT);
 337                 }
 338         }
 339
 340         return (ENXIO);
 341 }
 342
 343 static void
 344 age_get_macaddr(struct age_softc *sc)
 345 {
 346         uint32_t ea[2], reg;
 347         int i, vpdc;
 348
 349         reg = CSR_READ_4(sc, AGE_SPI_CTRL);
 350         if ((reg & SPI_VPD_ENB) != 0) {
 351                 /* Get VPD stored in TWSI EEPROM. */
 352                 reg &= ~SPI_VPD_ENB;
 353                 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
 354         }
 355
 356         if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
 357                 /*
 358                  * PCI VPD capability found, let TWSI reload EEPROM.
 359                  * This will set ethernet address of controller.
 360                  */
 361                 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
 362                     TWSI_CTRL_SW_LD_START);
 363                 for (i = 100; i > 0; i--) {
 364                         DELAY(1000);
 365                         reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
 366                         if ((reg & TWSI_CTRL_SW_LD_START) == 0)
 367                                 break;
 368                 }
 369                 if (i == 0)
 370                         device_printf(sc->age_dev,
 371                             "reloading EEPROM timeout!\n");
 372         } else {
 373                 if (bootverbose)
 374                         device_printf(sc->age_dev,
 375                             "PCI VPD capability not found!\n");
 376         }
 377
 378         ea[0] = CSR_READ_4(sc, AGE_PAR0);
 379         ea[1] = CSR_READ_4(sc, AGE_PAR1);
 380         sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
 381         sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
 382         sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
 383         sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
 384         sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
 385         sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
 386 }
 387
 388 static void
 389 age_phy_reset(struct age_softc *sc)
 390 {
 391         uint16_t reg, pn;
 392         int i, linkup;
 393
 394         /* Reset PHY. */
 395         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
 396         DELAY(2000);
 397         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
 398         DELAY(2000);
 399
 400 #define ATPHY_DBG_ADDR          0x1D
 401 #define ATPHY_DBG_DATA          0x1E
 402 #define ATPHY_CDTC              0x16
 403 #define PHY_CDTC_ENB            0x0001
 404 #define PHY_CDTC_POFF           8
 405 #define ATPHY_CDTS              0x1C
 406 #define PHY_CDTS_STAT_OK        0x0000
 407 #define PHY_CDTS_STAT_SHORT     0x0100
 408 #define PHY_CDTS_STAT_OPEN      0x0200
 409 #define PHY_CDTS_STAT_INVAL     0x0300
 410 #define PHY_CDTS_STAT_MASK      0x0300
 411
 412         /* Check power saving mode. Magic from Linux. */
 413         age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
 414         for (linkup = 0, pn = 0; pn < 4; pn++) {
 415                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
 416                     (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
 417                 for (i = 200; i > 0; i--) {
 418                         DELAY(1000);
 419                         reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 420                             ATPHY_CDTC);
 421                         if ((reg & PHY_CDTC_ENB) == 0)
 422                                 break;
 423                 }
 424                 DELAY(1000);
 425                 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 426                     ATPHY_CDTS);
 427                 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
 428                         linkup++;
 429                         break;
 430                 }
 431         }
 432         age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
 433             BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
 434         if (linkup == 0) {
 435                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 436                     ATPHY_DBG_ADDR, 0);
 437                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 438                     ATPHY_DBG_DATA, 0x124E);
 439                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 440                     ATPHY_DBG_ADDR, 1);
 441                 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 442                     ATPHY_DBG_DATA);
 443                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 444                     ATPHY_DBG_DATA, reg | 0x03);
 445                 /* XXX */
 446                 DELAY(1500 * 1000);
 447                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 448                     ATPHY_DBG_ADDR, 0);
 449                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 450                     ATPHY_DBG_DATA, 0x024E);
 451     }
 452
 453 #undef  ATPHY_DBG_ADDR
 454 #undef  ATPHY_DBG_DATA
 455 #undef  ATPHY_CDTC
 456 #undef  PHY_CDTC_ENB
 457 #undef  PHY_CDTC_POFF
 458 #undef  ATPHY_CDTS
 459 #undef  PHY_CDTS_STAT_OK
 460 #undef  PHY_CDTS_STAT_SHORT
 461 #undef  PHY_CDTS_STAT_OPEN
 462 #undef  PHY_CDTS_STAT_INVAL
 463 #undef  PHY_CDTS_STAT_MASK
 464 }
 465
 466 static int
 467 age_attach(device_t dev)
 468 {
 469         struct age_softc *sc;
 470         struct ifnet *ifp;
 471         uint16_t burst;
 472         int error, i, msic, msixc, pmc;
 473
 474         error = 0;
 475         sc = device_get_softc(dev);
 476         sc->age_dev = dev;
 477
 478         mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 479             MTX_DEF);
 480         callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
 481         TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
 482         TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
 483
 484         /* Map the device. */
 485         pci_enable_busmaster(dev);
 486         sc->age_res_spec = age_res_spec_mem;
 487         sc->age_irq_spec = age_irq_spec_legacy;
 488         error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
 489         if (error != 0) {
 490                 device_printf(dev, "cannot allocate memory resources.\n");
 491                 goto fail;
 492         }
 493
 494         /* Set PHY address. */
 495         sc->age_phyaddr = AGE_PHY_ADDR;
 496
 497         /* Reset PHY. */
 498         age_phy_reset(sc);
 499
 500         /* Reset the ethernet controller. */
 501         age_reset(sc);
 502
 503         /* Get PCI and chip id/revision. */
 504         sc->age_rev = pci_get_revid(dev);
 505         sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
 506             MASTER_CHIP_REV_SHIFT;
 507         if (bootverbose) {
 508                 device_printf(dev, "PCI device revision : 0x%04x\n",
 509                     sc->age_rev);
 510                 device_printf(dev, "Chip id/revision : 0x%04x\n",
 511                     sc->age_chip_rev);
 512         }
 513
 514         /*
 515          * XXX
 516          * Unintialized hardware returns an invalid chip id/revision
 517          * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
 518          * unplugged cable results in putting hardware into automatic
 519          * power down mode which in turn returns invalld chip revision.
 520          */
 521         if (sc->age_chip_rev == 0xFFFF) {
 522                 device_printf(dev,"invalid chip revision : 0x%04x -- "
 523                     "not initialized?\n", sc->age_chip_rev);
 524                 error = ENXIO;
 525                 goto fail;
 526         }
 527
 528         device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
 529             CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
 530             CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
 531
 532         /* Allocate IRQ resources. */
 533         msixc = pci_msix_count(dev);
 534         msic = pci_msi_count(dev);
 535         if (bootverbose) {
 536                 device_printf(dev, "MSIX count : %d\n", msixc);
 537                 device_printf(dev, "MSI count : %d\n", msic);
 538         }
 539
 540         /* Prefer MSIX over MSI. */
 541         if (msix_disable == 0 || msi_disable == 0) {
 542                 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
 543                     pci_alloc_msix(dev, &msixc) == 0) {
 544                         if (msic == AGE_MSIX_MESSAGES) {
 545                                 device_printf(dev, "Using %d MSIX messages.\n",
 546                                     msixc);
 547                                 sc->age_flags |= AGE_FLAG_MSIX;
 548                                 sc->age_irq_spec = age_irq_spec_msix;
 549                         } else
 550                                 pci_release_msi(dev);
 551                 }
 552                 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
 553                     msic == AGE_MSI_MESSAGES &&
 554                     pci_alloc_msi(dev, &msic) == 0) {
 555                         if (msic == AGE_MSI_MESSAGES) {
 556                                 device_printf(dev, "Using %d MSI messages.\n",
 557                                     msic);
 558                                 sc->age_flags |= AGE_FLAG_MSI;
 559                                 sc->age_irq_spec = age_irq_spec_msi;
 560                         } else
 561                                 pci_release_msi(dev);
 562                 }
 563         }
 564
 565         error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
 566         if (error != 0) {
 567                 device_printf(dev, "cannot allocate IRQ resources.\n");
 568                 goto fail;
 569         }
 570
 571
 572         /* Get DMA parameters from PCIe device control register. */
 573         if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
 574                 sc->age_flags |= AGE_FLAG_PCIE;
 575                 burst = pci_read_config(dev, i + 0x08, 2);
 576                 /* Max read request size. */
 577                 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
 578                     DMA_CFG_RD_BURST_SHIFT;
 579                 /* Max payload size. */
 580                 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
 581                     DMA_CFG_WR_BURST_SHIFT;
 582                 if (bootverbose) {
 583                         device_printf(dev, "Read request size : %d bytes.\n",
 584                             128 << ((burst >> 12) & 0x07));
 585                         device_printf(dev, "TLP payload size : %d bytes.\n",
 586                             128 << ((burst >> 5) & 0x07));
 587                 }
 588         } else {
 589                 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
 590                 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
 591         }
 592
 593         /* Create device sysctl node. */
 594         age_sysctl_node(sc);
 595
 596         if ((error = age_dma_alloc(sc) != 0))
 597                 goto fail;
 598
 599         /* Load station address. */
 600         age_get_macaddr(sc);
 601
 602         ifp = sc->age_ifp = if_alloc(IFT_ETHER);
 603         if (ifp == NULL) {
 604                 device_printf(dev, "cannot allocate ifnet structure.\n");
 605                 error = ENXIO;
 606                 goto fail;
 607         }
 608
 609         ifp->if_softc = sc;
 610         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 611         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 612         ifp->if_ioctl = age_ioctl;
 613         ifp->if_start = age_start;
 614         ifp->if_init = age_init;
 615         ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1;
 616         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
 617         IFQ_SET_READY(&ifp->if_snd);
 618         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
 619         ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
 620         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
 621                 sc->age_flags |= AGE_FLAG_PMCAP;
 622                 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
 623         }
 624         ifp->if_capenable = ifp->if_capabilities;
 625
 626         /* Set up MII bus. */
 627         if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange,
 628             age_mediastatus)) != 0) {
 629                 device_printf(dev, "no PHY found!\n");
 630                 goto fail;
 631         }
 632
 633         ether_ifattach(ifp, sc->age_eaddr);
 634
 635         /* VLAN capability setup. */
 636         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 637         ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
 638         ifp->if_capenable = ifp->if_capabilities;
 639
 640         /* Tell the upper layer(s) we support long frames. */
 641         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 642
 643         /* Create local taskq. */
 644         TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp);
 645         sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
 646             taskqueue_thread_enqueue, &sc->age_tq);
 647         if (sc->age_tq == NULL) {
 648                 device_printf(dev, "could not create taskqueue.\n");
 649                 ether_ifdetach(ifp);
 650                 error = ENXIO;
 651                 goto fail;
 652         }
 653         taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
 654             device_get_nameunit(sc->age_dev));
 655
 656         if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
 657                 msic = AGE_MSIX_MESSAGES;
 658         else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
 659                 msic = AGE_MSI_MESSAGES;
 660         else
 661                 msic = 1;
 662         for (i = 0; i < msic; i++) {
 663                 error = bus_setup_intr(dev, sc->age_irq[i],
 664                     INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
 665                     &sc->age_intrhand[i]);
 666                 if (error != 0)
 667                         break;
 668         }
 669         if (error != 0) {
 670                 device_printf(dev, "could not set up interrupt handler.\n");
 671                 taskqueue_free(sc->age_tq);
 672                 sc->age_tq = NULL;
 673                 ether_ifdetach(ifp);
 674                 goto fail;
 675         }
 676
 677 fail:
 678         if (error != 0)
 679                 age_detach(dev);
 680
 681         return (error);
 682 }
 683
 684 static int
 685 age_detach(device_t dev)
 686 {
 687         struct age_softc *sc;
 688         struct ifnet *ifp;
 689         int i, msic;
 690
 691         sc = device_get_softc(dev);
 692
 693         ifp = sc->age_ifp;
 694         if (device_is_attached(dev)) {
 695                 AGE_LOCK(sc);
 696                 sc->age_flags |= AGE_FLAG_DETACH;
 697                 age_stop(sc);
 698                 AGE_UNLOCK(sc);
 699                 callout_drain(&sc->age_tick_ch);
 700                 taskqueue_drain(sc->age_tq, &sc->age_int_task);
 701                 taskqueue_drain(sc->age_tq, &sc->age_tx_task);
 702                 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
 703                 ether_ifdetach(ifp);
 704         }
 705
 706         if (sc->age_tq != NULL) {
 707                 taskqueue_drain(sc->age_tq, &sc->age_int_task);
 708                 taskqueue_free(sc->age_tq);
 709                 sc->age_tq = NULL;
 710         }
 711
 712         if (sc->age_miibus != NULL) {
 713                 device_delete_child(dev, sc->age_miibus);
 714                 sc->age_miibus = NULL;
 715         }
 716         bus_generic_detach(dev);
 717         age_dma_free(sc);
 718
 719         if (ifp != NULL) {
 720                 if_free(ifp);
 721                 sc->age_ifp = NULL;
 722         }
 723
 724         if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
 725                 msic = AGE_MSIX_MESSAGES;
 726         else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
 727                 msic = AGE_MSI_MESSAGES;
 728         else
 729                 msic = 1;
 730         for (i = 0; i < msic; i++) {
 731                 if (sc->age_intrhand[i] != NULL) {
 732                         bus_teardown_intr(dev, sc->age_irq[i],
 733                             sc->age_intrhand[i]);
 734                         sc->age_intrhand[i] = NULL;
 735                 }
 736         }
 737
 738         bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
 739         if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
 740                 pci_release_msi(dev);
 741         bus_release_resources(dev, sc->age_res_spec, sc->age_res);
 742         mtx_destroy(&sc->age_mtx);
 743
 744         return (0);
 745 }
 746
 747 static void
 748 age_sysctl_node(struct age_softc *sc)
 749 {
 750         int error;
 751
 752         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 753             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 754             "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats,
 755             "I", "Statistics");
 756
 757         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 758             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 759             "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0,
 760             sysctl_hw_age_int_mod, "I", "age interrupt moderation");
 761
 762         /* Pull in device tunables. */
 763         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 764         error = resource_int_value(device_get_name(sc->age_dev),
 765             device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
 766         if (error == 0) {
 767                 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
 768                     sc->age_int_mod > AGE_IM_TIMER_MAX) {
 769                         device_printf(sc->age_dev,
 770                             "int_mod value out of range; using default: %d\n",
 771                             AGE_IM_TIMER_DEFAULT);
 772                         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 773                 }
 774         }
 775
 776         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 777             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 778             "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit,
 779             0, sysctl_hw_age_proc_limit, "I",
 780             "max number of Rx events to process");
 781
 782         /* Pull in device tunables. */
 783         sc->age_process_limit = AGE_PROC_DEFAULT;
 784         error = resource_int_value(device_get_name(sc->age_dev),
 785             device_get_unit(sc->age_dev), "process_limit",
 786             &sc->age_process_limit);
 787         if (error == 0) {
 788                 if (sc->age_process_limit < AGE_PROC_MIN ||
 789                     sc->age_process_limit > AGE_PROC_MAX) {
 790                         device_printf(sc->age_dev,
 791                             "process_limit value out of range; "
 792                             "using default: %d\n", AGE_PROC_DEFAULT);
 793                         sc->age_process_limit = AGE_PROC_DEFAULT;
 794                 }
 795         }
 796 }
 797
 798 struct age_dmamap_arg {
 799         bus_addr_t      age_busaddr;
 800 };
 801
 802 static void
 803 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 804 {
 805         struct age_dmamap_arg *ctx;
 806
 807         if (error != 0)
 808                 return;
 809
 810         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 811
 812         ctx = (struct age_dmamap_arg *)arg;
 813         ctx->age_busaddr = segs[0].ds_addr;
 814 }
 815
 816 /*
 817  * Attansic L1 controller have single register to specify high
 818  * address part of DMA blocks. So all descriptor structures and
 819  * DMA memory blocks should have the same high address of given
 820  * 4GB address space(i.e. crossing 4GB boundary is not allowed).
 821  */
 822 static int
 823 age_check_boundary(struct age_softc *sc)
 824 {
 825         bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
 826         bus_addr_t cmb_block_end, smb_block_end;
 827
 828         /* Tx/Rx descriptor queue should reside within 4GB boundary. */
 829         tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
 830         rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
 831         rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
 832         cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
 833         smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
 834
 835         if ((AGE_ADDR_HI(tx_ring_end) !=
 836             AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
 837             (AGE_ADDR_HI(rx_ring_end) !=
 838             AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
 839             (AGE_ADDR_HI(rr_ring_end) !=
 840             AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
 841             (AGE_ADDR_HI(cmb_block_end) !=
 842             AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
 843             (AGE_ADDR_HI(smb_block_end) !=
 844             AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
 845                 return (EFBIG);
 846
 847         if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
 848             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
 849             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
 850             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
 851                 return (EFBIG);
 852
 853         return (0);
 854 }
 855
 856 static int
 857 age_dma_alloc(struct age_softc *sc)
 858 {
 859         struct age_txdesc *txd;
 860         struct age_rxdesc *rxd;
 861         bus_addr_t lowaddr;
 862         struct age_dmamap_arg ctx;
 863         int error, i;
 864
 865         lowaddr = BUS_SPACE_MAXADDR;
 866
 867 again:
 868         /* Create parent ring/DMA block tag. */
 869         error = bus_dma_tag_create(
 870             bus_get_dma_tag(sc->age_dev), /* parent */
 871             1, 0,                       /* alignment, boundary */
 872             lowaddr,                    /* lowaddr */
 873             BUS_SPACE_MAXADDR,          /* highaddr */
 874             NULL, NULL,                 /* filter, filterarg */
 875             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
 876             0,                          /* nsegments */
 877             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
 878             0,                          /* flags */
 879             NULL, NULL,                 /* lockfunc, lockarg */
 880             &sc->age_cdata.age_parent_tag);
 881         if (error != 0) {
 882                 device_printf(sc->age_dev,
 883                     "could not create parent DMA tag.\n");
 884                 goto fail;
 885         }
 886
 887         /* Create tag for Tx ring. */
 888         error = bus_dma_tag_create(
 889             sc->age_cdata.age_parent_tag, /* parent */
 890             AGE_TX_RING_ALIGN, 0,       /* alignment, boundary */
 891             BUS_SPACE_MAXADDR,          /* lowaddr */
 892             BUS_SPACE_MAXADDR,          /* highaddr */
 893             NULL, NULL,                 /* filter, filterarg */
 894             AGE_TX_RING_SZ,             /* maxsize */
 895             1,                          /* nsegments */
 896             AGE_TX_RING_SZ,             /* maxsegsize */
 897             0,                          /* flags */
 898             NULL, NULL,                 /* lockfunc, lockarg */
 899             &sc->age_cdata.age_tx_ring_tag);
 900         if (error != 0) {
 901                 device_printf(sc->age_dev,
 902                     "could not create Tx ring DMA tag.\n");
 903                 goto fail;
 904         }
 905
 906         /* Create tag for Rx ring. */
 907         error = bus_dma_tag_create(
 908             sc->age_cdata.age_parent_tag, /* parent */
 909             AGE_RX_RING_ALIGN, 0,       /* alignment, boundary */
 910             BUS_SPACE_MAXADDR,          /* lowaddr */
 911             BUS_SPACE_MAXADDR,          /* highaddr */
 912             NULL, NULL,                 /* filter, filterarg */
 913             AGE_RX_RING_SZ,             /* maxsize */
 914             1,                          /* nsegments */
 915             AGE_RX_RING_SZ,             /* maxsegsize */
 916             0,                          /* flags */
 917             NULL, NULL,                 /* lockfunc, lockarg */
 918             &sc->age_cdata.age_rx_ring_tag);
 919         if (error != 0) {
 920                 device_printf(sc->age_dev,
 921                     "could not create Rx ring DMA tag.\n");
 922                 goto fail;
 923         }
 924
 925         /* Create tag for Rx return ring. */
 926         error = bus_dma_tag_create(
 927             sc->age_cdata.age_parent_tag, /* parent */
 928             AGE_RR_RING_ALIGN, 0,       /* alignment, boundary */
 929             BUS_SPACE_MAXADDR,          /* lowaddr */
 930             BUS_SPACE_MAXADDR,          /* highaddr */
 931             NULL, NULL,                 /* filter, filterarg */
 932             AGE_RR_RING_SZ,             /* maxsize */
 933             1,                          /* nsegments */
 934             AGE_RR_RING_SZ,             /* maxsegsize */
 935             0,                          /* flags */
 936             NULL, NULL,                 /* lockfunc, lockarg */
 937             &sc->age_cdata.age_rr_ring_tag);
 938         if (error != 0) {
 939                 device_printf(sc->age_dev,
 940                     "could not create Rx return ring DMA tag.\n");
 941                 goto fail;
 942         }
 943
 944         /* Create tag for coalesing message block. */
 945         error = bus_dma_tag_create(
 946             sc->age_cdata.age_parent_tag, /* parent */
 947             AGE_CMB_ALIGN, 0,           /* alignment, boundary */
 948             BUS_SPACE_MAXADDR,          /* lowaddr */
 949             BUS_SPACE_MAXADDR,          /* highaddr */
 950             NULL, NULL,                 /* filter, filterarg */
 951             AGE_CMB_BLOCK_SZ,           /* maxsize */
 952             1,                          /* nsegments */
 953             AGE_CMB_BLOCK_SZ,           /* maxsegsize */
 954             0,                          /* flags */
 955             NULL, NULL,                 /* lockfunc, lockarg */
 956             &sc->age_cdata.age_cmb_block_tag);
 957         if (error != 0) {
 958                 device_printf(sc->age_dev,
 959                     "could not create CMB DMA tag.\n");
 960                 goto fail;
 961         }
 962
 963         /* Create tag for statistics message block. */
 964         error = bus_dma_tag_create(
 965             sc->age_cdata.age_parent_tag, /* parent */
 966             AGE_SMB_ALIGN, 0,           /* alignment, boundary */
 967             BUS_SPACE_MAXADDR,          /* lowaddr */
 968             BUS_SPACE_MAXADDR,          /* highaddr */
 969             NULL, NULL,                 /* filter, filterarg */
 970             AGE_SMB_BLOCK_SZ,           /* maxsize */
 971             1,                          /* nsegments */
 972             AGE_SMB_BLOCK_SZ,           /* maxsegsize */
 973             0,                          /* flags */
 974             NULL, NULL,                 /* lockfunc, lockarg */
 975             &sc->age_cdata.age_smb_block_tag);
 976         if (error != 0) {
 977                 device_printf(sc->age_dev,
 978                     "could not create SMB DMA tag.\n");
 979                 goto fail;
 980         }
 981
 982         /* Allocate DMA'able memory and load the DMA map. */
 983         error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
 984             (void **)&sc->age_rdata.age_tx_ring,
 985             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
 986             &sc->age_cdata.age_tx_ring_map);
 987         if (error != 0) {
 988                 device_printf(sc->age_dev,
 989                     "could not allocate DMA'able memory for Tx ring.\n");
 990                 goto fail;
 991         }
 992         ctx.age_busaddr = 0;
 993         error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
 994             sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
 995             AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
 996         if (error != 0 || ctx.age_busaddr == 0) {
 997                 device_printf(sc->age_dev,
 998                     "could not load DMA'able memory for Tx ring.\n");
 999                 goto fail;
1000         }
1001         sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
1002         /* Rx ring */
1003         error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
1004             (void **)&sc->age_rdata.age_rx_ring,
1005             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1006             &sc->age_cdata.age_rx_ring_map);
1007         if (error != 0) {
1008                 device_printf(sc->age_dev,
1009                     "could not allocate DMA'able memory for Rx ring.\n");
1010                 goto fail;
1011         }
1012         ctx.age_busaddr = 0;
1013         error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1014             sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1015             AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1016         if (error != 0 || ctx.age_busaddr == 0) {
1017                 device_printf(sc->age_dev,
1018                     "could not load DMA'able memory for Rx ring.\n");
1019                 goto fail;
1020         }
1021         sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1022         /* Rx return ring */
1023         error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1024             (void **)&sc->age_rdata.age_rr_ring,
1025             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1026             &sc->age_cdata.age_rr_ring_map);
1027         if (error != 0) {
1028                 device_printf(sc->age_dev,
1029                     "could not allocate DMA'able memory for Rx return ring.\n");
1030                 goto fail;
1031         }
1032         ctx.age_busaddr = 0;
1033         error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1034             sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1035             AGE_RR_RING_SZ, age_dmamap_cb,
1036             &ctx, 0);
1037         if (error != 0 || ctx.age_busaddr == 0) {
1038                 device_printf(sc->age_dev,
1039                     "could not load DMA'able memory for Rx return ring.\n");
1040                 goto fail;
1041         }
1042         sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1043         /* CMB block */
1044         error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1045             (void **)&sc->age_rdata.age_cmb_block,
1046             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1047             &sc->age_cdata.age_cmb_block_map);
1048         if (error != 0) {
1049                 device_printf(sc->age_dev,
1050                     "could not allocate DMA'able memory for CMB block.\n");
1051                 goto fail;
1052         }
1053         ctx.age_busaddr = 0;
1054         error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1055             sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1056             AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1057         if (error != 0 || ctx.age_busaddr == 0) {
1058                 device_printf(sc->age_dev,
1059                     "could not load DMA'able memory for CMB block.\n");
1060                 goto fail;
1061         }
1062         sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1063         /* SMB block */
1064         error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1065             (void **)&sc->age_rdata.age_smb_block,
1066             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1067             &sc->age_cdata.age_smb_block_map);
1068         if (error != 0) {
1069                 device_printf(sc->age_dev,
1070                     "could not allocate DMA'able memory for SMB block.\n");
1071                 goto fail;
1072         }
1073         ctx.age_busaddr = 0;
1074         error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1075             sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1076             AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1077         if (error != 0 || ctx.age_busaddr == 0) {
1078                 device_printf(sc->age_dev,
1079                     "could not load DMA'able memory for SMB block.\n");
1080                 goto fail;
1081         }
1082         sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1083
1084         /*
1085          * All ring buffer and DMA blocks should have the same
1086          * high address part of 64bit DMA address space.
1087          */
1088         if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1089             (error = age_check_boundary(sc)) != 0) {
1090                 device_printf(sc->age_dev, "4GB boundary crossed, "
1091                     "switching to 32bit DMA addressing mode.\n");
1092                 age_dma_free(sc);
1093                 /* Limit DMA address space to 32bit and try again. */
1094                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1095                 goto again;
1096         }
1097
1098         /*
1099          * Create Tx/Rx buffer parent tag.
1100          * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1101          * so it needs separate parent DMA tag.
1102          */
1103         error = bus_dma_tag_create(
1104             bus_get_dma_tag(sc->age_dev), /* parent */
1105             1, 0,                       /* alignment, boundary */
1106             BUS_SPACE_MAXADDR,          /* lowaddr */
1107             BUS_SPACE_MAXADDR,          /* highaddr */
1108             NULL, NULL,                 /* filter, filterarg */
1109             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1110             0,                          /* nsegments */
1111             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1112             0,                          /* flags */
1113             NULL, NULL,                 /* lockfunc, lockarg */
1114             &sc->age_cdata.age_buffer_tag);
1115         if (error != 0) {
1116                 device_printf(sc->age_dev,
1117                     "could not create parent buffer DMA tag.\n");
1118                 goto fail;
1119         }
1120
1121         /* Create tag for Tx buffers. */
1122         error = bus_dma_tag_create(
1123             sc->age_cdata.age_buffer_tag, /* parent */
1124             1, 0,                       /* alignment, boundary */
1125             BUS_SPACE_MAXADDR,          /* lowaddr */
1126             BUS_SPACE_MAXADDR,          /* highaddr */
1127             NULL, NULL,                 /* filter, filterarg */
1128             AGE_TSO_MAXSIZE,            /* maxsize */
1129             AGE_MAXTXSEGS,              /* nsegments */
1130             AGE_TSO_MAXSEGSIZE,         /* maxsegsize */
1131             0,                          /* flags */
1132             NULL, NULL,                 /* lockfunc, lockarg */
1133             &sc->age_cdata.age_tx_tag);
1134         if (error != 0) {
1135                 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1136                 goto fail;
1137         }
1138
1139         /* Create tag for Rx buffers. */
1140         error = bus_dma_tag_create(
1141             sc->age_cdata.age_buffer_tag, /* parent */
1142             1, 0,                       /* alignment, boundary */
1143             BUS_SPACE_MAXADDR,          /* lowaddr */
1144             BUS_SPACE_MAXADDR,          /* highaddr */
1145             NULL, NULL,                 /* filter, filterarg */
1146             MCLBYTES,                   /* maxsize */
1147             1,                          /* nsegments */
1148             MCLBYTES,                   /* maxsegsize */
1149             0,                          /* flags */
1150             NULL, NULL,                 /* lockfunc, lockarg */
1151             &sc->age_cdata.age_rx_tag);
1152         if (error != 0) {
1153                 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1154                 goto fail;
1155         }
1156
1157         /* Create DMA maps for Tx buffers. */
1158         for (i = 0; i < AGE_TX_RING_CNT; i++) {
1159                 txd = &sc->age_cdata.age_txdesc[i];
1160                 txd->tx_m = NULL;
1161                 txd->tx_dmamap = NULL;
1162                 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1163                     &txd->tx_dmamap);
1164                 if (error != 0) {
1165                         device_printf(sc->age_dev,
1166                             "could not create Tx dmamap.\n");
1167                         goto fail;
1168                 }
1169         }
1170         /* Create DMA maps for Rx buffers. */
1171         if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1172             &sc->age_cdata.age_rx_sparemap)) != 0) {
1173                 device_printf(sc->age_dev,
1174                     "could not create spare Rx dmamap.\n");
1175                 goto fail;
1176         }
1177         for (i = 0; i < AGE_RX_RING_CNT; i++) {
1178                 rxd = &sc->age_cdata.age_rxdesc[i];
1179                 rxd->rx_m = NULL;
1180                 rxd->rx_dmamap = NULL;
1181                 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1182                     &rxd->rx_dmamap);
1183                 if (error != 0) {
1184                         device_printf(sc->age_dev,
1185                             "could not create Rx dmamap.\n");
1186                         goto fail;
1187                 }
1188         }
1189
1190 fail:
1191         return (error);
1192 }
1193
1194 static void
1195 age_dma_free(struct age_softc *sc)
1196 {
1197         struct age_txdesc *txd;
1198         struct age_rxdesc *rxd;
1199         int i;
1200
1201         /* Tx buffers */
1202         if (sc->age_cdata.age_tx_tag != NULL) {
1203                 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1204                         txd = &sc->age_cdata.age_txdesc[i];
1205                         if (txd->tx_dmamap != NULL) {
1206                                 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1207                                     txd->tx_dmamap);
1208                                 txd->tx_dmamap = NULL;
1209                         }
1210                 }
1211                 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1212                 sc->age_cdata.age_tx_tag = NULL;
1213         }
1214         /* Rx buffers */
1215         if (sc->age_cdata.age_rx_tag != NULL) {
1216                 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1217                         rxd = &sc->age_cdata.age_rxdesc[i];
1218                         if (rxd->rx_dmamap != NULL) {
1219                                 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1220                                     rxd->rx_dmamap);
1221                                 rxd->rx_dmamap = NULL;
1222                         }
1223                 }
1224                 if (sc->age_cdata.age_rx_sparemap != NULL) {
1225                         bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1226                             sc->age_cdata.age_rx_sparemap);
1227                         sc->age_cdata.age_rx_sparemap = NULL;
1228                 }
1229                 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1230                 sc->age_cdata.age_rx_tag = NULL;
1231         }
1232         /* Tx ring. */
1233         if (sc->age_cdata.age_tx_ring_tag != NULL) {
1234                 if (sc->age_cdata.age_tx_ring_map != NULL)
1235                         bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1236                             sc->age_cdata.age_tx_ring_map);
1237                 if (sc->age_cdata.age_tx_ring_map != NULL &&
1238                     sc->age_rdata.age_tx_ring != NULL)
1239                         bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1240                             sc->age_rdata.age_tx_ring,
1241                             sc->age_cdata.age_tx_ring_map);
1242                 sc->age_rdata.age_tx_ring = NULL;
1243                 sc->age_cdata.age_tx_ring_map = NULL;
1244                 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1245                 sc->age_cdata.age_tx_ring_tag = NULL;
1246         }
1247         /* Rx ring. */
1248         if (sc->age_cdata.age_rx_ring_tag != NULL) {
1249                 if (sc->age_cdata.age_rx_ring_map != NULL)
1250                         bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1251                             sc->age_cdata.age_rx_ring_map);
1252                 if (sc->age_cdata.age_rx_ring_map != NULL &&
1253                     sc->age_rdata.age_rx_ring != NULL)
1254                         bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1255                             sc->age_rdata.age_rx_ring,
1256                             sc->age_cdata.age_rx_ring_map);
1257                 sc->age_rdata.age_rx_ring = NULL;
1258                 sc->age_cdata.age_rx_ring_map = NULL;
1259                 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1260                 sc->age_cdata.age_rx_ring_tag = NULL;
1261         }
1262         /* Rx return ring. */
1263         if (sc->age_cdata.age_rr_ring_tag != NULL) {
1264                 if (sc->age_cdata.age_rr_ring_map != NULL)
1265                         bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1266                             sc->age_cdata.age_rr_ring_map);
1267                 if (sc->age_cdata.age_rr_ring_map != NULL &&
1268                     sc->age_rdata.age_rr_ring != NULL)
1269                         bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1270                             sc->age_rdata.age_rr_ring,
1271                             sc->age_cdata.age_rr_ring_map);
1272                 sc->age_rdata.age_rr_ring = NULL;
1273                 sc->age_cdata.age_rr_ring_map = NULL;
1274                 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1275                 sc->age_cdata.age_rr_ring_tag = NULL;
1276         }
1277         /* CMB block */
1278         if (sc->age_cdata.age_cmb_block_tag != NULL) {
1279                 if (sc->age_cdata.age_cmb_block_map != NULL)
1280                         bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1281                             sc->age_cdata.age_cmb_block_map);
1282                 if (sc->age_cdata.age_cmb_block_map != NULL &&
1283                     sc->age_rdata.age_cmb_block != NULL)
1284                         bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1285                             sc->age_rdata.age_cmb_block,
1286                             sc->age_cdata.age_cmb_block_map);
1287                 sc->age_rdata.age_cmb_block = NULL;
1288                 sc->age_cdata.age_cmb_block_map = NULL;
1289                 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1290                 sc->age_cdata.age_cmb_block_tag = NULL;
1291         }
1292         /* SMB block */
1293         if (sc->age_cdata.age_smb_block_tag != NULL) {
1294                 if (sc->age_cdata.age_smb_block_map != NULL)
1295                         bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1296                             sc->age_cdata.age_smb_block_map);
1297                 if (sc->age_cdata.age_smb_block_map != NULL &&
1298                     sc->age_rdata.age_smb_block != NULL)
1299                         bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1300                             sc->age_rdata.age_smb_block,
1301                             sc->age_cdata.age_smb_block_map);
1302                 sc->age_rdata.age_smb_block = NULL;
1303                 sc->age_cdata.age_smb_block_map = NULL;
1304                 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1305                 sc->age_cdata.age_smb_block_tag = NULL;
1306         }
1307
1308         if (sc->age_cdata.age_buffer_tag != NULL) {
1309                 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1310                 sc->age_cdata.age_buffer_tag = NULL;
1311         }
1312         if (sc->age_cdata.age_parent_tag != NULL) {
1313                 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1314                 sc->age_cdata.age_parent_tag = NULL;
1315         }
1316 }
1317
1318 /*
1319  *      Make sure the interface is stopped at reboot time.
1320  */
1321 static int
1322 age_shutdown(device_t dev)
1323 {
1324
1325         return (age_suspend(dev));
1326 }
1327
1328 static void
1329 age_setwol(struct age_softc *sc)
1330 {
1331         struct ifnet *ifp;
1332         struct mii_data *mii;
1333         uint32_t reg, pmcs;
1334         uint16_t pmstat;
1335         int aneg, i, pmc;
1336
1337         AGE_LOCK_ASSERT(sc);
1338
1339         if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1340                 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1341                 /*
1342                  * No PME capability, PHY power down.
1343                  * XXX
1344                  * Due to an unknown reason powering down PHY resulted
1345                  * in unexpected results such as inaccessbility of
1346                  * hardware of freshly rebooted system. Disable
1347                  * powering down PHY until I got more information for
1348                  * Attansic/Atheros PHY hardwares.
1349                  */
1350 #ifdef notyet
1351                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1352                     MII_BMCR, BMCR_PDOWN);
1353 #endif
1354                 return;
1355         }
1356
1357         ifp = sc->age_ifp;
1358         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1359                 /*
1360                  * Note, this driver resets the link speed to 10/100Mbps with
1361                  * auto-negotiation but we don't know whether that operation
1362                  * would succeed or not as it have no control after powering
1363                  * off. If the renegotiation fail WOL may not work. Running
1364                  * at 1Gbps will draw more power than 375mA at 3.3V which is
1365                  * specified in PCI specification and that would result in
1366                  * complete shutdowning power to ethernet controller.
1367                  *
1368                  * TODO
1369                  *  Save current negotiated media speed/duplex/flow-control
1370                  *  to softc and restore the same link again after resuming.
1371                  *  PHY handling such as power down/resetting to 100Mbps
1372                  *  may be better handled in suspend method in phy driver.
1373                  */
1374                 mii = device_get_softc(sc->age_miibus);
1375                 mii_pollstat(mii);
1376                 aneg = 0;
1377                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1378                         switch IFM_SUBTYPE(mii->mii_media_active) {
1379                         case IFM_10_T:
1380                         case IFM_100_TX:
1381                                 goto got_link;
1382                         case IFM_1000_T:
1383                                 aneg++;
1384                         default:
1385                                 break;
1386                         }
1387                 }
1388                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1389                     MII_100T2CR, 0);
1390                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1391                     MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1392                     ANAR_10 | ANAR_CSMA);
1393                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1394                     MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1395                 DELAY(1000);
1396                 if (aneg != 0) {
1397                         /* Poll link state until age(4) get a 10/100 link. */
1398                         for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1399                                 mii_pollstat(mii);
1400                                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1401                                         switch (IFM_SUBTYPE(
1402                                             mii->mii_media_active)) {
1403                                         case IFM_10_T:
1404                                         case IFM_100_TX:
1405                                                 age_mac_config(sc);
1406                                                 goto got_link;
1407                                         default:
1408                                                 break;
1409                                         }
1410                                 }
1411                                 AGE_UNLOCK(sc);
1412                                 pause("agelnk", hz);
1413                                 AGE_LOCK(sc);
1414                         }
1415                         if (i == MII_ANEGTICKS_GIGE)
1416                                 device_printf(sc->age_dev,
1417                                     "establishing link failed, "
1418                                     "WOL may not work!");
1419                 }
1420                 /*
1421                  * No link, force MAC to have 100Mbps, full-duplex link.
1422                  * This is the last resort and may/may not work.
1423                  */
1424                 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1425                 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1426                 age_mac_config(sc);
1427         }
1428
1429 got_link:
1430         pmcs = 0;
1431         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1432                 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1433         CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1434         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1435         reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1436         reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1437         if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1438                 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1439         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1440                 reg |= MAC_CFG_RX_ENB;
1441                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1442         }
1443
1444         /* Request PME. */
1445         pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1446         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1447         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1448                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1449         pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1450 #ifdef notyet
1451         /* See above for powering down PHY issues. */
1452         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1453                 /* No WOL, PHY power down. */
1454                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1455                     MII_BMCR, BMCR_PDOWN);
1456         }
1457 #endif
1458 }
1459
1460 static int
1461 age_suspend(device_t dev)
1462 {
1463         struct age_softc *sc;
1464
1465         sc = device_get_softc(dev);
1466
1467         AGE_LOCK(sc);
1468         age_stop(sc);
1469         age_setwol(sc);
1470         AGE_UNLOCK(sc);
1471
1472         return (0);
1473 }
1474
1475 static int
1476 age_resume(device_t dev)
1477 {
1478         struct age_softc *sc;
1479         struct ifnet *ifp;
1480
1481         sc = device_get_softc(dev);
1482
1483         AGE_LOCK(sc);
1484         age_phy_reset(sc);
1485         ifp = sc->age_ifp;
1486         if ((ifp->if_flags & IFF_UP) != 0)
1487                 age_init_locked(sc);
1488
1489         AGE_UNLOCK(sc);
1490
1491         return (0);
1492 }
1493
1494 static int
1495 age_encap(struct age_softc *sc, struct mbuf **m_head)
1496 {
1497         struct age_txdesc *txd, *txd_last;
1498         struct tx_desc *desc;
1499         struct mbuf *m;
1500         struct ip *ip;
1501         struct tcphdr *tcp;
1502         bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1503         bus_dmamap_t map;
1504         uint32_t cflags, ip_off, poff, vtag;
1505         int error, i, nsegs, prod, si;
1506
1507         AGE_LOCK_ASSERT(sc);
1508
1509         M_ASSERTPKTHDR((*m_head));
1510
1511         m = *m_head;
1512         ip = NULL;
1513         tcp = NULL;
1514         cflags = vtag = 0;
1515         ip_off = poff = 0;
1516         if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1517                 /*
1518                  * L1 requires offset of TCP/UDP payload in its Tx
1519                  * descriptor to perform hardware Tx checksum offload.
1520                  * Additionally, TSO requires IP/TCP header size and
1521                  * modification of IP/TCP header in order to make TSO
1522                  * engine work. This kind of operation takes many CPU
1523                  * cycles on FreeBSD so fast host CPU is needed to get
1524                  * smooth TSO performance.
1525                  */
1526                 struct ether_header *eh;
1527
1528                 if (M_WRITABLE(m) == 0) {
1529                         /* Get a writable copy. */
1530                         m = m_dup(*m_head, M_DONTWAIT);
1531                         /* Release original mbufs. */
1532                         m_freem(*m_head);
1533                         if (m == NULL) {
1534                                 *m_head = NULL;
1535                                 return (ENOBUFS);
1536                         }
1537                         *m_head = m;
1538                 }
1539                 ip_off = sizeof(struct ether_header);
1540                 m = m_pullup(m, ip_off);
1541                 if (m == NULL) {
1542                         *m_head = NULL;
1543                         return (ENOBUFS);
1544                 }
1545                 eh = mtod(m, struct ether_header *);
1546                 /*
1547                  * Check if hardware VLAN insertion is off.
1548                  * Additional check for LLC/SNAP frame?
1549                  */
1550                 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1551                         ip_off = sizeof(struct ether_vlan_header);
1552                         m = m_pullup(m, ip_off);
1553                         if (m == NULL) {
1554                                 *m_head = NULL;
1555                                 return (ENOBUFS);
1556                         }
1557                 }
1558                 m = m_pullup(m, ip_off + sizeof(struct ip));
1559                 if (m == NULL) {
1560                         *m_head = NULL;
1561                         return (ENOBUFS);
1562                 }
1563                 ip = (struct ip *)(mtod(m, char *) + ip_off);
1564                 poff = ip_off + (ip->ip_hl << 2);
1565                 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1566                         m = m_pullup(m, poff + sizeof(struct tcphdr));
1567                         if (m == NULL) {
1568                                 *m_head = NULL;
1569                                 return (ENOBUFS);
1570                         }
1571                         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1572                         /*
1573                          * L1 requires IP/TCP header size and offset as
1574                          * well as TCP pseudo checksum which complicates
1575                          * TSO configuration. I guess this comes from the
1576                          * adherence to Microsoft NDIS Large Send
1577                          * specification which requires insertion of
1578                          * pseudo checksum by upper stack. The pseudo
1579                          * checksum that NDIS refers to doesn't include
1580                          * TCP payload length so age(4) should recompute
1581                          * the pseudo checksum here. Hopefully this wouldn't
1582                          * be much burden on modern CPUs.
1583                          * Reset IP checksum and recompute TCP pseudo
1584                          * checksum as NDIS specification said.
1585                          */
1586                         ip->ip_sum = 0;
1587                         if (poff + (tcp->th_off << 2) == m->m_pkthdr.len)
1588                                 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1589                                     ip->ip_dst.s_addr,
1590                                     htons((tcp->th_off << 2) + IPPROTO_TCP));
1591                         else
1592                                 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1593                                     ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1594                 }
1595                 *m_head = m;
1596         }
1597
1598         si = prod = sc->age_cdata.age_tx_prod;
1599         txd = &sc->age_cdata.age_txdesc[prod];
1600         txd_last = txd;
1601         map = txd->tx_dmamap;
1602
1603         error =  bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1604             *m_head, txsegs, &nsegs, 0);
1605         if (error == EFBIG) {
1606                 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS);
1607                 if (m == NULL) {
1608                         m_freem(*m_head);
1609                         *m_head = NULL;
1610                         return (ENOMEM);
1611                 }
1612                 *m_head = m;
1613                 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1614                     *m_head, txsegs, &nsegs, 0);
1615                 if (error != 0) {
1616                         m_freem(*m_head);
1617                         *m_head = NULL;
1618                         return (error);
1619                 }
1620         } else if (error != 0)
1621                 return (error);
1622         if (nsegs == 0) {
1623                 m_freem(*m_head);
1624                 *m_head = NULL;
1625                 return (EIO);
1626         }
1627
1628         /* Check descriptor overrun. */
1629         if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1630                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1631                 return (ENOBUFS);
1632         }
1633
1634         m = *m_head;
1635         /* Configure Tx IP/TCP/UDP checksum offload. */
1636         if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1637                 cflags |= AGE_TD_CSUM;
1638                 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1639                         cflags |= AGE_TD_TCPCSUM;
1640                 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1641                         cflags |= AGE_TD_UDPCSUM;
1642                 /* Set checksum start offset. */
1643                 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1644                 /* Set checksum insertion position of TCP/UDP. */
1645                 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1646                     AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1647         }
1648
1649         /* Configure TSO. */
1650         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1651                 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1652                         /* Not TSO but IP/TCP checksum offload. */
1653                         cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1654                         /* Clear TSO in order not to set AGE_TD_TSO_HDR. */
1655                         m->m_pkthdr.csum_flags &= ~CSUM_TSO;
1656                 } else {
1657                         /* Request TSO and set MSS. */
1658                         cflags |= AGE_TD_TSO_IPV4;
1659                         cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1660                         cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1661                             AGE_TD_TSO_MSS_SHIFT);
1662                 }
1663                 /* Set IP/TCP header size. */
1664                 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1665                 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1666         }
1667
1668         /* Configure VLAN hardware tag insertion. */
1669         if ((m->m_flags & M_VLANTAG) != 0) {
1670                 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1671                 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1672                 cflags |= AGE_TD_INSERT_VLAN_TAG;
1673         }
1674
1675         desc = NULL;
1676         for (i = 0; i < nsegs; i++) {
1677                 desc = &sc->age_rdata.age_tx_ring[prod];
1678                 desc->addr = htole64(txsegs[i].ds_addr);
1679                 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1680                 desc->flags = htole32(cflags);
1681                 sc->age_cdata.age_tx_cnt++;
1682                 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1683         }
1684         /* Update producer index. */
1685         sc->age_cdata.age_tx_prod = prod;
1686
1687         /* Set EOP on the last descriptor. */
1688         prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1689         desc = &sc->age_rdata.age_tx_ring[prod];
1690         desc->flags |= htole32(AGE_TD_EOP);
1691
1692         /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1693         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1694                 desc = &sc->age_rdata.age_tx_ring[si];
1695                 desc->flags |= htole32(AGE_TD_TSO_HDR);
1696         }
1697
1698         /* Swap dmamap of the first and the last. */
1699         txd = &sc->age_cdata.age_txdesc[prod];
1700         map = txd_last->tx_dmamap;
1701         txd_last->tx_dmamap = txd->tx_dmamap;
1702         txd->tx_dmamap = map;
1703         txd->tx_m = m;
1704
1705         /* Sync descriptors. */
1706         bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1707         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1708             sc->age_cdata.age_tx_ring_map,
1709             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1710
1711         return (0);
1712 }
1713
1714 static void
1715 age_tx_task(void *arg, int pending)
1716 {
1717         struct ifnet *ifp;
1718
1719         ifp = (struct ifnet *)arg;
1720         age_start(ifp);
1721 }
1722
1723 static void
1724 age_start(struct ifnet *ifp)
1725 {
1726         struct age_softc *sc;
1727         struct mbuf *m_head;
1728         int enq;
1729
1730         sc = ifp->if_softc;
1731
1732         AGE_LOCK(sc);
1733
1734         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1735             IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) {
1736                 AGE_UNLOCK(sc);
1737                 return;
1738         }
1739
1740         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1741                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1742                 if (m_head == NULL)
1743                         break;
1744                 /*
1745                  * Pack the data into the transmit ring. If we
1746                  * don't have room, set the OACTIVE flag and wait
1747                  * for the NIC to drain the ring.
1748                  */
1749                 if (age_encap(sc, &m_head)) {
1750                         if (m_head == NULL)
1751                                 break;
1752                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1753                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1754                         break;
1755                 }
1756
1757                 enq++;
1758                 /*
1759                  * If there's a BPF listener, bounce a copy of this frame
1760                  * to him.
1761                  */
1762                 ETHER_BPF_MTAP(ifp, m_head);
1763         }
1764
1765         if (enq > 0) {
1766                 /* Update mbox. */
1767                 AGE_COMMIT_MBOX(sc);
1768                 /* Set a timeout in case the chip goes out to lunch. */
1769                 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1770         }
1771
1772         AGE_UNLOCK(sc);
1773 }
1774
1775 static void
1776 age_watchdog(struct age_softc *sc)
1777 {
1778         struct ifnet *ifp;
1779
1780         AGE_LOCK_ASSERT(sc);
1781
1782         if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1783                 return;
1784
1785         ifp = sc->age_ifp;
1786         if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1787                 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1788                 ifp->if_oerrors++;
1789                 age_init_locked(sc);
1790                 return;
1791         }
1792         if (sc->age_cdata.age_tx_cnt == 0) {
1793                 if_printf(sc->age_ifp,
1794                     "watchdog timeout (missed Tx interrupts) -- recovering\n");
1795                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1796                         taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
1797                 return;
1798         }
1799         if_printf(sc->age_ifp, "watchdog timeout\n");
1800         ifp->if_oerrors++;
1801         age_init_locked(sc);
1802         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1803                 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
1804 }
1805
1806 static int
1807 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1808 {
1809         struct age_softc *sc;
1810         struct ifreq *ifr;
1811         struct mii_data *mii;
1812         uint32_t reg;
1813         int error, mask;
1814
1815         sc = ifp->if_softc;
1816         ifr = (struct ifreq *)data;
1817         error = 0;
1818         switch (cmd) {
1819         case SIOCSIFMTU:
1820                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1821                         error = EINVAL;
1822                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1823                         AGE_LOCK(sc);
1824                         ifp->if_mtu = ifr->ifr_mtu;
1825                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1826                                 age_init_locked(sc);
1827                         AGE_UNLOCK(sc);
1828                 }
1829                 break;
1830         case SIOCSIFFLAGS:
1831                 AGE_LOCK(sc);
1832                 if ((ifp->if_flags & IFF_UP) != 0) {
1833                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1834                                 if (((ifp->if_flags ^ sc->age_if_flags)
1835                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1836                                         age_rxfilter(sc);
1837                         } else {
1838                                 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1839                                         age_init_locked(sc);
1840                         }
1841                 } else {
1842                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1843                                 age_stop(sc);
1844                 }
1845                 sc->age_if_flags = ifp->if_flags;
1846                 AGE_UNLOCK(sc);
1847                 break;
1848         case SIOCADDMULTI:
1849         case SIOCDELMULTI:
1850                 AGE_LOCK(sc);
1851                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1852                         age_rxfilter(sc);
1853                 AGE_UNLOCK(sc);
1854                 break;
1855         case SIOCSIFMEDIA:
1856         case SIOCGIFMEDIA:
1857                 mii = device_get_softc(sc->age_miibus);
1858                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1859                 break;
1860         case SIOCSIFCAP:
1861                 AGE_LOCK(sc);
1862                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1863                 if ((mask & IFCAP_TXCSUM) != 0 &&
1864                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1865                         ifp->if_capenable ^= IFCAP_TXCSUM;
1866                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1867                                 ifp->if_hwassist |= AGE_CSUM_FEATURES;
1868                         else
1869                                 ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1870                 }
1871                 if ((mask & IFCAP_RXCSUM) != 0 &&
1872                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1873                         ifp->if_capenable ^= IFCAP_RXCSUM;
1874                         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1875                         reg &= ~MAC_CFG_RXCSUM_ENB;
1876                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1877                                 reg |= MAC_CFG_RXCSUM_ENB;
1878                         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1879                 }
1880                 if ((mask & IFCAP_TSO4) != 0 &&
1881                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1882                         ifp->if_capenable ^= IFCAP_TSO4;
1883                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1884                                 ifp->if_hwassist |= CSUM_TSO;
1885                         else
1886                                 ifp->if_hwassist &= ~CSUM_TSO;
1887                 }
1888
1889                 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1890                     (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
1891                         ifp->if_capenable ^= IFCAP_WOL_MCAST;
1892                 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1893                     (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1894                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1895
1896                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1897                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1898                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1899                         age_rxvlan(sc);
1900                 }
1901                 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1902                     (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1903                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1904                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1905                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1906                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1907                 /*
1908                  * VLAN hardware tagging is required to do checksum
1909                  * offload or TSO on VLAN interface. Checksum offload
1910                  * on VLAN interface also requires hardware assistance
1911                  * of parent interface.
1912                  */
1913                 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0)
1914                         ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
1915                 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1916                         ifp->if_capenable &=
1917                             ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1918                 AGE_UNLOCK(sc);
1919                 VLAN_CAPABILITIES(ifp);
1920                 break;
1921         default:
1922                 error = ether_ioctl(ifp, cmd, data);
1923                 break;
1924         }
1925
1926         return (error);
1927 }
1928
1929 static void
1930 age_mac_config(struct age_softc *sc)
1931 {
1932         struct mii_data *mii;
1933         uint32_t reg;
1934
1935         AGE_LOCK_ASSERT(sc);
1936
1937         mii = device_get_softc(sc->age_miibus);
1938         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1939         reg &= ~MAC_CFG_FULL_DUPLEX;
1940         reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1941         reg &= ~MAC_CFG_SPEED_MASK;
1942         /* Reprogram MAC with resolved speed/duplex. */
1943         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1944         case IFM_10_T:
1945         case IFM_100_TX:
1946                 reg |= MAC_CFG_SPEED_10_100;
1947                 break;
1948         case IFM_1000_T:
1949                 reg |= MAC_CFG_SPEED_1000;
1950                 break;
1951         }
1952         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1953                 reg |= MAC_CFG_FULL_DUPLEX;
1954 #ifdef notyet
1955                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1956                         reg |= MAC_CFG_TX_FC;
1957                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1958                         reg |= MAC_CFG_RX_FC;
1959 #endif
1960         }
1961
1962         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1963 }
1964
1965 static void
1966 age_link_task(void *arg, int pending)
1967 {
1968         struct age_softc *sc;
1969         struct mii_data *mii;
1970         struct ifnet *ifp;
1971         uint32_t reg;
1972
1973         sc = (struct age_softc *)arg;
1974
1975         AGE_LOCK(sc);
1976         mii = device_get_softc(sc->age_miibus);
1977         ifp = sc->age_ifp;
1978         if (mii == NULL || ifp == NULL ||
1979             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1980                 AGE_UNLOCK(sc);
1981                 return;
1982         }
1983
1984         sc->age_flags &= ~AGE_FLAG_LINK;
1985         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1986                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1987                 case IFM_10_T:
1988                 case IFM_100_TX:
1989                 case IFM_1000_T:
1990                         sc->age_flags |= AGE_FLAG_LINK;
1991                         break;
1992                 default:
1993                         break;
1994                 }
1995         }
1996
1997         /* Stop Rx/Tx MACs. */
1998         age_stop_rxmac(sc);
1999         age_stop_txmac(sc);
2000
2001         /* Program MACs with resolved speed/duplex/flow-control. */
2002         if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
2003                 age_mac_config(sc);
2004                 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2005                 /* Restart DMA engine and Tx/Rx MAC. */
2006                 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2007                     DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
2008                 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2009                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2010         }
2011
2012         AGE_UNLOCK(sc);
2013 }
2014
2015 static void
2016 age_stats_update(struct age_softc *sc)
2017 {
2018         struct age_stats *stat;
2019         struct smb *smb;
2020         struct ifnet *ifp;
2021
2022         AGE_LOCK_ASSERT(sc);
2023
2024         stat = &sc->age_stat;
2025
2026         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2027             sc->age_cdata.age_smb_block_map,
2028             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2029
2030         smb = sc->age_rdata.age_smb_block;
2031         if (smb->updated == 0)
2032                 return;
2033
2034         ifp = sc->age_ifp;
2035         /* Rx stats. */
2036         stat->rx_frames += smb->rx_frames;
2037         stat->rx_bcast_frames += smb->rx_bcast_frames;
2038         stat->rx_mcast_frames += smb->rx_mcast_frames;
2039         stat->rx_pause_frames += smb->rx_pause_frames;
2040         stat->rx_control_frames += smb->rx_control_frames;
2041         stat->rx_crcerrs += smb->rx_crcerrs;
2042         stat->rx_lenerrs += smb->rx_lenerrs;
2043         stat->rx_bytes += smb->rx_bytes;
2044         stat->rx_runts += smb->rx_runts;
2045         stat->rx_fragments += smb->rx_fragments;
2046         stat->rx_pkts_64 += smb->rx_pkts_64;
2047         stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2048         stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2049         stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2050         stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2051         stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2052         stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2053         stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2054         stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2055         stat->rx_desc_oflows += smb->rx_desc_oflows;
2056         stat->rx_alignerrs += smb->rx_alignerrs;
2057         stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2058         stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2059         stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2060
2061         /* Tx stats. */
2062         stat->tx_frames += smb->tx_frames;
2063         stat->tx_bcast_frames += smb->tx_bcast_frames;
2064         stat->tx_mcast_frames += smb->tx_mcast_frames;
2065         stat->tx_pause_frames += smb->tx_pause_frames;
2066         stat->tx_excess_defer += smb->tx_excess_defer;
2067         stat->tx_control_frames += smb->tx_control_frames;
2068         stat->tx_deferred += smb->tx_deferred;
2069         stat->tx_bytes += smb->tx_bytes;
2070         stat->tx_pkts_64 += smb->tx_pkts_64;
2071         stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2072         stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2073         stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2074         stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2075         stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2076         stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2077         stat->tx_single_colls += smb->tx_single_colls;
2078         stat->tx_multi_colls += smb->tx_multi_colls;
2079         stat->tx_late_colls += smb->tx_late_colls;
2080         stat->tx_excess_colls += smb->tx_excess_colls;
2081         stat->tx_underrun += smb->tx_underrun;
2082         stat->tx_desc_underrun += smb->tx_desc_underrun;
2083         stat->tx_lenerrs += smb->tx_lenerrs;
2084         stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2085         stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2086         stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2087
2088         /* Update counters in ifnet. */
2089         ifp->if_opackets += smb->tx_frames;
2090
2091         ifp->if_collisions += smb->tx_single_colls +
2092             smb->tx_multi_colls + smb->tx_late_colls +
2093             smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
2094
2095         ifp->if_oerrors += smb->tx_excess_colls +
2096             smb->tx_late_colls + smb->tx_underrun +
2097             smb->tx_pkts_truncated;
2098
2099         ifp->if_ipackets += smb->rx_frames;
2100
2101         ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2102             smb->rx_runts + smb->rx_pkts_truncated +
2103             smb->rx_fifo_oflows + smb->rx_desc_oflows +
2104             smb->rx_alignerrs;
2105
2106         /* Update done, clear. */
2107         smb->updated = 0;
2108
2109         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2110             sc->age_cdata.age_smb_block_map,
2111             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2112 }
2113
2114 static int
2115 age_intr(void *arg)
2116 {
2117         struct age_softc *sc;
2118         uint32_t status;
2119
2120         sc = (struct age_softc *)arg;
2121
2122         status = CSR_READ_4(sc, AGE_INTR_STATUS);
2123         if (status == 0 || (status & AGE_INTRS) == 0)
2124                 return (FILTER_STRAY);
2125         /* Disable interrupts. */
2126         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2127         taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2128
2129         return (FILTER_HANDLED);
2130 }
2131
2132 static void
2133 age_int_task(void *arg, int pending)
2134 {
2135         struct age_softc *sc;
2136         struct ifnet *ifp;
2137         struct cmb *cmb;
2138         uint32_t status;
2139
2140         sc = (struct age_softc *)arg;
2141
2142         AGE_LOCK(sc);
2143
2144         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2145             sc->age_cdata.age_cmb_block_map,
2146             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2147         cmb = sc->age_rdata.age_cmb_block;
2148         status = le32toh(cmb->intr_status);
2149         if (sc->age_morework != 0)
2150                 status |= INTR_CMB_RX;
2151         if ((status & AGE_INTRS) == 0)
2152                 goto done;
2153
2154         sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2155             TPD_CONS_SHIFT;
2156         sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2157             RRD_PROD_SHIFT;
2158         /* Let hardware know CMB was served. */
2159         cmb->intr_status = 0;
2160         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2161             sc->age_cdata.age_cmb_block_map,
2162             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2163
2164 #if 0
2165         printf("INTR: 0x%08x\n", status);
2166         status &= ~INTR_DIS_DMA;
2167         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2168 #endif
2169         ifp = sc->age_ifp;
2170         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2171                 if ((status & INTR_CMB_RX) != 0)
2172                         sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2173                             sc->age_process_limit);
2174                 if ((status & INTR_CMB_TX) != 0)
2175                         age_txintr(sc, sc->age_tpd_cons);
2176                 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2177                         if ((status & INTR_DMA_RD_TO_RST) != 0)
2178                                 device_printf(sc->age_dev,
2179                                     "DMA read error! -- resetting\n");
2180                         if ((status & INTR_DMA_WR_TO_RST) != 0)
2181                                 device_printf(sc->age_dev,
2182                                     "DMA write error! -- resetting\n");
2183                         age_init_locked(sc);
2184                 }
2185                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2186                         taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
2187                 if ((status & INTR_SMB) != 0)
2188                         age_stats_update(sc);
2189         }
2190
2191         /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2192         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2193             sc->age_cdata.age_cmb_block_map,
2194             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2195         status = le32toh(cmb->intr_status);
2196         if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2197                 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2198                 AGE_UNLOCK(sc);
2199                 return;
2200         }
2201
2202 done:
2203         /* Re-enable interrupts. */
2204         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2205         AGE_UNLOCK(sc);
2206 }
2207
2208 static void
2209 age_txintr(struct age_softc *sc, int tpd_cons)
2210 {
2211         struct ifnet *ifp;
2212         struct age_txdesc *txd;
2213         int cons, prog;
2214
2215         AGE_LOCK_ASSERT(sc);
2216
2217         ifp = sc->age_ifp;
2218
2219         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2220             sc->age_cdata.age_tx_ring_map,
2221             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2222
2223         /*
2224          * Go through our Tx list and free mbufs for those
2225          * frames which have been transmitted.
2226          */
2227         cons = sc->age_cdata.age_tx_cons;
2228         for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2229                 if (sc->age_cdata.age_tx_cnt <= 0)
2230                         break;
2231                 prog++;
2232                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2233                 sc->age_cdata.age_tx_cnt--;
2234                 txd = &sc->age_cdata.age_txdesc[cons];
2235                 /*
2236                  * Clear Tx descriptors, it's not required but would
2237                  * help debugging in case of Tx issues.
2238                  */
2239                 txd->tx_desc->addr = 0;
2240                 txd->tx_desc->len = 0;
2241                 txd->tx_desc->flags = 0;
2242
2243                 if (txd->tx_m == NULL)
2244                         continue;
2245                 /* Reclaim transmitted mbufs. */
2246                 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2247                     BUS_DMASYNC_POSTWRITE);
2248                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2249                 m_freem(txd->tx_m);
2250                 txd->tx_m = NULL;
2251         }
2252
2253         if (prog > 0) {
2254                 sc->age_cdata.age_tx_cons = cons;
2255
2256                 /*
2257                  * Unarm watchdog timer only when there are no pending
2258                  * Tx descriptors in queue.
2259                  */
2260                 if (sc->age_cdata.age_tx_cnt == 0)
2261                         sc->age_watchdog_timer = 0;
2262                 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2263                     sc->age_cdata.age_tx_ring_map,
2264                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2265         }
2266 }
2267
2268 /* Receive a frame. */
2269 static void
2270 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2271 {
2272         struct age_rxdesc *rxd;
2273         struct rx_desc *desc;
2274         struct ifnet *ifp;
2275         struct mbuf *mp, *m;
2276         uint32_t status, index, vtag;
2277         int count, nsegs, pktlen;
2278         int rx_cons;
2279
2280         AGE_LOCK_ASSERT(sc);
2281
2282         ifp = sc->age_ifp;
2283         status = le32toh(rxrd->flags);
2284         index = le32toh(rxrd->index);
2285         rx_cons = AGE_RX_CONS(index);
2286         nsegs = AGE_RX_NSEGS(index);
2287
2288         sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2289         if ((status & AGE_RRD_ERROR) != 0 &&
2290             (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2291             AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) {
2292                 /*
2293                  * We want to pass the following frames to upper
2294                  * layer regardless of error status of Rx return
2295                  * ring.
2296                  *
2297                  *  o IP/TCP/UDP checksum is bad.
2298                  *  o frame length and protocol specific length
2299                  *     does not match.
2300                  */
2301                 sc->age_cdata.age_rx_cons += nsegs;
2302                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2303                 return;
2304         }
2305
2306         pktlen = 0;
2307         for (count = 0; count < nsegs; count++,
2308             AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2309                 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2310                 mp = rxd->rx_m;
2311                 desc = rxd->rx_desc;
2312                 /* Add a new receive buffer to the ring. */
2313                 if (age_newbuf(sc, rxd) != 0) {
2314                         ifp->if_iqdrops++;
2315                         /* Reuse Rx buffers. */
2316                         if (sc->age_cdata.age_rxhead != NULL) {
2317                                 m_freem(sc->age_cdata.age_rxhead);
2318                                 AGE_RXCHAIN_RESET(sc);
2319                         }
2320                         break;
2321                 }
2322
2323                 /* The length of the first mbuf is computed last. */
2324                 if (count != 0) {
2325                         mp->m_len = AGE_RX_BYTES(le32toh(desc->len));
2326                         pktlen += mp->m_len;
2327                 }
2328
2329                 /* Chain received mbufs. */
2330                 if (sc->age_cdata.age_rxhead == NULL) {
2331                         sc->age_cdata.age_rxhead = mp;
2332                         sc->age_cdata.age_rxtail = mp;
2333                 } else {
2334                         mp->m_flags &= ~M_PKTHDR;
2335                         sc->age_cdata.age_rxprev_tail =
2336                             sc->age_cdata.age_rxtail;
2337                         sc->age_cdata.age_rxtail->m_next = mp;
2338                         sc->age_cdata.age_rxtail = mp;
2339                 }
2340
2341                 if (count == nsegs - 1) {
2342                         /*
2343                          * It seems that L1 controller has no way
2344                          * to tell hardware to strip CRC bytes.
2345                          */
2346                         sc->age_cdata.age_rxlen -= ETHER_CRC_LEN;
2347                         if (nsegs > 1) {
2348                                 /* Remove the CRC bytes in chained mbufs. */
2349                                 pktlen -= ETHER_CRC_LEN;
2350                                 if (mp->m_len <= ETHER_CRC_LEN) {
2351                                         sc->age_cdata.age_rxtail =
2352                                             sc->age_cdata.age_rxprev_tail;
2353                                         sc->age_cdata.age_rxtail->m_len -=
2354                                             (ETHER_CRC_LEN - mp->m_len);
2355                                         sc->age_cdata.age_rxtail->m_next = NULL;
2356                                         m_freem(mp);
2357                                 } else {
2358                                         mp->m_len -= ETHER_CRC_LEN;
2359                                 }
2360                         }
2361
2362                         m = sc->age_cdata.age_rxhead;
2363                         m->m_flags |= M_PKTHDR;
2364                         m->m_pkthdr.rcvif = ifp;
2365                         m->m_pkthdr.len = sc->age_cdata.age_rxlen;
2366                         /* Set the first mbuf length. */
2367                         m->m_len = sc->age_cdata.age_rxlen - pktlen;
2368
2369                         /*
2370                          * Set checksum information.
2371                          * It seems that L1 controller can compute partial
2372                          * checksum. The partial checksum value can be used
2373                          * to accelerate checksum computation for fragmented
2374                          * TCP/UDP packets. Upper network stack already
2375                          * takes advantage of the partial checksum value in
2376                          * IP reassembly stage. But I'm not sure the
2377                          * correctness of the partial hardware checksum
2378                          * assistance due to lack of data sheet. If it is
2379                          * proven to work on L1 I'll enable it.
2380                          */
2381                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2382                             (status & AGE_RRD_IPV4) != 0) {
2383                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2384                                 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2385                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2386                                 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2387                                     (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2388                                         m->m_pkthdr.csum_flags |=
2389                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2390                                         m->m_pkthdr.csum_data = 0xffff;
2391                                 }
2392                                 /*
2393                                  * Don't mark bad checksum for TCP/UDP frames
2394                                  * as fragmented frames may always have set
2395                                  * bad checksummed bit of descriptor status.
2396                                  */
2397                         }
2398
2399                         /* Check for VLAN tagged frames. */
2400                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2401                             (status & AGE_RRD_VLAN) != 0) {
2402                                 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2403                                 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2404                                 m->m_flags |= M_VLANTAG;
2405                         }
2406
2407                         /* Pass it on. */
2408                         AGE_UNLOCK(sc);
2409                         (*ifp->if_input)(ifp, m);
2410                         AGE_LOCK(sc);
2411
2412                         /* Reset mbuf chains. */
2413                         AGE_RXCHAIN_RESET(sc);
2414                 }
2415         }
2416
2417         if (count != nsegs) {
2418                 sc->age_cdata.age_rx_cons += nsegs;
2419                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2420         } else
2421                 sc->age_cdata.age_rx_cons = rx_cons;
2422 }
2423
2424 static int
2425 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2426 {
2427         struct rx_rdesc *rxrd;
2428         int rr_cons, nsegs, pktlen, prog;
2429
2430         AGE_LOCK_ASSERT(sc);
2431
2432         rr_cons = sc->age_cdata.age_rr_cons;
2433         if (rr_cons == rr_prod)
2434                 return (0);
2435
2436         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2437             sc->age_cdata.age_rr_ring_map,
2438             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2439
2440         for (prog = 0; rr_cons != rr_prod; prog++) {
2441                 if (count <= 0)
2442                         break;
2443                 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2444                 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2445                 if (nsegs == 0)
2446                         break;
2447                 /*
2448                  * Check number of segments against received bytes.
2449                  * Non-matching value would indicate that hardware
2450                  * is still trying to update Rx return descriptors.
2451                  * I'm not sure whether this check is really needed.
2452                  */
2453                 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2454                 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) /
2455                     (MCLBYTES - ETHER_ALIGN)))
2456                         break;
2457
2458                 prog++;
2459                 /* Received a frame. */
2460                 age_rxeof(sc, rxrd);
2461                 /* Clear return ring. */
2462                 rxrd->index = 0;
2463                 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2464         }
2465
2466         if (prog > 0) {
2467                 /* Update the consumer index. */
2468                 sc->age_cdata.age_rr_cons = rr_cons;
2469
2470                 /* Sync descriptors. */
2471                 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2472                     sc->age_cdata.age_rr_ring_map,
2473                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2474
2475                 /* Notify hardware availability of new Rx buffers. */
2476                 AGE_COMMIT_MBOX(sc);
2477         }
2478
2479         return (count > 0 ? 0 : EAGAIN);
2480 }
2481
2482 static void
2483 age_tick(void *arg)
2484 {
2485         struct age_softc *sc;
2486         struct mii_data *mii;
2487
2488         sc = (struct age_softc *)arg;
2489
2490         AGE_LOCK_ASSERT(sc);
2491
2492         mii = device_get_softc(sc->age_miibus);
2493         mii_tick(mii);
2494         age_watchdog(sc);
2495         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2496 }
2497
2498 static void
2499 age_reset(struct age_softc *sc)
2500 {
2501         uint32_t reg;
2502         int i;
2503
2504         CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2505         CSR_READ_4(sc, AGE_MASTER_CFG);
2506         DELAY(1000);
2507         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2508                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2509                         break;
2510                 DELAY(10);
2511         }
2512
2513         if (i == 0)
2514                 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2515         /* Initialize PCIe module. From Linux. */
2516         CSR_WRITE_4(sc, 0x12FC, 0x6500);
2517         CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2518 }
2519
2520 static void
2521 age_init(void *xsc)
2522 {
2523         struct age_softc *sc;
2524
2525         sc = (struct age_softc *)xsc;
2526         AGE_LOCK(sc);
2527         age_init_locked(sc);
2528         AGE_UNLOCK(sc);
2529 }
2530
2531 static void
2532 age_init_locked(struct age_softc *sc)
2533 {
2534         struct ifnet *ifp;
2535         struct mii_data *mii;
2536         uint8_t eaddr[ETHER_ADDR_LEN];
2537         bus_addr_t paddr;
2538         uint32_t reg, fsize;
2539         uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2540         int error;
2541
2542         AGE_LOCK_ASSERT(sc);
2543
2544         ifp = sc->age_ifp;
2545         mii = device_get_softc(sc->age_miibus);
2546
2547         /*
2548          * Cancel any pending I/O.
2549          */
2550         age_stop(sc);
2551
2552         /*
2553          * Reset the chip to a known state.
2554          */
2555         age_reset(sc);
2556
2557         /* Initialize descriptors. */
2558         error = age_init_rx_ring(sc);
2559         if (error != 0) {
2560                 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2561                 age_stop(sc);
2562                 return;
2563         }
2564         age_init_rr_ring(sc);
2565         age_init_tx_ring(sc);
2566         age_init_cmb_block(sc);
2567         age_init_smb_block(sc);
2568
2569         /* Reprogram the station address. */
2570         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2571         CSR_WRITE_4(sc, AGE_PAR0,
2572             eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2573         CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2574
2575         /* Set descriptor base addresses. */
2576         paddr = sc->age_rdata.age_tx_ring_paddr;
2577         CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2578         paddr = sc->age_rdata.age_rx_ring_paddr;
2579         CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2580         paddr = sc->age_rdata.age_rr_ring_paddr;
2581         CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2582         paddr = sc->age_rdata.age_tx_ring_paddr;
2583         CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2584         paddr = sc->age_rdata.age_cmb_block_paddr;
2585         CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2586         paddr = sc->age_rdata.age_smb_block_paddr;
2587         CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2588         /* Set Rx/Rx return descriptor counter. */
2589         CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2590             ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2591             DESC_RRD_CNT_MASK) |
2592             ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2593         /* Set Tx descriptor counter. */
2594         CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2595             (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2596
2597         /* Tell hardware that we're ready to load descriptors. */
2598         CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2599
2600         /*
2601          * Initialize mailbox register.
2602          * Updated producer/consumer index information is exchanged
2603          * through this mailbox register. However Tx producer and
2604          * Rx return consumer/Rx producer are all shared such that
2605          * it's hard to separate code path between Tx and Rx without
2606          * locking. If L1 hardware have a separate mail box register
2607          * for Tx and Rx consumer/producer management we could have
2608          * indepent Tx/Rx handler which in turn Rx handler could have
2609          * been run without any locking.
2610          */
2611         AGE_COMMIT_MBOX(sc);
2612
2613         /* Configure IPG/IFG parameters. */
2614         CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2615             ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2616             ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2617             ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2618             ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2619
2620         /* Set parameters for half-duplex media. */
2621         CSR_WRITE_4(sc, AGE_HDPX_CFG,
2622             ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2623             HDPX_CFG_LCOL_MASK) |
2624             ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2625             HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2626             ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2627             HDPX_CFG_ABEBT_MASK) |
2628             ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2629             HDPX_CFG_JAMIPG_MASK));
2630
2631         /* Configure interrupt moderation timer. */
2632         CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2633         reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2634         reg &= ~MASTER_MTIMER_ENB;
2635         if (AGE_USECS(sc->age_int_mod) == 0)
2636                 reg &= ~MASTER_ITIMER_ENB;
2637         else
2638                 reg |= MASTER_ITIMER_ENB;
2639         CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2640         if (bootverbose)
2641                 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2642                     sc->age_int_mod);
2643         CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2644
2645         /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2646         if (ifp->if_mtu < ETHERMTU)
2647                 sc->age_max_frame_size = ETHERMTU;
2648         else
2649                 sc->age_max_frame_size = ifp->if_mtu;
2650         sc->age_max_frame_size += ETHER_HDR_LEN +
2651             sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2652         CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2653         /* Configure jumbo frame. */
2654         fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2655         CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2656             (((fsize / sizeof(uint64_t)) <<
2657             RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2658             ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2659             RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2660             ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2661             RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2662
2663         /* Configure flow-control parameters. From Linux. */
2664         if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2665                 /*
2666                  * Magic workaround for old-L1.
2667                  * Don't know which hw revision requires this magic.
2668                  */
2669                 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2670                 /*
2671                  * Another magic workaround for flow-control mode
2672                  * change. From Linux.
2673                  */
2674                 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2675         }
2676         /*
2677          * TODO
2678          *  Should understand pause parameter relationships between FIFO
2679          *  size and number of Rx descriptors and Rx return descriptors.
2680          *
2681          *  Magic parameters came from Linux.
2682          */
2683         switch (sc->age_chip_rev) {
2684         case 0x8001:
2685         case 0x9001:
2686         case 0x9002:
2687         case 0x9003:
2688                 rxf_hi = AGE_RX_RING_CNT / 16;
2689                 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2690                 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2691                 rrd_lo = AGE_RR_RING_CNT / 16;
2692                 break;
2693         default:
2694                 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2695                 rxf_lo = reg / 16;
2696                 if (rxf_lo < 192)
2697                         rxf_lo = 192;
2698                 rxf_hi = (reg * 7) / 8;
2699                 if (rxf_hi < rxf_lo)
2700                         rxf_hi = rxf_lo + 16;
2701                 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2702                 rrd_lo = reg / 8;
2703                 rrd_hi = (reg * 7) / 8;
2704                 if (rrd_lo < 2)
2705                         rrd_lo = 2;
2706                 if (rrd_hi < rrd_lo)
2707                         rrd_hi = rrd_lo + 3;
2708                 break;
2709         }
2710         CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2711             ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2712             RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2713             ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2714             RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2715         CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2716             ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2717             RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2718             ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2719             RXQ_RRD_PAUSE_THRESH_HI_MASK));
2720
2721         /* Configure RxQ. */
2722         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2723             ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2724             RXQ_CFG_RD_BURST_MASK) |
2725             ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2726             RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2727             ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2728             RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2729             RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2730
2731         /* Configure TxQ. */
2732         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2733             ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2734             TXQ_CFG_TPD_BURST_MASK) |
2735             ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2736             TXQ_CFG_TX_FIFO_BURST_MASK) |
2737             ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2738             TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2739             TXQ_CFG_ENB);
2740
2741         CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2742             (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2743             TX_JUMBO_TPD_TH_MASK) |
2744             ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2745             TX_JUMBO_TPD_IPG_MASK));
2746         /* Configure DMA parameters. */
2747         CSR_WRITE_4(sc, AGE_DMA_CFG,
2748             DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2749             sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2750             sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2751
2752         /* Configure CMB DMA write threshold. */
2753         CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2754             ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2755             CMB_WR_THRESH_RRD_MASK) |
2756             ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2757             CMB_WR_THRESH_TPD_MASK));
2758
2759         /* Set CMB/SMB timer and enable them. */
2760         CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2761             ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2762             ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2763         /* Request SMB updates for every seconds. */
2764         CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2765         CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2766
2767         /*
2768          * Disable all WOL bits as WOL can interfere normal Rx
2769          * operation.
2770          */
2771         CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2772
2773         /*
2774          * Configure Tx/Rx MACs.
2775          *  - Auto-padding for short frames.
2776          *  - Enable CRC generation.
2777          *  Start with full-duplex/1000Mbps media. Actual reconfiguration
2778          *  of MAC is followed after link establishment.
2779          */
2780         CSR_WRITE_4(sc, AGE_MAC_CFG,
2781             MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2782             MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2783             ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2784             MAC_CFG_PREAMBLE_MASK));
2785         /* Set up the receive filter. */
2786         age_rxfilter(sc);
2787         age_rxvlan(sc);
2788
2789         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2790         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2791                 reg |= MAC_CFG_RXCSUM_ENB;
2792
2793         /* Ack all pending interrupts and clear it. */
2794         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2795         CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2796
2797         /* Finally enable Tx/Rx MAC. */
2798         CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2799
2800         sc->age_flags &= ~AGE_FLAG_LINK;
2801         /* Switch to the current media. */
2802         mii_mediachg(mii);
2803
2804         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2805
2806         ifp->if_drv_flags |= IFF_DRV_RUNNING;
2807         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2808 }
2809
2810 static void
2811 age_stop(struct age_softc *sc)
2812 {
2813         struct ifnet *ifp;
2814         struct age_txdesc *txd;
2815         struct age_rxdesc *rxd;
2816         uint32_t reg;
2817         int i;
2818
2819         AGE_LOCK_ASSERT(sc);
2820         /*
2821          * Mark the interface down and cancel the watchdog timer.
2822          */
2823         ifp = sc->age_ifp;
2824         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2825         sc->age_flags &= ~AGE_FLAG_LINK;
2826         callout_stop(&sc->age_tick_ch);
2827         sc->age_watchdog_timer = 0;
2828
2829         /*
2830          * Disable interrupts.
2831          */
2832         CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2833         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2834         /* Stop CMB/SMB updates. */
2835         CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2836         /* Stop Rx/Tx MAC. */
2837         age_stop_rxmac(sc);
2838         age_stop_txmac(sc);
2839         /* Stop DMA. */
2840         CSR_WRITE_4(sc, AGE_DMA_CFG,
2841             CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2842         /* Stop TxQ/RxQ. */
2843         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2844             CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2845         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2846             CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2847         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2848                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2849                         break;
2850                 DELAY(10);
2851         }
2852         if (i == 0)
2853                 device_printf(sc->age_dev,
2854                     "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2855
2856          /* Reclaim Rx buffers that have been processed. */
2857         if (sc->age_cdata.age_rxhead != NULL)
2858                 m_freem(sc->age_cdata.age_rxhead);
2859         AGE_RXCHAIN_RESET(sc);
2860         /*
2861          * Free RX and TX mbufs still in the queues.
2862          */
2863         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2864                 rxd = &sc->age_cdata.age_rxdesc[i];
2865                 if (rxd->rx_m != NULL) {
2866                         bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2867                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2868                         bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2869                             rxd->rx_dmamap);
2870                         m_freem(rxd->rx_m);
2871                         rxd->rx_m = NULL;
2872                 }
2873         }
2874         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2875                 txd = &sc->age_cdata.age_txdesc[i];
2876                 if (txd->tx_m != NULL) {
2877                         bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2878                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2879                         bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2880                             txd->tx_dmamap);
2881                         m_freem(txd->tx_m);
2882                         txd->tx_m = NULL;
2883                 }
2884         }
2885 }
2886
2887 static void
2888 age_stop_txmac(struct age_softc *sc)
2889 {
2890         uint32_t reg;
2891         int i;
2892
2893         AGE_LOCK_ASSERT(sc);
2894
2895         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2896         if ((reg & MAC_CFG_TX_ENB) != 0) {
2897                 reg &= ~MAC_CFG_TX_ENB;
2898                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2899         }
2900         /* Stop Tx DMA engine. */
2901         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2902         if ((reg & DMA_CFG_RD_ENB) != 0) {
2903                 reg &= ~DMA_CFG_RD_ENB;
2904                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2905         }
2906         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2907                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2908                     (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2909                         break;
2910                 DELAY(10);
2911         }
2912         if (i == 0)
2913                 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2914 }
2915
2916 static void
2917 age_stop_rxmac(struct age_softc *sc)
2918 {
2919         uint32_t reg;
2920         int i;
2921
2922         AGE_LOCK_ASSERT(sc);
2923
2924         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2925         if ((reg & MAC_CFG_RX_ENB) != 0) {
2926                 reg &= ~MAC_CFG_RX_ENB;
2927                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2928         }
2929         /* Stop Rx DMA engine. */
2930         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2931         if ((reg & DMA_CFG_WR_ENB) != 0) {
2932                 reg &= ~DMA_CFG_WR_ENB;
2933                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2934         }
2935         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2936                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2937                     (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2938                         break;
2939                 DELAY(10);
2940         }
2941         if (i == 0)
2942                 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2943 }
2944
2945 static void
2946 age_init_tx_ring(struct age_softc *sc)
2947 {
2948         struct age_ring_data *rd;
2949         struct age_txdesc *txd;
2950         int i;
2951
2952         AGE_LOCK_ASSERT(sc);
2953
2954         sc->age_cdata.age_tx_prod = 0;
2955         sc->age_cdata.age_tx_cons = 0;
2956         sc->age_cdata.age_tx_cnt = 0;
2957
2958         rd = &sc->age_rdata;
2959         bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2960         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2961                 txd = &sc->age_cdata.age_txdesc[i];
2962                 txd->tx_desc = &rd->age_tx_ring[i];
2963                 txd->tx_m = NULL;
2964         }
2965
2966         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2967             sc->age_cdata.age_tx_ring_map,
2968             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2969 }
2970
2971 static int
2972 age_init_rx_ring(struct age_softc *sc)
2973 {
2974         struct age_ring_data *rd;
2975         struct age_rxdesc *rxd;
2976         int i;
2977
2978         AGE_LOCK_ASSERT(sc);
2979
2980         sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
2981         sc->age_morework = 0;
2982         rd = &sc->age_rdata;
2983         bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
2984         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2985                 rxd = &sc->age_cdata.age_rxdesc[i];
2986                 rxd->rx_m = NULL;
2987                 rxd->rx_desc = &rd->age_rx_ring[i];
2988                 if (age_newbuf(sc, rxd) != 0)
2989                         return (ENOBUFS);
2990         }
2991
2992         bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2993             sc->age_cdata.age_rx_ring_map,
2994             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2995
2996         return (0);
2997 }
2998
2999 static void
3000 age_init_rr_ring(struct age_softc *sc)
3001 {
3002         struct age_ring_data *rd;
3003
3004         AGE_LOCK_ASSERT(sc);
3005
3006         sc->age_cdata.age_rr_cons = 0;
3007         AGE_RXCHAIN_RESET(sc);
3008
3009         rd = &sc->age_rdata;
3010         bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3011         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3012             sc->age_cdata.age_rr_ring_map,
3013             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3014 }
3015
3016 static void
3017 age_init_cmb_block(struct age_softc *sc)
3018 {
3019         struct age_ring_data *rd;
3020
3021         AGE_LOCK_ASSERT(sc);
3022
3023         rd = &sc->age_rdata;
3024         bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3025         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3026             sc->age_cdata.age_cmb_block_map,
3027             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3028 }
3029
3030 static void
3031 age_init_smb_block(struct age_softc *sc)
3032 {
3033         struct age_ring_data *rd;
3034
3035         AGE_LOCK_ASSERT(sc);
3036
3037         rd = &sc->age_rdata;
3038         bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3039         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3040             sc->age_cdata.age_smb_block_map,
3041             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3042 }
3043
3044 static int
3045 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3046 {
3047         struct rx_desc *desc;
3048         struct mbuf *m;
3049         bus_dma_segment_t segs[1];
3050         bus_dmamap_t map;
3051         int nsegs;
3052
3053         AGE_LOCK_ASSERT(sc);
3054
3055         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3056         if (m == NULL)
3057                 return (ENOBUFS);
3058         m->m_len = m->m_pkthdr.len = MCLBYTES;
3059         m_adj(m, ETHER_ALIGN);
3060
3061         if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3062             sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3063                 m_freem(m);
3064                 return (ENOBUFS);
3065         }
3066         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3067
3068         if (rxd->rx_m != NULL) {
3069                 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3070                     BUS_DMASYNC_POSTREAD);
3071                 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3072         }
3073         map = rxd->rx_dmamap;
3074         rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3075         sc->age_cdata.age_rx_sparemap = map;
3076         bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3077             BUS_DMASYNC_PREREAD);
3078         rxd->rx_m = m;
3079
3080         desc = rxd->rx_desc;
3081         desc->addr = htole64(segs[0].ds_addr);
3082         desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3083             AGE_RD_LEN_SHIFT);
3084         return (0);
3085 }
3086
3087 static void
3088 age_rxvlan(struct age_softc *sc)
3089 {
3090         struct ifnet *ifp;
3091         uint32_t reg;
3092
3093         AGE_LOCK_ASSERT(sc);
3094
3095         ifp = sc->age_ifp;
3096         reg = CSR_READ_4(sc, AGE_MAC_CFG);
3097         reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3098         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3099                 reg |= MAC_CFG_VLAN_TAG_STRIP;
3100         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3101 }
3102
3103 static void
3104 age_rxfilter(struct age_softc *sc)
3105 {
3106         struct ifnet *ifp;
3107         struct ifmultiaddr *ifma;
3108         uint32_t crc;
3109         uint32_t mchash[2];
3110         uint32_t rxcfg;
3111
3112         AGE_LOCK_ASSERT(sc);
3113
3114         ifp = sc->age_ifp;
3115
3116         rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3117         rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3118         if ((ifp->if_flags & IFF_BROADCAST) != 0)
3119                 rxcfg |= MAC_CFG_BCAST;
3120         if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3121                 if ((ifp->if_flags & IFF_PROMISC) != 0)
3122                         rxcfg |= MAC_CFG_PROMISC;
3123                 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3124                         rxcfg |= MAC_CFG_ALLMULTI;
3125                 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3126                 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3127                 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3128                 return;
3129         }
3130
3131         /* Program new filter. */
3132         bzero(mchash, sizeof(mchash));
3133
3134         if_maddr_rlock(ifp);
3135         TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) {
3136                 if (ifma->ifma_addr->sa_family != AF_LINK)
3137                         continue;
3138                 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
3139                     ifma->ifma_addr), ETHER_ADDR_LEN);
3140                 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3141         }
3142         if_maddr_runlock(ifp);
3143
3144         CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3145         CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3146         CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3147 }
3148
3149 static int
3150 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3151 {
3152         struct age_softc *sc;
3153         struct age_stats *stats;
3154         int error, result;
3155
3156         result = -1;
3157         error = sysctl_handle_int(oidp, &result, 0, req);
3158
3159         if (error != 0 || req->newptr == NULL)
3160                 return (error);
3161
3162         if (result != 1)
3163                 return (error);
3164
3165         sc = (struct age_softc *)arg1;
3166         stats = &sc->age_stat;
3167         printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3168         printf("Transmit good frames : %ju\n",
3169             (uintmax_t)stats->tx_frames);
3170         printf("Transmit good broadcast frames : %ju\n",
3171             (uintmax_t)stats->tx_bcast_frames);
3172         printf("Transmit good multicast frames : %ju\n",
3173             (uintmax_t)stats->tx_mcast_frames);
3174         printf("Transmit pause control frames : %u\n",
3175             stats->tx_pause_frames);
3176         printf("Transmit control frames : %u\n",
3177             stats->tx_control_frames);
3178         printf("Transmit frames with excessive deferrals : %u\n",
3179             stats->tx_excess_defer);
3180         printf("Transmit deferrals : %u\n",
3181             stats->tx_deferred);
3182         printf("Transmit good octets : %ju\n",
3183             (uintmax_t)stats->tx_bytes);
3184         printf("Transmit good broadcast octets : %ju\n",
3185             (uintmax_t)stats->tx_bcast_bytes);
3186         printf("Transmit good multicast octets : %ju\n",
3187             (uintmax_t)stats->tx_mcast_bytes);
3188         printf("Transmit frames 64 bytes : %ju\n",
3189             (uintmax_t)stats->tx_pkts_64);
3190         printf("Transmit frames 65 to 127 bytes : %ju\n",
3191             (uintmax_t)stats->tx_pkts_65_127);
3192         printf("Transmit frames 128 to 255 bytes : %ju\n",
3193             (uintmax_t)stats->tx_pkts_128_255);
3194         printf("Transmit frames 256 to 511 bytes : %ju\n",
3195             (uintmax_t)stats->tx_pkts_256_511);
3196         printf("Transmit frames 512 to 1024 bytes : %ju\n",
3197             (uintmax_t)stats->tx_pkts_512_1023);
3198         printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3199             (uintmax_t)stats->tx_pkts_1024_1518);
3200         printf("Transmit frames 1519 to MTU bytes : %ju\n",
3201             (uintmax_t)stats->tx_pkts_1519_max);
3202         printf("Transmit single collisions : %u\n",
3203             stats->tx_single_colls);
3204         printf("Transmit multiple collisions : %u\n",
3205             stats->tx_multi_colls);
3206         printf("Transmit late collisions : %u\n",
3207             stats->tx_late_colls);
3208         printf("Transmit abort due to excessive collisions : %u\n",
3209             stats->tx_excess_colls);
3210         printf("Transmit underruns due to FIFO underruns : %u\n",
3211             stats->tx_underrun);
3212         printf("Transmit descriptor write-back errors : %u\n",
3213             stats->tx_desc_underrun);
3214         printf("Transmit frames with length mismatched frame size : %u\n",
3215             stats->tx_lenerrs);
3216         printf("Transmit frames with truncated due to MTU size : %u\n",
3217             stats->tx_lenerrs);
3218
3219         printf("Receive good frames : %ju\n",
3220             (uintmax_t)stats->rx_frames);
3221         printf("Receive good broadcast frames : %ju\n",
3222             (uintmax_t)stats->rx_bcast_frames);
3223         printf("Receive good multicast frames : %ju\n",
3224             (uintmax_t)stats->rx_mcast_frames);
3225         printf("Receive pause control frames : %u\n",
3226             stats->rx_pause_frames);
3227         printf("Receive control frames : %u\n",
3228             stats->rx_control_frames);
3229         printf("Receive CRC errors : %u\n",
3230             stats->rx_crcerrs);
3231         printf("Receive frames with length errors : %u\n",
3232             stats->rx_lenerrs);
3233         printf("Receive good octets : %ju\n",
3234             (uintmax_t)stats->rx_bytes);
3235         printf("Receive good broadcast octets : %ju\n",
3236             (uintmax_t)stats->rx_bcast_bytes);
3237         printf("Receive good multicast octets : %ju\n",
3238             (uintmax_t)stats->rx_mcast_bytes);
3239         printf("Receive frames too short : %u\n",
3240             stats->rx_runts);
3241         printf("Receive fragmented frames : %ju\n",
3242             (uintmax_t)stats->rx_fragments);
3243         printf("Receive frames 64 bytes : %ju\n",
3244             (uintmax_t)stats->rx_pkts_64);
3245         printf("Receive frames 65 to 127 bytes : %ju\n",
3246             (uintmax_t)stats->rx_pkts_65_127);
3247         printf("Receive frames 128 to 255 bytes : %ju\n",
3248             (uintmax_t)stats->rx_pkts_128_255);
3249         printf("Receive frames 256 to 511 bytes : %ju\n",
3250             (uintmax_t)stats->rx_pkts_256_511);
3251         printf("Receive frames 512 to 1024 bytes : %ju\n",
3252             (uintmax_t)stats->rx_pkts_512_1023);
3253         printf("Receive frames 1024 to 1518 bytes : %ju\n",
3254             (uintmax_t)stats->rx_pkts_1024_1518);
3255         printf("Receive frames 1519 to MTU bytes : %ju\n",
3256             (uintmax_t)stats->rx_pkts_1519_max);
3257         printf("Receive frames too long : %ju\n",
3258             (uint64_t)stats->rx_pkts_truncated);
3259         printf("Receive frames with FIFO overflow : %u\n",
3260             stats->rx_fifo_oflows);
3261         printf("Receive frames with return descriptor overflow : %u\n",
3262             stats->rx_desc_oflows);
3263         printf("Receive frames with alignment errors : %u\n",
3264             stats->rx_alignerrs);
3265         printf("Receive frames dropped due to address filtering : %ju\n",
3266             (uint64_t)stats->rx_pkts_filtered);
3267
3268         return (error);
3269 }
3270
3271 static int
3272 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3273 {
3274         int error, value;
3275
3276         if (arg1 == NULL)
3277                 return (EINVAL);
3278         value = *(int *)arg1;
3279         error = sysctl_handle_int(oidp, &value, 0, req);
3280         if (error || req->newptr == NULL)
3281                 return (error);
3282         if (value < low || value > high)
3283                 return (EINVAL);
3284         *(int *)arg1 = value;
3285
3286         return (0);
3287 }
3288
3289 static int
3290 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3291 {
3292         return (sysctl_int_range(oidp, arg1, arg2, req,
3293             AGE_PROC_MIN, AGE_PROC_MAX));
3294 }
3295
3296 static int
3297 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3298 {
3299
3300         return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3301             AGE_IM_TIMER_MAX));
3302 }