2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/ata/ata-all.h>
51 ata_sata_phy_check_events(device_t dev)
53 struct ata_channel *ch = device_get_softc(dev);
54 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
56 /* clear error bits/interrupt */
57 ATA_IDX_OUTL(ch, ATA_SERROR, error);
59 /* if we have a connection event deal with it */
60 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
62 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
63 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
64 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
65 device_printf(dev, "CONNECT requested\n");
67 device_printf(dev, "DISCONNECT requested\n");
69 taskqueue_enqueue(taskqueue_thread, &ch->conntask);
74 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)
79 *val = ATA_IDX_INL(ch, reg);
95 return (ch->hw.pm_read(ch->dev, port, r, val));
100 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)
105 ATA_IDX_OUTL(ch, reg, val);
118 return (ch->hw.pm_write(ch->dev, port, r, val));
123 ata_sata_connect(struct ata_channel *ch, int port)
128 /* wait up to 1 second for "connect well" */
129 for (timeout = 0; timeout < 100 ; timeout++) {
130 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status))
132 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
133 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
137 if (timeout >= 100) {
140 device_printf(ch->dev, "SATA connect timeout status=%08x\n",
143 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n",
151 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
152 timeout * 10, status);
154 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n",
155 port, timeout * 10, status);
159 /* clear SATA error register */
160 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
166 ata_sata_phy_reset(device_t dev, int port, int quick)
168 struct ata_channel *ch = device_get_softc(dev);
173 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
175 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
176 return ata_sata_connect(ch, port);
181 device_printf(dev, "hardware reset ...\n");
183 device_printf(dev, "p%d: hardware reset ...\n", port);
186 for (retry = 0; retry < 10; retry++) {
187 for (loop = 0; loop < 10; loop++) {
188 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET))
191 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
193 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
197 for (loop = 0; loop < 10; loop++) {
198 if (ata_sata_scr_write(ch, port, ATA_SCONTROL,
199 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 :
200 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)))
203 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
205 if ((val & ATA_SC_DET_MASK) == 0)
206 return ata_sata_connect(ch, port);
213 ata_sata_setmode(device_t dev, int mode)
215 struct ata_device *atadev = device_get_softc(dev);
218 * if we detect that the device isn't a real SATA device we limit
219 * the transfer mode to UDMA5/ATA100.
220 * this works around the problems some devices has with the
221 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
223 if (atadev->param.satacapabilities != 0x0000 &&
224 atadev->param.satacapabilities != 0xffff) {
225 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
227 /* on some drives we need to set the transfer mode */
228 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
229 ata_limit_mode(dev, mode, ATA_UDMA6));
231 /* query SATA STATUS for the speed */
232 if (ch->r_io[ATA_SSTATUS].res &&
233 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
234 ATA_SS_CONWELL_GEN2))
235 atadev->mode = ATA_SA300;
237 atadev->mode = ATA_SA150;
240 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
241 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
247 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
249 struct ata_device *atadev = device_get_softc(request->dev);
251 if (request->flags & ATA_R_ATAPI) {
252 fis[0] = 0x27; /* host to device */
253 fis[1] = 0x80 | (atadev->unit & 0x0f);
254 fis[2] = ATA_PACKET_CMD;
255 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
258 fis[5] = request->transfersize;
259 fis[6] = request->transfersize >> 8;
262 fis[15] = ATA_A_4BIT;
266 ata_modify_if_48bit(request);
267 fis[0] = 0x27; /* host to device */
268 fis[1] = 0x80 | (atadev->unit & 0x0f);
269 fis[2] = request->u.ata.command;
270 fis[3] = request->u.ata.feature;
271 fis[4] = request->u.ata.lba;
272 fis[5] = request->u.ata.lba >> 8;
273 fis[6] = request->u.ata.lba >> 16;
275 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
276 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f));
277 fis[8] = request->u.ata.lba >> 24;
278 fis[9] = request->u.ata.lba >> 32;
279 fis[10] = request->u.ata.lba >> 40;
280 fis[11] = request->u.ata.feature >> 8;
281 fis[12] = request->u.ata.count;
282 fis[13] = request->u.ata.count >> 8;
283 fis[15] = ATA_A_4BIT;
290 ata_pm_identify(device_t dev)
292 struct ata_channel *ch = device_get_softc(dev);
293 u_int32_t pm_chipid, pm_revision, pm_ports;
296 /* get PM vendor & product data */
297 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) {
298 device_printf(dev, "error getting PM vendor data\n");
302 /* get PM revision data */
303 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) {
304 device_printf(dev, "error getting PM revison data\n");
308 /* get number of HW ports on the PM */
309 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) {
310 device_printf(dev, "error getting PM port info\n");
313 pm_ports &= 0x0000000f;
315 /* chip specific quirks */
318 /* This PM declares 6 ports, while only 5 of them are real.
319 * Port 5 is enclosure management bridge port, which has implementation
320 * problems, causing probe faults. Hide it for now. */
321 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n",
322 pm_revision, pm_ports);
327 /* This PM declares 7 ports, while only 5 of them are real.
328 * Port 5 is some fake "Config Disk" with 640 sectors size,
329 * port 6 is enclosure management bridge port.
330 * Both fake ports has implementation problems, causing
331 * probe faults. Hide them for now. */
332 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n",
333 pm_revision, pm_ports);
338 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n",
339 pm_chipid, pm_revision, pm_ports);
342 /* realloc space for needed DMA slots */
343 ch->dma.dma_slots = pm_ports;
345 /* reset all ports and register if anything connected */
346 for (port=0; port < pm_ports; port++) {
349 if (!ata_sata_phy_reset(dev, port, 1))
353 * XXX: I have no idea how to properly wait for PMP port hardreset
354 * completion. Without this delay soft reset does not completes
359 signature = ch->hw.softreset(dev, port);
362 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature);
364 /* figure out whats there */
365 switch (signature >> 16) {
367 ch->devices |= (ATA_ATA_MASTER << port);
370 ch->devices |= (ATA_ATAPI_MASTER << port);