2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
47 #include <sys/pciio.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
55 /* local prototypes */
56 static int ata_ati_chipinit(device_t dev);
57 static void ata_ati_setmode(device_t dev, int mode);
58 static void ata_ati_ahci_enable(device_t dev);
59 static int ata_ati_ahci_chipinit(device_t dev);
60 static int ata_ati_ahci_resume(device_t dev);
69 /* Misc Control Register */
70 #define ATI_PCI_MISC_CTRL 0x40
71 #define ATI_PCI_MISCCTRL_ENABLE_WR 0x00000001
73 /* Watchdog Control/Status Register */
74 #define ATI_PCI_WD_CTRL 0x44
75 #define ATI_PCI_WDCTRL_ENABLE 0x0001
78 * ATI chipset support functions
81 ata_ati_probe(device_t dev)
83 struct ata_pci_controller *ctlr = device_get_softc(dev);
84 static struct ata_chip_id ids[] =
85 {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" },
86 { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" },
87 { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, 0, ATA_SA150, "IXP300" },
88 { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" },
89 { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, 0, ATA_SA150, "IXP400" },
90 { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, 0, ATA_SA150, "IXP400" },
91 { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" },
92 { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" },
93 { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" },
94 { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
95 { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
96 { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
97 { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
98 { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
99 { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
100 { 0, 0, 0, 0, 0, 0}};
102 if (pci_get_vendor(dev) != ATA_ATI_ID)
105 if (!(ctlr->chip = ata_match_chip(dev, ids)))
110 switch (ctlr->chip->cfg1) {
112 ctlr->chipinit = ata_ati_chipinit;
116 * the ATI SATA controller is actually a SiI 3112 controller
117 * cfg values below much match those in ata-siliconimage.c
119 ctlr->chip->cfg1 = SII_MEMIO;
120 ctlr->chip->cfg2 = SII_BUG;
121 ctlr->chipinit = ata_sii_chipinit;
125 * Force AHCI mode if IDE mode is set from BIOS.
127 if ((ctlr->chip->chipid == ATA_ATI_IXP600_S1 ||
128 ctlr->chip->chipid == ATA_ATI_IXP700_S1) &&
129 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
130 struct pci_devinfo *dinfo = device_get_ivars(dev);
131 pcicfgregs *cfg = &dinfo->cfg;
132 cfg->subclass = PCIS_STORAGE_SATA;
133 cfg->progif = PCIP_STORAGE_SATA_AHCI_1_0;
134 ata_ati_ahci_enable(dev);
136 ctlr->chipinit = ata_ati_ahci_chipinit;
139 return (BUS_PROBE_DEFAULT);
143 ata_ati_chipinit(device_t dev)
145 struct ata_pci_controller *ctlr = device_get_softc(dev);
147 if (ata_setup_interrupt(dev, ata_generic_intr))
150 /* IXP600 only has 1 PATA channel */
151 if (ctlr->chip->chipid == ATA_ATI_IXP600)
154 ctlr->setmode = ata_ati_setmode;
159 ata_ati_setmode(device_t dev, int mode)
161 device_t gparent = GRANDPARENT(dev);
162 struct ata_pci_controller *ctlr = device_get_softc(gparent);
163 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
164 struct ata_device *atadev = device_get_softc(dev);
165 int devno = (ch->unit << 1) + atadev->unit;
166 int offset = (devno ^ 0x01) << 3;
168 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
169 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
170 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
172 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
174 mode = ata_check_80pin(dev, mode);
176 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
179 device_printf(dev, "%ssetting %s on %s chip\n",
180 (error) ? "FAILURE " : "",
181 ata_mode2str(mode), ctlr->chip->text);
183 if (mode >= ATA_UDMA0) {
184 pci_write_config(gparent, 0x56,
185 (pci_read_config(gparent, 0x56, 2) &
186 ~(0xf << (devno << 2))) |
187 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
188 pci_write_config(gparent, 0x54,
189 pci_read_config(gparent, 0x54, 1) |
191 pci_write_config(gparent, 0x44,
192 (pci_read_config(gparent, 0x44, 4) &
194 (dmatimings[2] << offset), 4);
196 else if (mode >= ATA_WDMA0) {
197 pci_write_config(gparent, 0x54,
198 pci_read_config(gparent, 0x54, 1) &
199 ~(0x01 << devno), 1);
200 pci_write_config(gparent, 0x44,
201 (pci_read_config(gparent, 0x44, 4) &
203 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
206 pci_write_config(gparent, 0x54,
207 pci_read_config(gparent, 0x54, 1) &
208 ~(0x01 << devno), 1);
210 pci_write_config(gparent, 0x4a,
211 (pci_read_config(gparent, 0x4a, 2) &
212 ~(0xf << (devno << 2))) |
213 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
214 pci_write_config(gparent, 0x40,
215 (pci_read_config(gparent, 0x40, 4) &
217 (piotimings[ata_mode2idx(mode)] << offset), 4);
223 ata_ati_ahci_enable(device_t dev)
225 struct pci_devinfo *dinfo = device_get_ivars(dev);
226 pcicfgregs *cfg = &dinfo->cfg;
229 ctrl = pci_read_config(dev, ATI_PCI_MISC_CTRL, 4);
230 pci_write_config(dev, ATI_PCI_MISC_CTRL,
231 ctrl | ATI_PCI_MISCCTRL_ENABLE_WR, 4);
232 pci_write_config(dev, PCIR_SUBCLASS, cfg->subclass, 1);
233 pci_write_config(dev, PCIR_PROGIF, cfg->progif, 1);
234 pci_write_config(dev, ATI_PCI_WD_CTRL,
235 pci_read_config(dev, ATI_PCI_WD_CTRL, 2) | ATI_PCI_WDCTRL_ENABLE, 2);
236 pci_write_config(dev, ATI_PCI_MISC_CTRL,
237 ctrl & ~ATI_PCI_MISCCTRL_ENABLE_WR, 4);
241 ata_ati_ahci_chipinit(device_t dev)
243 struct ata_pci_controller *ctlr = device_get_softc(dev);
246 error = ata_ahci_chipinit(dev);
247 ctlr->resume = ata_ati_ahci_resume;
252 ata_ati_ahci_resume(device_t dev)
255 ata_ati_ahci_enable(dev);
256 return (ata_ahci_ctlr_reset(dev));
259 ATA_DECLARE_DRIVER(ata_ati);
260 MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
261 MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);