2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/sysctl.h>
48 #include <sys/malloc.h>
50 #include <sys/mutex.h>
51 #include <sys/kernel.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/errno.h>
55 #include <sys/callout.h>
57 #include <sys/endian.h>
58 #include <sys/kthread.h>
59 #include <sys/taskqueue.h>
62 #include <machine/bus.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_types.h>
68 #include <net/if_arp.h>
69 #include <net/ethernet.h>
70 #include <net/if_llc.h>
72 #include <net80211/ieee80211_var.h>
73 #include <net80211/ieee80211_regdomain.h>
74 #ifdef IEEE80211_SUPPORT_SUPERG
75 #include <net80211/ieee80211_superg.h>
77 #ifdef IEEE80211_SUPPORT_TDMA
78 #include <net80211/ieee80211_tdma.h>
84 #include <netinet/in.h>
85 #include <netinet/if_ether.h>
88 #include <dev/ath/if_athvar.h>
89 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
92 #include <dev/ath/ath_tx99/ath_tx99.h>
96 * ATH_BCBUF determines the number of vap's that can transmit
97 * beacons and also (currently) the number of vap's that can
98 * have unique mac addresses/bssid. When staggering beacons
99 * 4 is probably a good max as otherwise the beacons become
100 * very closely spaced and there is limited time for cab q traffic
101 * to go out. You can burst beacons instead but that is not good
102 * for stations in power save and at some point you really want
103 * another radio (and channel).
105 * The limit on the number of mac addresses is tied to our use of
106 * the U/L bit and tracking addresses in a byte; it would be
107 * worthwhile to allow more for applications like proxy sta.
109 CTASSERT(ATH_BCBUF <= 8);
111 /* unaligned little endian access */
112 #define LE_READ_2(p) \
114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
115 #define LE_READ_4(p) \
117 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
118 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
120 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
121 const char name[IFNAMSIZ], int unit, int opmode,
122 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
123 const uint8_t mac[IEEE80211_ADDR_LEN]);
124 static void ath_vap_delete(struct ieee80211vap *);
125 static void ath_init(void *);
126 static void ath_stop_locked(struct ifnet *);
127 static void ath_stop(struct ifnet *);
128 static void ath_start(struct ifnet *);
129 static int ath_reset(struct ifnet *);
130 static int ath_reset_vap(struct ieee80211vap *, u_long);
131 static int ath_media_change(struct ifnet *);
132 static void ath_watchdog(void *);
133 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
134 static void ath_fatal_proc(void *, int);
135 static void ath_bmiss_vap(struct ieee80211vap *);
136 static void ath_bmiss_proc(void *, int);
137 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *,
138 struct ieee80211_node *);
139 static int ath_key_alloc(struct ieee80211vap *,
140 struct ieee80211_key *,
141 ieee80211_keyix *, ieee80211_keyix *);
142 static int ath_key_delete(struct ieee80211vap *,
143 const struct ieee80211_key *);
144 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *,
145 const u_int8_t mac[IEEE80211_ADDR_LEN]);
146 static void ath_key_update_begin(struct ieee80211vap *);
147 static void ath_key_update_end(struct ieee80211vap *);
148 static void ath_update_mcast(struct ifnet *);
149 static void ath_update_promisc(struct ifnet *);
150 static void ath_mode_init(struct ath_softc *);
151 static void ath_setslottime(struct ath_softc *);
152 static void ath_updateslot(struct ifnet *);
153 static int ath_beaconq_setup(struct ath_hal *);
154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
155 static void ath_beacon_update(struct ieee80211vap *, int item);
156 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
157 static void ath_beacon_proc(void *, int);
158 static struct ath_buf *ath_beacon_generate(struct ath_softc *,
159 struct ieee80211vap *);
160 static void ath_bstuck_proc(void *, int);
161 static void ath_beacon_return(struct ath_softc *, struct ath_buf *);
162 static void ath_beacon_free(struct ath_softc *);
163 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *);
164 static void ath_descdma_cleanup(struct ath_softc *sc,
165 struct ath_descdma *, ath_bufhead *);
166 static int ath_desc_alloc(struct ath_softc *);
167 static void ath_desc_free(struct ath_softc *);
168 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
169 const uint8_t [IEEE80211_ADDR_LEN]);
170 static void ath_node_free(struct ieee80211_node *);
171 static void ath_node_getsignal(const struct ieee80211_node *,
173 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
174 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
175 int subtype, int rssi, int nf);
176 static void ath_setdefantenna(struct ath_softc *, u_int);
177 static void ath_rx_proc(void *, int);
178 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
179 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
180 static int ath_tx_setup(struct ath_softc *, int, int);
181 static int ath_wme_update(struct ieee80211com *);
182 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
183 static void ath_tx_cleanup(struct ath_softc *);
184 static void ath_freetx(struct mbuf *);
185 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
186 struct ath_buf *, struct mbuf *);
187 static void ath_tx_proc_q0(void *, int);
188 static void ath_tx_proc_q0123(void *, int);
189 static void ath_tx_proc(void *, int);
190 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *);
191 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
192 static void ath_draintxq(struct ath_softc *);
193 static void ath_stoprecv(struct ath_softc *);
194 static int ath_startrecv(struct ath_softc *);
195 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
196 static void ath_scan_start(struct ieee80211com *);
197 static void ath_scan_end(struct ieee80211com *);
198 static void ath_set_channel(struct ieee80211com *);
199 static void ath_calibrate(void *);
200 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
201 static void ath_setup_stationkey(struct ieee80211_node *);
202 static void ath_newassoc(struct ieee80211_node *, int);
203 static int ath_setregdomain(struct ieee80211com *,
204 struct ieee80211_regdomain *, int,
205 struct ieee80211_channel []);
206 static void ath_getradiocaps(struct ieee80211com *, int, int *,
207 struct ieee80211_channel []);
208 static int ath_getchannels(struct ath_softc *);
209 static void ath_led_event(struct ath_softc *, int);
211 static int ath_rate_setup(struct ath_softc *, u_int mode);
212 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
214 static void ath_sysctlattach(struct ath_softc *);
215 static int ath_raw_xmit(struct ieee80211_node *,
216 struct mbuf *, const struct ieee80211_bpf_params *);
217 static void ath_announce(struct ath_softc *);
219 #ifdef IEEE80211_SUPPORT_TDMA
220 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
222 static void ath_tdma_bintvalsetup(struct ath_softc *sc,
223 const struct ieee80211_tdma_state *tdma);
224 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap);
225 static void ath_tdma_update(struct ieee80211_node *ni,
226 const struct ieee80211_tdma_param *tdma, int);
227 static void ath_tdma_beacon_send(struct ath_softc *sc,
228 struct ieee80211vap *vap);
231 ath_hal_setcca(struct ath_hal *ah, int ena)
234 * NB: fill me in; this is not provided by default because disabling
235 * CCA in most locales violates regulatory.
240 ath_hal_getcca(struct ath_hal *ah)
243 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK)
245 return ((diag & 0x500000) == 0);
248 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */
249 #define TDMA_LPF_LEN 6
250 #define TDMA_DUMMY_MARKER 0x127
251 #define TDMA_EP_MUL(x, mul) ((x) * (mul))
252 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER))
253 #define TDMA_LPF(x, y, len) \
254 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y))
255 #define TDMA_SAMPLE(x, y) do { \
256 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \
258 #define TDMA_EP_RND(x,mul) \
259 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
260 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER)
261 #endif /* IEEE80211_SUPPORT_TDMA */
263 SYSCTL_DECL(_hw_ath);
265 /* XXX validate sysctl values */
266 static int ath_longcalinterval = 30; /* long cals every 30 secs */
267 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
268 0, "long chip calibration interval (secs)");
269 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
270 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
271 0, "short chip calibration interval (msecs)");
272 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
273 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
274 0, "reset chip calibration results (secs)");
276 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
277 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
278 0, "rx buffers allocated");
279 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
280 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
281 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
282 0, "tx buffers allocated");
283 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
285 static int ath_bstuck_threshold = 4; /* max missed beacons */
286 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
287 0, "max missed beacon xmits before chip reset");
291 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
292 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
293 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
294 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
295 ATH_DEBUG_RATE = 0x00000010, /* rate control */
296 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
297 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
298 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
299 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
300 ATH_DEBUG_INTR = 0x00001000, /* ISR */
301 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
302 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
303 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
304 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
305 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
306 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
307 ATH_DEBUG_NODE = 0x00080000, /* node management */
308 ATH_DEBUG_LED = 0x00100000, /* led management */
309 ATH_DEBUG_FF = 0x00200000, /* fast frames */
310 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
311 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */
312 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */
313 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */
314 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
315 ATH_DEBUG_ANY = 0xffffffff
317 static int ath_debug = 0;
318 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
319 0, "control debugging printfs");
320 TUNABLE_INT("hw.ath.debug", &ath_debug);
322 #define IFF_DUMPPKTS(sc, m) \
323 ((sc->sc_debug & (m)) || \
324 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
325 #define DPRINTF(sc, m, fmt, ...) do { \
326 if (sc->sc_debug & (m)) \
327 printf(fmt, __VA_ARGS__); \
329 #define KEYPRINTF(sc, ix, hk, mac) do { \
330 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
331 ath_keyprint(sc, __func__, ix, hk, mac); \
333 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf,
335 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf,
336 u_int qnum, u_int ix, int done);
338 #define IFF_DUMPPKTS(sc, m) \
339 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
340 #define DPRINTF(sc, m, fmt, ...) do { \
343 #define KEYPRINTF(sc, k, ix, mac) do { \
348 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
351 ath_attach(u_int16_t devid, struct ath_softc *sc)
354 struct ieee80211com *ic;
355 struct ath_hal *ah = NULL;
359 uint8_t macaddr[IEEE80211_ADDR_LEN];
361 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
363 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
365 device_printf(sc->sc_dev, "can not if_alloc()\n");
371 /* set these up early for if_printf use */
372 if_initname(ifp, device_get_name(sc->sc_dev),
373 device_get_unit(sc->sc_dev));
375 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
377 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
383 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
385 sc->sc_debug = ath_debug;
389 * Check if the MAC has multi-rate retry support.
390 * We do this by trying to setup a fake extended
391 * descriptor. MAC's that don't have support will
392 * return false w/o doing anything. MAC's that do
393 * support it will return true w/o doing anything.
395 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
398 * Check if the device has hardware counters for PHY
399 * errors. If so we need to enable the MIB interrupt
400 * so we can act on stat triggers.
402 if (ath_hal_hwphycounters(ah))
406 * Get the hardware key cache size.
408 sc->sc_keymax = ath_hal_keycachesize(ah);
409 if (sc->sc_keymax > ATH_KEYMAX) {
410 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
411 ATH_KEYMAX, sc->sc_keymax);
412 sc->sc_keymax = ATH_KEYMAX;
415 * Reset the key cache since some parts do not
416 * reset the contents on initial power up.
418 for (i = 0; i < sc->sc_keymax; i++)
419 ath_hal_keyreset(ah, i);
422 * Collect the default channel list.
424 error = ath_getchannels(sc);
429 * Setup rate tables for all potential media types.
431 ath_rate_setup(sc, IEEE80211_MODE_11A);
432 ath_rate_setup(sc, IEEE80211_MODE_11B);
433 ath_rate_setup(sc, IEEE80211_MODE_11G);
434 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
435 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
436 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
437 ath_rate_setup(sc, IEEE80211_MODE_11NA);
438 ath_rate_setup(sc, IEEE80211_MODE_11NG);
439 ath_rate_setup(sc, IEEE80211_MODE_HALF);
440 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
442 /* NB: setup here so ath_rate_update is happy */
443 ath_setcurmode(sc, IEEE80211_MODE_11A);
446 * Allocate tx+rx descriptors and populate the lists.
448 error = ath_desc_alloc(sc);
450 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
453 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
454 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
456 ATH_TXBUF_LOCK_INIT(sc);
458 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
459 taskqueue_thread_enqueue, &sc->sc_tq);
460 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
461 "%s taskq", ifp->if_xname);
463 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
464 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
465 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
468 * Allocate hardware transmit queues: one queue for
469 * beacon frames and one data queue for each QoS
470 * priority. Note that the hal handles reseting
471 * these queues at the needed time.
475 sc->sc_bhalq = ath_beaconq_setup(ah);
476 if (sc->sc_bhalq == (u_int) -1) {
477 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
481 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
482 if (sc->sc_cabq == NULL) {
483 if_printf(ifp, "unable to setup CAB xmit queue!\n");
487 /* NB: insure BK queue is the lowest priority h/w queue */
488 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
489 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
490 ieee80211_wme_acnames[WME_AC_BK]);
494 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
495 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
496 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
498 * Not enough hardware tx queues to properly do WME;
499 * just punt and assign them all to the same h/w queue.
500 * We could do a better job of this if, for example,
501 * we allocate queues when we switch from station to
504 if (sc->sc_ac2q[WME_AC_VI] != NULL)
505 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
506 if (sc->sc_ac2q[WME_AC_BE] != NULL)
507 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
508 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
509 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
510 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
514 * Special case certain configurations. Note the
515 * CAB queue is handled by these specially so don't
516 * include them when checking the txq setup mask.
518 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
520 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
523 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
526 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
531 * Setup rate control. Some rate control modules
532 * call back to change the anntena state so expose
533 * the necessary entry points.
534 * XXX maybe belongs in struct ath_ratectrl?
536 sc->sc_setdefantenna = ath_setdefantenna;
537 sc->sc_rc = ath_rate_attach(sc);
538 if (sc->sc_rc == NULL) {
545 sc->sc_ledon = 0; /* low true */
546 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
547 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
549 * Auto-enable soft led processing for IBM cards and for
550 * 5211 minipci cards. Users can also manually enable/disable
551 * support with a sysctl.
553 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
554 if (sc->sc_softled) {
555 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
556 HAL_GPIO_MUX_MAC_NETWORK_LED);
557 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
561 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
562 ifp->if_start = ath_start;
563 ifp->if_watchdog = NULL;
564 ifp->if_ioctl = ath_ioctl;
565 ifp->if_init = ath_init;
566 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
567 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
568 IFQ_SET_READY(&ifp->if_snd);
571 /* XXX not right but it's not used anywhere important */
572 ic->ic_phytype = IEEE80211_T_OFDM;
573 ic->ic_opmode = IEEE80211_M_STA;
575 IEEE80211_C_STA /* station mode */
576 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
577 | IEEE80211_C_HOSTAP /* hostap mode */
578 | IEEE80211_C_MONITOR /* monitor mode */
579 | IEEE80211_C_AHDEMO /* adhoc demo mode */
580 | IEEE80211_C_WDS /* 4-address traffic works */
581 | IEEE80211_C_MBSS /* mesh point link mode */
582 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
583 | IEEE80211_C_SHSLOT /* short slot time supported */
584 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
585 | IEEE80211_C_BGSCAN /* capable of bg scanning */
586 | IEEE80211_C_TXFRAG /* handle tx frags */
589 * Query the hal to figure out h/w crypto support.
591 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
592 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
593 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
594 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
595 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
596 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
597 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
598 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
599 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
600 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
602 * Check if h/w does the MIC and/or whether the
603 * separate key cache entries are required to
604 * handle both tx+rx MIC keys.
606 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
607 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
609 * If the h/w supports storing tx+rx MIC keys
610 * in one cache slot automatically enable use.
612 if (ath_hal_hastkipsplit(ah) ||
613 !ath_hal_settkipsplit(ah, AH_FALSE))
616 * If the h/w can do TKIP MIC together with WME then
617 * we use it; otherwise we force the MIC to be done
618 * in software by the net80211 layer.
620 if (ath_hal_haswmetkipmic(ah))
621 sc->sc_wmetkipmic = 1;
623 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
624 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
626 * Mark key cache slots associated with global keys
627 * as in use. If we knew TKIP was not to be used we
628 * could leave the +32, +64, and +32+64 slots free.
630 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
631 setbit(sc->sc_keymap, i);
632 setbit(sc->sc_keymap, i+64);
633 if (sc->sc_splitmic) {
634 setbit(sc->sc_keymap, i+32);
635 setbit(sc->sc_keymap, i+32+64);
639 * TPC support can be done either with a global cap or
640 * per-packet support. The latter is not available on
641 * all parts. We're a bit pedantic here as all parts
642 * support a global cap.
644 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
645 ic->ic_caps |= IEEE80211_C_TXPMGT;
648 * Mark WME capability only if we have sufficient
649 * hardware queues to do proper priority scheduling.
651 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
652 ic->ic_caps |= IEEE80211_C_WME;
654 * Check for misc other capabilities.
656 if (ath_hal_hasbursting(ah))
657 ic->ic_caps |= IEEE80211_C_BURST;
658 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
659 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
660 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
661 if (ath_hal_hasfastframes(ah))
662 ic->ic_caps |= IEEE80211_C_FF;
663 wmodes = ath_hal_getwirelessmodes(ah);
664 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
665 ic->ic_caps |= IEEE80211_C_TURBOP;
666 #ifdef IEEE80211_SUPPORT_TDMA
667 if (ath_hal_macversion(ah) > 0x78) {
668 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
669 ic->ic_tdma_update = ath_tdma_update;
673 * Indicate we need the 802.11 header padded to a
674 * 32-bit boundary for 4-address and QoS frames.
676 ic->ic_flags |= IEEE80211_F_DATAPAD;
679 * Query the hal about antenna support.
681 sc->sc_defant = ath_hal_getdefantenna(ah);
684 * Not all chips have the VEOL support we want to
685 * use with IBSS beacons; check here for it.
687 sc->sc_hasveol = ath_hal_hasveol(ah);
689 /* get mac address from hardware */
690 ath_hal_getmac(ah, macaddr);
692 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
694 /* NB: used to size node table key mapping array */
695 ic->ic_max_keyix = sc->sc_keymax;
696 /* call MI attach routine. */
697 ieee80211_ifattach(ic, macaddr);
698 ic->ic_setregdomain = ath_setregdomain;
699 ic->ic_getradiocaps = ath_getradiocaps;
700 sc->sc_opmode = HAL_M_STA;
702 /* override default methods */
703 ic->ic_newassoc = ath_newassoc;
704 ic->ic_updateslot = ath_updateslot;
705 ic->ic_wme.wme_update = ath_wme_update;
706 ic->ic_vap_create = ath_vap_create;
707 ic->ic_vap_delete = ath_vap_delete;
708 ic->ic_raw_xmit = ath_raw_xmit;
709 ic->ic_update_mcast = ath_update_mcast;
710 ic->ic_update_promisc = ath_update_promisc;
711 ic->ic_node_alloc = ath_node_alloc;
712 sc->sc_node_free = ic->ic_node_free;
713 ic->ic_node_free = ath_node_free;
714 ic->ic_node_getsignal = ath_node_getsignal;
715 ic->ic_scan_start = ath_scan_start;
716 ic->ic_scan_end = ath_scan_end;
717 ic->ic_set_channel = ath_set_channel;
719 ieee80211_radiotap_attach(ic,
720 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
721 ATH_TX_RADIOTAP_PRESENT,
722 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
723 ATH_RX_RADIOTAP_PRESENT);
726 * Setup dynamic sysctl's now that country code and
727 * regdomain are available from the hal.
729 ath_sysctlattach(sc);
732 ieee80211_announce(ic);
748 ath_detach(struct ath_softc *sc)
750 struct ifnet *ifp = sc->sc_ifp;
752 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
753 __func__, ifp->if_flags);
756 * NB: the order of these is important:
757 * o stop the chip so no more interrupts will fire
758 * o call the 802.11 layer before detaching the hal to
759 * insure callbacks into the driver to delete global
760 * key cache entries can be handled
761 * o free the taskqueue which drains any pending tasks
762 * o reclaim the tx queue data structures after calling
763 * the 802.11 layer as we'll get called back to reclaim
764 * node state and potentially want to use them
765 * o to cleanup the tx queues the hal is called, so detach
767 * Other than that, it's straightforward...
770 ieee80211_ifdetach(ifp->if_l2com);
771 taskqueue_free(sc->sc_tq);
773 if (sc->sc_tx99 != NULL)
774 sc->sc_tx99->detach(sc->sc_tx99);
776 ath_rate_detach(sc->sc_rc);
779 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
786 * MAC address handling for multiple BSS on the same radio.
787 * The first vap uses the MAC address from the EEPROM. For
788 * subsequent vap's we set the U/L bit (bit 1) in the MAC
789 * address and use the next six bits as an index.
792 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
796 if (clone && sc->sc_hasbmask) {
797 /* NB: we only do this if h/w supports multiple bssid */
798 for (i = 0; i < 8; i++)
799 if ((sc->sc_bssidmask & (1<<i)) == 0)
802 mac[0] |= (i << 2)|0x2;
805 sc->sc_bssidmask |= 1<<i;
806 sc->sc_hwbssidmask[0] &= ~mac[0];
812 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
817 if (i != 0 || --sc->sc_nbssid0 == 0) {
818 sc->sc_bssidmask &= ~(1<<i);
819 /* recalculate bssid mask from remaining addresses */
821 for (i = 1; i < 8; i++)
822 if (sc->sc_bssidmask & (1<<i))
823 mask &= ~((i<<2)|0x2);
824 sc->sc_hwbssidmask[0] |= mask;
829 * Assign a beacon xmit slot. We try to space out
830 * assignments so when beacons are staggered the
831 * traffic coming out of the cab q has maximal time
832 * to go out before the next beacon is scheduled.
835 assign_bslot(struct ath_softc *sc)
840 for (slot = 0; slot < ATH_BCBUF; slot++)
841 if (sc->sc_bslot[slot] == NULL) {
842 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
843 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
846 /* NB: keep looking for a double slot */
851 static struct ieee80211vap *
852 ath_vap_create(struct ieee80211com *ic,
853 const char name[IFNAMSIZ], int unit, int opmode, int flags,
854 const uint8_t bssid[IEEE80211_ADDR_LEN],
855 const uint8_t mac0[IEEE80211_ADDR_LEN])
857 struct ath_softc *sc = ic->ic_ifp->if_softc;
859 struct ieee80211vap *vap;
860 uint8_t mac[IEEE80211_ADDR_LEN];
861 int ic_opmode, needbeacon, error;
863 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
864 M_80211_VAP, M_WAITOK | M_ZERO);
866 IEEE80211_ADDR_COPY(mac, mac0);
869 ic_opmode = opmode; /* default to opmode of new vap */
871 case IEEE80211_M_STA:
872 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
873 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
878 * With multiple vaps we must fall back
879 * to s/w beacon miss handling.
881 flags |= IEEE80211_CLONE_NOBEACONS;
883 if (flags & IEEE80211_CLONE_NOBEACONS) {
885 * Station mode w/o beacons are implemented w/ AP mode.
887 ic_opmode = IEEE80211_M_HOSTAP;
890 case IEEE80211_M_IBSS:
891 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
892 device_printf(sc->sc_dev,
893 "only 1 ibss vap supported\n");
898 case IEEE80211_M_AHDEMO:
899 #ifdef IEEE80211_SUPPORT_TDMA
900 if (flags & IEEE80211_CLONE_TDMA) {
901 if (sc->sc_nvaps != 0) {
902 device_printf(sc->sc_dev,
903 "only 1 tdma vap supported\n");
907 flags |= IEEE80211_CLONE_NOBEACONS;
911 case IEEE80211_M_MONITOR:
912 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
914 * Adopt existing mode. Adding a monitor or ahdemo
915 * vap to an existing configuration is of dubious
916 * value but should be ok.
918 /* XXX not right for monitor mode */
919 ic_opmode = ic->ic_opmode;
922 case IEEE80211_M_HOSTAP:
923 case IEEE80211_M_MBSS:
926 case IEEE80211_M_WDS:
927 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
928 device_printf(sc->sc_dev,
929 "wds not supported in sta mode\n");
933 * Silently remove any request for a unique
934 * bssid; WDS vap's always share the local
937 flags &= ~IEEE80211_CLONE_BSSID;
938 if (sc->sc_nvaps == 0)
939 ic_opmode = IEEE80211_M_HOSTAP;
941 ic_opmode = ic->ic_opmode;
944 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
948 * Check that a beacon buffer is available; the code below assumes it.
950 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) {
951 device_printf(sc->sc_dev, "no beacon buffer available\n");
956 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
957 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
958 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
962 /* XXX can't hold mutex across if_alloc */
964 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
968 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
973 /* h/w crypto support */
974 vap->iv_key_alloc = ath_key_alloc;
975 vap->iv_key_delete = ath_key_delete;
976 vap->iv_key_set = ath_key_set;
977 vap->iv_key_update_begin = ath_key_update_begin;
978 vap->iv_key_update_end = ath_key_update_end;
980 /* override various methods */
981 avp->av_recv_mgmt = vap->iv_recv_mgmt;
982 vap->iv_recv_mgmt = ath_recv_mgmt;
983 vap->iv_reset = ath_reset_vap;
984 vap->iv_update_beacon = ath_beacon_update;
985 avp->av_newstate = vap->iv_newstate;
986 vap->iv_newstate = ath_newstate;
987 avp->av_bmiss = vap->iv_bmiss;
988 vap->iv_bmiss = ath_bmiss_vap;
993 * Allocate beacon state and setup the q for buffered
994 * multicast frames. We know a beacon buffer is
995 * available because we checked above.
997 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf);
998 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list);
999 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1001 * Assign the vap to a beacon xmit slot. As above
1002 * this cannot fail to find a free one.
1004 avp->av_bslot = assign_bslot(sc);
1005 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1006 ("beacon slot %u not empty", avp->av_bslot));
1007 sc->sc_bslot[avp->av_bslot] = vap;
1010 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1012 * Multple vaps are to transmit beacons and we
1013 * have h/w support for TSF adjusting; enable
1014 * use of staggered beacons.
1016 sc->sc_stagbeacons = 1;
1018 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1021 ic->ic_opmode = ic_opmode;
1022 if (opmode != IEEE80211_M_WDS) {
1024 if (opmode == IEEE80211_M_STA)
1026 if (opmode == IEEE80211_M_MBSS)
1029 switch (ic_opmode) {
1030 case IEEE80211_M_IBSS:
1031 sc->sc_opmode = HAL_M_IBSS;
1033 case IEEE80211_M_STA:
1034 sc->sc_opmode = HAL_M_STA;
1036 case IEEE80211_M_AHDEMO:
1037 #ifdef IEEE80211_SUPPORT_TDMA
1038 if (vap->iv_caps & IEEE80211_C_TDMA) {
1040 /* NB: disable tsf adjust */
1041 sc->sc_stagbeacons = 0;
1044 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1049 case IEEE80211_M_HOSTAP:
1050 case IEEE80211_M_MBSS:
1051 sc->sc_opmode = HAL_M_HOSTAP;
1053 case IEEE80211_M_MONITOR:
1054 sc->sc_opmode = HAL_M_MONITOR;
1057 /* XXX should not happen */
1060 if (sc->sc_hastsfadd) {
1062 * Configure whether or not TSF adjust should be done.
1064 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1066 if (flags & IEEE80211_CLONE_NOBEACONS) {
1068 * Enable s/w beacon miss handling.
1074 /* complete setup */
1075 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1078 reclaim_address(sc, mac);
1079 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1081 free(avp, M_80211_VAP);
1087 ath_vap_delete(struct ieee80211vap *vap)
1089 struct ieee80211com *ic = vap->iv_ic;
1090 struct ifnet *ifp = ic->ic_ifp;
1091 struct ath_softc *sc = ifp->if_softc;
1092 struct ath_hal *ah = sc->sc_ah;
1093 struct ath_vap *avp = ATH_VAP(vap);
1095 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1097 * Quiesce the hardware while we remove the vap. In
1098 * particular we need to reclaim all references to
1099 * the vap state by any frames pending on the tx queues.
1101 ath_hal_intrset(ah, 0); /* disable interrupts */
1102 ath_draintxq(sc); /* stop xmit side */
1103 ath_stoprecv(sc); /* stop recv side */
1106 ieee80211_vap_detach(vap);
1109 * Reclaim beacon state. Note this must be done before
1110 * the vap instance is reclaimed as we may have a reference
1111 * to it in the buffer for the beacon frame.
1113 if (avp->av_bcbuf != NULL) {
1114 if (avp->av_bslot != -1) {
1115 sc->sc_bslot[avp->av_bslot] = NULL;
1118 ath_beacon_return(sc, avp->av_bcbuf);
1119 avp->av_bcbuf = NULL;
1120 if (sc->sc_nbcnvaps == 0) {
1121 sc->sc_stagbeacons = 0;
1122 if (sc->sc_hastsfadd)
1123 ath_hal_settsfadjust(sc->sc_ah, 0);
1126 * Reclaim any pending mcast frames for the vap.
1128 ath_tx_draintxq(sc, &avp->av_mcastq);
1129 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq);
1132 * Update bookkeeping.
1134 if (vap->iv_opmode == IEEE80211_M_STA) {
1136 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1138 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1139 vap->iv_opmode == IEEE80211_M_MBSS) {
1140 reclaim_address(sc, vap->iv_myaddr);
1141 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1142 if (vap->iv_opmode == IEEE80211_M_MBSS)
1145 if (vap->iv_opmode != IEEE80211_M_WDS)
1147 #ifdef IEEE80211_SUPPORT_TDMA
1148 /* TDMA operation ceases when the last vap is destroyed */
1149 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1155 free(avp, M_80211_VAP);
1157 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1159 * Restart rx+tx machines if still running (RUNNING will
1160 * be reset if we just destroyed the last vap).
1162 if (ath_startrecv(sc) != 0)
1163 if_printf(ifp, "%s: unable to restart recv logic\n",
1165 if (sc->sc_beacons) { /* restart beacons */
1166 #ifdef IEEE80211_SUPPORT_TDMA
1168 ath_tdma_config(sc, NULL);
1171 ath_beacon_config(sc, NULL);
1173 ath_hal_intrset(ah, sc->sc_imask);
1178 ath_suspend(struct ath_softc *sc)
1180 struct ifnet *ifp = sc->sc_ifp;
1181 struct ieee80211com *ic = ifp->if_l2com;
1183 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1184 __func__, ifp->if_flags);
1186 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1187 if (ic->ic_opmode == IEEE80211_M_STA)
1190 ieee80211_suspend_all(ic);
1192 * NB: don't worry about putting the chip in low power
1193 * mode; pci will power off our socket on suspend and
1194 * cardbus detaches the device.
1199 * Reset the key cache since some parts do not reset the
1200 * contents on resume. First we clear all entries, then
1201 * re-load keys that the 802.11 layer assumes are setup
1205 ath_reset_keycache(struct ath_softc *sc)
1207 struct ifnet *ifp = sc->sc_ifp;
1208 struct ieee80211com *ic = ifp->if_l2com;
1209 struct ath_hal *ah = sc->sc_ah;
1212 for (i = 0; i < sc->sc_keymax; i++)
1213 ath_hal_keyreset(ah, i);
1214 ieee80211_crypto_reload_keys(ic);
1218 ath_resume(struct ath_softc *sc)
1220 struct ifnet *ifp = sc->sc_ifp;
1221 struct ieee80211com *ic = ifp->if_l2com;
1222 struct ath_hal *ah = sc->sc_ah;
1225 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1226 __func__, ifp->if_flags);
1229 * Must reset the chip before we reload the
1230 * keycache as we were powered down on suspend.
1232 ath_hal_reset(ah, sc->sc_opmode,
1233 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1235 ath_reset_keycache(sc);
1236 if (sc->sc_resume_up) {
1237 if (ic->ic_opmode == IEEE80211_M_STA) {
1240 * Program the beacon registers using the last rx'd
1241 * beacon frame and enable sync on the next beacon
1242 * we see. This should handle the case where we
1243 * wakeup and find the same AP and also the case where
1244 * we wakeup and need to roam. For the latter we
1245 * should get bmiss events that trigger a roam.
1247 ath_beacon_config(sc, NULL);
1248 sc->sc_syncbeacon = 1;
1250 ieee80211_resume_all(ic);
1252 if (sc->sc_softled) {
1253 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
1254 HAL_GPIO_MUX_MAC_NETWORK_LED);
1255 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
1260 ath_shutdown(struct ath_softc *sc)
1262 struct ifnet *ifp = sc->sc_ifp;
1264 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1265 __func__, ifp->if_flags);
1268 /* NB: no point powering down chip as we're about to reboot */
1272 * Interrupt handler. Most of the actual processing is deferred.
1277 struct ath_softc *sc = arg;
1278 struct ifnet *ifp = sc->sc_ifp;
1279 struct ath_hal *ah = sc->sc_ah;
1282 if (sc->sc_invalid) {
1284 * The hardware is not ready/present, don't touch anything.
1285 * Note this can happen early on if the IRQ is shared.
1287 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1290 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
1292 if ((ifp->if_flags & IFF_UP) == 0 ||
1293 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1296 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1297 __func__, ifp->if_flags);
1298 ath_hal_getisr(ah, &status); /* clear ISR */
1299 ath_hal_intrset(ah, 0); /* disable further intr's */
1303 * Figure out the reason(s) for the interrupt. Note
1304 * that the hal returns a pseudo-ISR that may include
1305 * bits we haven't explicitly enabled so we mask the
1306 * value to insure we only process bits we requested.
1308 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1309 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1310 status &= sc->sc_imask; /* discard unasked for bits */
1311 if (status & HAL_INT_FATAL) {
1312 sc->sc_stats.ast_hardware++;
1313 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1314 ath_fatal_proc(sc, 0);
1316 if (status & HAL_INT_SWBA) {
1318 * Software beacon alert--time to send a beacon.
1319 * Handle beacon transmission directly; deferring
1320 * this is too slow to meet timing constraints
1323 #ifdef IEEE80211_SUPPORT_TDMA
1325 if (sc->sc_tdmaswba == 0) {
1326 struct ieee80211com *ic = ifp->if_l2com;
1327 struct ieee80211vap *vap =
1328 TAILQ_FIRST(&ic->ic_vaps);
1329 ath_tdma_beacon_send(sc, vap);
1331 vap->iv_tdma->tdma_bintval;
1337 ath_beacon_proc(sc, 0);
1338 #ifdef IEEE80211_SUPPORT_SUPERG
1340 * Schedule the rx taskq in case there's no
1341 * traffic so any frames held on the staging
1342 * queue are aged and potentially flushed.
1344 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1348 if (status & HAL_INT_RXEOL) {
1350 * NB: the hardware should re-read the link when
1351 * RXE bit is written, but it doesn't work at
1352 * least on older hardware revs.
1354 sc->sc_stats.ast_rxeol++;
1355 sc->sc_rxlink = NULL;
1357 if (status & HAL_INT_TXURN) {
1358 sc->sc_stats.ast_txurn++;
1359 /* bump tx trigger level */
1360 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1362 if (status & HAL_INT_RX)
1363 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1364 if (status & HAL_INT_TX)
1365 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1366 if (status & HAL_INT_BMISS) {
1367 sc->sc_stats.ast_bmiss++;
1368 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1370 if (status & HAL_INT_MIB) {
1371 sc->sc_stats.ast_mib++;
1373 * Disable interrupts until we service the MIB
1374 * interrupt; otherwise it will continue to fire.
1376 ath_hal_intrset(ah, 0);
1378 * Let the hal handle the event. We assume it will
1379 * clear whatever condition caused the interrupt.
1381 ath_hal_mibevent(ah, &sc->sc_halstats);
1382 ath_hal_intrset(ah, sc->sc_imask);
1384 if (status & HAL_INT_RXORN) {
1385 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1386 sc->sc_stats.ast_rxorn++;
1392 ath_fatal_proc(void *arg, int pending)
1394 struct ath_softc *sc = arg;
1395 struct ifnet *ifp = sc->sc_ifp;
1400 if_printf(ifp, "hardware error; resetting\n");
1402 * Fatal errors are unrecoverable. Typically these
1403 * are caused by DMA errors. Collect h/w state from
1404 * the hal so we can diagnose what's going on.
1406 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1407 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1409 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1410 state[0], state[1] , state[2], state[3],
1411 state[4], state[5]);
1417 ath_bmiss_vap(struct ieee80211vap *vap)
1420 * Workaround phantom bmiss interrupts by sanity-checking
1421 * the time of our last rx'd frame. If it is within the
1422 * beacon miss interval then ignore the interrupt. If it's
1423 * truly a bmiss we'll get another interrupt soon and that'll
1424 * be dispatched up for processing. Note this applies only
1425 * for h/w beacon miss events.
1427 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1428 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1429 struct ath_softc *sc = ifp->if_softc;
1430 u_int64_t lastrx = sc->sc_lastrx;
1431 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1432 u_int bmisstimeout =
1433 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1435 DPRINTF(sc, ATH_DEBUG_BEACON,
1436 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1437 __func__, (unsigned long long) tsf,
1438 (unsigned long long)(tsf - lastrx),
1439 (unsigned long long) lastrx, bmisstimeout);
1441 if (tsf - lastrx <= bmisstimeout) {
1442 sc->sc_stats.ast_bmiss_phantom++;
1446 ATH_VAP(vap)->av_bmiss(vap);
1450 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1455 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(&mask), &sp, &rsize))
1457 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1458 *hangs = *(uint32_t *)sp;
1463 ath_bmiss_proc(void *arg, int pending)
1465 struct ath_softc *sc = arg;
1466 struct ifnet *ifp = sc->sc_ifp;
1469 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1471 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1472 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs);
1475 ieee80211_beacon_miss(ifp->if_l2com);
1479 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1480 * calcs together with WME. If necessary disable the crypto
1481 * hardware and mark the 802.11 state so keys will be setup
1482 * with the MIC work done in software.
1485 ath_settkipmic(struct ath_softc *sc)
1487 struct ifnet *ifp = sc->sc_ifp;
1488 struct ieee80211com *ic = ifp->if_l2com;
1490 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1491 if (ic->ic_flags & IEEE80211_F_WME) {
1492 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1493 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1495 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1496 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1504 struct ath_softc *sc = (struct ath_softc *) arg;
1505 struct ifnet *ifp = sc->sc_ifp;
1506 struct ieee80211com *ic = ifp->if_l2com;
1507 struct ath_hal *ah = sc->sc_ah;
1510 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1511 __func__, ifp->if_flags);
1515 * Stop anything previously setup. This is safe
1516 * whether this is the first time through or not.
1518 ath_stop_locked(ifp);
1521 * The basic interface to setting the hardware in a good
1522 * state is ``reset''. On return the hardware is known to
1523 * be powered up and with interrupts disabled. This must
1524 * be followed by initialization of the appropriate bits
1525 * and then setup of the interrupt mask.
1528 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
1529 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1534 ath_chan_change(sc, ic->ic_curchan);
1537 * Likewise this is set during reset so update
1538 * state cached in the driver.
1540 sc->sc_diversity = ath_hal_getdiversity(ah);
1541 sc->sc_lastlongcal = 0;
1542 sc->sc_resetcal = 1;
1543 sc->sc_lastcalreset = 0;
1546 * Setup the hardware after reset: the key cache
1547 * is filled as needed and the receive engine is
1548 * set going. Frame transmit is handled entirely
1549 * in the frame output path; there's nothing to do
1550 * here except setup the interrupt mask.
1552 if (ath_startrecv(sc) != 0) {
1553 if_printf(ifp, "unable to start recv logic\n");
1559 * Enable interrupts.
1561 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1562 | HAL_INT_RXEOL | HAL_INT_RXORN
1563 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1565 * Enable MIB interrupts when there are hardware phy counters.
1566 * Note we only do this (at the moment) for station mode.
1568 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1569 sc->sc_imask |= HAL_INT_MIB;
1571 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1572 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
1573 ath_hal_intrset(ah, sc->sc_imask);
1577 #ifdef ATH_TX99_DIAG
1578 if (sc->sc_tx99 != NULL)
1579 sc->sc_tx99->start(sc->sc_tx99);
1582 ieee80211_start_all(ic); /* start all vap's */
1586 ath_stop_locked(struct ifnet *ifp)
1588 struct ath_softc *sc = ifp->if_softc;
1589 struct ath_hal *ah = sc->sc_ah;
1591 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1592 __func__, sc->sc_invalid, ifp->if_flags);
1594 ATH_LOCK_ASSERT(sc);
1595 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1597 * Shutdown the hardware and driver:
1598 * reset 802.11 state machine
1600 * disable interrupts
1601 * turn off the radio
1602 * clear transmit machinery
1603 * clear receive machinery
1604 * drain and release tx queues
1605 * reclaim beacon resources
1606 * power down hardware
1608 * Note that some of this work is not possible if the
1609 * hardware is gone (invalid).
1611 #ifdef ATH_TX99_DIAG
1612 if (sc->sc_tx99 != NULL)
1613 sc->sc_tx99->stop(sc->sc_tx99);
1615 callout_stop(&sc->sc_wd_ch);
1616 sc->sc_wd_timer = 0;
1617 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1618 if (!sc->sc_invalid) {
1619 if (sc->sc_softled) {
1620 callout_stop(&sc->sc_ledtimer);
1621 ath_hal_gpioset(ah, sc->sc_ledpin,
1623 sc->sc_blinking = 0;
1625 ath_hal_intrset(ah, 0);
1628 if (!sc->sc_invalid) {
1630 ath_hal_phydisable(ah);
1632 sc->sc_rxlink = NULL;
1633 ath_beacon_free(sc); /* XXX not needed */
1638 ath_stop(struct ifnet *ifp)
1640 struct ath_softc *sc = ifp->if_softc;
1643 ath_stop_locked(ifp);
1648 * Reset the hardware w/o losing operational state. This is
1649 * basically a more efficient way of doing ath_stop, ath_init,
1650 * followed by state transitions to the current 802.11
1651 * operational state. Used to recover from various errors and
1652 * to reset or reload hardware state.
1655 ath_reset(struct ifnet *ifp)
1657 struct ath_softc *sc = ifp->if_softc;
1658 struct ieee80211com *ic = ifp->if_l2com;
1659 struct ath_hal *ah = sc->sc_ah;
1662 ath_hal_intrset(ah, 0); /* disable interrupts */
1663 ath_draintxq(sc); /* stop xmit side */
1664 ath_stoprecv(sc); /* stop recv side */
1665 ath_settkipmic(sc); /* configure TKIP MIC handling */
1666 /* NB: indicate channel change so we do a full reset */
1667 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
1668 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1670 sc->sc_diversity = ath_hal_getdiversity(ah);
1671 if (ath_startrecv(sc) != 0) /* restart recv */
1672 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1674 * We may be doing a reset in response to an ioctl
1675 * that changes the channel so update any state that
1676 * might change as a result.
1678 ath_chan_change(sc, ic->ic_curchan);
1679 if (sc->sc_beacons) { /* restart beacons */
1680 #ifdef IEEE80211_SUPPORT_TDMA
1682 ath_tdma_config(sc, NULL);
1685 ath_beacon_config(sc, NULL);
1687 ath_hal_intrset(ah, sc->sc_imask);
1689 ath_start(ifp); /* restart xmit */
1694 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
1696 struct ieee80211com *ic = vap->iv_ic;
1697 struct ifnet *ifp = ic->ic_ifp;
1698 struct ath_softc *sc = ifp->if_softc;
1699 struct ath_hal *ah = sc->sc_ah;
1702 case IEEE80211_IOC_TXPOWER:
1704 * If per-packet TPC is enabled, then we have nothing
1705 * to do; otherwise we need to force the global limit.
1706 * All this can happen directly; no need to reset.
1708 if (!ath_hal_gettpc(ah))
1709 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
1712 return ath_reset(ifp);
1715 static struct ath_buf *
1716 _ath_getbuf_locked(struct ath_softc *sc)
1720 ATH_TXBUF_LOCK_ASSERT(sc);
1722 bf = STAILQ_FIRST(&sc->sc_txbuf);
1723 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0)
1724 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1728 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
1729 STAILQ_FIRST(&sc->sc_txbuf) == NULL ?
1730 "out of xmit buffers" : "xmit buffer busy");
1735 static struct ath_buf *
1736 ath_getbuf(struct ath_softc *sc)
1741 bf = _ath_getbuf_locked(sc);
1743 struct ifnet *ifp = sc->sc_ifp;
1745 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
1746 sc->sc_stats.ast_tx_qstop++;
1747 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1749 ATH_TXBUF_UNLOCK(sc);
1754 * Cleanup driver resources when we run out of buffers
1755 * while processing fragments; return the tx buffers
1756 * allocated and drop node references.
1759 ath_txfrag_cleanup(struct ath_softc *sc,
1760 ath_bufhead *frags, struct ieee80211_node *ni)
1762 struct ath_buf *bf, *next;
1764 ATH_TXBUF_LOCK_ASSERT(sc);
1766 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
1767 /* NB: bf assumed clean */
1768 STAILQ_REMOVE_HEAD(frags, bf_list);
1769 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1770 ieee80211_node_decref(ni);
1775 * Setup xmit of a fragmented frame. Allocate a buffer
1776 * for each frag and bump the node reference count to
1777 * reflect the held reference to be setup by ath_tx_start.
1780 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
1781 struct mbuf *m0, struct ieee80211_node *ni)
1787 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
1788 bf = _ath_getbuf_locked(sc);
1789 if (bf == NULL) { /* out of buffers, cleanup */
1790 ath_txfrag_cleanup(sc, frags, ni);
1793 ieee80211_node_incref(ni);
1794 STAILQ_INSERT_TAIL(frags, bf, bf_list);
1796 ATH_TXBUF_UNLOCK(sc);
1798 return !STAILQ_EMPTY(frags);
1802 ath_start(struct ifnet *ifp)
1804 struct ath_softc *sc = ifp->if_softc;
1805 struct ieee80211_node *ni;
1807 struct mbuf *m, *next;
1810 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1814 * Grab a TX buffer and associated resources.
1816 bf = ath_getbuf(sc);
1820 IFQ_DEQUEUE(&ifp->if_snd, m);
1823 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1824 ATH_TXBUF_UNLOCK(sc);
1827 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1829 * Check for fragmentation. If this frame
1830 * has been broken up verify we have enough
1831 * buffers to send all the fragments so all
1834 STAILQ_INIT(&frags);
1835 if ((m->m_flags & M_FRAG) &&
1836 !ath_txfrag_setup(sc, &frags, m, ni)) {
1837 DPRINTF(sc, ATH_DEBUG_XMIT,
1838 "%s: out of txfrag buffers\n", __func__);
1839 sc->sc_stats.ast_tx_nofrag++;
1847 * Pass the frame to the h/w for transmission.
1848 * Fragmented frames have each frag chained together
1849 * with m_nextpkt. We know there are sufficient ath_buf's
1850 * to send all the frags because of work done by
1851 * ath_txfrag_setup. We leave m_nextpkt set while
1852 * calling ath_tx_start so it can use it to extend the
1853 * the tx duration to cover the subsequent frag and
1854 * so it can reclaim all the mbufs in case of an error;
1855 * ath_tx_start clears m_nextpkt once it commits to
1856 * handing the frame to the hardware.
1858 next = m->m_nextpkt;
1859 if (ath_tx_start(sc, ni, bf, m)) {
1866 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1867 ath_txfrag_cleanup(sc, &frags, ni);
1868 ATH_TXBUF_UNLOCK(sc);
1870 ieee80211_free_node(ni);
1875 * Beware of state changing between frags.
1876 * XXX check sta power-save state?
1878 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
1879 DPRINTF(sc, ATH_DEBUG_XMIT,
1880 "%s: flush fragmented packet, state %s\n",
1882 ieee80211_state_name[ni->ni_vap->iv_state]);
1887 bf = STAILQ_FIRST(&frags);
1888 KASSERT(bf != NULL, ("no buf for txfrag"));
1889 STAILQ_REMOVE_HEAD(&frags, bf_list);
1893 sc->sc_wd_timer = 5;
1898 ath_media_change(struct ifnet *ifp)
1900 int error = ieee80211_media_change(ifp);
1901 /* NB: only the fixed rate can change and that doesn't need a reset */
1902 return (error == ENETRESET ? 0 : error);
1907 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix,
1908 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1910 static const char *ciphers[] = {
1920 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1921 for (i = 0, n = hk->kv_len; i < n; i++)
1922 printf("%02x", hk->kv_val[i]);
1923 printf(" mac %s", ether_sprintf(mac));
1924 if (hk->kv_type == HAL_CIPHER_TKIP) {
1925 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic");
1926 for (i = 0; i < sizeof(hk->kv_mic); i++)
1927 printf("%02x", hk->kv_mic[i]);
1928 if (!sc->sc_splitmic) {
1930 for (i = 0; i < sizeof(hk->kv_txmic); i++)
1931 printf("%02x", hk->kv_txmic[i]);
1939 * Set a TKIP key into the hardware. This handles the
1940 * potential distribution of key state to multiple key
1941 * cache slots for TKIP.
1944 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1945 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1947 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1948 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1949 struct ath_hal *ah = sc->sc_ah;
1951 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1952 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1953 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1954 if (sc->sc_splitmic) {
1956 * TX key goes at first index, RX key at the rx index.
1957 * The hal handles the MIC keys at index+64.
1959 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1960 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1961 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1964 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1965 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1966 /* XXX delete tx key on failure? */
1967 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1970 * Room for both TX+RX MIC keys in one key cache
1971 * slot, just set key at the first index; the hal
1972 * will handle the rest.
1974 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1975 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1976 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1977 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1979 } else if (k->wk_flags & IEEE80211_KEY_XMIT) {
1980 if (sc->sc_splitmic) {
1982 * NB: must pass MIC key in expected location when
1983 * the keycache only holds one MIC key per entry.
1985 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic));
1987 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1988 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1989 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1990 } else if (k->wk_flags & IEEE80211_KEY_RECV) {
1991 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1992 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1993 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1996 #undef IEEE80211_KEY_XR
2000 * Set a net80211 key into the hardware. This handles the
2001 * potential distribution of key state to multiple key
2002 * cache slots for TKIP with hardware MIC support.
2005 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
2006 struct ieee80211_node *bss)
2008 #define N(a) (sizeof(a)/sizeof(a[0]))
2009 static const u_int8_t ciphermap[] = {
2010 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
2011 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
2012 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
2013 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
2014 (u_int8_t) -1, /* 4 is not allocated */
2015 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
2016 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
2018 struct ath_hal *ah = sc->sc_ah;
2019 const struct ieee80211_cipher *cip = k->wk_cipher;
2020 u_int8_t gmac[IEEE80211_ADDR_LEN];
2021 const u_int8_t *mac;
2024 memset(&hk, 0, sizeof(hk));
2026 * Software crypto uses a "clear key" so non-crypto
2027 * state kept in the key cache are maintained and
2028 * so that rx frames have an entry to match.
2030 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
2031 KASSERT(cip->ic_cipher < N(ciphermap),
2032 ("invalid cipher type %u", cip->ic_cipher));
2033 hk.kv_type = ciphermap[cip->ic_cipher];
2034 hk.kv_len = k->wk_keylen;
2035 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
2037 hk.kv_type = HAL_CIPHER_CLR;
2039 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
2041 * Group keys on hardware that supports multicast frame
2042 * key search use a mac that is the sender's address with
2043 * the high bit set instead of the app-specified address.
2045 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
2049 mac = k->wk_macaddr;
2051 if (hk.kv_type == HAL_CIPHER_TKIP &&
2052 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2053 return ath_keyset_tkip(sc, k, &hk, mac);
2055 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
2056 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
2062 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2063 * each key, one for decrypt/encrypt and the other for the MIC.
2066 key_alloc_2pair(struct ath_softc *sc,
2067 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2069 #define N(a) (sizeof(a)/sizeof(a[0]))
2072 KASSERT(sc->sc_splitmic, ("key cache !split"));
2073 /* XXX could optimize */
2074 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2075 u_int8_t b = sc->sc_keymap[i];
2078 * One or more slots in this byte are free.
2086 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
2087 if (isset(sc->sc_keymap, keyix+32) ||
2088 isset(sc->sc_keymap, keyix+64) ||
2089 isset(sc->sc_keymap, keyix+32+64)) {
2090 /* full pair unavailable */
2092 if (keyix == (i+1)*NBBY) {
2093 /* no slots were appropriate, advance */
2098 setbit(sc->sc_keymap, keyix);
2099 setbit(sc->sc_keymap, keyix+64);
2100 setbit(sc->sc_keymap, keyix+32);
2101 setbit(sc->sc_keymap, keyix+32+64);
2102 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2103 "%s: key pair %u,%u %u,%u\n",
2104 __func__, keyix, keyix+64,
2105 keyix+32, keyix+32+64);
2107 *rxkeyix = keyix+32;
2111 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2117 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2118 * each key, one for decrypt/encrypt and the other for the MIC.
2121 key_alloc_pair(struct ath_softc *sc,
2122 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2124 #define N(a) (sizeof(a)/sizeof(a[0]))
2127 KASSERT(!sc->sc_splitmic, ("key cache split"));
2128 /* XXX could optimize */
2129 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2130 u_int8_t b = sc->sc_keymap[i];
2133 * One or more slots in this byte are free.
2141 if (isset(sc->sc_keymap, keyix+64)) {
2142 /* full pair unavailable */
2144 if (keyix == (i+1)*NBBY) {
2145 /* no slots were appropriate, advance */
2150 setbit(sc->sc_keymap, keyix);
2151 setbit(sc->sc_keymap, keyix+64);
2152 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2153 "%s: key pair %u,%u\n",
2154 __func__, keyix, keyix+64);
2155 *txkeyix = *rxkeyix = keyix;
2159 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2165 * Allocate a single key cache slot.
2168 key_alloc_single(struct ath_softc *sc,
2169 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2171 #define N(a) (sizeof(a)/sizeof(a[0]))
2174 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
2175 for (i = 0; i < N(sc->sc_keymap); i++) {
2176 u_int8_t b = sc->sc_keymap[i];
2179 * One or more slots are free.
2184 setbit(sc->sc_keymap, keyix);
2185 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
2187 *txkeyix = *rxkeyix = keyix;
2191 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
2197 * Allocate one or more key cache slots for a uniacst key. The
2198 * key itself is needed only to identify the cipher. For hardware
2199 * TKIP with split cipher+MIC keys we allocate two key cache slot
2200 * pairs so that we can setup separate TX and RX MIC keys. Note
2201 * that the MIC key for a TKIP key at slot i is assumed by the
2202 * hardware to be at slot i+64. This limits TKIP keys to the first
2206 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
2207 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2209 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2212 * Group key allocation must be handled specially for
2213 * parts that do not support multicast key cache search
2214 * functionality. For those parts the key id must match
2215 * the h/w key index so lookups find the right key. On
2216 * parts w/ the key search facility we install the sender's
2217 * mac address (with the high bit set) and let the hardware
2218 * find the key w/o using the key id. This is preferred as
2219 * it permits us to support multiple users for adhoc and/or
2220 * multi-station operation.
2222 if (k->wk_keyix != IEEE80211_KEYIX_NONE || /* global key */
2223 ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey)) {
2224 if (!(&vap->iv_nw_keys[0] <= k &&
2225 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
2226 /* should not happen */
2227 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2228 "%s: bogus group key\n", __func__);
2232 * XXX we pre-allocate the global keys so
2233 * have no way to check if they've already been allocated.
2235 *keyix = *rxkeyix = k - vap->iv_nw_keys;
2240 * We allocate two pair for TKIP when using the h/w to do
2241 * the MIC. For everything else, including software crypto,
2242 * we allocate a single entry. Note that s/w crypto requires
2243 * a pass-through slot on the 5211 and 5212. The 5210 does
2244 * not support pass-through cache entries and we map all
2245 * those requests to slot 0.
2247 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2248 return key_alloc_single(sc, keyix, rxkeyix);
2249 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
2250 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2251 if (sc->sc_splitmic)
2252 return key_alloc_2pair(sc, keyix, rxkeyix);
2254 return key_alloc_pair(sc, keyix, rxkeyix);
2256 return key_alloc_single(sc, keyix, rxkeyix);
2261 * Delete an entry in the key cache allocated by ath_key_alloc.
2264 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k)
2266 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2267 struct ath_hal *ah = sc->sc_ah;
2268 const struct ieee80211_cipher *cip = k->wk_cipher;
2269 u_int keyix = k->wk_keyix;
2271 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
2273 ath_hal_keyreset(ah, keyix);
2275 * Handle split tx/rx keying required for TKIP with h/w MIC.
2277 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2278 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
2279 ath_hal_keyreset(ah, keyix+32); /* RX key */
2280 if (keyix >= IEEE80211_WEP_NKID) {
2282 * Don't touch keymap entries for global keys so
2283 * they are never considered for dynamic allocation.
2285 clrbit(sc->sc_keymap, keyix);
2286 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2287 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2288 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
2289 if (sc->sc_splitmic) {
2290 /* +32 for RX key, +32+64 for RX key MIC */
2291 clrbit(sc->sc_keymap, keyix+32);
2292 clrbit(sc->sc_keymap, keyix+32+64);
2300 * Set the key cache contents for the specified key. Key cache
2301 * slot(s) must already have been allocated by ath_key_alloc.
2304 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k,
2305 const u_int8_t mac[IEEE80211_ADDR_LEN])
2307 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2309 return ath_keyset(sc, k, vap->iv_bss);
2313 * Block/unblock tx+rx processing while a key change is done.
2314 * We assume the caller serializes key management operations
2315 * so we only need to worry about synchronization with other
2316 * uses that originate in the driver.
2319 ath_key_update_begin(struct ieee80211vap *vap)
2321 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2322 struct ath_softc *sc = ifp->if_softc;
2324 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2325 taskqueue_block(sc->sc_tq);
2326 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2330 ath_key_update_end(struct ieee80211vap *vap)
2332 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2333 struct ath_softc *sc = ifp->if_softc;
2335 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2336 IF_UNLOCK(&ifp->if_snd);
2337 taskqueue_unblock(sc->sc_tq);
2341 * Calculate the receive filter according to the
2342 * operating mode and state:
2344 * o always accept unicast, broadcast, and multicast traffic
2345 * o accept PHY error frames when hardware doesn't have MIB support
2346 * to count and we need them for ANI (sta mode only until recently)
2347 * and we are not scanning (ANI is disabled)
2348 * NB: older hal's add rx filter bits out of sight and we need to
2349 * blindly preserve them
2350 * o probe request frames are accepted only when operating in
2351 * hostap, adhoc, mesh, or monitor modes
2352 * o enable promiscuous mode
2353 * - when in monitor mode
2354 * - if interface marked PROMISC (assumes bridge setting is filtered)
2356 * - when operating in station mode for collecting rssi data when
2357 * the station is otherwise quiet, or
2358 * - when operating in adhoc mode so the 802.11 layer creates
2359 * node table entries for peers,
2361 * - when doing s/w beacon miss (e.g. for ap+sta)
2362 * - when operating in ap mode in 11g to detect overlapping bss that
2363 * require protection
2364 * - when operating in mesh mode to detect neighbors
2365 * o accept control frames:
2366 * - when in monitor mode
2367 * XXX BAR frames for 11n
2368 * XXX HT protection for 11n
2371 ath_calcrxfilter(struct ath_softc *sc)
2373 struct ifnet *ifp = sc->sc_ifp;
2374 struct ieee80211com *ic = ifp->if_l2com;
2377 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
2378 if (!sc->sc_needmib && !sc->sc_scanning)
2379 rfilt |= HAL_RX_FILTER_PHYERR;
2380 if (ic->ic_opmode != IEEE80211_M_STA)
2381 rfilt |= HAL_RX_FILTER_PROBEREQ;
2382 /* XXX ic->ic_monvaps != 0? */
2383 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
2384 rfilt |= HAL_RX_FILTER_PROM;
2385 if (ic->ic_opmode == IEEE80211_M_STA ||
2386 ic->ic_opmode == IEEE80211_M_IBSS ||
2387 sc->sc_swbmiss || sc->sc_scanning)
2388 rfilt |= HAL_RX_FILTER_BEACON;
2390 * NB: We don't recalculate the rx filter when
2391 * ic_protmode changes; otherwise we could do
2392 * this only when ic_protmode != NONE.
2394 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
2395 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
2396 rfilt |= HAL_RX_FILTER_BEACON;
2397 if (sc->sc_nmeshvaps) {
2398 rfilt |= HAL_RX_FILTER_BEACON;
2399 if (sc->sc_hasbmatch)
2400 rfilt |= HAL_RX_FILTER_BSSID;
2402 rfilt |= HAL_RX_FILTER_PROM;
2404 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2405 rfilt |= HAL_RX_FILTER_CONTROL;
2406 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
2407 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
2412 ath_update_promisc(struct ifnet *ifp)
2414 struct ath_softc *sc = ifp->if_softc;
2417 /* configure rx filter */
2418 rfilt = ath_calcrxfilter(sc);
2419 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2421 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2425 ath_update_mcast(struct ifnet *ifp)
2427 struct ath_softc *sc = ifp->if_softc;
2430 /* calculate and install multicast filter */
2431 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2432 struct ifmultiaddr *ifma;
2434 * Merge multicast addresses to form the hardware filter.
2436 mfilt[0] = mfilt[1] = 0;
2437 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2438 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2443 /* calculate XOR of eight 6bit values */
2444 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2445 val = LE_READ_4(dl + 0);
2446 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2447 val = LE_READ_4(dl + 3);
2448 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2450 mfilt[pos / 32] |= (1 << (pos % 32));
2452 if_maddr_runlock(ifp);
2454 mfilt[0] = mfilt[1] = ~0;
2455 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2456 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2457 __func__, mfilt[0], mfilt[1]);
2461 ath_mode_init(struct ath_softc *sc)
2463 struct ifnet *ifp = sc->sc_ifp;
2464 struct ath_hal *ah = sc->sc_ah;
2467 /* configure rx filter */
2468 rfilt = ath_calcrxfilter(sc);
2469 ath_hal_setrxfilter(ah, rfilt);
2471 /* configure operational mode */
2472 ath_hal_setopmode(ah);
2474 /* handle any link-level address change */
2475 ath_hal_setmac(ah, IF_LLADDR(ifp));
2477 /* calculate and install multicast filter */
2478 ath_update_mcast(ifp);
2482 * Set the slot time based on the current setting.
2485 ath_setslottime(struct ath_softc *sc)
2487 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2488 struct ath_hal *ah = sc->sc_ah;
2491 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
2493 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
2495 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
2496 /* honor short/long slot time only in 11g */
2497 /* XXX shouldn't honor on pure g or turbo g channel */
2498 if (ic->ic_flags & IEEE80211_F_SHSLOT)
2499 usec = HAL_SLOT_TIME_9;
2501 usec = HAL_SLOT_TIME_20;
2503 usec = HAL_SLOT_TIME_9;
2505 DPRINTF(sc, ATH_DEBUG_RESET,
2506 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
2507 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
2508 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
2510 ath_hal_setslottime(ah, usec);
2511 sc->sc_updateslot = OK;
2515 * Callback from the 802.11 layer to update the
2516 * slot time based on the current setting.
2519 ath_updateslot(struct ifnet *ifp)
2521 struct ath_softc *sc = ifp->if_softc;
2522 struct ieee80211com *ic = ifp->if_l2com;
2525 * When not coordinating the BSS, change the hardware
2526 * immediately. For other operation we defer the change
2527 * until beacon updates have propagated to the stations.
2529 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2530 ic->ic_opmode == IEEE80211_M_MBSS)
2531 sc->sc_updateslot = UPDATE;
2533 ath_setslottime(sc);
2537 * Setup a h/w transmit queue for beacons.
2540 ath_beaconq_setup(struct ath_hal *ah)
2544 memset(&qi, 0, sizeof(qi));
2545 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2546 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2547 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2548 /* NB: for dynamic turbo, don't enable any other interrupts */
2549 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
2550 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
2554 * Setup the transmit queue parameters for the beacon queue.
2557 ath_beaconq_config(struct ath_softc *sc)
2559 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
2560 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2561 struct ath_hal *ah = sc->sc_ah;
2564 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
2565 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2566 ic->ic_opmode == IEEE80211_M_MBSS) {
2568 * Always burst out beacon and CAB traffic.
2570 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
2571 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
2572 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
2574 struct wmeParams *wmep =
2575 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
2577 * Adhoc mode; important thing is to use 2x cwmin.
2579 qi.tqi_aifs = wmep->wmep_aifsn;
2580 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
2581 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
2584 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
2585 device_printf(sc->sc_dev, "unable to update parameters for "
2586 "beacon hardware queue!\n");
2589 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
2592 #undef ATH_EXPONENT_TO_VALUE
2596 * Allocate and setup an initial beacon frame.
2599 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
2601 struct ieee80211vap *vap = ni->ni_vap;
2602 struct ath_vap *avp = ATH_VAP(vap);
2608 if (bf->bf_m != NULL) {
2609 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2613 if (bf->bf_node != NULL) {
2614 ieee80211_free_node(bf->bf_node);
2619 * NB: the beacon data buffer must be 32-bit aligned;
2620 * we assume the mbuf routines will return us something
2621 * with this alignment (perhaps should assert).
2623 m = ieee80211_beacon_alloc(ni, &avp->av_boff);
2625 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
2626 sc->sc_stats.ast_be_nombuf++;
2629 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2630 bf->bf_segs, &bf->bf_nseg,
2633 device_printf(sc->sc_dev,
2634 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
2641 * Calculate a TSF adjustment factor required for staggered
2642 * beacons. Note that we assume the format of the beacon
2643 * frame leaves the tstamp field immediately following the
2646 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
2648 struct ieee80211_frame *wh;
2651 * The beacon interval is in TU's; the TSF is in usecs.
2652 * We figure out how many TU's to add to align the timestamp
2653 * then convert to TSF units and handle byte swapping before
2654 * inserting it in the frame. The hardware will then add this
2655 * each time a beacon frame is sent. Note that we align vap's
2656 * 1..N and leave vap 0 untouched. This means vap 0 has a
2657 * timestamp in one beacon interval while the others get a
2658 * timstamp aligned to the next interval.
2660 tsfadjust = ni->ni_intval *
2661 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
2662 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
2664 DPRINTF(sc, ATH_DEBUG_BEACON,
2665 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
2666 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
2667 avp->av_bslot, ni->ni_intval,
2668 (long long unsigned) le64toh(tsfadjust));
2670 wh = mtod(m, struct ieee80211_frame *);
2671 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
2674 bf->bf_node = ieee80211_ref_node(ni);
2680 * Setup the beacon frame for transmit.
2683 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2685 #define USE_SHPREAMBLE(_ic) \
2686 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2687 == IEEE80211_F_SHPREAMBLE)
2688 struct ieee80211_node *ni = bf->bf_node;
2689 struct ieee80211com *ic = ni->ni_ic;
2690 struct mbuf *m = bf->bf_m;
2691 struct ath_hal *ah = sc->sc_ah;
2692 struct ath_desc *ds;
2694 const HAL_RATE_TABLE *rt;
2697 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2698 __func__, m, m->m_len);
2700 /* setup descriptors */
2703 flags = HAL_TXDESC_NOACK;
2704 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2705 ds->ds_link = bf->bf_daddr; /* self-linked */
2706 flags |= HAL_TXDESC_VEOL;
2708 * Let hardware handle antenna switching.
2710 antenna = sc->sc_txantenna;
2714 * Switch antenna every 4 beacons.
2715 * XXX assumes two antenna
2717 if (sc->sc_txantenna != 0)
2718 antenna = sc->sc_txantenna;
2719 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
2720 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
2722 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2725 KASSERT(bf->bf_nseg == 1,
2726 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2727 ds->ds_data = bf->bf_segs[0].ds_addr;
2729 * Calculate rate code.
2730 * XXX everything at min xmit rate
2733 rt = sc->sc_currates;
2734 rate = rt->info[rix].rateCode;
2735 if (USE_SHPREAMBLE(ic))
2736 rate |= rt->info[rix].shortPreamble;
2737 ath_hal_setuptxdesc(ah, ds
2738 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2739 , sizeof(struct ieee80211_frame)/* header length */
2740 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2741 , ni->ni_txpower /* txpower XXX */
2742 , rate, 1 /* series 0 rate/tries */
2743 , HAL_TXKEYIX_INVALID /* no encryption */
2744 , antenna /* antenna mode */
2745 , flags /* no ack, veol for beacons */
2746 , 0 /* rts/cts rate */
2747 , 0 /* rts/cts duration */
2749 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2750 ath_hal_filltxdesc(ah, ds
2751 , roundup(m->m_len, 4) /* buffer length */
2752 , AH_TRUE /* first segment */
2753 , AH_TRUE /* last segment */
2754 , ds /* first descriptor */
2759 #undef USE_SHPREAMBLE
2763 ath_beacon_update(struct ieee80211vap *vap, int item)
2765 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
2767 setbit(bo->bo_flags, item);
2771 * Append the contents of src to dst; both queues
2772 * are assumed to be locked.
2775 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2777 STAILQ_CONCAT(&dst->axq_q, &src->axq_q);
2778 dst->axq_link = src->axq_link;
2779 src->axq_link = NULL;
2780 dst->axq_depth += src->axq_depth;
2785 * Transmit a beacon frame at SWBA. Dynamic updates to the
2786 * frame contents are done as needed and the slot time is
2787 * also adjusted based on current state.
2790 ath_beacon_proc(void *arg, int pending)
2792 struct ath_softc *sc = arg;
2793 struct ath_hal *ah = sc->sc_ah;
2794 struct ieee80211vap *vap;
2799 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
2802 * Check if the previous beacon has gone out. If
2803 * not don't try to post another, skip this period
2804 * and wait for the next. Missed beacons indicate
2805 * a problem and should not occur. If we miss too
2806 * many consecutive beacons reset the device.
2808 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2809 sc->sc_bmisscount++;
2810 DPRINTF(sc, ATH_DEBUG_BEACON,
2811 "%s: missed %u consecutive beacons\n",
2812 __func__, sc->sc_bmisscount);
2813 if (sc->sc_bmisscount >= ath_bstuck_threshold)
2814 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
2817 if (sc->sc_bmisscount != 0) {
2818 DPRINTF(sc, ATH_DEBUG_BEACON,
2819 "%s: resume beacon xmit after %u misses\n",
2820 __func__, sc->sc_bmisscount);
2821 sc->sc_bmisscount = 0;
2824 if (sc->sc_stagbeacons) { /* staggered beacons */
2825 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2828 tsftu = ath_hal_gettsf32(ah) >> 10;
2830 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
2831 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
2833 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
2834 bf = ath_beacon_generate(sc, vap);
2836 bfaddr = bf->bf_daddr;
2838 } else { /* burst'd beacons */
2839 uint32_t *bflink = &bfaddr;
2841 for (slot = 0; slot < ATH_BCBUF; slot++) {
2842 vap = sc->sc_bslot[slot];
2843 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
2844 bf = ath_beacon_generate(sc, vap);
2846 *bflink = bf->bf_daddr;
2847 bflink = &bf->bf_desc->ds_link;
2851 *bflink = 0; /* terminate list */
2855 * Handle slot time change when a non-ERP station joins/leaves
2856 * an 11g network. The 802.11 layer notifies us via callback,
2857 * we mark updateslot, then wait one beacon before effecting
2858 * the change. This gives associated stations at least one
2859 * beacon interval to note the state change.
2862 if (sc->sc_updateslot == UPDATE) {
2863 sc->sc_updateslot = COMMIT; /* commit next beacon */
2864 sc->sc_slotupdate = slot;
2865 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
2866 ath_setslottime(sc); /* commit change to h/w */
2869 * Check recent per-antenna transmit statistics and flip
2870 * the default antenna if noticeably more frames went out
2871 * on the non-default antenna.
2872 * XXX assumes 2 anntenae
2874 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
2875 otherant = sc->sc_defant & 1 ? 2 : 1;
2876 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2877 ath_setdefantenna(sc, otherant);
2878 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2883 * Stop any current dma and put the new frame on the queue.
2884 * This should never fail since we check above that no frames
2885 * are still pending on the queue.
2887 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2888 DPRINTF(sc, ATH_DEBUG_ANY,
2889 "%s: beacon queue %u did not stop?\n",
2890 __func__, sc->sc_bhalq);
2892 /* NB: cabq traffic should already be queued and primed */
2893 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
2894 ath_hal_txstart(ah, sc->sc_bhalq);
2896 sc->sc_stats.ast_be_xmit++;
2900 static struct ath_buf *
2901 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
2903 struct ath_vap *avp = ATH_VAP(vap);
2904 struct ath_txq *cabq = sc->sc_cabq;
2909 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
2910 ("not running, state %d", vap->iv_state));
2911 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
2914 * Update dynamic beacon contents. If this returns
2915 * non-zero then we need to remap the memory because
2916 * the beacon frame changed size (probably because
2917 * of the TIM bitmap).
2921 nmcastq = avp->av_mcastq.axq_depth;
2922 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
2923 /* XXX too conservative? */
2924 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2925 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2926 bf->bf_segs, &bf->bf_nseg,
2929 if_printf(vap->iv_ifp,
2930 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
2935 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
2936 DPRINTF(sc, ATH_DEBUG_BEACON,
2937 "%s: cabq did not drain, mcastq %u cabq %u\n",
2938 __func__, nmcastq, cabq->axq_depth);
2939 sc->sc_stats.ast_cabq_busy++;
2940 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
2942 * CABQ traffic from a previous vap is still pending.
2943 * We must drain the q before this beacon frame goes
2944 * out as otherwise this vap's stations will get cab
2945 * frames from a different vap.
2946 * XXX could be slow causing us to miss DBA
2948 ath_tx_draintxq(sc, cabq);
2951 ath_beacon_setup(sc, bf);
2952 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2955 * Enable the CAB queue before the beacon queue to
2956 * insure cab frames are triggered by this beacon.
2958 if (avp->av_boff.bo_tim[4] & 1) {
2959 struct ath_hal *ah = sc->sc_ah;
2961 /* NB: only at DTIM */
2963 ATH_TXQ_LOCK(&avp->av_mcastq);
2965 struct ath_buf *bfm;
2968 * Move frames from the s/w mcast q to the h/w cab q.
2971 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q);
2972 if (cabq->axq_link != NULL) {
2973 *cabq->axq_link = bfm->bf_daddr;
2975 ath_hal_puttxbuf(ah, cabq->axq_qnum,
2977 ath_txqmove(cabq, &avp->av_mcastq);
2979 sc->sc_stats.ast_cabq_xmit += nmcastq;
2981 /* NB: gated by beacon so safe to start here */
2982 ath_hal_txstart(ah, cabq->axq_qnum);
2983 ATH_TXQ_UNLOCK(cabq);
2984 ATH_TXQ_UNLOCK(&avp->av_mcastq);
2990 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
2992 struct ath_vap *avp = ATH_VAP(vap);
2993 struct ath_hal *ah = sc->sc_ah;
2998 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3001 * Update dynamic beacon contents. If this returns
3002 * non-zero then we need to remap the memory because
3003 * the beacon frame changed size (probably because
3004 * of the TIM bitmap).
3008 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
3009 /* XXX too conservative? */
3010 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3011 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3012 bf->bf_segs, &bf->bf_nseg,
3015 if_printf(vap->iv_ifp,
3016 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3021 ath_beacon_setup(sc, bf);
3022 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3024 /* NB: caller is known to have already stopped tx dma */
3025 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
3026 ath_hal_txstart(ah, sc->sc_bhalq);
3030 * Reset the hardware after detecting beacons have stopped.
3033 ath_bstuck_proc(void *arg, int pending)
3035 struct ath_softc *sc = arg;
3036 struct ifnet *ifp = sc->sc_ifp;
3038 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3040 sc->sc_stats.ast_bstuck++;
3045 * Reclaim beacon resources and return buffer to the pool.
3048 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
3051 if (bf->bf_m != NULL) {
3052 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3056 if (bf->bf_node != NULL) {
3057 ieee80211_free_node(bf->bf_node);
3060 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
3064 * Reclaim beacon resources.
3067 ath_beacon_free(struct ath_softc *sc)
3071 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
3072 if (bf->bf_m != NULL) {
3073 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3077 if (bf->bf_node != NULL) {
3078 ieee80211_free_node(bf->bf_node);
3085 * Configure the beacon and sleep timers.
3087 * When operating as an AP this resets the TSF and sets
3088 * up the hardware to notify us when we need to issue beacons.
3090 * When operating in station mode this sets up the beacon
3091 * timers according to the timestamp of the last received
3092 * beacon and the current TSF, configures PCF and DTIM
3093 * handling, programs the sleep registers so the hardware
3094 * will wakeup in time to receive beacons, and configures
3095 * the beacon miss handling so we'll receive a BMISS
3096 * interrupt when we stop seeing beacons from the AP
3097 * we've associated with.
3100 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
3102 #define TSF_TO_TU(_h,_l) \
3103 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
3105 struct ath_hal *ah = sc->sc_ah;
3106 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3107 struct ieee80211_node *ni;
3108 u_int32_t nexttbtt, intval, tsftu;
3112 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
3115 /* extract tstamp from last beacon and convert to TU */
3116 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
3117 LE_READ_4(ni->ni_tstamp.data));
3118 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3119 ic->ic_opmode == IEEE80211_M_MBSS) {
3121 * For multi-bss ap/mesh support beacons are either staggered
3122 * evenly over N slots or burst together. For the former
3123 * arrange for the SWBA to be delivered for each slot.
3124 * Slots that are not occupied will generate nothing.
3126 /* NB: the beacon interval is kept internally in TU's */
3127 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3128 if (sc->sc_stagbeacons)
3129 intval /= ATH_BCBUF;
3131 /* NB: the beacon interval is kept internally in TU's */
3132 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3134 if (nexttbtt == 0) /* e.g. for ap mode */
3136 else if (intval) /* NB: can be 0 for monitor mode */
3137 nexttbtt = roundup(nexttbtt, intval);
3138 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
3139 __func__, nexttbtt, intval, ni->ni_intval);
3140 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
3141 HAL_BEACON_STATE bs;
3142 int dtimperiod, dtimcount;
3143 int cfpperiod, cfpcount;
3146 * Setup dtim and cfp parameters according to
3147 * last beacon we received (which may be none).
3149 dtimperiod = ni->ni_dtim_period;
3150 if (dtimperiod <= 0) /* NB: 0 if not known */
3152 dtimcount = ni->ni_dtim_count;
3153 if (dtimcount >= dtimperiod) /* NB: sanity check */
3154 dtimcount = 0; /* XXX? */
3155 cfpperiod = 1; /* NB: no PCF support yet */
3158 * Pull nexttbtt forward to reflect the current
3159 * TSF and calculate dtim+cfp state for the result.
3161 tsf = ath_hal_gettsf64(ah);
3162 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3165 if (--dtimcount < 0) {
3166 dtimcount = dtimperiod - 1;
3168 cfpcount = cfpperiod - 1;
3170 } while (nexttbtt < tsftu);
3171 memset(&bs, 0, sizeof(bs));
3172 bs.bs_intval = intval;
3173 bs.bs_nexttbtt = nexttbtt;
3174 bs.bs_dtimperiod = dtimperiod*intval;
3175 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
3176 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
3177 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
3178 bs.bs_cfpmaxduration = 0;
3181 * The 802.11 layer records the offset to the DTIM
3182 * bitmap while receiving beacons; use it here to
3183 * enable h/w detection of our AID being marked in
3184 * the bitmap vector (to indicate frames for us are
3185 * pending at the AP).
3186 * XXX do DTIM handling in s/w to WAR old h/w bugs
3187 * XXX enable based on h/w rev for newer chips
3189 bs.bs_timoffset = ni->ni_timoff;
3192 * Calculate the number of consecutive beacons to miss
3193 * before taking a BMISS interrupt.
3194 * Note that we clamp the result to at most 10 beacons.
3196 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
3197 if (bs.bs_bmissthreshold > 10)
3198 bs.bs_bmissthreshold = 10;
3199 else if (bs.bs_bmissthreshold <= 0)
3200 bs.bs_bmissthreshold = 1;
3203 * Calculate sleep duration. The configuration is
3204 * given in ms. We insure a multiple of the beacon
3205 * period is used. Also, if the sleep duration is
3206 * greater than the DTIM period then it makes senses
3207 * to make it a multiple of that.
3209 * XXX fixed at 100ms
3211 bs.bs_sleepduration =
3212 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
3213 if (bs.bs_sleepduration > bs.bs_dtimperiod)
3214 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
3216 DPRINTF(sc, ATH_DEBUG_BEACON,
3217 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
3224 , bs.bs_bmissthreshold
3225 , bs.bs_sleepduration
3227 , bs.bs_cfpmaxduration
3231 ath_hal_intrset(ah, 0);
3232 ath_hal_beacontimers(ah, &bs);
3233 sc->sc_imask |= HAL_INT_BMISS;
3234 ath_hal_intrset(ah, sc->sc_imask);
3236 ath_hal_intrset(ah, 0);
3237 if (nexttbtt == intval)
3238 intval |= HAL_BEACON_RESET_TSF;
3239 if (ic->ic_opmode == IEEE80211_M_IBSS) {
3241 * In IBSS mode enable the beacon timers but only
3242 * enable SWBA interrupts if we need to manually
3243 * prepare beacon frames. Otherwise we use a
3244 * self-linked tx descriptor and let the hardware
3247 intval |= HAL_BEACON_ENA;
3248 if (!sc->sc_hasveol)
3249 sc->sc_imask |= HAL_INT_SWBA;
3250 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
3252 * Pull nexttbtt forward to reflect
3255 tsf = ath_hal_gettsf64(ah);
3256 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3259 } while (nexttbtt < tsftu);
3261 ath_beaconq_config(sc);
3262 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3263 ic->ic_opmode == IEEE80211_M_MBSS) {
3265 * In AP/mesh mode we enable the beacon timers
3266 * and SWBA interrupts to prepare beacon frames.
3268 intval |= HAL_BEACON_ENA;
3269 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
3270 ath_beaconq_config(sc);
3272 ath_hal_beaconinit(ah, nexttbtt, intval);
3273 sc->sc_bmisscount = 0;
3274 ath_hal_intrset(ah, sc->sc_imask);
3276 * When using a self-linked beacon descriptor in
3277 * ibss mode load it once here.
3279 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
3280 ath_beacon_start_adhoc(sc, vap);
3282 sc->sc_syncbeacon = 0;
3288 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3290 bus_addr_t *paddr = (bus_addr_t*) arg;
3291 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3292 *paddr = segs->ds_addr;
3296 ath_descdma_setup(struct ath_softc *sc,
3297 struct ath_descdma *dd, ath_bufhead *head,
3298 const char *name, int nbuf, int ndesc)
3300 #define DS2PHYS(_dd, _ds) \
3301 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3302 struct ifnet *ifp = sc->sc_ifp;
3303 struct ath_desc *ds;
3305 int i, bsize, error;
3307 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
3308 __func__, name, nbuf, ndesc);
3311 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
3314 * Setup DMA descriptor area.
3316 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3317 PAGE_SIZE, 0, /* alignment, bounds */
3318 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3319 BUS_SPACE_MAXADDR, /* highaddr */
3320 NULL, NULL, /* filter, filterarg */
3321 dd->dd_desc_len, /* maxsize */
3323 dd->dd_desc_len, /* maxsegsize */
3324 BUS_DMA_ALLOCNOW, /* flags */
3325 NULL, /* lockfunc */
3329 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3333 /* allocate descriptors */
3334 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
3336 if_printf(ifp, "unable to create dmamap for %s descriptors, "
3337 "error %u\n", dd->dd_name, error);
3341 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3342 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3345 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3346 "error %u\n", nbuf * ndesc, dd->dd_name, error);
3350 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3351 dd->dd_desc, dd->dd_desc_len,
3352 ath_load_cb, &dd->dd_desc_paddr,
3355 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3356 dd->dd_name, error);
3361 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3362 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
3363 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
3365 /* allocate rx buffers */
3366 bsize = sizeof(struct ath_buf) * nbuf;
3367 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3369 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3370 dd->dd_name, bsize);
3376 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
3378 bf->bf_daddr = DS2PHYS(dd, ds);
3379 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3382 if_printf(ifp, "unable to create dmamap for %s "
3383 "buffer %u, error %u\n", dd->dd_name, i, error);
3384 ath_descdma_cleanup(sc, dd, head);
3387 STAILQ_INSERT_TAIL(head, bf, bf_list);
3391 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3393 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3395 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3397 bus_dma_tag_destroy(dd->dd_dmat);
3398 memset(dd, 0, sizeof(*dd));
3404 ath_descdma_cleanup(struct ath_softc *sc,
3405 struct ath_descdma *dd, ath_bufhead *head)
3408 struct ieee80211_node *ni;
3410 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3411 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3412 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3413 bus_dma_tag_destroy(dd->dd_dmat);
3415 STAILQ_FOREACH(bf, head, bf_list) {
3420 if (bf->bf_dmamap != NULL) {
3421 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3422 bf->bf_dmamap = NULL;
3428 * Reclaim node reference.
3430 ieee80211_free_node(ni);
3435 free(dd->dd_bufptr, M_ATHDEV);
3436 memset(dd, 0, sizeof(*dd));
3440 ath_desc_alloc(struct ath_softc *sc)
3444 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
3445 "rx", ath_rxbuf, 1);
3449 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3450 "tx", ath_txbuf, ATH_TXDESC);
3452 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3456 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3457 "beacon", ATH_BCBUF, 1);
3459 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3460 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3467 ath_desc_free(struct ath_softc *sc)
3470 if (sc->sc_bdma.dd_desc_len != 0)
3471 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3472 if (sc->sc_txdma.dd_desc_len != 0)
3473 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3474 if (sc->sc_rxdma.dd_desc_len != 0)
3475 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3478 static struct ieee80211_node *
3479 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3481 struct ieee80211com *ic = vap->iv_ic;
3482 struct ath_softc *sc = ic->ic_ifp->if_softc;
3483 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3484 struct ath_node *an;
3486 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3491 ath_rate_node_init(sc, an);
3493 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
3494 return &an->an_node;
3498 ath_node_free(struct ieee80211_node *ni)
3500 struct ieee80211com *ic = ni->ni_ic;
3501 struct ath_softc *sc = ic->ic_ifp->if_softc;
3503 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
3505 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3506 sc->sc_node_free(ni);
3510 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3512 struct ieee80211com *ic = ni->ni_ic;
3513 struct ath_softc *sc = ic->ic_ifp->if_softc;
3514 struct ath_hal *ah = sc->sc_ah;
3516 *rssi = ic->ic_node_getrssi(ni);
3517 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3518 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3520 *noise = -95; /* nominally correct */
3524 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
3526 struct ath_hal *ah = sc->sc_ah;
3529 struct ath_desc *ds;
3534 * NB: by assigning a page to the rx dma buffer we
3535 * implicitly satisfy the Atheros requirement that
3536 * this buffer be cache-line-aligned and sized to be
3537 * multiple of the cache line size. Not doing this
3538 * causes weird stuff to happen (for the 5210 at least).
3540 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3542 DPRINTF(sc, ATH_DEBUG_ANY,
3543 "%s: no mbuf/cluster\n", __func__);
3544 sc->sc_stats.ast_rx_nombuf++;
3547 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
3549 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
3551 bf->bf_segs, &bf->bf_nseg,
3554 DPRINTF(sc, ATH_DEBUG_ANY,
3555 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
3557 sc->sc_stats.ast_rx_busdma++;
3561 KASSERT(bf->bf_nseg == 1,
3562 ("multi-segment packet; nseg %u", bf->bf_nseg));
3565 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
3568 * Setup descriptors. For receive we always terminate
3569 * the descriptor list with a self-linked entry so we'll
3570 * not get overrun under high load (as can happen with a
3571 * 5212 when ANI processing enables PHY error frames).
3573 * To insure the last descriptor is self-linked we create
3574 * each descriptor as self-linked and add it to the end. As
3575 * each additional descriptor is added the previous self-linked
3576 * entry is ``fixed'' naturally. This should be safe even
3577 * if DMA is happening. When processing RX interrupts we
3578 * never remove/process the last, self-linked, entry on the
3579 * descriptor list. This insures the hardware always has
3580 * someplace to write a new frame.
3583 ds->ds_link = bf->bf_daddr; /* link to self */
3584 ds->ds_data = bf->bf_segs[0].ds_addr;
3585 ath_hal_setuprxdesc(ah, ds
3586 , m->m_len /* buffer size */
3590 if (sc->sc_rxlink != NULL)
3591 *sc->sc_rxlink = bf->bf_daddr;
3592 sc->sc_rxlink = &ds->ds_link;
3597 * Extend 15-bit time stamp from rx descriptor to
3598 * a full 64-bit TSF using the specified TSF.
3600 static __inline u_int64_t
3601 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
3603 if ((tsf & 0x7fff) < rstamp)
3605 return ((tsf &~ 0x7fff) | rstamp);
3609 * Intercept management frames to collect beacon rssi data
3610 * and to do ibss merges.
3613 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
3614 int subtype, int rssi, int nf)
3616 struct ieee80211vap *vap = ni->ni_vap;
3617 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
3620 * Call up first so subsequent work can use information
3621 * potentially stored in the node (e.g. for ibss merge).
3623 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
3625 case IEEE80211_FC0_SUBTYPE_BEACON:
3626 /* update rssi statistics for use by the hal */
3627 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
3628 if (sc->sc_syncbeacon &&
3629 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
3631 * Resync beacon timers using the tsf of the beacon
3632 * frame we just received.
3634 ath_beacon_config(sc, vap);
3637 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3638 if (vap->iv_opmode == IEEE80211_M_IBSS &&
3639 vap->iv_state == IEEE80211_S_RUN) {
3640 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
3641 u_int64_t tsf = ath_extend_tsf(rstamp,
3642 ath_hal_gettsf64(sc->sc_ah));
3644 * Handle ibss merge as needed; check the tsf on the
3645 * frame before attempting the merge. The 802.11 spec
3646 * says the station should change it's bssid to match
3647 * the oldest station with the same ssid, where oldest
3648 * is determined by the tsf. Note that hardware
3649 * reconfiguration happens through callback to
3650 * ath_newstate as the state machine will go from
3651 * RUN -> RUN when this happens.
3653 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
3654 DPRINTF(sc, ATH_DEBUG_STATE,
3655 "ibss merge, rstamp %u tsf %ju "
3656 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
3657 (uintmax_t)ni->ni_tstamp.tsf);
3658 (void) ieee80211_ibss_merge(ni);
3666 * Set the default antenna.
3669 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3671 struct ath_hal *ah = sc->sc_ah;
3673 /* XXX block beacon interrupts */
3674 ath_hal_setdefantenna(ah, antenna);
3675 if (sc->sc_defant != antenna)
3676 sc->sc_stats.ast_ant_defswitch++;
3677 sc->sc_defant = antenna;
3678 sc->sc_rxotherant = 0;
3682 ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
3683 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
3685 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
3686 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
3687 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
3688 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
3689 struct ath_softc *sc = ifp->if_softc;
3690 const HAL_RATE_TABLE *rt;
3693 rt = sc->sc_currates;
3694 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3695 rix = rt->rateCodeToIndex[rs->rs_rate];
3696 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
3697 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
3698 #ifdef AH_SUPPORT_AR5416
3699 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
3700 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
3701 struct ieee80211com *ic = ifp->if_l2com;
3703 if ((rs->rs_flags & HAL_RX_2040) == 0)
3704 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
3705 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
3706 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
3708 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
3709 if ((rs->rs_flags & HAL_RX_GI) == 0)
3710 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
3713 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
3714 if (rs->rs_status & HAL_RXERR_CRC)
3715 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
3716 /* XXX propagate other error flags from descriptor */
3717 sc->sc_rx_th.wr_antnoise = nf;
3718 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
3719 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
3727 ath_handle_micerror(struct ieee80211com *ic,
3728 struct ieee80211_frame *wh, int keyix)
3730 struct ieee80211_node *ni;
3732 /* XXX recheck MIC to deal w/ chips that lie */
3733 /* XXX discard MIC errors on !data frames */
3734 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
3736 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
3737 ieee80211_free_node(ni);
3742 ath_rx_proc(void *arg, int npending)
3744 #define PA2DESC(_sc, _pa) \
3745 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3746 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3747 struct ath_softc *sc = arg;
3749 struct ifnet *ifp = sc->sc_ifp;
3750 struct ieee80211com *ic = ifp->if_l2com;
3751 struct ath_hal *ah = sc->sc_ah;
3752 struct ath_desc *ds;
3753 struct ath_rx_status *rs;
3755 struct ieee80211_node *ni;
3756 int len, type, ngood;
3762 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
3764 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
3765 sc->sc_stats.ast_rx_noise = nf;
3766 tsf = ath_hal_gettsf64(ah);
3768 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3769 if (bf == NULL) { /* NB: shouldn't happen */
3770 if_printf(ifp, "%s: no buffer!\n", __func__);
3774 if (m == NULL) { /* NB: shouldn't happen */
3776 * If mbuf allocation failed previously there
3777 * will be no mbuf; try again to re-populate it.
3779 /* XXX make debug msg */
3780 if_printf(ifp, "%s: no mbuf!\n", __func__);
3781 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3785 if (ds->ds_link == bf->bf_daddr) {
3786 /* NB: never process the self-linked entry at the end */
3789 /* XXX sync descriptor memory */
3791 * Must provide the virtual address of the current
3792 * descriptor, the physical address, and the virtual
3793 * address of the next descriptor in the h/w chain.
3794 * This allows the HAL to look ahead to see if the
3795 * hardware is done with a descriptor by checking the
3796 * done bit in the following descriptor and the address
3797 * of the current descriptor the DMA engine is working
3798 * on. All this is necessary because of our use of
3799 * a self-linked list to avoid rx overruns.
3801 rs = &bf->bf_status.ds_rxstat;
3802 status = ath_hal_rxprocdesc(ah, ds,
3803 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
3805 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
3806 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
3808 if (status == HAL_EINPROGRESS)
3810 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3811 if (rs->rs_status != 0) {
3812 if (rs->rs_status & HAL_RXERR_CRC)
3813 sc->sc_stats.ast_rx_crcerr++;
3814 if (rs->rs_status & HAL_RXERR_FIFO)
3815 sc->sc_stats.ast_rx_fifoerr++;
3816 if (rs->rs_status & HAL_RXERR_PHY) {
3817 sc->sc_stats.ast_rx_phyerr++;
3818 phyerr = rs->rs_phyerr & 0x1f;
3819 sc->sc_stats.ast_rx_phy[phyerr]++;
3820 goto rx_error; /* NB: don't count in ierrors */
3822 if (rs->rs_status & HAL_RXERR_DECRYPT) {
3824 * Decrypt error. If the error occurred
3825 * because there was no hardware key, then
3826 * let the frame through so the upper layers
3827 * can process it. This is necessary for 5210
3828 * parts which have no way to setup a ``clear''
3831 * XXX do key cache faulting
3833 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
3835 sc->sc_stats.ast_rx_badcrypt++;
3837 if (rs->rs_status & HAL_RXERR_MIC) {
3838 sc->sc_stats.ast_rx_badmic++;
3840 * Do minimal work required to hand off
3841 * the 802.11 header for notification.
3843 /* XXX frag's and qos frames */
3844 len = rs->rs_datalen;
3845 if (len >= sizeof (struct ieee80211_frame)) {
3846 bus_dmamap_sync(sc->sc_dmat,
3848 BUS_DMASYNC_POSTREAD);
3849 ath_handle_micerror(ic,
3850 mtod(m, struct ieee80211_frame *),
3852 rs->rs_keyix-32 : rs->rs_keyix);
3858 * Cleanup any pending partial frame.
3860 if (sc->sc_rxpending != NULL) {
3861 m_freem(sc->sc_rxpending);
3862 sc->sc_rxpending = NULL;
3865 * When a tap is present pass error frames
3866 * that have been requested. By default we
3867 * pass decrypt+mic errors but others may be
3868 * interesting (e.g. crc).
3870 if (ieee80211_radiotap_active(ic) &&
3871 (rs->rs_status & sc->sc_monpass)) {
3872 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3873 BUS_DMASYNC_POSTREAD);
3874 /* NB: bpf needs the mbuf length setup */
3875 len = rs->rs_datalen;
3876 m->m_pkthdr.len = m->m_len = len;
3877 ath_rx_tap(ifp, m, rs, tsf, nf);
3878 ieee80211_radiotap_rx_all(ic, m);
3880 /* XXX pass MIC errors up for s/w reclaculation */
3885 * Sync and unmap the frame. At this point we're
3886 * committed to passing the mbuf somewhere so clear
3887 * bf_m; this means a new mbuf must be allocated
3888 * when the rx descriptor is setup again to receive
3891 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3892 BUS_DMASYNC_POSTREAD);
3893 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3896 len = rs->rs_datalen;
3901 * Frame spans multiple descriptors; save
3902 * it for the next completed descriptor, it
3903 * will be used to construct a jumbogram.
3905 if (sc->sc_rxpending != NULL) {
3906 /* NB: max frame size is currently 2 clusters */
3907 sc->sc_stats.ast_rx_toobig++;
3908 m_freem(sc->sc_rxpending);
3910 m->m_pkthdr.rcvif = ifp;
3911 m->m_pkthdr.len = len;
3912 sc->sc_rxpending = m;
3914 } else if (sc->sc_rxpending != NULL) {
3916 * This is the second part of a jumbogram,
3917 * chain it to the first mbuf, adjust the
3918 * frame length, and clear the rxpending state.
3920 sc->sc_rxpending->m_next = m;
3921 sc->sc_rxpending->m_pkthdr.len += len;
3922 m = sc->sc_rxpending;
3923 sc->sc_rxpending = NULL;
3926 * Normal single-descriptor receive; setup
3927 * the rcvif and packet length.
3929 m->m_pkthdr.rcvif = ifp;
3930 m->m_pkthdr.len = len;
3934 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
3937 * Populate the rx status block. When there are bpf
3938 * listeners we do the additional work to provide
3939 * complete status. Otherwise we fill in only the
3940 * material required by ieee80211_input. Note that
3941 * noise setting is filled in above.
3943 if (ieee80211_radiotap_active(ic))
3944 ath_rx_tap(ifp, m, rs, tsf, nf);
3947 * From this point on we assume the frame is at least
3948 * as large as ieee80211_frame_min; verify that.
3950 if (len < IEEE80211_MIN_LEN) {
3951 if (!ieee80211_radiotap_active(ic)) {
3952 DPRINTF(sc, ATH_DEBUG_RECV,
3953 "%s: short packet %d\n", __func__, len);
3954 sc->sc_stats.ast_rx_tooshort++;
3956 /* NB: in particular this captures ack's */
3957 ieee80211_radiotap_rx_all(ic, m);
3963 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3964 const HAL_RATE_TABLE *rt = sc->sc_currates;
3965 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
3967 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
3968 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
3971 m_adj(m, -IEEE80211_CRC_LEN);
3974 * Locate the node for sender, track state, and then
3975 * pass the (referenced) node up to the 802.11 layer
3978 ni = ieee80211_find_rxnode_withkey(ic,
3979 mtod(m, const struct ieee80211_frame_min *),
3980 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
3981 IEEE80211_KEYIX_NONE : rs->rs_keyix);
3984 * Sending station is known, dispatch directly.
3987 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
3988 ieee80211_free_node(ni);
3990 * Arrange to update the last rx timestamp only for
3991 * frames from our ap when operating in station mode.
3992 * This assumes the rx key is always setup when
3995 if (ic->ic_opmode == IEEE80211_M_STA &&
3996 rs->rs_keyix != HAL_RXKEYIX_INVALID)
3999 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
4002 * Track rx rssi and do any rx antenna management.
4004 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
4005 if (sc->sc_diversity) {
4007 * When using fast diversity, change the default rx
4008 * antenna if diversity chooses the other antenna 3
4011 if (sc->sc_defant != rs->rs_antenna) {
4012 if (++sc->sc_rxotherant >= 3)
4013 ath_setdefantenna(sc, rs->rs_antenna);
4015 sc->sc_rxotherant = 0;
4017 if (sc->sc_softled) {
4019 * Blink for any data frame. Otherwise do a
4020 * heartbeat-style blink when idle. The latter
4021 * is mainly for station mode where we depend on
4022 * periodic beacon frames to trigger the poll event.
4024 if (type == IEEE80211_FC0_TYPE_DATA) {
4025 const HAL_RATE_TABLE *rt = sc->sc_currates;
4027 rt->rateCodeToIndex[rs->rs_rate]);
4028 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
4029 ath_led_event(sc, 0);
4032 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
4033 } while (ath_rxbuf_init(sc, bf) == 0);
4035 /* rx signal state monitoring */
4036 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
4038 sc->sc_lastrx = tsf;
4040 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
4041 #ifdef IEEE80211_SUPPORT_SUPERG
4042 ieee80211_ff_age_all(ic, 100);
4044 if (!IFQ_IS_EMPTY(&ifp->if_snd))
4051 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4053 txq->axq_qnum = qnum;
4056 txq->axq_intrcnt = 0;
4057 txq->axq_link = NULL;
4058 STAILQ_INIT(&txq->axq_q);
4059 ATH_TXQ_LOCK_INIT(sc, txq);
4063 * Setup a h/w transmit queue.
4065 static struct ath_txq *
4066 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4068 #define N(a) (sizeof(a)/sizeof(a[0]))
4069 struct ath_hal *ah = sc->sc_ah;
4073 memset(&qi, 0, sizeof(qi));
4074 qi.tqi_subtype = subtype;
4075 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4076 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4077 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4079 * Enable interrupts only for EOL and DESC conditions.
4080 * We mark tx descriptors to receive a DESC interrupt
4081 * when a tx queue gets deep; otherwise waiting for the
4082 * EOL to reap descriptors. Note that this is done to
4083 * reduce interrupt load and this only defers reaping
4084 * descriptors, never transmitting frames. Aside from
4085 * reducing interrupts this also permits more concurrency.
4086 * The only potential downside is if the tx queue backs
4087 * up in which case the top half of the kernel may backup
4088 * due to a lack of tx descriptors.
4090 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
4091 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4094 * NB: don't print a message, this happens
4095 * normally on parts with too few tx queues
4099 if (qnum >= N(sc->sc_txq)) {
4100 device_printf(sc->sc_dev,
4101 "hal qnum %u out of range, max %zu!\n",
4102 qnum, N(sc->sc_txq));
4103 ath_hal_releasetxqueue(ah, qnum);
4106 if (!ATH_TXQ_SETUP(sc, qnum)) {
4107 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4108 sc->sc_txqsetup |= 1<<qnum;
4110 return &sc->sc_txq[qnum];
4115 * Setup a hardware data transmit queue for the specified
4116 * access control. The hal may not support all requested
4117 * queues in which case it will return a reference to a
4118 * previously setup queue. We record the mapping from ac's
4119 * to h/w queues for use by ath_tx_start and also track
4120 * the set of h/w queues being used to optimize work in the
4121 * transmit interrupt handler and related routines.
4124 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4126 #define N(a) (sizeof(a)/sizeof(a[0]))
4127 struct ath_txq *txq;
4129 if (ac >= N(sc->sc_ac2q)) {
4130 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4131 ac, N(sc->sc_ac2q));
4134 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4137 sc->sc_ac2q[ac] = txq;
4145 * Update WME parameters for a transmit queue.
4148 ath_txq_update(struct ath_softc *sc, int ac)
4150 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4151 #define ATH_TXOP_TO_US(v) (v<<5)
4152 struct ifnet *ifp = sc->sc_ifp;
4153 struct ieee80211com *ic = ifp->if_l2com;
4154 struct ath_txq *txq = sc->sc_ac2q[ac];
4155 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4156 struct ath_hal *ah = sc->sc_ah;
4159 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4160 #ifdef IEEE80211_SUPPORT_TDMA
4163 * AIFS is zero so there's no pre-transmit wait. The
4164 * burst time defines the slot duration and is configured
4165 * through net80211. The QCU is setup to not do post-xmit
4166 * back off, lockout all lower-priority QCU's, and fire
4167 * off the DMA beacon alert timer which is setup based
4168 * on the slot configuration.
4170 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4171 | HAL_TXQ_TXERRINT_ENABLE
4172 | HAL_TXQ_TXURNINT_ENABLE
4173 | HAL_TXQ_TXEOLINT_ENABLE
4175 | HAL_TXQ_BACKOFF_DISABLE
4176 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4180 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4181 qi.tqi_burstTime = qi.tqi_readyTime;
4184 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4185 | HAL_TXQ_TXERRINT_ENABLE
4186 | HAL_TXQ_TXDESCINT_ENABLE
4187 | HAL_TXQ_TXURNINT_ENABLE
4189 qi.tqi_aifs = wmep->wmep_aifsn;
4190 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4191 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4192 qi.tqi_readyTime = 0;
4193 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4194 #ifdef IEEE80211_SUPPORT_TDMA
4198 DPRINTF(sc, ATH_DEBUG_RESET,
4199 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4200 __func__, txq->axq_qnum, qi.tqi_qflags,
4201 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4203 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4204 if_printf(ifp, "unable to update hardware queue "
4205 "parameters for %s traffic!\n",
4206 ieee80211_wme_acnames[ac]);
4209 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4212 #undef ATH_TXOP_TO_US
4213 #undef ATH_EXPONENT_TO_VALUE
4217 * Callback from the 802.11 layer to update WME parameters.
4220 ath_wme_update(struct ieee80211com *ic)
4222 struct ath_softc *sc = ic->ic_ifp->if_softc;
4224 return !ath_txq_update(sc, WME_AC_BE) ||
4225 !ath_txq_update(sc, WME_AC_BK) ||
4226 !ath_txq_update(sc, WME_AC_VI) ||
4227 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4231 * Reclaim resources for a setup queue.
4234 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4237 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4238 ATH_TXQ_LOCK_DESTROY(txq);
4239 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4243 * Reclaim all tx queue resources.
4246 ath_tx_cleanup(struct ath_softc *sc)
4250 ATH_TXBUF_LOCK_DESTROY(sc);
4251 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4252 if (ATH_TXQ_SETUP(sc, i))
4253 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4257 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4258 * using the current rates in sc_rixmap.
4261 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4263 int rix = sc->sc_rixmap[rate];
4264 /* NB: return lowest rix for invalid rate */
4265 return (rix == 0xff ? 0 : rix);
4269 * Reclaim mbuf resources. For fragmented frames we
4270 * need to claim each frag chained with m_nextpkt.
4273 ath_freetx(struct mbuf *m)
4278 next = m->m_nextpkt;
4279 m->m_nextpkt = NULL;
4281 } while ((m = next) != NULL);
4285 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
4291 * Load the DMA map so any coalescing is done. This
4292 * also calculates the number of descriptors we need.
4294 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4295 bf->bf_segs, &bf->bf_nseg,
4297 if (error == EFBIG) {
4298 /* XXX packet requires too many descriptors */
4299 bf->bf_nseg = ATH_TXDESC+1;
4300 } else if (error != 0) {
4301 sc->sc_stats.ast_tx_busdma++;
4306 * Discard null packets and check for packets that
4307 * require too many TX descriptors. We try to convert
4308 * the latter to a cluster.
4310 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
4311 sc->sc_stats.ast_tx_linear++;
4312 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
4315 sc->sc_stats.ast_tx_nombuf++;
4319 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4320 bf->bf_segs, &bf->bf_nseg,
4323 sc->sc_stats.ast_tx_busdma++;
4327 KASSERT(bf->bf_nseg <= ATH_TXDESC,
4328 ("too many segments after defrag; nseg %u", bf->bf_nseg));
4329 } else if (bf->bf_nseg == 0) { /* null packet, discard */
4330 sc->sc_stats.ast_tx_nodata++;
4334 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
4335 __func__, m0, m0->m_pkthdr.len);
4336 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
4343 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
4345 struct ath_hal *ah = sc->sc_ah;
4346 struct ath_desc *ds, *ds0;
4350 * Fillin the remainder of the descriptor info.
4352 ds0 = ds = bf->bf_desc;
4353 for (i = 0; i < bf->bf_nseg; i++, ds++) {
4354 ds->ds_data = bf->bf_segs[i].ds_addr;
4355 if (i == bf->bf_nseg - 1)
4358 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
4359 ath_hal_filltxdesc(ah, ds
4360 , bf->bf_segs[i].ds_len /* segment length */
4361 , i == 0 /* first segment */
4362 , i == bf->bf_nseg - 1 /* last segment */
4363 , ds0 /* first descriptor */
4365 DPRINTF(sc, ATH_DEBUG_XMIT,
4366 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
4367 __func__, i, ds->ds_link, ds->ds_data,
4368 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
4371 * Insert the frame on the outbound list and pass it on
4372 * to the hardware. Multicast frames buffered for power
4373 * save stations and transmit from the CAB queue are stored
4374 * on a s/w only queue and loaded on to the CAB queue in
4375 * the SWBA handler since frames only go out on DTIM and
4376 * to avoid possible races.
4379 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
4380 ("busy status 0x%x", bf->bf_flags));
4381 if (txq->axq_qnum != ATH_TXQ_SWQ) {
4382 #ifdef IEEE80211_SUPPORT_TDMA
4385 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4386 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
4387 if (txq->axq_link == NULL) {
4389 * Be careful writing the address to TXDP. If
4390 * the tx q is enabled then this write will be
4391 * ignored. Normally this is not an issue but
4392 * when tdma is in use and the q is beacon gated
4393 * this race can occur. If the q is busy then
4394 * defer the work to later--either when another
4395 * packet comes along or when we prepare a beacon
4399 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4400 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
4401 DPRINTF(sc, ATH_DEBUG_XMIT,
4402 "%s: TXDP[%u] = %p (%p) depth %d\n",
4403 __func__, txq->axq_qnum,
4404 (caddr_t)bf->bf_daddr, bf->bf_desc,
4407 txq->axq_flags |= ATH_TXQ_PUTPENDING;
4408 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
4409 "%s: Q%u busy, defer enable\n", __func__,
4413 *txq->axq_link = bf->bf_daddr;
4414 DPRINTF(sc, ATH_DEBUG_XMIT,
4415 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4416 txq->axq_qnum, txq->axq_link,
4417 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4418 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
4420 * The q was busy when we previously tried
4421 * to write the address of the first buffer
4422 * in the chain. Since it's not busy now
4423 * handle this chore. We are certain the
4424 * buffer at the front is the right one since
4425 * axq_link is NULL only when the buffer list
4428 ath_hal_puttxbuf(ah, txq->axq_qnum,
4429 STAILQ_FIRST(&txq->axq_q)->bf_daddr);
4430 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
4431 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
4432 "%s: Q%u restarted\n", __func__,
4437 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4438 if (txq->axq_link == NULL) {
4439 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4440 DPRINTF(sc, ATH_DEBUG_XMIT,
4441 "%s: TXDP[%u] = %p (%p) depth %d\n",
4442 __func__, txq->axq_qnum,
4443 (caddr_t)bf->bf_daddr, bf->bf_desc,
4446 *txq->axq_link = bf->bf_daddr;
4447 DPRINTF(sc, ATH_DEBUG_XMIT,
4448 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4449 txq->axq_qnum, txq->axq_link,
4450 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4452 #endif /* IEEE80211_SUPPORT_TDMA */
4453 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4454 ath_hal_txstart(ah, txq->axq_qnum);
4456 if (txq->axq_link != NULL) {
4457 struct ath_buf *last = ATH_TXQ_LAST(txq);
4458 struct ieee80211_frame *wh;
4460 /* mark previous frame */
4461 wh = mtod(last->bf_m, struct ieee80211_frame *);
4462 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
4463 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
4464 BUS_DMASYNC_PREWRITE);
4466 /* link descriptor */
4467 *txq->axq_link = bf->bf_daddr;
4469 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4470 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4472 ATH_TXQ_UNLOCK(txq);
4476 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
4479 struct ieee80211vap *vap = ni->ni_vap;
4480 struct ath_vap *avp = ATH_VAP(vap);
4481 struct ath_hal *ah = sc->sc_ah;
4482 struct ifnet *ifp = sc->sc_ifp;
4483 struct ieee80211com *ic = ifp->if_l2com;
4484 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
4485 int error, iswep, ismcast, isfrag, ismrr;
4486 int keyix, hdrlen, pktlen, try0;
4487 u_int8_t rix, txrate, ctsrate;
4488 u_int8_t cix = 0xff; /* NB: silence compiler */
4489 struct ath_desc *ds;
4490 struct ath_txq *txq;
4491 struct ieee80211_frame *wh;
4492 u_int subtype, flags, ctsduration;
4494 const HAL_RATE_TABLE *rt;
4495 HAL_BOOL shortPreamble;
4496 struct ath_node *an;
4499 wh = mtod(m0, struct ieee80211_frame *);
4500 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
4501 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
4502 isfrag = m0->m_flags & M_FRAG;
4503 hdrlen = ieee80211_anyhdrsize(wh);
4505 * Packet length must not include any
4506 * pad bytes; deduct them here.
4508 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
4511 const struct ieee80211_cipher *cip;
4512 struct ieee80211_key *k;
4515 * Construct the 802.11 header+trailer for an encrypted
4516 * frame. The only reason this can fail is because of an
4517 * unknown or unsupported cipher/key type.
4519 k = ieee80211_crypto_encap(ni, m0);
4522 * This can happen when the key is yanked after the
4523 * frame was queued. Just discard the frame; the
4524 * 802.11 layer counts failures and provides
4525 * debugging/diagnostics.
4531 * Adjust the packet + header lengths for the crypto
4532 * additions and calculate the h/w key index. When
4533 * a s/w mic is done the frame will have had any mic
4534 * added to it prior to entry so m0->m_pkthdr.len will
4535 * account for it. Otherwise we need to add it to the
4539 hdrlen += cip->ic_header;
4540 pktlen += cip->ic_header + cip->ic_trailer;
4541 /* NB: frags always have any TKIP MIC done in s/w */
4542 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
4543 pktlen += cip->ic_miclen;
4544 keyix = k->wk_keyix;
4546 /* packet header may have moved, reset our local pointer */
4547 wh = mtod(m0, struct ieee80211_frame *);
4548 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
4550 * Use station key cache slot, if assigned.
4552 keyix = ni->ni_ucastkey.wk_keyix;
4553 if (keyix == IEEE80211_KEYIX_NONE)
4554 keyix = HAL_TXKEYIX_INVALID;
4556 keyix = HAL_TXKEYIX_INVALID;
4558 pktlen += IEEE80211_CRC_LEN;
4561 * Load the DMA map so any coalescing is done. This
4562 * also calculates the number of descriptors we need.
4564 error = ath_tx_dmasetup(sc, bf, m0);
4567 bf->bf_node = ni; /* NB: held reference */
4568 m0 = bf->bf_m; /* NB: may have changed */
4569 wh = mtod(m0, struct ieee80211_frame *);
4571 /* setup descriptors */
4573 rt = sc->sc_currates;
4574 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
4577 * NB: the 802.11 layer marks whether or not we should
4578 * use short preamble based on the current mode and
4579 * negotiated parameters.
4581 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
4582 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
4583 shortPreamble = AH_TRUE;
4584 sc->sc_stats.ast_tx_shortpre++;
4586 shortPreamble = AH_FALSE;
4590 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
4591 ismrr = 0; /* default no multi-rate retry*/
4592 pri = M_WME_GETAC(m0); /* honor classification */
4593 /* XXX use txparams instead of fixed values */
4595 * Calculate Atheros packet type from IEEE80211 packet header,
4596 * setup for rate calculations, and select h/w transmit queue.
4598 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
4599 case IEEE80211_FC0_TYPE_MGT:
4600 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4601 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
4602 atype = HAL_PKT_TYPE_BEACON;
4603 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4604 atype = HAL_PKT_TYPE_PROBE_RESP;
4605 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
4606 atype = HAL_PKT_TYPE_ATIM;
4608 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
4609 rix = an->an_mgmtrix;
4610 txrate = rt->info[rix].rateCode;
4612 txrate |= rt->info[rix].shortPreamble;
4613 try0 = ATH_TXMGTTRY;
4614 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4616 case IEEE80211_FC0_TYPE_CTL:
4617 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
4618 rix = an->an_mgmtrix;
4619 txrate = rt->info[rix].rateCode;
4621 txrate |= rt->info[rix].shortPreamble;
4622 try0 = ATH_TXMGTTRY;
4623 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4625 case IEEE80211_FC0_TYPE_DATA:
4626 atype = HAL_PKT_TYPE_NORMAL; /* default */
4628 * Data frames: multicast frames go out at a fixed rate,
4629 * EAPOL frames use the mgmt frame rate; otherwise consult
4630 * the rate control module for the rate to use.
4633 rix = an->an_mcastrix;
4634 txrate = rt->info[rix].rateCode;
4636 txrate |= rt->info[rix].shortPreamble;
4638 } else if (m0->m_flags & M_EAPOL) {
4639 /* XXX? maybe always use long preamble? */
4640 rix = an->an_mgmtrix;
4641 txrate = rt->info[rix].rateCode;
4643 txrate |= rt->info[rix].shortPreamble;
4644 try0 = ATH_TXMAXTRY; /* XXX?too many? */
4646 ath_rate_findrate(sc, an, shortPreamble, pktlen,
4647 &rix, &try0, &txrate);
4648 sc->sc_txrix = rix; /* for LED blinking */
4649 sc->sc_lastdatarix = rix; /* for fast frames */
4650 if (try0 != ATH_TXMAXTRY)
4653 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
4654 flags |= HAL_TXDESC_NOACK;
4657 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
4658 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
4663 txq = sc->sc_ac2q[pri];
4666 * When servicing one or more stations in power-save mode
4667 * (or) if there is some mcast data waiting on the mcast
4668 * queue (to prevent out of order delivery) multicast
4669 * frames must be buffered until after the beacon.
4671 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
4672 txq = &avp->av_mcastq;
4675 * Calculate miscellaneous flags.
4678 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
4679 } else if (pktlen > vap->iv_rtsthreshold &&
4680 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
4681 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
4682 cix = rt->info[rix].controlRate;
4683 sc->sc_stats.ast_tx_rts++;
4685 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
4686 sc->sc_stats.ast_tx_noack++;
4687 #ifdef IEEE80211_SUPPORT_TDMA
4688 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
4689 DPRINTF(sc, ATH_DEBUG_TDMA,
4690 "%s: discard frame, ACK required w/ TDMA\n", __func__);
4691 sc->sc_stats.ast_tdma_ack++;
4698 * If 802.11g protection is enabled, determine whether
4699 * to use RTS/CTS or just CTS. Note that this is only
4700 * done for OFDM unicast frames.
4702 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
4703 rt->info[rix].phy == IEEE80211_T_OFDM &&
4704 (flags & HAL_TXDESC_NOACK) == 0) {
4705 /* XXX fragments must use CCK rates w/ protection */
4706 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4707 flags |= HAL_TXDESC_RTSENA;
4708 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4709 flags |= HAL_TXDESC_CTSENA;
4712 * For frags it would be desirable to use the
4713 * highest CCK rate for RTS/CTS. But stations
4714 * farther away may detect it at a lower CCK rate
4715 * so use the configured protection rate instead
4718 cix = rt->info[sc->sc_protrix].controlRate;
4720 cix = rt->info[sc->sc_protrix].controlRate;
4721 sc->sc_stats.ast_tx_protect++;
4725 * Calculate duration. This logically belongs in the 802.11
4726 * layer but it lacks sufficient information to calculate it.
4728 if ((flags & HAL_TXDESC_NOACK) == 0 &&
4729 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
4732 dur = rt->info[rix].spAckDuration;
4734 dur = rt->info[rix].lpAckDuration;
4735 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
4736 dur += dur; /* additional SIFS+ACK */
4737 KASSERT(m0->m_nextpkt != NULL, ("no fragment"));
4739 * Include the size of next fragment so NAV is
4740 * updated properly. The last fragment uses only
4743 dur += ath_hal_computetxtime(ah, rt,
4744 m0->m_nextpkt->m_pkthdr.len,
4745 rix, shortPreamble);
4749 * Force hardware to use computed duration for next
4750 * fragment by disabling multi-rate retry which updates
4751 * duration based on the multi-rate duration table.
4754 try0 = ATH_TXMGTTRY; /* XXX? */
4756 *(u_int16_t *)wh->i_dur = htole16(dur);
4760 * Calculate RTS/CTS rate and duration if needed.
4763 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
4765 * CTS transmit rate is derived from the transmit rate
4766 * by looking in the h/w rate table. We must also factor
4767 * in whether or not a short preamble is to be used.
4769 /* NB: cix is set above where RTS/CTS is enabled */
4770 KASSERT(cix != 0xff, ("cix not setup"));
4771 ctsrate = rt->info[cix].rateCode;
4773 * Compute the transmit duration based on the frame
4774 * size and the size of an ACK frame. We call into the
4775 * HAL to do the computation since it depends on the
4776 * characteristics of the actual PHY being used.
4778 * NB: CTS is assumed the same size as an ACK so we can
4779 * use the precalculated ACK durations.
4781 if (shortPreamble) {
4782 ctsrate |= rt->info[cix].shortPreamble;
4783 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4784 ctsduration += rt->info[cix].spAckDuration;
4785 ctsduration += ath_hal_computetxtime(ah,
4786 rt, pktlen, rix, AH_TRUE);
4787 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4788 ctsduration += rt->info[rix].spAckDuration;
4790 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4791 ctsduration += rt->info[cix].lpAckDuration;
4792 ctsduration += ath_hal_computetxtime(ah,
4793 rt, pktlen, rix, AH_FALSE);
4794 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4795 ctsduration += rt->info[rix].lpAckDuration;
4798 * Must disable multi-rate retry when using RTS/CTS.
4801 try0 = ATH_TXMGTTRY; /* XXX */
4806 * At this point we are committed to sending the frame
4807 * and we don't need to look at m_nextpkt; clear it in
4808 * case this frame is part of frag chain.
4810 m0->m_nextpkt = NULL;
4812 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
4813 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
4814 sc->sc_hwmap[rix].ieeerate, -1);
4816 if (ieee80211_radiotap_active_vap(vap)) {
4817 u_int64_t tsf = ath_hal_gettsf64(ah);
4819 sc->sc_tx_th.wt_tsf = htole64(tsf);
4820 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
4822 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4824 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
4825 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
4826 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
4827 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
4829 ieee80211_radiotap_tx(vap, m0);
4833 * Determine if a tx interrupt should be generated for
4834 * this descriptor. We take a tx interrupt to reap
4835 * descriptors when the h/w hits an EOL condition or
4836 * when the descriptor is specifically marked to generate
4837 * an interrupt. We periodically mark descriptors in this
4838 * way to insure timely replenishing of the supply needed
4839 * for sending frames. Defering interrupts reduces system
4840 * load and potentially allows more concurrent work to be
4841 * done but if done to aggressively can cause senders to
4844 * NB: use >= to deal with sc_txintrperiod changing
4845 * dynamically through sysctl.
4847 if (flags & HAL_TXDESC_INTREQ) {
4848 txq->axq_intrcnt = 0;
4849 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
4850 flags |= HAL_TXDESC_INTREQ;
4851 txq->axq_intrcnt = 0;
4855 * Formulate first tx descriptor with tx controls.
4857 /* XXX check return value? */
4858 ath_hal_setuptxdesc(ah, ds
4859 , pktlen /* packet length */
4860 , hdrlen /* header length */
4861 , atype /* Atheros packet type */
4862 , ni->ni_txpower /* txpower */
4863 , txrate, try0 /* series 0 rate/tries */
4864 , keyix /* key cache index */
4865 , sc->sc_txantenna /* antenna mode */
4867 , ctsrate /* rts/cts rate */
4868 , ctsduration /* rts/cts duration */
4870 bf->bf_txflags = flags;
4872 * Setup the multi-rate retry state only when we're
4873 * going to use it. This assumes ath_hal_setuptxdesc
4874 * initializes the descriptors (so we don't have to)
4875 * when the hardware supports multi-rate retry and
4879 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
4881 ath_tx_handoff(sc, txq, bf);
4886 * Process completed xmit descriptors from the specified queue.
4889 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
4891 struct ath_hal *ah = sc->sc_ah;
4892 struct ifnet *ifp = sc->sc_ifp;
4893 struct ieee80211com *ic = ifp->if_l2com;
4894 struct ath_buf *bf, *last;
4895 struct ath_desc *ds, *ds0;
4896 struct ath_tx_status *ts;
4897 struct ieee80211_node *ni;
4898 struct ath_node *an;
4899 int sr, lr, pri, nacked;
4902 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4903 __func__, txq->axq_qnum,
4904 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4909 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4910 bf = STAILQ_FIRST(&txq->axq_q);
4912 ATH_TXQ_UNLOCK(txq);
4915 ds0 = &bf->bf_desc[0];
4916 ds = &bf->bf_desc[bf->bf_nseg - 1];
4917 ts = &bf->bf_status.ds_txstat;
4918 status = ath_hal_txprocdesc(ah, ds, ts);
4920 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4921 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4924 if (status == HAL_EINPROGRESS) {
4925 ATH_TXQ_UNLOCK(txq);
4928 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4929 #ifdef IEEE80211_SUPPORT_TDMA
4930 if (txq->axq_depth > 0) {
4932 * More frames follow. Mark the buffer busy
4933 * so it's not re-used while the hardware may
4934 * still re-read the link field in the descriptor.
4936 bf->bf_flags |= ATH_BUF_BUSY;
4939 if (txq->axq_depth == 0)
4941 txq->axq_link = NULL;
4942 ATH_TXQ_UNLOCK(txq);
4947 if (ts->ts_status == 0) {
4948 u_int8_t txant = ts->ts_antenna;
4949 sc->sc_stats.ast_ant_tx[txant]++;
4950 sc->sc_ant_tx[txant]++;
4951 if (ts->ts_finaltsi != 0)
4952 sc->sc_stats.ast_tx_altrate++;
4953 pri = M_WME_GETAC(bf->bf_m);
4954 if (pri >= WME_AC_VO)
4955 ic->ic_wme.wme_hipri_traffic++;
4956 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0)
4957 ni->ni_inact = ni->ni_inact_reload;
4959 if (ts->ts_status & HAL_TXERR_XRETRY)
4960 sc->sc_stats.ast_tx_xretries++;
4961 if (ts->ts_status & HAL_TXERR_FIFO)
4962 sc->sc_stats.ast_tx_fifoerr++;
4963 if (ts->ts_status & HAL_TXERR_FILT)
4964 sc->sc_stats.ast_tx_filtered++;
4965 if (bf->bf_m->m_flags & M_FF)
4966 sc->sc_stats.ast_ff_txerr++;
4968 sr = ts->ts_shortretry;
4969 lr = ts->ts_longretry;
4970 sc->sc_stats.ast_tx_shortretry += sr;
4971 sc->sc_stats.ast_tx_longretry += lr;
4973 * Hand the descriptor to the rate control algorithm.
4975 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4976 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) {
4978 * If frame was ack'd update statistics,
4979 * including the last rx time used to
4980 * workaround phantom bmiss interrupts.
4982 if (ts->ts_status == 0) {
4984 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4985 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4988 ath_rate_tx_complete(sc, an, bf);
4991 * Do any tx complete callback. Note this must
4992 * be done before releasing the node reference.
4994 if (bf->bf_m->m_flags & M_TXCB)
4995 ieee80211_process_callback(ni, bf->bf_m,
4996 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ?
4997 ts->ts_status : HAL_TXERR_XRETRY);
4998 ieee80211_free_node(ni);
5000 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
5001 BUS_DMASYNC_POSTWRITE);
5002 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5009 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
5011 last->bf_flags &= ~ATH_BUF_BUSY;
5012 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5013 ATH_TXBUF_UNLOCK(sc);
5015 #ifdef IEEE80211_SUPPORT_SUPERG
5017 * Flush fast-frame staging queue when traffic slows.
5019 if (txq->axq_depth <= 1)
5020 ieee80211_ff_flush(ic, txq->axq_ac);
5026 txqactive(struct ath_hal *ah, int qnum)
5028 u_int32_t txqs = 1<<qnum;
5029 ath_hal_gettxintrtxqs(ah, &txqs);
5030 return (txqs & (1<<qnum));
5034 * Deferred processing of transmit interrupt; special-cased
5035 * for a single hardware transmit queue (e.g. 5210 and 5211).
5038 ath_tx_proc_q0(void *arg, int npending)
5040 struct ath_softc *sc = arg;
5041 struct ifnet *ifp = sc->sc_ifp;
5043 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
5044 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5045 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5046 ath_tx_processq(sc, sc->sc_cabq);
5047 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5048 sc->sc_wd_timer = 0;
5051 ath_led_event(sc, sc->sc_txrix);
5057 * Deferred processing of transmit interrupt; special-cased
5058 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
5061 ath_tx_proc_q0123(void *arg, int npending)
5063 struct ath_softc *sc = arg;
5064 struct ifnet *ifp = sc->sc_ifp;
5068 * Process each active queue.
5071 if (txqactive(sc->sc_ah, 0))
5072 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
5073 if (txqactive(sc->sc_ah, 1))
5074 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
5075 if (txqactive(sc->sc_ah, 2))
5076 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
5077 if (txqactive(sc->sc_ah, 3))
5078 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
5079 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5080 ath_tx_processq(sc, sc->sc_cabq);
5082 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5084 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5085 sc->sc_wd_timer = 0;
5088 ath_led_event(sc, sc->sc_txrix);
5094 * Deferred processing of transmit interrupt.
5097 ath_tx_proc(void *arg, int npending)
5099 struct ath_softc *sc = arg;
5100 struct ifnet *ifp = sc->sc_ifp;
5104 * Process each active queue.
5107 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5108 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
5109 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
5111 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5113 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5114 sc->sc_wd_timer = 0;
5117 ath_led_event(sc, sc->sc_txrix);
5123 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5126 struct ath_hal *ah = sc->sc_ah;
5128 struct ieee80211_node *ni;
5133 * NB: this assumes output has been stopped and
5134 * we do not need to block ath_tx_proc
5137 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
5139 bf->bf_flags &= ~ATH_BUF_BUSY;
5140 ATH_TXBUF_UNLOCK(sc);
5141 for (ix = 0;; ix++) {
5143 bf = STAILQ_FIRST(&txq->axq_q);
5145 txq->axq_link = NULL;
5146 ATH_TXQ_UNLOCK(txq);
5149 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
5150 ATH_TXQ_UNLOCK(txq);
5152 if (sc->sc_debug & ATH_DEBUG_RESET) {
5153 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5155 ath_printtxbuf(sc, bf, txq->axq_qnum, ix,
5156 ath_hal_txprocdesc(ah, bf->bf_desc,
5157 &bf->bf_status.ds_txstat) == HAL_OK);
5158 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5159 bf->bf_m->m_len, 0, -1);
5161 #endif /* ATH_DEBUG */
5162 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5167 * Do any callback and reclaim the node reference.
5169 if (bf->bf_m->m_flags & M_TXCB)
5170 ieee80211_process_callback(ni, bf->bf_m, -1);
5171 ieee80211_free_node(ni);
5175 bf->bf_flags &= ~ATH_BUF_BUSY;
5178 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5179 ATH_TXBUF_UNLOCK(sc);
5184 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5186 struct ath_hal *ah = sc->sc_ah;
5188 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5189 __func__, txq->axq_qnum,
5190 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5192 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5196 * Drain the transmit queues and reclaim resources.
5199 ath_draintxq(struct ath_softc *sc)
5201 struct ath_hal *ah = sc->sc_ah;
5202 struct ifnet *ifp = sc->sc_ifp;
5205 /* XXX return value */
5206 if (!sc->sc_invalid) {
5207 /* don't touch the hardware if marked invalid */
5208 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5209 __func__, sc->sc_bhalq,
5210 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5212 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5213 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5214 if (ATH_TXQ_SETUP(sc, i))
5215 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5217 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5218 if (ATH_TXQ_SETUP(sc, i))
5219 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5221 if (sc->sc_debug & ATH_DEBUG_RESET) {
5222 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
5223 if (bf != NULL && bf->bf_m != NULL) {
5224 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5225 ath_hal_txprocdesc(ah, bf->bf_desc,
5226 &bf->bf_status.ds_txstat) == HAL_OK);
5227 ieee80211_dump_pkt(ifp->if_l2com,
5228 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5232 #endif /* ATH_DEBUG */
5233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5234 sc->sc_wd_timer = 0;
5238 * Disable the receive h/w in preparation for a reset.
5241 ath_stoprecv(struct ath_softc *sc)
5243 #define PA2DESC(_sc, _pa) \
5244 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
5245 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
5246 struct ath_hal *ah = sc->sc_ah;
5248 ath_hal_stoppcurecv(ah); /* disable PCU */
5249 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
5250 ath_hal_stopdmarecv(ah); /* disable DMA engine */
5251 DELAY(3000); /* 3ms is long enough for 1 frame */
5253 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
5257 printf("%s: rx queue %p, link %p\n", __func__,
5258 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
5260 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5261 struct ath_desc *ds = bf->bf_desc;
5262 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5263 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
5264 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
5265 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
5266 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
5271 if (sc->sc_rxpending != NULL) {
5272 m_freem(sc->sc_rxpending);
5273 sc->sc_rxpending = NULL;
5275 sc->sc_rxlink = NULL; /* just in case */
5280 * Enable the receive h/w following a reset.
5283 ath_startrecv(struct ath_softc *sc)
5285 struct ath_hal *ah = sc->sc_ah;
5288 sc->sc_rxlink = NULL;
5289 sc->sc_rxpending = NULL;
5290 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5291 int error = ath_rxbuf_init(sc, bf);
5293 DPRINTF(sc, ATH_DEBUG_RECV,
5294 "%s: ath_rxbuf_init failed %d\n",
5300 bf = STAILQ_FIRST(&sc->sc_rxbuf);
5301 ath_hal_putrxbuf(ah, bf->bf_daddr);
5302 ath_hal_rxena(ah); /* enable recv descriptors */
5303 ath_mode_init(sc); /* set filters, etc. */
5304 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
5309 * Update internal state after a channel change.
5312 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5314 enum ieee80211_phymode mode;
5317 * Change channels and update the h/w rate map
5318 * if we're switching; e.g. 11a to 11b/g.
5320 mode = ieee80211_chan2mode(chan);
5321 if (mode != sc->sc_curmode)
5322 ath_setcurmode(sc, mode);
5323 sc->sc_curchan = chan;
5327 * Set/change channels. If the channel is really being changed,
5328 * it's done by reseting the chip. To accomplish this we must
5329 * first cleanup any pending DMA, then restart stuff after a la
5333 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5335 struct ifnet *ifp = sc->sc_ifp;
5336 struct ieee80211com *ic = ifp->if_l2com;
5337 struct ath_hal *ah = sc->sc_ah;
5339 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5340 __func__, ieee80211_chan2ieee(ic, chan),
5341 chan->ic_freq, chan->ic_flags);
5342 if (chan != sc->sc_curchan) {
5345 * To switch channels clear any pending DMA operations;
5346 * wait long enough for the RX fifo to drain, reset the
5347 * hardware at the new frequency, and then re-enable
5348 * the relevant bits of the h/w.
5350 ath_hal_intrset(ah, 0); /* disable interrupts */
5351 ath_draintxq(sc); /* clear pending tx frames */
5352 ath_stoprecv(sc); /* turn off frame recv */
5353 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5354 if_printf(ifp, "%s: unable to reset "
5355 "channel %u (%u Mhz, flags 0x%x), hal status %u\n",
5356 __func__, ieee80211_chan2ieee(ic, chan),
5357 chan->ic_freq, chan->ic_flags, status);
5360 sc->sc_diversity = ath_hal_getdiversity(ah);
5363 * Re-enable rx framework.
5365 if (ath_startrecv(sc) != 0) {
5366 if_printf(ifp, "%s: unable to restart recv logic\n",
5372 * Change channels and update the h/w rate map
5373 * if we're switching; e.g. 11a to 11b/g.
5375 ath_chan_change(sc, chan);
5378 * Re-enable interrupts.
5380 ath_hal_intrset(ah, sc->sc_imask);
5386 * Periodically recalibrate the PHY to account
5387 * for temperature/environment changes.
5390 ath_calibrate(void *arg)
5392 struct ath_softc *sc = arg;
5393 struct ath_hal *ah = sc->sc_ah;
5394 struct ifnet *ifp = sc->sc_ifp;
5395 struct ieee80211com *ic = ifp->if_l2com;
5396 HAL_BOOL longCal, isCalDone;
5399 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5401 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5403 sc->sc_stats.ast_per_cal++;
5404 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5406 * Rfgain is out of bounds, reset the chip
5407 * to load new gain values.
5409 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5410 "%s: rfgain change\n", __func__);
5411 sc->sc_stats.ast_per_rfgain++;
5415 * If this long cal is after an idle period, then
5416 * reset the data collection state so we start fresh.
5418 if (sc->sc_resetcal) {
5419 (void) ath_hal_calreset(ah, sc->sc_curchan);
5420 sc->sc_lastcalreset = ticks;
5421 sc->sc_resetcal = 0;
5424 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5427 * Calibrate noise floor data again in case of change.
5429 ath_hal_process_noisefloor(ah);
5432 DPRINTF(sc, ATH_DEBUG_ANY,
5433 "%s: calibration of channel %u failed\n",
5434 __func__, sc->sc_curchan->ic_freq);
5435 sc->sc_stats.ast_per_calfail++;
5440 * Use a shorter interval to potentially collect multiple
5441 * data samples required to complete calibration. Once
5442 * we're told the work is done we drop back to a longer
5443 * interval between requests. We're more aggressive doing
5444 * work when operating as an AP to improve operation right
5447 nextcal = (1000*ath_shortcalinterval)/hz;
5448 if (sc->sc_opmode != HAL_M_HOSTAP)
5451 nextcal = ath_longcalinterval*hz;
5452 sc->sc_lastlongcal = ticks;
5453 if (sc->sc_lastcalreset == 0)
5454 sc->sc_lastcalreset = sc->sc_lastlongcal;
5455 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5456 sc->sc_resetcal = 1; /* setup reset next trip */
5460 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5461 __func__, nextcal, isCalDone ? "" : "!");
5462 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5464 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5466 /* NB: don't rearm timer */
5471 ath_scan_start(struct ieee80211com *ic)
5473 struct ifnet *ifp = ic->ic_ifp;
5474 struct ath_softc *sc = ifp->if_softc;
5475 struct ath_hal *ah = sc->sc_ah;
5478 /* XXX calibration timer? */
5480 sc->sc_scanning = 1;
5481 sc->sc_syncbeacon = 0;
5482 rfilt = ath_calcrxfilter(sc);
5483 ath_hal_setrxfilter(ah, rfilt);
5484 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5486 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5487 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5491 ath_scan_end(struct ieee80211com *ic)
5493 struct ifnet *ifp = ic->ic_ifp;
5494 struct ath_softc *sc = ifp->if_softc;
5495 struct ath_hal *ah = sc->sc_ah;
5498 sc->sc_scanning = 0;
5499 rfilt = ath_calcrxfilter(sc);
5500 ath_hal_setrxfilter(ah, rfilt);
5501 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5503 ath_hal_process_noisefloor(ah);
5505 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5506 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5511 ath_set_channel(struct ieee80211com *ic)
5513 struct ifnet *ifp = ic->ic_ifp;
5514 struct ath_softc *sc = ifp->if_softc;
5516 (void) ath_chan_set(sc, ic->ic_curchan);
5518 * If we are returning to our bss channel then mark state
5519 * so the next recv'd beacon's tsf will be used to sync the
5520 * beacon timers. Note that since we only hear beacons in
5521 * sta/ibss mode this has no effect in other operating modes.
5523 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5524 sc->sc_syncbeacon = 1;
5528 * Walk the vap list and check if there any vap's in RUN state.
5531 ath_isanyrunningvaps(struct ieee80211vap *this)
5533 struct ieee80211com *ic = this->iv_ic;
5534 struct ieee80211vap *vap;
5536 IEEE80211_LOCK_ASSERT(ic);
5538 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5539 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5546 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5548 struct ieee80211com *ic = vap->iv_ic;
5549 struct ath_softc *sc = ic->ic_ifp->if_softc;
5550 struct ath_vap *avp = ATH_VAP(vap);
5551 struct ath_hal *ah = sc->sc_ah;
5552 struct ieee80211_node *ni = NULL;
5553 int i, error, stamode;
5555 static const HAL_LED_STATE leds[] = {
5556 HAL_LED_INIT, /* IEEE80211_S_INIT */
5557 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5558 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5559 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5560 HAL_LED_RUN, /* IEEE80211_S_CAC */
5561 HAL_LED_RUN, /* IEEE80211_S_RUN */
5562 HAL_LED_RUN, /* IEEE80211_S_CSA */
5563 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5566 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5567 ieee80211_state_name[vap->iv_state],
5568 ieee80211_state_name[nstate]);
5570 callout_drain(&sc->sc_cal_ch);
5571 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5573 if (nstate == IEEE80211_S_SCAN) {
5575 * Scanning: turn off beacon miss and don't beacon.
5576 * Mark beacon state so when we reach RUN state we'll
5577 * [re]setup beacons. Unblock the task q thread so
5578 * deferred interrupt processing is done.
5581 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5582 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5584 taskqueue_unblock(sc->sc_tq);
5588 rfilt = ath_calcrxfilter(sc);
5589 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5590 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5591 vap->iv_opmode == IEEE80211_M_IBSS);
5592 if (stamode && nstate == IEEE80211_S_RUN) {
5593 sc->sc_curaid = ni->ni_associd;
5594 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5595 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5597 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5598 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5599 ath_hal_setrxfilter(ah, rfilt);
5601 /* XXX is this to restore keycache on resume? */
5602 if (vap->iv_opmode != IEEE80211_M_STA &&
5603 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5604 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5605 if (ath_hal_keyisvalid(ah, i))
5606 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5610 * Invoke the parent method to do net80211 work.
5612 error = avp->av_newstate(vap, nstate, arg);
5616 if (nstate == IEEE80211_S_RUN) {
5617 /* NB: collect bss node again, it may have changed */
5620 DPRINTF(sc, ATH_DEBUG_STATE,
5621 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5622 "capinfo 0x%04x chan %d\n", __func__,
5623 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5624 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5626 switch (vap->iv_opmode) {
5627 #ifdef IEEE80211_SUPPORT_TDMA
5628 case IEEE80211_M_AHDEMO:
5629 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5633 case IEEE80211_M_HOSTAP:
5634 case IEEE80211_M_IBSS:
5635 case IEEE80211_M_MBSS:
5637 * Allocate and setup the beacon frame.
5639 * Stop any previous beacon DMA. This may be
5640 * necessary, for example, when an ibss merge
5641 * causes reconfiguration; there will be a state
5642 * transition from RUN->RUN that means we may
5643 * be called with beacon transmission active.
5645 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5647 error = ath_beacon_alloc(sc, ni);
5651 * If joining an adhoc network defer beacon timer
5652 * configuration to the next beacon frame so we
5653 * have a current TSF to use. Otherwise we're
5654 * starting an ibss/bss so there's no need to delay;
5655 * if this is the first vap moving to RUN state, then
5656 * beacon state needs to be [re]configured.
5658 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5659 ni->ni_tstamp.tsf != 0) {
5660 sc->sc_syncbeacon = 1;
5661 } else if (!sc->sc_beacons) {
5662 #ifdef IEEE80211_SUPPORT_TDMA
5663 if (vap->iv_caps & IEEE80211_C_TDMA)
5664 ath_tdma_config(sc, vap);
5667 ath_beacon_config(sc, vap);
5671 case IEEE80211_M_STA:
5673 * Defer beacon timer configuration to the next
5674 * beacon frame so we have a current TSF to use
5675 * (any TSF collected when scanning is likely old).
5677 sc->sc_syncbeacon = 1;
5679 case IEEE80211_M_MONITOR:
5681 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5682 * transitions so we must re-enable interrupts here to
5683 * handle the case of a single monitor mode vap.
5685 ath_hal_intrset(ah, sc->sc_imask);
5687 case IEEE80211_M_WDS:
5693 * Let the hal process statistics collected during a
5694 * scan so it can provide calibrated noise floor data.
5696 ath_hal_process_noisefloor(ah);
5698 * Reset rssi stats; maybe not the best place...
5700 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5701 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5702 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5704 * Finally, start any timers and the task q thread
5705 * (in case we didn't go through SCAN state).
5707 if (ath_longcalinterval != 0) {
5708 /* start periodic recalibration timer */
5709 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5711 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5712 "%s: calibration disabled\n", __func__);
5714 taskqueue_unblock(sc->sc_tq);
5715 } else if (nstate == IEEE80211_S_INIT) {
5717 * If there are no vaps left in RUN state then
5718 * shutdown host/driver operation:
5719 * o disable interrupts
5720 * o disable the task queue thread
5721 * o mark beacon processing as stopped
5723 if (!ath_isanyrunningvaps(vap)) {
5724 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5725 /* disable interrupts */
5726 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5727 taskqueue_block(sc->sc_tq);
5730 #ifdef IEEE80211_SUPPORT_TDMA
5731 ath_hal_setcca(ah, AH_TRUE);
5739 * Allocate a key cache slot to the station so we can
5740 * setup a mapping from key index to node. The key cache
5741 * slot is needed for managing antenna state and for
5742 * compression when stations do not use crypto. We do
5743 * it uniliaterally here; if crypto is employed this slot
5744 * will be reassigned.
5747 ath_setup_stationkey(struct ieee80211_node *ni)
5749 struct ieee80211vap *vap = ni->ni_vap;
5750 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5751 ieee80211_keyix keyix, rxkeyix;
5753 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5755 * Key cache is full; we'll fall back to doing
5756 * the more expensive lookup in software. Note
5757 * this also means no h/w compression.
5759 /* XXX msg+statistic */
5762 ni->ni_ucastkey.wk_keyix = keyix;
5763 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5764 /* NB: must mark device key to get called back on delete */
5765 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
5766 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
5767 /* NB: this will create a pass-thru key entry */
5768 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss);
5773 * Setup driver-specific state for a newly associated node.
5774 * Note that we're called also on a re-associate, the isnew
5775 * param tells us if this is the first time or not.
5778 ath_newassoc(struct ieee80211_node *ni, int isnew)
5780 struct ath_node *an = ATH_NODE(ni);
5781 struct ieee80211vap *vap = ni->ni_vap;
5782 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5783 const struct ieee80211_txparam *tp = ni->ni_txparms;
5785 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
5786 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
5788 ath_rate_newassoc(sc, an, isnew);
5790 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5791 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5792 ath_setup_stationkey(ni);
5796 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
5797 int nchans, struct ieee80211_channel chans[])
5799 struct ath_softc *sc = ic->ic_ifp->if_softc;
5800 struct ath_hal *ah = sc->sc_ah;
5803 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5804 "%s: rd %u cc %u location %c%s\n",
5805 __func__, reg->regdomain, reg->country, reg->location,
5806 reg->ecm ? " ecm" : "");
5808 status = ath_hal_set_channels(ah, chans, nchans,
5809 reg->country, reg->regdomain);
5810 if (status != HAL_OK) {
5811 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
5813 return EINVAL; /* XXX */
5819 ath_getradiocaps(struct ieee80211com *ic,
5820 int maxchans, int *nchans, struct ieee80211_channel chans[])
5822 struct ath_softc *sc = ic->ic_ifp->if_softc;
5823 struct ath_hal *ah = sc->sc_ah;
5825 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
5826 __func__, SKU_DEBUG, CTRY_DEFAULT);
5828 /* XXX check return */
5829 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
5830 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
5835 ath_getchannels(struct ath_softc *sc)
5837 struct ifnet *ifp = sc->sc_ifp;
5838 struct ieee80211com *ic = ifp->if_l2com;
5839 struct ath_hal *ah = sc->sc_ah;
5843 * Collect channel set based on EEPROM contents.
5845 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
5846 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
5847 if (status != HAL_OK) {
5848 if_printf(ifp, "%s: unable to collect channel list from hal, "
5849 "status %d\n", __func__, status);
5852 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
5853 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
5854 /* XXX map Atheros sku's to net80211 SKU's */
5855 /* XXX net80211 types too small */
5856 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
5857 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
5858 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5859 ic->ic_regdomain.isocc[1] = ' ';
5861 ic->ic_regdomain.ecm = 1;
5862 ic->ic_regdomain.location = 'I';
5864 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5865 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
5866 __func__, sc->sc_eerd, sc->sc_eecc,
5867 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
5868 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
5873 ath_led_done(void *arg)
5875 struct ath_softc *sc = arg;
5877 sc->sc_blinking = 0;
5881 * Turn the LED off: flip the pin and then set a timer so no
5882 * update will happen for the specified duration.
5885 ath_led_off(void *arg)
5887 struct ath_softc *sc = arg;
5889 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
5890 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
5894 * Blink the LED according to the specified on/off times.
5897 ath_led_blink(struct ath_softc *sc, int on, int off)
5899 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
5900 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
5901 sc->sc_blinking = 1;
5902 sc->sc_ledoff = off;
5903 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
5907 ath_led_event(struct ath_softc *sc, int rix)
5909 sc->sc_ledevent = ticks; /* time of last event */
5910 if (sc->sc_blinking) /* don't interrupt active blink */
5912 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff);
5916 ath_rate_setup(struct ath_softc *sc, u_int mode)
5918 struct ath_hal *ah = sc->sc_ah;
5919 const HAL_RATE_TABLE *rt;
5922 case IEEE80211_MODE_11A:
5923 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
5925 case IEEE80211_MODE_HALF:
5926 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
5928 case IEEE80211_MODE_QUARTER:
5929 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
5931 case IEEE80211_MODE_11B:
5932 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
5934 case IEEE80211_MODE_11G:
5935 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
5937 case IEEE80211_MODE_TURBO_A:
5938 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
5940 case IEEE80211_MODE_TURBO_G:
5941 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
5943 case IEEE80211_MODE_STURBO_A:
5944 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
5946 case IEEE80211_MODE_11NA:
5947 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
5949 case IEEE80211_MODE_11NG:
5950 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
5953 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
5957 sc->sc_rates[mode] = rt;
5958 return (rt != NULL);
5962 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
5964 #define N(a) (sizeof(a)/sizeof(a[0]))
5965 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
5966 static const struct {
5967 u_int rate; /* tx/rx 802.11 rate */
5968 u_int16_t timeOn; /* LED on time (ms) */
5969 u_int16_t timeOff; /* LED off time (ms) */
5985 /* XXX half/quarter rates */
5987 const HAL_RATE_TABLE *rt;
5990 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
5991 rt = sc->sc_rates[mode];
5992 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
5993 for (i = 0; i < rt->rateCount; i++) {
5994 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5995 if (rt->info[i].phy != IEEE80211_T_HT)
5996 sc->sc_rixmap[ieeerate] = i;
5998 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6000 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6001 for (i = 0; i < N(sc->sc_hwmap); i++) {
6002 if (i >= rt->rateCount) {
6003 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6004 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6007 sc->sc_hwmap[i].ieeerate =
6008 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6009 if (rt->info[i].phy == IEEE80211_T_HT)
6010 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6011 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6012 if (rt->info[i].shortPreamble ||
6013 rt->info[i].phy == IEEE80211_T_OFDM)
6014 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6015 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6016 for (j = 0; j < N(blinkrates)-1; j++)
6017 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6019 /* NB: this uses the last entry if the rate isn't found */
6020 /* XXX beware of overlow */
6021 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6022 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6024 sc->sc_currates = rt;
6025 sc->sc_curmode = mode;
6027 * All protection frames are transmited at 2Mb/s for
6028 * 11g, otherwise at 1Mb/s.
6030 if (mode == IEEE80211_MODE_11G)
6031 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6033 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6034 /* NB: caller is responsible for reseting rate control state */
6040 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf,
6043 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
6044 struct ath_hal *ah = sc->sc_ah;
6045 const struct ath_desc *ds;
6048 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6049 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
6050 " %08x %08x %08x %08x\n",
6051 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
6052 ds->ds_link, ds->ds_data,
6053 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
6054 ds->ds_ctl0, ds->ds_ctl1,
6055 ds->ds_hw[0], ds->ds_hw[1]);
6056 if (ah->ah_magic == 0x20065416) {
6057 printf(" %08x %08x %08x %08x %08x %08x %08x\n",
6058 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4],
6059 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7],
6066 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf,
6067 u_int qnum, u_int ix, int done)
6069 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
6070 struct ath_hal *ah = sc->sc_ah;
6071 const struct ath_desc *ds;
6074 printf("Q%u[%3u]", qnum, ix);
6075 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6076 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
6077 " %08x %08x %08x %08x %08x %08x\n",
6078 ds, (const struct ath_desc *)bf->bf_daddr + i,
6079 ds->ds_link, ds->ds_data, bf->bf_txflags,
6080 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
6081 ds->ds_ctl0, ds->ds_ctl1,
6082 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
6083 if (ah->ah_magic == 0x20065416) {
6084 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n",
6085 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6],
6086 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9],
6087 ds->ds_hw[10],ds->ds_hw[11]);
6088 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n",
6089 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14],
6090 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17],
6091 ds->ds_hw[18], ds->ds_hw[19]);
6095 #endif /* ATH_DEBUG */
6098 ath_watchdog(void *arg)
6100 struct ath_softc *sc = arg;
6102 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6103 struct ifnet *ifp = sc->sc_ifp;
6106 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6108 if_printf(ifp, "%s hang detected (0x%x)\n",
6109 hangs & 0xff ? "bb" : "mac", hangs);
6111 if_printf(ifp, "device timeout\n");
6114 sc->sc_stats.ast_watchdog++;
6116 callout_schedule(&sc->sc_wd_ch, hz);
6121 * Diagnostic interface to the HAL. This is used by various
6122 * tools to do things like retrieve register contents for
6123 * debugging. The mechanism is intentionally opaque so that
6124 * it can change frequently w/o concern for compatiblity.
6127 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6129 struct ath_hal *ah = sc->sc_ah;
6130 u_int id = ad->ad_id & ATH_DIAG_ID;
6131 void *indata = NULL;
6132 void *outdata = NULL;
6133 u_int32_t insize = ad->ad_in_size;
6134 u_int32_t outsize = ad->ad_out_size;
6137 if (ad->ad_id & ATH_DIAG_IN) {
6141 indata = malloc(insize, M_TEMP, M_NOWAIT);
6142 if (indata == NULL) {
6146 error = copyin(ad->ad_in_data, indata, insize);
6150 if (ad->ad_id & ATH_DIAG_DYN) {
6152 * Allocate a buffer for the results (otherwise the HAL
6153 * returns a pointer to a buffer where we can read the
6154 * results). Note that we depend on the HAL leaving this
6155 * pointer for us to use below in reclaiming the buffer;
6156 * may want to be more defensive.
6158 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
6159 if (outdata == NULL) {
6164 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6165 if (outsize < ad->ad_out_size)
6166 ad->ad_out_size = outsize;
6167 if (outdata != NULL)
6168 error = copyout(outdata, ad->ad_out_data,
6174 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6175 free(indata, M_TEMP);
6176 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6177 free(outdata, M_TEMP);
6180 #endif /* ATH_DIAGAPI */
6183 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6185 #define IS_RUNNING(ifp) \
6186 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
6187 struct ath_softc *sc = ifp->if_softc;
6188 struct ieee80211com *ic = ifp->if_l2com;
6189 struct ifreq *ifr = (struct ifreq *)data;
6190 const HAL_RATE_TABLE *rt;
6196 if (IS_RUNNING(ifp)) {
6198 * To avoid rescanning another access point,
6199 * do not call ath_init() here. Instead,
6200 * only reflect promisc mode settings.
6203 } else if (ifp->if_flags & IFF_UP) {
6205 * Beware of being called during attach/detach
6206 * to reset promiscuous mode. In that case we
6207 * will still be marked UP but not RUNNING.
6208 * However trying to re-init the interface
6209 * is the wrong thing to do as we've already
6210 * torn down much of our state. There's
6211 * probably a better way to deal with this.
6213 if (!sc->sc_invalid)
6214 ath_init(sc); /* XXX lose error */
6216 ath_stop_locked(ifp);
6218 /* XXX must wakeup in places like ath_vap_delete */
6219 if (!sc->sc_invalid)
6220 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
6227 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6230 /* NB: embed these numbers to get a consistent view */
6231 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
6232 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
6233 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
6234 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
6235 #ifdef IEEE80211_SUPPORT_TDMA
6236 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
6237 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
6239 rt = sc->sc_currates;
6241 sc->sc_stats.ast_tx_rate =
6242 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
6243 return copyout(&sc->sc_stats,
6244 ifr->ifr_data, sizeof (sc->sc_stats));
6246 error = priv_check(curthread, PRIV_DRIVER);
6248 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6252 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6256 error = ether_ioctl(ifp, cmd, data);
6267 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
6269 struct ath_softc *sc = arg1;
6270 u_int slottime = ath_hal_getslottime(sc->sc_ah);
6273 error = sysctl_handle_int(oidp, &slottime, 0, req);
6274 if (error || !req->newptr)
6276 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
6280 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
6282 struct ath_softc *sc = arg1;
6283 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
6286 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
6287 if (error || !req->newptr)
6289 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
6293 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
6295 struct ath_softc *sc = arg1;
6296 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
6299 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
6300 if (error || !req->newptr)
6302 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
6306 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
6308 struct ath_softc *sc = arg1;
6309 int softled = sc->sc_softled;
6312 error = sysctl_handle_int(oidp, &softled, 0, req);
6313 if (error || !req->newptr)
6315 softled = (softled != 0);
6316 if (softled != sc->sc_softled) {
6318 /* NB: handle any sc_ledpin change */
6319 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
6320 HAL_GPIO_MUX_MAC_NETWORK_LED);
6321 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6324 sc->sc_softled = softled;
6330 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)
6332 struct ath_softc *sc = arg1;
6333 int ledpin = sc->sc_ledpin;
6336 error = sysctl_handle_int(oidp, &ledpin, 0, req);
6337 if (error || !req->newptr)
6339 if (ledpin != sc->sc_ledpin) {
6340 sc->sc_ledpin = ledpin;
6341 if (sc->sc_softled) {
6342 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
6343 HAL_GPIO_MUX_MAC_NETWORK_LED);
6344 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6352 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)
6354 struct ath_softc *sc = arg1;
6355 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah);
6358 error = sysctl_handle_int(oidp, &txantenna, 0, req);
6359 if (!error && req->newptr) {
6360 /* XXX assumes 2 antenna ports */
6361 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B)
6363 ath_hal_setantennaswitch(sc->sc_ah, txantenna);
6365 * NB: with the switch locked this isn't meaningful,
6366 * but set it anyway so things like radiotap get
6367 * consistent info in their data.
6369 sc->sc_txantenna = txantenna;
6375 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
6377 struct ath_softc *sc = arg1;
6378 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
6381 error = sysctl_handle_int(oidp, &defantenna, 0, req);
6382 if (!error && req->newptr)
6383 ath_hal_setdefantenna(sc->sc_ah, defantenna);
6388 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
6390 struct ath_softc *sc = arg1;
6391 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
6394 error = sysctl_handle_int(oidp, &diversity, 0, req);
6395 if (error || !req->newptr)
6397 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
6399 sc->sc_diversity = diversity;
6404 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
6406 struct ath_softc *sc = arg1;
6410 if (!ath_hal_getdiag(sc->sc_ah, &diag))
6412 error = sysctl_handle_int(oidp, &diag, 0, req);
6413 if (error || !req->newptr)
6415 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
6419 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
6421 struct ath_softc *sc = arg1;
6422 struct ifnet *ifp = sc->sc_ifp;
6426 (void) ath_hal_gettpscale(sc->sc_ah, &scale);
6427 error = sysctl_handle_int(oidp, &scale, 0, req);
6428 if (error || !req->newptr)
6430 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL :
6431 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6435 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
6437 struct ath_softc *sc = arg1;
6438 u_int tpc = ath_hal_gettpc(sc->sc_ah);
6441 error = sysctl_handle_int(oidp, &tpc, 0, req);
6442 if (error || !req->newptr)
6444 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
6448 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
6450 struct ath_softc *sc = arg1;
6451 struct ifnet *ifp = sc->sc_ifp;
6452 struct ath_hal *ah = sc->sc_ah;
6453 u_int rfkill = ath_hal_getrfkill(ah);
6456 error = sysctl_handle_int(oidp, &rfkill, 0, req);
6457 if (error || !req->newptr)
6459 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
6461 if (!ath_hal_setrfkill(ah, rfkill))
6463 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6467 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
6469 struct ath_softc *sc = arg1;
6473 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
6474 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
6475 if (error || !req->newptr)
6477 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent))
6479 sc->sc_rfsilentpin = rfsilent & 0x1c;
6480 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
6485 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
6487 struct ath_softc *sc = arg1;
6491 (void) ath_hal_gettpack(sc->sc_ah, &tpack);
6492 error = sysctl_handle_int(oidp, &tpack, 0, req);
6493 if (error || !req->newptr)
6495 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
6499 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
6501 struct ath_softc *sc = arg1;
6505 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
6506 error = sysctl_handle_int(oidp, &tpcts, 0, req);
6507 if (error || !req->newptr)
6509 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
6513 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS)
6515 struct ath_softc *sc = arg1;
6518 intmit = ath_hal_getintmit(sc->sc_ah);
6519 error = sysctl_handle_int(oidp, &intmit, 0, req);
6520 if (error || !req->newptr)
6522 return !ath_hal_setintmit(sc->sc_ah, intmit) ? EINVAL : 0;
6525 #ifdef IEEE80211_SUPPORT_TDMA
6527 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS)
6529 struct ath_softc *sc = arg1;
6532 setcca = sc->sc_setcca;
6533 error = sysctl_handle_int(oidp, &setcca, 0, req);
6534 if (error || !req->newptr)
6536 sc->sc_setcca = (setcca != 0);
6539 #endif /* IEEE80211_SUPPORT_TDMA */
6542 ath_sysctlattach(struct ath_softc *sc)
6544 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
6545 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
6546 struct ath_hal *ah = sc->sc_ah;
6548 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6549 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0,
6550 "EEPROM country code");
6551 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6552 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0,
6553 "EEPROM regdomain code");
6555 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6556 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
6557 "control debugging printfs");
6559 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6560 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6561 ath_sysctl_slottime, "I", "802.11 slot time (us)");
6562 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6563 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6564 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
6565 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6566 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6567 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
6568 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6569 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6570 ath_sysctl_softled, "I", "enable/disable software LED support");
6571 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6572 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6573 ath_sysctl_ledpin, "I", "GPIO pin connected to LED");
6574 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6575 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
6576 "setting to turn LED on");
6577 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6578 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
6579 "idle time for inactivity LED (ticks)");
6580 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6581 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6582 ath_sysctl_txantenna, "I", "antenna switch");
6583 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6584 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6585 ath_sysctl_rxantenna, "I", "default/rx antenna");
6586 if (ath_hal_hasdiversity(ah))
6587 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6588 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6589 ath_sysctl_diversity, "I", "antenna diversity");
6590 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
6591 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6592 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
6593 "tx descriptor batching");
6594 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6595 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6596 ath_sysctl_diag, "I", "h/w diagnostic control");
6597 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6598 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6599 ath_sysctl_tpscale, "I", "tx power scaling");
6600 if (ath_hal_hastpc(ah)) {
6601 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6602 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6603 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
6604 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6605 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6606 ath_sysctl_tpack, "I", "tx power for ack frames");
6607 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6608 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6609 ath_sysctl_tpcts, "I", "tx power for cts frames");
6611 if (ath_hal_hasrfsilent(ah)) {
6612 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6613 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6614 ath_sysctl_rfsilent, "I", "h/w RF silent config");
6615 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6616 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6617 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
6619 if (ath_hal_hasintmit(ah)) {
6620 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6621 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6622 ath_sysctl_intmit, "I", "interference mitigation");
6624 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
6625 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6626 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
6627 "mask of error frames to pass when monitoring");
6628 #ifdef IEEE80211_SUPPORT_TDMA
6629 if (ath_hal_macversion(ah) > 0x78) {
6630 sc->sc_tdmadbaprep = 2;
6631 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6632 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0,
6633 "TDMA DBA preparation time");
6634 sc->sc_tdmaswbaprep = 10;
6635 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6636 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0,
6637 "TDMA SWBA preparation time");
6638 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6639 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0,
6640 "TDMA slot guard time");
6641 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6642 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0,
6643 "TDMA calculated super frame");
6644 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6645 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6646 ath_sysctl_setcca, "I", "enable CCA control");
6652 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
6653 struct ath_buf *bf, struct mbuf *m0,
6654 const struct ieee80211_bpf_params *params)
6656 struct ifnet *ifp = sc->sc_ifp;
6657 struct ieee80211com *ic = ifp->if_l2com;
6658 struct ath_hal *ah = sc->sc_ah;
6659 struct ieee80211vap *vap = ni->ni_vap;
6660 int error, ismcast, ismrr;
6661 int keyix, hdrlen, pktlen, try0, txantenna;
6662 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3;
6663 struct ieee80211_frame *wh;
6664 u_int flags, ctsduration;
6666 const HAL_RATE_TABLE *rt;
6667 struct ath_desc *ds;
6670 wh = mtod(m0, struct ieee80211_frame *);
6671 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6672 hdrlen = ieee80211_anyhdrsize(wh);
6674 * Packet length must not include any
6675 * pad bytes; deduct them here.
6677 /* XXX honor IEEE80211_BPF_DATAPAD */
6678 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
6680 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) {
6681 const struct ieee80211_cipher *cip;
6682 struct ieee80211_key *k;
6685 * Construct the 802.11 header+trailer for an encrypted
6686 * frame. The only reason this can fail is because of an
6687 * unknown or unsupported cipher/key type.
6689 k = ieee80211_crypto_encap(ni, m0);
6692 * This can happen when the key is yanked after the
6693 * frame was queued. Just discard the frame; the
6694 * 802.11 layer counts failures and provides
6695 * debugging/diagnostics.
6701 * Adjust the packet + header lengths for the crypto
6702 * additions and calculate the h/w key index. When
6703 * a s/w mic is done the frame will have had any mic
6704 * added to it prior to entry so m0->m_pkthdr.len will
6705 * account for it. Otherwise we need to add it to the
6709 hdrlen += cip->ic_header;
6710 pktlen += cip->ic_header + cip->ic_trailer;
6711 /* NB: frags always have any TKIP MIC done in s/w */
6712 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
6713 pktlen += cip->ic_miclen;
6714 keyix = k->wk_keyix;
6716 /* packet header may have moved, reset our local pointer */
6717 wh = mtod(m0, struct ieee80211_frame *);
6718 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
6720 * Use station key cache slot, if assigned.
6722 keyix = ni->ni_ucastkey.wk_keyix;
6723 if (keyix == IEEE80211_KEYIX_NONE)
6724 keyix = HAL_TXKEYIX_INVALID;
6726 keyix = HAL_TXKEYIX_INVALID;
6728 error = ath_tx_dmasetup(sc, bf, m0);
6731 m0 = bf->bf_m; /* NB: may have changed */
6732 wh = mtod(m0, struct ieee80211_frame *);
6733 bf->bf_node = ni; /* NB: held reference */
6735 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
6736 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
6737 if (params->ibp_flags & IEEE80211_BPF_RTS)
6738 flags |= HAL_TXDESC_RTSENA;
6739 else if (params->ibp_flags & IEEE80211_BPF_CTS)
6740 flags |= HAL_TXDESC_CTSENA;
6741 /* XXX leave ismcast to injector? */
6742 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
6743 flags |= HAL_TXDESC_NOACK;
6745 rt = sc->sc_currates;
6746 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
6747 rix = ath_tx_findrix(sc, params->ibp_rate0);
6748 txrate = rt->info[rix].rateCode;
6749 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6750 txrate |= rt->info[rix].shortPreamble;
6752 try0 = params->ibp_try0;
6753 ismrr = (params->ibp_try1 != 0);
6754 txantenna = params->ibp_pri >> 2;
6755 if (txantenna == 0) /* XXX? */
6756 txantenna = sc->sc_txantenna;
6758 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) {
6759 cix = ath_tx_findrix(sc, params->ibp_ctsrate);
6760 ctsrate = rt->info[cix].rateCode;
6761 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) {
6762 ctsrate |= rt->info[cix].shortPreamble;
6763 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6764 ctsduration += rt->info[cix].spAckDuration;
6765 ctsduration += ath_hal_computetxtime(ah,
6766 rt, pktlen, rix, AH_TRUE);
6767 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6768 ctsduration += rt->info[rix].spAckDuration;
6770 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6771 ctsduration += rt->info[cix].lpAckDuration;
6772 ctsduration += ath_hal_computetxtime(ah,
6773 rt, pktlen, rix, AH_FALSE);
6774 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6775 ctsduration += rt->info[rix].lpAckDuration;
6777 ismrr = 0; /* XXX */
6780 pri = params->ibp_pri & 3;
6782 * NB: we mark all packets as type PSPOLL so the h/w won't
6783 * set the sequence number, duration, etc.
6785 atype = HAL_PKT_TYPE_PSPOLL;
6787 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
6788 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
6789 sc->sc_hwmap[rix].ieeerate, -1);
6791 if (ieee80211_radiotap_active_vap(vap)) {
6792 u_int64_t tsf = ath_hal_gettsf64(ah);
6794 sc->sc_tx_th.wt_tsf = htole64(tsf);
6795 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
6796 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
6797 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6798 if (m0->m_flags & M_FRAG)
6799 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
6800 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
6801 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
6802 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
6804 ieee80211_radiotap_tx(vap, m0);
6808 * Formulate first tx descriptor with tx controls.
6811 /* XXX check return value? */
6812 ath_hal_setuptxdesc(ah, ds
6813 , pktlen /* packet length */
6814 , hdrlen /* header length */
6815 , atype /* Atheros packet type */
6816 , params->ibp_power /* txpower */
6817 , txrate, try0 /* series 0 rate/tries */
6818 , keyix /* key cache index */
6819 , txantenna /* antenna mode */
6821 , ctsrate /* rts/cts rate */
6822 , ctsduration /* rts/cts duration */
6824 bf->bf_txflags = flags;
6827 rix = ath_tx_findrix(sc, params->ibp_rate1);
6828 rate1 = rt->info[rix].rateCode;
6829 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6830 rate1 |= rt->info[rix].shortPreamble;
6831 if (params->ibp_try2) {
6832 rix = ath_tx_findrix(sc, params->ibp_rate2);
6833 rate2 = rt->info[rix].rateCode;
6834 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6835 rate2 |= rt->info[rix].shortPreamble;
6838 if (params->ibp_try3) {
6839 rix = ath_tx_findrix(sc, params->ibp_rate3);
6840 rate3 = rt->info[rix].rateCode;
6841 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6842 rate3 |= rt->info[rix].shortPreamble;
6845 ath_hal_setupxtxdesc(ah, ds
6846 , rate1, params->ibp_try1 /* series 1 */
6847 , rate2, params->ibp_try2 /* series 2 */
6848 , rate3, params->ibp_try3 /* series 3 */
6852 /* NB: no buffered multicast in power save support */
6853 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf);
6858 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
6859 const struct ieee80211_bpf_params *params)
6861 struct ieee80211com *ic = ni->ni_ic;
6862 struct ifnet *ifp = ic->ic_ifp;
6863 struct ath_softc *sc = ifp->if_softc;
6867 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
6868 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
6869 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
6870 "!running" : "invalid");
6876 * Grab a TX buffer and associated resources.
6878 bf = ath_getbuf(sc);
6880 sc->sc_stats.ast_tx_nobuf++;
6886 if (params == NULL) {
6888 * Legacy path; interpret frame contents to decide
6889 * precisely how to send the frame.
6891 if (ath_tx_start(sc, ni, bf, m)) {
6892 error = EIO; /* XXX */
6897 * Caller supplied explicit parameters to use in
6898 * sending the frame.
6900 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
6901 error = EIO; /* XXX */
6905 sc->sc_wd_timer = 5;
6907 sc->sc_stats.ast_tx_raw++;
6912 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
6913 ATH_TXBUF_UNLOCK(sc);
6916 sc->sc_stats.ast_tx_raw_fail++;
6917 ieee80211_free_node(ni);
6922 * Announce various information on device/driver attach.
6925 ath_announce(struct ath_softc *sc)
6927 struct ifnet *ifp = sc->sc_ifp;
6928 struct ath_hal *ah = sc->sc_ah;
6930 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6931 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6932 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6935 for (i = 0; i <= WME_AC_VO; i++) {
6936 struct ath_txq *txq = sc->sc_ac2q[i];
6937 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6938 txq->axq_qnum, ieee80211_wme_acnames[i]);
6940 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6941 sc->sc_cabq->axq_qnum);
6942 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6944 if (ath_rxbuf != ATH_RXBUF)
6945 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6946 if (ath_txbuf != ATH_TXBUF)
6947 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6950 #ifdef IEEE80211_SUPPORT_TDMA
6951 static __inline uint32_t
6952 ath_hal_getnexttbtt(struct ath_hal *ah)
6954 #define AR_TIMER0 0x8028
6955 return OS_REG_READ(ah, AR_TIMER0);
6958 static __inline void
6959 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta)
6961 /* XXX handle wrap/overflow */
6962 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta);
6966 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
6968 struct ath_hal *ah = sc->sc_ah;
6969 HAL_BEACON_TIMERS bt;
6971 bt.bt_intval = bintval | HAL_BEACON_ENA;
6972 bt.bt_nexttbtt = nexttbtt;
6973 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
6974 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
6975 bt.bt_nextatim = nexttbtt+1;
6976 ath_hal_beaconsettimers(ah, &bt);
6980 * Calculate the beacon interval. This is periodic in the
6981 * superframe for the bss. We assume each station is configured
6982 * identically wrt transmit rate so the guard time we calculate
6983 * above will be the same on all stations. Note we need to
6984 * factor in the xmit time because the hardware will schedule
6985 * a frame for transmit if the start of the frame is within
6986 * the burst time. When we get hardware that properly kills
6987 * frames in the PCU we can reduce/eliminate the guard time.
6989 * Roundup to 1024 is so we have 1 TU buffer in the guard time
6990 * to deal with the granularity of the nexttbtt timer. 11n MAC's
6991 * with 1us timer granularity should allow us to reduce/eliminate
6995 ath_tdma_bintvalsetup(struct ath_softc *sc,
6996 const struct ieee80211_tdma_state *tdma)
6998 /* copy from vap state (XXX check all vaps have same value?) */
6999 sc->sc_tdmaslotlen = tdma->tdma_slotlen;
7001 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
7002 tdma->tdma_slotcnt, 1024);
7003 sc->sc_tdmabintval >>= 10; /* TSF -> TU */
7004 if (sc->sc_tdmabintval & 1)
7005 sc->sc_tdmabintval++;
7007 if (tdma->tdma_slot == 0) {
7009 * Only slot 0 beacons; other slots respond.
7011 sc->sc_imask |= HAL_INT_SWBA;
7012 sc->sc_tdmaswba = 0; /* beacon immediately */
7014 /* XXX all vaps must be slot 0 or slot !0 */
7015 sc->sc_imask &= ~HAL_INT_SWBA;
7020 * Max 802.11 overhead. This assumes no 4-address frames and
7021 * the encapsulation done by ieee80211_encap (llc). We also
7022 * include potential crypto overhead.
7024 #define IEEE80211_MAXOVERHEAD \
7025 (sizeof(struct ieee80211_qosframe) \
7026 + sizeof(struct llc) \
7027 + IEEE80211_ADDR_LEN \
7028 + IEEE80211_WEP_IVLEN \
7029 + IEEE80211_WEP_KIDLEN \
7030 + IEEE80211_WEP_CRCLEN \
7031 + IEEE80211_WEP_MICLEN \
7032 + IEEE80211_CRC_LEN)
7035 * Setup initially for tdma operation. Start the beacon
7036 * timers and enable SWBA if we are slot 0. Otherwise
7037 * we wait for slot 0 to arrive so we can sync up before
7038 * starting to transmit.
7041 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
7043 struct ath_hal *ah = sc->sc_ah;
7044 struct ifnet *ifp = sc->sc_ifp;
7045 struct ieee80211com *ic = ifp->if_l2com;
7046 const struct ieee80211_txparam *tp;
7047 const struct ieee80211_tdma_state *tdma = NULL;
7051 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
7053 if_printf(ifp, "%s: no vaps?\n", __func__);
7057 tp = vap->iv_bss->ni_txparms;
7059 * Calculate the guard time for each slot. This is the
7060 * time to send a maximal-size frame according to the
7061 * fixed/lowest transmit rate. Note that the interface
7062 * mtu does not include the 802.11 overhead so we must
7063 * tack that on (ath_hal_computetxtime includes the
7064 * preamble and plcp in it's calculation).
7066 tdma = vap->iv_tdma;
7067 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
7068 rix = ath_tx_findrix(sc, tp->ucastrate);
7070 rix = ath_tx_findrix(sc, tp->mcastrate);
7071 /* XXX short preamble assumed */
7072 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
7073 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
7075 ath_hal_intrset(ah, 0);
7077 ath_beaconq_config(sc); /* setup h/w beacon q */
7079 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */
7080 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */
7081 ath_tdma_settimers(sc, sc->sc_tdmabintval,
7082 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
7083 sc->sc_syncbeacon = 0;
7085 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
7086 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
7088 ath_hal_intrset(ah, sc->sc_imask);
7090 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
7091 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
7092 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
7093 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
7094 sc->sc_tdmadbaprep);
7098 * Update tdma operation. Called from the 802.11 layer
7099 * when a beacon is received from the TDMA station operating
7100 * in the slot immediately preceding us in the bss. Use
7101 * the rx timestamp for the beacon frame to update our
7102 * beacon timers so we follow their schedule. Note that
7103 * by using the rx timestamp we implicitly include the
7104 * propagation delay in our schedule.
7107 ath_tdma_update(struct ieee80211_node *ni,
7108 const struct ieee80211_tdma_param *tdma, int changed)
7110 #define TSF_TO_TU(_h,_l) \
7111 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
7112 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
7113 struct ieee80211vap *vap = ni->ni_vap;
7114 struct ieee80211com *ic = ni->ni_ic;
7115 struct ath_softc *sc = ic->ic_ifp->if_softc;
7116 struct ath_hal *ah = sc->sc_ah;
7117 const HAL_RATE_TABLE *rt = sc->sc_currates;
7118 u_int64_t tsf, rstamp, nextslot;
7119 u_int32_t txtime, nextslottu, timer0;
7120 int32_t tudelta, tsfdelta;
7121 const struct ath_rx_status *rs;
7124 sc->sc_stats.ast_tdma_update++;
7127 * Check for and adopt configuration changes.
7130 const struct ieee80211_tdma_state *ts = vap->iv_tdma;
7132 ath_tdma_bintvalsetup(sc, ts);
7133 if (changed & TDMA_UPDATE_SLOTLEN)
7136 DPRINTF(sc, ATH_DEBUG_TDMA,
7137 "%s: adopt slot %u slotcnt %u slotlen %u us "
7138 "bintval %u TU\n", __func__,
7139 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
7140 sc->sc_tdmabintval);
7143 ath_hal_intrset(ah, sc->sc_imask);
7144 /* NB: beacon timers programmed below */
7147 /* extend rx timestamp to 64 bits */
7149 tsf = ath_hal_gettsf64(ah);
7150 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf);
7152 * The rx timestamp is set by the hardware on completing
7153 * reception (at the point where the rx descriptor is DMA'd
7154 * to the host). To find the start of our next slot we
7155 * must adjust this time by the time required to send
7156 * the packet just received.
7158 rix = rt->rateCodeToIndex[rs->rs_rate];
7159 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
7160 rt->info[rix].shortPreamble);
7161 /* NB: << 9 is to cvt to TU and /2 */
7162 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
7163 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD;
7166 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert
7167 * to usecs and calculate the difference between what the
7168 * other station thinks and what we have programmed. This
7169 * lets us figure how to adjust our timers to match. The
7170 * adjustments are done by pulling the TSF forward and possibly
7171 * rewriting the beacon timers.
7173 timer0 = ath_hal_getnexttbtt(ah);
7174 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0));
7176 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
7177 "tsfdelta %d avg +%d/-%d\n", tsfdelta,
7178 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
7181 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
7182 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
7183 tsfdelta = -tsfdelta % 1024;
7185 } else if (tsfdelta > 0) {
7186 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
7187 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
7188 tsfdelta = 1024 - (tsfdelta % 1024);
7191 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
7192 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
7194 tudelta = nextslottu - timer0;
7197 * Copy sender's timetstamp into tdma ie so they can
7198 * calculate roundtrip time. We submit a beacon frame
7199 * below after any timer adjustment. The frame goes out
7200 * at the next TBTT so the sender can calculate the
7201 * roundtrip by inspecting the tdma ie in our beacon frame.
7203 * NB: This tstamp is subtlely preserved when
7204 * IEEE80211_BEACON_TDMA is marked (e.g. when the
7205 * slot position changes) because ieee80211_add_tdma
7206 * skips over the data.
7208 memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
7209 __offsetof(struct ieee80211_tdma_param, tdma_tstamp),
7210 &ni->ni_tstamp.data, 8);
7212 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
7213 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n",
7214 (unsigned long long) tsf, (unsigned long long) nextslot,
7215 (int)(nextslot - tsf), tsfdelta,
7216 nextslottu, timer0, tudelta);
7219 * Adjust the beacon timers only when pulling them forward
7220 * or when going back by less than the beacon interval.
7221 * Negative jumps larger than the beacon interval seem to
7222 * cause the timers to stop and generally cause instability.
7223 * This basically filters out jumps due to missed beacons.
7225 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
7226 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
7227 sc->sc_stats.ast_tdma_timers++;
7230 ath_hal_adjusttsf(ah, tsfdelta);
7231 sc->sc_stats.ast_tdma_tsf++;
7233 ath_tdma_beacon_send(sc, vap); /* prepare response */
7239 * Transmit a beacon frame at SWBA. Dynamic updates
7240 * to the frame contents are done as needed.
7243 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
7245 struct ath_hal *ah = sc->sc_ah;
7250 * Check if the previous beacon has gone out. If
7251 * not don't try to post another, skip this period
7252 * and wait for the next. Missed beacons indicate
7253 * a problem and should not occur. If we miss too
7254 * many consecutive beacons reset the device.
7256 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
7257 sc->sc_bmisscount++;
7258 DPRINTF(sc, ATH_DEBUG_BEACON,
7259 "%s: missed %u consecutive beacons\n",
7260 __func__, sc->sc_bmisscount);
7261 if (sc->sc_bmisscount >= ath_bstuck_threshold)
7262 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
7265 if (sc->sc_bmisscount != 0) {
7266 DPRINTF(sc, ATH_DEBUG_BEACON,
7267 "%s: resume beacon xmit after %u misses\n",
7268 __func__, sc->sc_bmisscount);
7269 sc->sc_bmisscount = 0;
7273 * Check recent per-antenna transmit statistics and flip
7274 * the default antenna if noticeably more frames went out
7275 * on the non-default antenna.
7276 * XXX assumes 2 anntenae
7278 if (!sc->sc_diversity) {
7279 otherant = sc->sc_defant & 1 ? 2 : 1;
7280 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
7281 ath_setdefantenna(sc, otherant);
7282 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
7285 bf = ath_beacon_generate(sc, vap);
7288 * Stop any current dma and put the new frame on the queue.
7289 * This should never fail since we check above that no frames
7290 * are still pending on the queue.
7292 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
7293 DPRINTF(sc, ATH_DEBUG_ANY,
7294 "%s: beacon queue %u did not stop?\n",
7295 __func__, sc->sc_bhalq);
7296 /* NB: the HAL still stops DMA, so proceed */
7298 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
7299 ath_hal_txstart(ah, sc->sc_bhalq);
7301 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */
7304 * Record local TSF for our last send for use
7305 * in arbitrating slot collisions.
7307 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
7310 #endif /* IEEE80211_SUPPORT_TDMA */