sys/dev/drm/radeon_cp.c

   1 /*-
   2  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * Copyright 2007 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "dev/drm/drmP.h"
  35 #include "dev/drm/drm.h"
  36 #include "dev/drm/drm_sarea.h"
  37 #include "dev/drm/radeon_drm.h"
  38 #include "dev/drm/radeon_drv.h"
  39 #include "dev/drm/r300_reg.h"
  40
  41 #include "dev/drm/radeon_microcode.h"
  42
  43 #define RADEON_FIFO_DEBUG       0
  44
  45 static int radeon_do_cleanup_cp(struct drm_device * dev);
  46 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  47
  48 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  49 {
  50         u32 val;
  51
  52         if (dev_priv->flags & RADEON_IS_AGP) {
  53                 val = DRM_READ32(dev_priv->ring_rptr, off);
  54         } else {
  55                 val = *(((volatile u32 *)
  56                          dev_priv->ring_rptr->handle) +
  57                         (off / sizeof(u32)));
  58                 val = le32_to_cpu(val);
  59         }
  60         return val;
  61 }
  62
  63 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  64 {
  65         if (dev_priv->writeback_works)
  66                 return radeon_read_ring_rptr(dev_priv, 0);
  67         else {
  68                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  69                         return RADEON_READ(R600_CP_RB_RPTR);
  70                 else
  71                         return RADEON_READ(RADEON_CP_RB_RPTR);
  72         }
  73 }
  74
  75 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  76 {
  77         if (dev_priv->flags & RADEON_IS_AGP)
  78                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  79         else
  80                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  81                   (off / sizeof(u32))) = cpu_to_le32(val);
  82 }
  83
  84 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  85 {
  86         radeon_write_ring_rptr(dev_priv, 0, val);
  87 }
  88
  89 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  90 {
  91         if (dev_priv->writeback_works) {
  92                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  93                         return radeon_read_ring_rptr(dev_priv,
  94                                                      R600_SCRATCHOFF(index));
  95                 else
  96                         return radeon_read_ring_rptr(dev_priv,
  97                                                      RADEON_SCRATCHOFF(index));
  98         } else {
  99                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 100                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 101                 else
 102                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 103         }
 104 }
 105
 106 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 107 {
 108         u32 ret;
 109
 110         if (addr < 0x10000)
 111                 ret = DRM_READ32(dev_priv->mmio, addr);
 112         else {
 113                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 114                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 115         }
 116
 117         return ret;
 118 }
 119
 120 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 121 {
 122         u32 ret;
 123         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 124         ret = RADEON_READ(R520_MC_IND_DATA);
 125         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 126         return ret;
 127 }
 128
 129 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 130 {
 131         u32 ret;
 132         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 133         ret = RADEON_READ(RS480_NB_MC_DATA);
 134         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 135         return ret;
 136 }
 137
 138 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 139 {
 140         u32 ret;
 141         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 142         ret = RADEON_READ(RS690_MC_DATA);
 143         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 144         return ret;
 145 }
 146
 147 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 148 {
 149         u32 ret;
 150         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 151                                       RS600_MC_IND_CITF_ARB0));
 152         ret = RADEON_READ(RS600_MC_DATA);
 153         return ret;
 154 }
 155
 156 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 157 {
 158         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 159             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 160                 return RS690_READ_MCIND(dev_priv, addr);
 161         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 162                 return RS600_READ_MCIND(dev_priv, addr);
 163         else
 164                 return RS480_READ_MCIND(dev_priv, addr);
 165 }
 166
 167 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 168 {
 169
 170         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 171                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 172         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 173                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 175                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 176         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 177                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 178                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 179         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 180                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 181         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 182                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 183         else
 184                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 185 }
 186
 187 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 188 {
 189         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 190                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 191         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 192                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 193         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 194                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 195         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 196                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 197                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 198         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 199                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 200         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 201                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 202         else
 203                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 204 }
 205
 206 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 207 {
 208         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 209         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 210                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 211                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 212         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 213                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 214                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 215         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 216                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 217         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 218                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 219                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 220         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 221                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 222         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 223                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 224         else
 225                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 226 }
 227
 228 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 229 {
 230         u32 agp_base_hi = upper_32_bits(agp_base);
 231         u32 agp_base_lo = agp_base & 0xffffffff;
 232         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 233
 234         /* R6xx/R7xx must be aligned to a 4MB boundry */
 235         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 236                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 237         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 238                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 239         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 240                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 241                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 242         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 243                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 244                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 245                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 246         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 247                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 248                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 249         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 250                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 251                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 252         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 253                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 254                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 255                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 256         } else {
 257                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 258                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 259                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 260         }
 261 }
 262
 263 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 264 {
 265         u32 tmp;
 266         /* Turn on bus mastering */
 267         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 268             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 269                 /* rs600/rs690/rs740 */
 270                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 271                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 272         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 273                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 274                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 275                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 276                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 277                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 278                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 279         } /* PCIE cards appears to not need this */
 280 }
 281
 282 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 283 {
 284         drm_radeon_private_t *dev_priv = dev->dev_private;
 285
 286         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 287         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 288 }
 289
 290 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 291 {
 292         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 293         return RADEON_READ(RADEON_PCIE_DATA);
 294 }
 295
 296 #if RADEON_FIFO_DEBUG
 297 static void radeon_status(drm_radeon_private_t * dev_priv)
 298 {
 299         printk("%s:\n", __func__);
 300         printk("RBBM_STATUS = 0x%08x\n",
 301                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 302         printk("CP_RB_RTPR = 0x%08x\n",
 303                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 304         printk("CP_RB_WTPR = 0x%08x\n",
 305                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 306         printk("AIC_CNTL = 0x%08x\n",
 307                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 308         printk("AIC_STAT = 0x%08x\n",
 309                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 310         printk("AIC_PT_BASE = 0x%08x\n",
 311                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 312         printk("TLB_ADDR = 0x%08x\n",
 313                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 314         printk("TLB_DATA = 0x%08x\n",
 315                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 316 }
 317 #endif
 318
 319 /* ================================================================
 320  * Engine, FIFO control
 321  */
 322
 323 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 324 {
 325         u32 tmp;
 326         int i;
 327
 328         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 329
 330         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 331                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 332                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 333                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 334
 335                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 336                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 337                               & RADEON_RB3D_DC_BUSY)) {
 338                                 return 0;
 339                         }
 340                         DRM_UDELAY(1);
 341                 }
 342         } else {
 343                 /* don't flush or purge cache here or lockup */
 344                 return 0;
 345         }
 346
 347 #if RADEON_FIFO_DEBUG
 348         DRM_ERROR("failed!\n");
 349         radeon_status(dev_priv);
 350 #endif
 351         return -EBUSY;
 352 }
 353
 354 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 355 {
 356         int i;
 357
 358         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 359
 360         for (i = 0; i < dev_priv->usec_timeout; i++) {
 361                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 362                              & RADEON_RBBM_FIFOCNT_MASK);
 363                 if (slots >= entries)
 364                         return 0;
 365                 DRM_UDELAY(1);
 366         }
 367         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 368                  RADEON_READ(RADEON_RBBM_STATUS),
 369                  RADEON_READ(R300_VAP_CNTL_STATUS));
 370
 371 #if RADEON_FIFO_DEBUG
 372         DRM_ERROR("failed!\n");
 373         radeon_status(dev_priv);
 374 #endif
 375         return -EBUSY;
 376 }
 377
 378 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 379 {
 380         int i, ret;
 381
 382         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 383
 384         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 385         if (ret)
 386                 return ret;
 387
 388         for (i = 0; i < dev_priv->usec_timeout; i++) {
 389                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 390                       & RADEON_RBBM_ACTIVE)) {
 391                         radeon_do_pixcache_flush(dev_priv);
 392                         return 0;
 393                 }
 394                 DRM_UDELAY(1);
 395         }
 396         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 397                  RADEON_READ(RADEON_RBBM_STATUS),
 398                  RADEON_READ(R300_VAP_CNTL_STATUS));
 399
 400 #if RADEON_FIFO_DEBUG
 401         DRM_ERROR("failed!\n");
 402         radeon_status(dev_priv);
 403 #endif
 404         return -EBUSY;
 405 }
 406
 407 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 408 {
 409         uint32_t gb_tile_config, gb_pipe_sel = 0;
 410
 411         /* RS4xx/RS6xx/R4xx/R5xx */
 412         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 413                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 414                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 415         } else {
 416                 /* R3xx */
 417                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 418                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 419                         dev_priv->num_gb_pipes = 2;
 420                 } else {
 421                         /* R3Vxx */
 422                         dev_priv->num_gb_pipes = 1;
 423                 }
 424         }
 425         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 426
 427         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 428
 429         switch (dev_priv->num_gb_pipes) {
 430         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 431         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 432         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 433         default:
 434         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 435         }
 436
 437         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 438                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 439                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 440         }
 441         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 442         radeon_do_wait_for_idle(dev_priv);
 443         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 444         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 445                                                R300_DC_AUTOFLUSH_ENABLE |
 446                                                R300_DC_DC_DISABLE_IGNORE_PE));
 447
 448
 449 }
 450
 451 /* ================================================================
 452  * CP control, initialization
 453  */
 454
 455 /* Load the microcode for the CP */
 456 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 457 {
 458         const u32 (*cp)[2];
 459         int i;
 460
 461         DRM_DEBUG("\n");
 462
 463         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 464         case CHIP_R100:
 465         case CHIP_RV100:
 466         case CHIP_RV200:
 467         case CHIP_RS100:
 468         case CHIP_RS200:
 469                 DRM_INFO("Loading R100 Microcode\n");
 470                 cp = R100_cp_microcode;
 471                 break;
 472         case CHIP_R200:
 473         case CHIP_RV250:
 474         case CHIP_RV280:
 475         case CHIP_RS300:
 476                 DRM_INFO("Loading R200 Microcode\n");
 477                 cp = R200_cp_microcode;
 478                 break;
 479         case CHIP_R300:
 480         case CHIP_R350:
 481         case CHIP_RV350:
 482         case CHIP_RV380:
 483         case CHIP_RS400:
 484         case CHIP_RS480:
 485                 DRM_INFO("Loading R300 Microcode\n");
 486                 cp = R300_cp_microcode;
 487                 break;
 488         case CHIP_R420:
 489         case CHIP_R423:
 490         case CHIP_RV410:
 491                 DRM_INFO("Loading R400 Microcode\n");
 492                 cp = R420_cp_microcode;
 493                 break;
 494         case CHIP_RS690:
 495         case CHIP_RS740:
 496                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 497                 cp = RS690_cp_microcode;
 498                 break;
 499         case CHIP_RS600:
 500                 DRM_INFO("Loading RS600 Microcode\n");
 501                 cp = RS600_cp_microcode;
 502                 break;
 503         case CHIP_RV515:
 504         case CHIP_R520:
 505         case CHIP_RV530:
 506         case CHIP_R580:
 507         case CHIP_RV560:
 508         case CHIP_RV570:
 509                 DRM_INFO("Loading R500 Microcode\n");
 510                 cp = R520_cp_microcode;
 511                 break;
 512         default:
 513                 return;
 514         }
 515
 516         radeon_do_wait_for_idle(dev_priv);
 517
 518         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 519
 520         for (i = 0; i != 256; i++) {
 521                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
 522                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
 523         }
 524 }
 525
 526 /* Flush any pending commands to the CP.  This should only be used just
 527  * prior to a wait for idle, as it informs the engine that the command
 528  * stream is ending.
 529  */
 530 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 531 {
 532         DRM_DEBUG("\n");
 533 #if 0
 534         u32 tmp;
 535
 536         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 537         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 538 #endif
 539 }
 540
 541 /* Wait for the CP to go idle.
 542  */
 543 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 544 {
 545         RING_LOCALS;
 546         DRM_DEBUG("\n");
 547
 548         BEGIN_RING(6);
 549
 550         RADEON_PURGE_CACHE();
 551         RADEON_PURGE_ZCACHE();
 552         RADEON_WAIT_UNTIL_IDLE();
 553
 554         ADVANCE_RING();
 555         COMMIT_RING();
 556
 557         return radeon_do_wait_for_idle(dev_priv);
 558 }
 559
 560 /* Start the Command Processor.
 561  */
 562 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 563 {
 564         RING_LOCALS;
 565         DRM_DEBUG("\n");
 566
 567         radeon_do_wait_for_idle(dev_priv);
 568
 569         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 570
 571         dev_priv->cp_running = 1;
 572
 573         BEGIN_RING(8);
 574         /* isync can only be written through cp on r5xx write it here */
 575         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 576         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 577                  RADEON_ISYNC_ANY3D_IDLE2D |
 578                  RADEON_ISYNC_WAIT_IDLEGUI |
 579                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 580         RADEON_PURGE_CACHE();
 581         RADEON_PURGE_ZCACHE();
 582         RADEON_WAIT_UNTIL_IDLE();
 583         ADVANCE_RING();
 584         COMMIT_RING();
 585
 586         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 587 }
 588
 589 /* Reset the Command Processor.  This will not flush any pending
 590  * commands, so you must wait for the CP command stream to complete
 591  * before calling this routine.
 592  */
 593 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 594 {
 595         u32 cur_read_ptr;
 596         DRM_DEBUG("\n");
 597
 598         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 599         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 600         SET_RING_HEAD(dev_priv, cur_read_ptr);
 601         dev_priv->ring.tail = cur_read_ptr;
 602 }
 603
 604 /* Stop the Command Processor.  This will not flush any pending
 605  * commands, so you must flush the command stream and wait for the CP
 606  * to go idle before calling this routine.
 607  */
 608 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 609 {
 610         DRM_DEBUG("\n");
 611
 612         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 613
 614         dev_priv->cp_running = 0;
 615 }
 616
 617 /* Reset the engine.  This will stop the CP if it is running.
 618  */
 619 static int radeon_do_engine_reset(struct drm_device * dev)
 620 {
 621         drm_radeon_private_t *dev_priv = dev->dev_private;
 622         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 623         DRM_DEBUG("\n");
 624
 625         radeon_do_pixcache_flush(dev_priv);
 626
 627         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 628                 /* may need something similar for newer chips */
 629                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 630                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 631
 632                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 633                                                     RADEON_FORCEON_MCLKA |
 634                                                     RADEON_FORCEON_MCLKB |
 635                                                     RADEON_FORCEON_YCLKA |
 636                                                     RADEON_FORCEON_YCLKB |
 637                                                     RADEON_FORCEON_MC |
 638                                                     RADEON_FORCEON_AIC));
 639         }
 640
 641         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 642
 643         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 644                                               RADEON_SOFT_RESET_CP |
 645                                               RADEON_SOFT_RESET_HI |
 646                                               RADEON_SOFT_RESET_SE |
 647                                               RADEON_SOFT_RESET_RE |
 648                                               RADEON_SOFT_RESET_PP |
 649                                               RADEON_SOFT_RESET_E2 |
 650                                               RADEON_SOFT_RESET_RB));
 651         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 652         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 653                                               ~(RADEON_SOFT_RESET_CP |
 654                                                 RADEON_SOFT_RESET_HI |
 655                                                 RADEON_SOFT_RESET_SE |
 656                                                 RADEON_SOFT_RESET_RE |
 657                                                 RADEON_SOFT_RESET_PP |
 658                                                 RADEON_SOFT_RESET_E2 |
 659                                                 RADEON_SOFT_RESET_RB)));
 660         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 661
 662         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 663                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 664                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 665                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 666         }
 667
 668         /* setup the raster pipes */
 669         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 670             radeon_init_pipes(dev_priv);
 671
 672         /* Reset the CP ring */
 673         radeon_do_cp_reset(dev_priv);
 674
 675         /* The CP is no longer running after an engine reset */
 676         dev_priv->cp_running = 0;
 677
 678         /* Reset any pending vertex, indirect buffers */
 679         radeon_freelist_reset(dev);
 680
 681         return 0;
 682 }
 683
 684 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 685                                        drm_radeon_private_t *dev_priv,
 686                                        struct drm_file *file_priv)
 687 {
 688         u32 ring_start, cur_read_ptr;
 689
 690         /* Initialize the memory controller. With new memory map, the fb location
 691          * is not changed, it should have been properly initialized already. Part
 692          * of the problem is that the code below is bogus, assuming the GART is
 693          * always appended to the fb which is not necessarily the case
 694          */
 695         if (!dev_priv->new_memmap)
 696                 radeon_write_fb_location(dev_priv,
 697                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 698                              | (dev_priv->fb_location >> 16));
 699
 700 #if __OS_HAS_AGP
 701         if (dev_priv->flags & RADEON_IS_AGP) {
 702                 radeon_write_agp_base(dev_priv, dev->agp->base);
 703
 704                 radeon_write_agp_location(dev_priv,
 705                              (((dev_priv->gart_vm_start - 1 +
 706                                 dev_priv->gart_size) & 0xffff0000) |
 707                               (dev_priv->gart_vm_start >> 16)));
 708
 709                 ring_start = (dev_priv->cp_ring->offset
 710                               - dev->agp->base
 711                               + dev_priv->gart_vm_start);
 712         } else
 713 #endif
 714                 ring_start = (dev_priv->cp_ring->offset
 715                               - (unsigned long)dev->sg->virtual
 716                               + dev_priv->gart_vm_start);
 717
 718         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 719
 720         /* Set the write pointer delay */
 721         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 722
 723         /* Initialize the ring buffer's read and write pointers */
 724         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 725         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 726         SET_RING_HEAD(dev_priv, cur_read_ptr);
 727         dev_priv->ring.tail = cur_read_ptr;
 728
 729 #if __OS_HAS_AGP
 730         if (dev_priv->flags & RADEON_IS_AGP) {
 731                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 732                              dev_priv->ring_rptr->offset
 733                              - dev->agp->base + dev_priv->gart_vm_start);
 734         } else
 735 #endif
 736         {
 737                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 738                              dev_priv->ring_rptr->offset
 739                              - ((unsigned long) dev->sg->virtual)
 740                              + dev_priv->gart_vm_start);
 741         }
 742
 743         /* Set ring buffer size */
 744 #ifdef __BIG_ENDIAN
 745         RADEON_WRITE(RADEON_CP_RB_CNTL,
 746                      RADEON_BUF_SWAP_32BIT |
 747                      (dev_priv->ring.fetch_size_l2ow << 18) |
 748                      (dev_priv->ring.rptr_update_l2qw << 8) |
 749                      dev_priv->ring.size_l2qw);
 750 #else
 751         RADEON_WRITE(RADEON_CP_RB_CNTL,
 752                      (dev_priv->ring.fetch_size_l2ow << 18) |
 753                      (dev_priv->ring.rptr_update_l2qw << 8) |
 754                      dev_priv->ring.size_l2qw);
 755 #endif
 756
 757
 758         /* Initialize the scratch register pointer.  This will cause
 759          * the scratch register values to be written out to memory
 760          * whenever they are updated.
 761          *
 762          * We simply put this behind the ring read pointer, this works
 763          * with PCI GART as well as (whatever kind of) AGP GART
 764          */
 765         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 766                      + RADEON_SCRATCH_REG_OFFSET);
 767
 768         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 769
 770         radeon_enable_bm(dev_priv);
 771
 772         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 773         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 774
 775         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 776         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 777
 778         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 779         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 780
 781         /* reset sarea copies of these */
 782         if (dev_priv->sarea_priv) {
 783                 dev_priv->sarea_priv->last_frame = 0;
 784                 dev_priv->sarea_priv->last_dispatch = 0;
 785                 dev_priv->sarea_priv->last_clear = 0;
 786         }
 787
 788         radeon_do_wait_for_idle(dev_priv);
 789
 790         /* Sync everything up */
 791         RADEON_WRITE(RADEON_ISYNC_CNTL,
 792                      (RADEON_ISYNC_ANY2D_IDLE3D |
 793                       RADEON_ISYNC_ANY3D_IDLE2D |
 794                       RADEON_ISYNC_WAIT_IDLEGUI |
 795                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 796
 797 }
 798
 799 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 800 {
 801         u32 tmp;
 802
 803         /* Start with assuming that writeback doesn't work */
 804         dev_priv->writeback_works = 0;
 805
 806         /* Writeback doesn't seem to work everywhere, test it here and possibly
 807          * enable it if it appears to work
 808          */
 809         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 810
 811         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 812
 813         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 814                 u32 val;
 815
 816                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 817                 if (val == 0xdeadbeef)
 818                         break;
 819                 DRM_UDELAY(1);
 820         }
 821
 822         if (tmp < dev_priv->usec_timeout) {
 823                 dev_priv->writeback_works = 1;
 824                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 825         } else {
 826                 dev_priv->writeback_works = 0;
 827                 DRM_INFO("writeback test failed\n");
 828         }
 829         if (radeon_no_wb == 1) {
 830                 dev_priv->writeback_works = 0;
 831                 DRM_INFO("writeback forced off\n");
 832         }
 833
 834         if (!dev_priv->writeback_works) {
 835                 /* Disable writeback to avoid unnecessary bus master transfer */
 836                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 837                              RADEON_RB_NO_UPDATE);
 838                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 839         }
 840 }
 841
 842 /* Enable or disable IGP GART on the chip */
 843 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 844 {
 845         u32 temp;
 846
 847         if (on) {
 848                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 849                           dev_priv->gart_vm_start,
 850                           (long)dev_priv->gart_info.bus_addr,
 851                           dev_priv->gart_size);
 852
 853                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 854                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 855                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 856                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 857                                                              RS690_BLOCK_GFX_D3_EN));
 858                 else
 859                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 860
 861                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 862                                                                RS480_VA_SIZE_32MB));
 863
 864                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 865                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 866                                                         RS480_TLB_ENABLE |
 867                                                         RS480_GTW_LAC_EN |
 868                                                         RS480_1LEVEL_GART));
 869
 870                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 871                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 872                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 873
 874                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 875                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 876                                                       RS480_REQ_TYPE_SNOOP_DIS));
 877
 878                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 879
 880                 dev_priv->gart_size = 32*1024*1024;
 881                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 882                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 883
 884                 radeon_write_agp_location(dev_priv, temp);
 885
 886                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 887                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 888                                                                RS480_VA_SIZE_32MB));
 889
 890                 do {
 891                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 892                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 893                                 break;
 894                         DRM_UDELAY(1);
 895                 } while (1);
 896
 897                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 898                                 RS480_GART_CACHE_INVALIDATE);
 899
 900                 do {
 901                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 902                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 903                                 break;
 904                         DRM_UDELAY(1);
 905                 } while (1);
 906
 907                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 908         } else {
 909                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 910         }
 911 }
 912
 913 /* Enable or disable IGP GART on the chip */
 914 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 915 {
 916         u32 temp;
 917         int i;
 918
 919         if (on) {
 920                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 921                          dev_priv->gart_vm_start,
 922                          (long)dev_priv->gart_info.bus_addr,
 923                          dev_priv->gart_size);
 924
 925                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 926                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 927
 928                 for (i = 0; i < 19; i++)
 929                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 930                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 931                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 932                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 933                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 934                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 935                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 936
 937                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 938                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 939
 940                 /* disable all other contexts */
 941                 for (i = 1; i < 8; i++)
 942                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 943
 944                 /* setup the page table aperture */
 945                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 946                                 dev_priv->gart_info.bus_addr);
 947                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
 948                                 dev_priv->gart_vm_start);
 949                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
 950                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 951                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 952
 953                 /* setup the system aperture */
 954                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
 955                                 dev_priv->gart_vm_start);
 956                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
 957                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 958
 959                 /* enable page tables */
 960                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 961                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
 962
 963                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 964                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
 965
 966                 /* invalidate the cache */
 967                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 968
 969                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 970                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 971                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 972
 973                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
 974                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 975                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 976
 977                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 978                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 979                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 980
 981         } else {
 982                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
 983                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 984                 temp &= ~RS600_ENABLE_PAGE_TABLES;
 985                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
 986         }
 987 }
 988
 989 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 990 {
 991         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 992         if (on) {
 993
 994                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 995                           dev_priv->gart_vm_start,
 996                           (long)dev_priv->gart_info.bus_addr,
 997                           dev_priv->gart_size);
 998                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 999                                   dev_priv->gart_vm_start);
1000                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1001                                   dev_priv->gart_info.bus_addr);
1002                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1003                                   dev_priv->gart_vm_start);
1004                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1005                                   dev_priv->gart_vm_start +
1006                                   dev_priv->gart_size - 1);
1007
1008                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1009
1010                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1011                                   RADEON_PCIE_TX_GART_EN);
1012         } else {
1013                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1014                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1015         }
1016 }
1017
1018 /* Enable or disable PCI GART on the chip */
1019 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1020 {
1021         u32 tmp;
1022
1023         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1024             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1025             (dev_priv->flags & RADEON_IS_IGPGART)) {
1026                 radeon_set_igpgart(dev_priv, on);
1027                 return;
1028         }
1029
1030         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1031                 rs600_set_igpgart(dev_priv, on);
1032                 return;
1033         }
1034
1035         if (dev_priv->flags & RADEON_IS_PCIE) {
1036                 radeon_set_pciegart(dev_priv, on);
1037                 return;
1038         }
1039
1040         tmp = RADEON_READ(RADEON_AIC_CNTL);
1041
1042         if (on) {
1043                 RADEON_WRITE(RADEON_AIC_CNTL,
1044                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1045
1046                 /* set PCI GART page-table base address
1047                  */
1048                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1049
1050                 /* set address range for PCI address translate
1051                  */
1052                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1053                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1054                              + dev_priv->gart_size - 1);
1055
1056                 /* Turn off AGP aperture -- is this required for PCI GART?
1057                  */
1058                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1059                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1060         } else {
1061                 RADEON_WRITE(RADEON_AIC_CNTL,
1062                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1063         }
1064 }
1065
1066 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1067 {
1068         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1069         struct radeon_virt_surface *vp;
1070         int i;
1071
1072         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1073                 if (!dev_priv->virt_surfaces[i].file_priv ||
1074                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1075                         break;
1076         }
1077         if (i >= 2 * RADEON_MAX_SURFACES)
1078                 return -ENOMEM;
1079         vp = &dev_priv->virt_surfaces[i];
1080
1081         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1082                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1083                 if (sp->refcount)
1084                         continue;
1085
1086                 vp->surface_index = i;
1087                 vp->lower = gart_info->bus_addr;
1088                 vp->upper = vp->lower + gart_info->table_size;
1089                 vp->flags = 0;
1090                 vp->file_priv = PCIGART_FILE_PRIV;
1091
1092                 sp->refcount = 1;
1093                 sp->lower = vp->lower;
1094                 sp->upper = vp->upper;
1095                 sp->flags = 0;
1096
1097                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1098                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1099                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1100                 return 0;
1101         }
1102
1103         return -ENOMEM;
1104 }
1105
1106 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1107                              struct drm_file *file_priv)
1108 {
1109         drm_radeon_private_t *dev_priv = dev->dev_private;
1110
1111         DRM_DEBUG("\n");
1112
1113         /* if we require new memory map but we don't have it fail */
1114         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1115                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1116                 radeon_do_cleanup_cp(dev);
1117                 return -EINVAL;
1118         }
1119
1120         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1121                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1122                 dev_priv->flags &= ~RADEON_IS_AGP;
1123         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1124                    && !init->is_pci) {
1125                 DRM_DEBUG("Restoring AGP flag\n");
1126                 dev_priv->flags |= RADEON_IS_AGP;
1127         }
1128
1129         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1130                 DRM_ERROR("PCI GART memory not allocated!\n");
1131                 radeon_do_cleanup_cp(dev);
1132                 return -EINVAL;
1133         }
1134
1135         dev_priv->usec_timeout = init->usec_timeout;
1136         if (dev_priv->usec_timeout < 1 ||
1137             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1138                 DRM_DEBUG("TIMEOUT problem!\n");
1139                 radeon_do_cleanup_cp(dev);
1140                 return -EINVAL;
1141         }
1142
1143         /* Enable vblank on CRTC1 for older X servers
1144          */
1145         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1146
1147         switch(init->func) {
1148         case RADEON_INIT_R200_CP:
1149                 dev_priv->microcode_version = UCODE_R200;
1150                 break;
1151         case RADEON_INIT_R300_CP:
1152                 dev_priv->microcode_version = UCODE_R300;
1153                 break;
1154         default:
1155                 dev_priv->microcode_version = UCODE_R100;
1156         }
1157
1158         dev_priv->do_boxes = 0;
1159         dev_priv->cp_mode = init->cp_mode;
1160
1161         /* We don't support anything other than bus-mastering ring mode,
1162          * but the ring can be in either AGP or PCI space for the ring
1163          * read pointer.
1164          */
1165         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1166             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1167                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1168                 radeon_do_cleanup_cp(dev);
1169                 return -EINVAL;
1170         }
1171
1172         switch (init->fb_bpp) {
1173         case 16:
1174                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1175                 break;
1176         case 32:
1177         default:
1178                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1179                 break;
1180         }
1181         dev_priv->front_offset = init->front_offset;
1182         dev_priv->front_pitch = init->front_pitch;
1183         dev_priv->back_offset = init->back_offset;
1184         dev_priv->back_pitch = init->back_pitch;
1185
1186         switch (init->depth_bpp) {
1187         case 16:
1188                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1189                 break;
1190         case 32:
1191         default:
1192                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1193                 break;
1194         }
1195         dev_priv->depth_offset = init->depth_offset;
1196         dev_priv->depth_pitch = init->depth_pitch;
1197
1198         /* Hardware state for depth clears.  Remove this if/when we no
1199          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1200          * all values to prevent unwanted 3D state from slipping through
1201          * and screwing with the clear operation.
1202          */
1203         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1204                                            (dev_priv->color_fmt << 10) |
1205                                            (dev_priv->microcode_version ==
1206                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1207
1208         dev_priv->depth_clear.rb3d_zstencilcntl =
1209             (dev_priv->depth_fmt |
1210              RADEON_Z_TEST_ALWAYS |
1211              RADEON_STENCIL_TEST_ALWAYS |
1212              RADEON_STENCIL_S_FAIL_REPLACE |
1213              RADEON_STENCIL_ZPASS_REPLACE |
1214              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1215
1216         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1217                                          RADEON_BFACE_SOLID |
1218                                          RADEON_FFACE_SOLID |
1219                                          RADEON_FLAT_SHADE_VTX_LAST |
1220                                          RADEON_DIFFUSE_SHADE_FLAT |
1221                                          RADEON_ALPHA_SHADE_FLAT |
1222                                          RADEON_SPECULAR_SHADE_FLAT |
1223                                          RADEON_FOG_SHADE_FLAT |
1224                                          RADEON_VTX_PIX_CENTER_OGL |
1225                                          RADEON_ROUND_MODE_TRUNC |
1226                                          RADEON_ROUND_PREC_8TH_PIX);
1227
1228
1229         dev_priv->ring_offset = init->ring_offset;
1230         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1231         dev_priv->buffers_offset = init->buffers_offset;
1232         dev_priv->gart_textures_offset = init->gart_textures_offset;
1233
1234         dev_priv->sarea = drm_getsarea(dev);
1235         if (!dev_priv->sarea) {
1236                 DRM_ERROR("could not find sarea!\n");
1237                 radeon_do_cleanup_cp(dev);
1238                 return -EINVAL;
1239         }
1240
1241         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1242         if (!dev_priv->cp_ring) {
1243                 DRM_ERROR("could not find cp ring region!\n");
1244                 radeon_do_cleanup_cp(dev);
1245                 return -EINVAL;
1246         }
1247         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1248         if (!dev_priv->ring_rptr) {
1249                 DRM_ERROR("could not find ring read pointer!\n");
1250                 radeon_do_cleanup_cp(dev);
1251                 return -EINVAL;
1252         }
1253         dev->agp_buffer_token = init->buffers_offset;
1254         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1255         if (!dev->agp_buffer_map) {
1256                 DRM_ERROR("could not find dma buffer region!\n");
1257                 radeon_do_cleanup_cp(dev);
1258                 return -EINVAL;
1259         }
1260
1261         if (init->gart_textures_offset) {
1262                 dev_priv->gart_textures =
1263                     drm_core_findmap(dev, init->gart_textures_offset);
1264                 if (!dev_priv->gart_textures) {
1265                         DRM_ERROR("could not find GART texture region!\n");
1266                         radeon_do_cleanup_cp(dev);
1267                         return -EINVAL;
1268                 }
1269         }
1270
1271         dev_priv->sarea_priv =
1272             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1273                                     init->sarea_priv_offset);
1274
1275 #if __OS_HAS_AGP
1276         if (dev_priv->flags & RADEON_IS_AGP) {
1277                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1278                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1279                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1280                 if (!dev_priv->cp_ring->handle ||
1281                     !dev_priv->ring_rptr->handle ||
1282                     !dev->agp_buffer_map->handle) {
1283                         DRM_ERROR("could not find ioremap agp regions!\n");
1284                         radeon_do_cleanup_cp(dev);
1285                         return -EINVAL;
1286                 }
1287         } else
1288 #endif
1289         {
1290                 dev_priv->cp_ring->handle =
1291                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1292                 dev_priv->ring_rptr->handle =
1293                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1294                 dev->agp_buffer_map->handle =
1295                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1296
1297                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1298                           dev_priv->cp_ring->handle);
1299                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1300                           dev_priv->ring_rptr->handle);
1301                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1302                           dev->agp_buffer_map->handle);
1303         }
1304
1305         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1306         dev_priv->fb_size =
1307                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1308                 - dev_priv->fb_location;
1309
1310         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1311                                         ((dev_priv->front_offset
1312                                           + dev_priv->fb_location) >> 10));
1313
1314         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1315                                        ((dev_priv->back_offset
1316                                          + dev_priv->fb_location) >> 10));
1317
1318         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1319                                         ((dev_priv->depth_offset
1320                                           + dev_priv->fb_location) >> 10));
1321
1322         dev_priv->gart_size = init->gart_size;
1323
1324         /* New let's set the memory map ... */
1325         if (dev_priv->new_memmap) {
1326                 u32 base = 0;
1327
1328                 DRM_INFO("Setting GART location based on new memory map\n");
1329
1330                 /* If using AGP, try to locate the AGP aperture at the same
1331                  * location in the card and on the bus, though we have to
1332                  * align it down.
1333                  */
1334 #if __OS_HAS_AGP
1335                 if (dev_priv->flags & RADEON_IS_AGP) {
1336                         base = dev->agp->base;
1337                         /* Check if valid */
1338                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1339                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1340                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1341                                          dev->agp->base);
1342                                 base = 0;
1343                         }
1344                 }
1345 #endif
1346                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1347                 if (base == 0) {
1348                         base = dev_priv->fb_location + dev_priv->fb_size;
1349                         if (base < dev_priv->fb_location ||
1350                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1351                                 base = dev_priv->fb_location
1352                                         - dev_priv->gart_size;
1353                 }
1354                 dev_priv->gart_vm_start = base & 0xffc00000u;
1355                 if (dev_priv->gart_vm_start != base)
1356                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1357                                  base, dev_priv->gart_vm_start);
1358         } else {
1359                 DRM_INFO("Setting GART location based on old memory map\n");
1360                 dev_priv->gart_vm_start = dev_priv->fb_location +
1361                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1362         }
1363
1364 #if __OS_HAS_AGP
1365         if (dev_priv->flags & RADEON_IS_AGP)
1366                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1367                                                  - dev->agp->base
1368                                                  + dev_priv->gart_vm_start);
1369         else
1370 #endif
1371                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1372                                         - (unsigned long)dev->sg->virtual
1373                                         + dev_priv->gart_vm_start);
1374
1375         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1376         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1377         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1378                   dev_priv->gart_buffers_offset);
1379
1380         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1381         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1382                               + init->ring_size / sizeof(u32));
1383         dev_priv->ring.size = init->ring_size;
1384         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1385
1386         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1387         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1388
1389         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1390         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1391         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1392
1393         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1394
1395 #if __OS_HAS_AGP
1396         if (dev_priv->flags & RADEON_IS_AGP) {
1397                 /* Turn off PCI GART */
1398                 radeon_set_pcigart(dev_priv, 0);
1399         } else
1400 #endif
1401         {
1402                 u32 sctrl;
1403                 int ret;
1404
1405                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1406                 /* if we have an offset set from userspace */
1407                 if (dev_priv->pcigart_offset_set) {
1408                         dev_priv->gart_info.bus_addr =
1409                             dev_priv->pcigart_offset + dev_priv->fb_location;
1410                         dev_priv->gart_info.mapping.offset =
1411                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1412                         dev_priv->gart_info.mapping.size =
1413                             dev_priv->gart_info.table_size;
1414
1415                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1416                         dev_priv->gart_info.addr =
1417                             dev_priv->gart_info.mapping.handle;
1418
1419                         if (dev_priv->flags & RADEON_IS_PCIE)
1420                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1421                         else
1422                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1423                         dev_priv->gart_info.gart_table_location =
1424                             DRM_ATI_GART_FB;
1425
1426                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1427                                   dev_priv->gart_info.addr,
1428                                   dev_priv->pcigart_offset);
1429                 } else {
1430                         if (dev_priv->flags & RADEON_IS_IGPGART)
1431                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1432                         else
1433                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1434                         dev_priv->gart_info.gart_table_location =
1435                             DRM_ATI_GART_MAIN;
1436                         dev_priv->gart_info.addr = NULL;
1437                         dev_priv->gart_info.bus_addr = 0;
1438                         if (dev_priv->flags & RADEON_IS_PCIE) {
1439                                 DRM_ERROR
1440                                     ("Cannot use PCI Express without GART in FB memory\n");
1441                                 radeon_do_cleanup_cp(dev);
1442                                 return -EINVAL;
1443                         }
1444                 }
1445
1446                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1447                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1448                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1449                         ret = r600_page_table_init(dev);
1450                 else
1451                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1452                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1453
1454                 if (!ret) {
1455                         DRM_ERROR("failed to init PCI GART!\n");
1456                         radeon_do_cleanup_cp(dev);
1457                         return -ENOMEM;
1458                 }
1459
1460                 ret = radeon_setup_pcigart_surface(dev_priv);
1461                 if (ret) {
1462                         DRM_ERROR("failed to setup GART surface!\n");
1463                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1464                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1465                         else
1466                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1467                         radeon_do_cleanup_cp(dev);
1468                         return ret;
1469                 }
1470
1471                 /* Turn on PCI GART */
1472                 radeon_set_pcigart(dev_priv, 1);
1473         }
1474
1475         radeon_cp_load_microcode(dev_priv);
1476         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1477
1478         dev_priv->last_buf = 0;
1479
1480         radeon_do_engine_reset(dev);
1481         radeon_test_writeback(dev_priv);
1482
1483         return 0;
1484 }
1485
1486 static int radeon_do_cleanup_cp(struct drm_device * dev)
1487 {
1488         drm_radeon_private_t *dev_priv = dev->dev_private;
1489         DRM_DEBUG("\n");
1490
1491         /* Make sure interrupts are disabled here because the uninstall ioctl
1492          * may not have been called from userspace and after dev_private
1493          * is freed, it's too late.
1494          */
1495         if (dev->irq_enabled)
1496                 drm_irq_uninstall(dev);
1497
1498 #if __OS_HAS_AGP
1499         if (dev_priv->flags & RADEON_IS_AGP) {
1500                 if (dev_priv->cp_ring != NULL) {
1501                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1502                         dev_priv->cp_ring = NULL;
1503                 }
1504                 if (dev_priv->ring_rptr != NULL) {
1505                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1506                         dev_priv->ring_rptr = NULL;
1507                 }
1508                 if (dev->agp_buffer_map != NULL) {
1509                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1510                         dev->agp_buffer_map = NULL;
1511                 }
1512         } else
1513 #endif
1514         {
1515
1516                 if (dev_priv->gart_info.bus_addr) {
1517                         /* Turn off PCI GART */
1518                         radeon_set_pcigart(dev_priv, 0);
1519                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1520                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1521                         else {
1522                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1523                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1524                         }
1525                 }
1526
1527                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1528                 {
1529                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1530                         dev_priv->gart_info.addr = 0;
1531                 }
1532         }
1533         /* only clear to the start of flags */
1534         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1535
1536         return 0;
1537 }
1538
1539 /* This code will reinit the Radeon CP hardware after a resume from disc.
1540  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1541  * here we make sure that all Radeon hardware initialisation is re-done without
1542  * affecting running applications.
1543  *
1544  * Charl P. Botha <http://cpbotha.net>
1545  */
1546 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1547 {
1548         drm_radeon_private_t *dev_priv = dev->dev_private;
1549
1550         if (!dev_priv) {
1551                 DRM_ERROR("Called with no initialization\n");
1552                 return -EINVAL;
1553         }
1554
1555         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1556
1557 #if __OS_HAS_AGP
1558         if (dev_priv->flags & RADEON_IS_AGP) {
1559                 /* Turn off PCI GART */
1560                 radeon_set_pcigart(dev_priv, 0);
1561         } else
1562 #endif
1563         {
1564                 /* Turn on PCI GART */
1565                 radeon_set_pcigart(dev_priv, 1);
1566         }
1567
1568         radeon_cp_load_microcode(dev_priv);
1569         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1570
1571         radeon_do_engine_reset(dev);
1572         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1573
1574         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1575
1576         return 0;
1577 }
1578
1579 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1580 {
1581         drm_radeon_private_t *dev_priv = dev->dev_private;
1582         drm_radeon_init_t *init = data;
1583
1584         LOCK_TEST_WITH_RETURN(dev, file_priv);
1585
1586         if (init->func == RADEON_INIT_R300_CP)
1587                 r300_init_reg_flags(dev);
1588
1589         switch (init->func) {
1590         case RADEON_INIT_CP:
1591         case RADEON_INIT_R200_CP:
1592         case RADEON_INIT_R300_CP:
1593                 return radeon_do_init_cp(dev, init, file_priv);
1594         case RADEON_INIT_R600_CP:
1595                 return r600_do_init_cp(dev, init, file_priv);
1596         case RADEON_CLEANUP_CP:
1597                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1598                         return r600_do_cleanup_cp(dev);
1599                 else
1600                         return radeon_do_cleanup_cp(dev);
1601         }
1602
1603         return -EINVAL;
1604 }
1605
1606 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1607 {
1608         drm_radeon_private_t *dev_priv = dev->dev_private;
1609         DRM_DEBUG("\n");
1610
1611         LOCK_TEST_WITH_RETURN(dev, file_priv);
1612
1613         if (dev_priv->cp_running) {
1614                 DRM_DEBUG("while CP running\n");
1615                 return 0;
1616         }
1617         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1618                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1619                           dev_priv->cp_mode);
1620                 return 0;
1621         }
1622
1623         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1624                 r600_do_cp_start(dev_priv);
1625         else
1626                 radeon_do_cp_start(dev_priv);
1627
1628         return 0;
1629 }
1630
1631 /* Stop the CP.  The engine must have been idled before calling this
1632  * routine.
1633  */
1634 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1635 {
1636         drm_radeon_private_t *dev_priv = dev->dev_private;
1637         drm_radeon_cp_stop_t *stop = data;
1638         int ret;
1639         DRM_DEBUG("\n");
1640
1641         LOCK_TEST_WITH_RETURN(dev, file_priv);
1642
1643         if (!dev_priv->cp_running)
1644                 return 0;
1645
1646         /* Flush any pending CP commands.  This ensures any outstanding
1647          * commands are exectuted by the engine before we turn it off.
1648          */
1649         if (stop->flush) {
1650                 radeon_do_cp_flush(dev_priv);
1651         }
1652
1653         /* If we fail to make the engine go idle, we return an error
1654          * code so that the DRM ioctl wrapper can try again.
1655          */
1656         if (stop->idle) {
1657                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1658                         ret = r600_do_cp_idle(dev_priv);
1659                 else
1660                         ret = radeon_do_cp_idle(dev_priv);
1661                 if (ret)
1662                         return ret;
1663         }
1664
1665         /* Finally, we can turn off the CP.  If the engine isn't idle,
1666          * we will get some dropped triangles as they won't be fully
1667          * rendered before the CP is shut down.
1668          */
1669         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1670                 r600_do_cp_stop(dev_priv);
1671         else
1672                 radeon_do_cp_stop(dev_priv);
1673
1674         /* Reset the engine */
1675         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1676                 r600_do_engine_reset(dev);
1677         else
1678                 radeon_do_engine_reset(dev);
1679
1680         return 0;
1681 }
1682
1683 void radeon_do_release(struct drm_device * dev)
1684 {
1685         drm_radeon_private_t *dev_priv = dev->dev_private;
1686         int i, ret;
1687
1688         if (dev_priv) {
1689                 if (dev_priv->cp_running) {
1690                         /* Stop the cp */
1691                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1692                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1693                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1694                                         mtx_sleep(&ret, &dev->dev_lock, 0,
1695                                             "rdnrel", 1);
1696                                 }
1697                         } else {
1698                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1699                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1700                                         mtx_sleep(&ret, &dev->dev_lock, 0,
1701                                             "rdnrel", 1);
1702                                 }
1703                         }
1704                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1705                                 r600_do_cp_stop(dev_priv);
1706                                 r600_do_engine_reset(dev);
1707                         } else {
1708                                 radeon_do_cp_stop(dev_priv);
1709                                 radeon_do_engine_reset(dev);
1710                         }
1711                 }
1712
1713                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1714                         /* Disable *all* interrupts */
1715                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1716                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1717
1718                         if (dev_priv->mmio) {   /* remove all surfaces */
1719                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1720                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1721                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1722                                                      16 * i, 0);
1723                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1724                                                      16 * i, 0);
1725                                 }
1726                         }
1727                 }
1728
1729                 /* Free memory heap structures */
1730                 radeon_mem_takedown(&(dev_priv->gart_heap));
1731                 radeon_mem_takedown(&(dev_priv->fb_heap));
1732
1733                 /* deallocate kernel resources */
1734                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1735                         r600_do_cleanup_cp(dev);
1736                 else
1737                         radeon_do_cleanup_cp(dev);
1738         }
1739 }
1740
1741 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1742  */
1743 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1744 {
1745         drm_radeon_private_t *dev_priv = dev->dev_private;
1746         DRM_DEBUG("\n");
1747
1748         LOCK_TEST_WITH_RETURN(dev, file_priv);
1749
1750         if (!dev_priv) {
1751                 DRM_DEBUG("called before init done\n");
1752                 return -EINVAL;
1753         }
1754
1755         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1756                 r600_do_cp_reset(dev_priv);
1757         else
1758                 radeon_do_cp_reset(dev_priv);
1759
1760         /* The CP is no longer running after an engine reset */
1761         dev_priv->cp_running = 0;
1762
1763         return 0;
1764 }
1765
1766 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1767 {
1768         drm_radeon_private_t *dev_priv = dev->dev_private;
1769         DRM_DEBUG("\n");
1770
1771         LOCK_TEST_WITH_RETURN(dev, file_priv);
1772
1773         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1774                 return r600_do_cp_idle(dev_priv);
1775         else
1776                 return radeon_do_cp_idle(dev_priv);
1777 }
1778
1779 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1780  */
1781 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1782 {
1783         drm_radeon_private_t *dev_priv = dev->dev_private;
1784         DRM_DEBUG("\n");
1785
1786         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1787                 return r600_do_resume_cp(dev, file_priv);
1788         else
1789                 return radeon_do_resume_cp(dev, file_priv);
1790 }
1791
1792 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1793 {
1794         drm_radeon_private_t *dev_priv = dev->dev_private;
1795         DRM_DEBUG("\n");
1796
1797         LOCK_TEST_WITH_RETURN(dev, file_priv);
1798
1799         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1800                 return r600_do_engine_reset(dev);
1801         else
1802                 return radeon_do_engine_reset(dev);
1803 }
1804
1805 /* ================================================================
1806  * Fullscreen mode
1807  */
1808
1809 /* KW: Deprecated to say the least:
1810  */
1811 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1812 {
1813         return 0;
1814 }
1815
1816 /* ================================================================
1817  * Freelist management
1818  */
1819
1820 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1821  *   bufs until freelist code is used.  Note this hides a problem with
1822  *   the scratch register * (used to keep track of last buffer
1823  *   completed) being written to before * the last buffer has actually
1824  *   completed rendering.
1825  *
1826  * KW:  It's also a good way to find free buffers quickly.
1827  *
1828  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1829  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1830  * we essentially have to do this, else old clients will break.
1831  *
1832  * However, it does leave open a potential deadlock where all the
1833  * buffers are held by other clients, which can't release them because
1834  * they can't get the lock.
1835  */
1836
1837 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1838 {
1839         struct drm_device_dma *dma = dev->dma;
1840         drm_radeon_private_t *dev_priv = dev->dev_private;
1841         drm_radeon_buf_priv_t *buf_priv;
1842         struct drm_buf *buf;
1843         int i, t;
1844         int start;
1845
1846         if (++dev_priv->last_buf >= dma->buf_count)
1847                 dev_priv->last_buf = 0;
1848
1849         start = dev_priv->last_buf;
1850
1851         for (t = 0; t < dev_priv->usec_timeout; t++) {
1852                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1853                 DRM_DEBUG("done_age = %d\n", done_age);
1854                 for (i = start; i < dma->buf_count; i++) {
1855                         buf = dma->buflist[i];
1856                         buf_priv = buf->dev_private;
1857                         if (buf->file_priv == NULL || (buf->pending &&
1858                                                        buf_priv->age <=
1859                                                        done_age)) {
1860                                 dev_priv->stats.requested_bufs++;
1861                                 buf->pending = 0;
1862                                 return buf;
1863                         }
1864                         start = 0;
1865                 }
1866
1867                 if (t) {
1868                         DRM_UDELAY(1);
1869                         dev_priv->stats.freelist_loops++;
1870                 }
1871         }
1872
1873         DRM_DEBUG("returning NULL!\n");
1874         return NULL;
1875 }
1876
1877 #if 0
1878 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1879 {
1880         struct drm_device_dma *dma = dev->dma;
1881         drm_radeon_private_t *dev_priv = dev->dev_private;
1882         drm_radeon_buf_priv_t *buf_priv;
1883         struct drm_buf *buf;
1884         int i, t;
1885         int start;
1886         u32 done_age;
1887
1888         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1889         if (++dev_priv->last_buf >= dma->buf_count)
1890                 dev_priv->last_buf = 0;
1891
1892         start = dev_priv->last_buf;
1893         dev_priv->stats.freelist_loops++;
1894
1895         for (t = 0; t < 2; t++) {
1896                 for (i = start; i < dma->buf_count; i++) {
1897                         buf = dma->buflist[i];
1898                         buf_priv = buf->dev_private;
1899                         if (buf->file_priv == 0 || (buf->pending &&
1900                                                     buf_priv->age <=
1901                                                     done_age)) {
1902                                 dev_priv->stats.requested_bufs++;
1903                                 buf->pending = 0;
1904                                 return buf;
1905                         }
1906                 }
1907                 start = 0;
1908         }
1909
1910         return NULL;
1911 }
1912 #endif
1913
1914 void radeon_freelist_reset(struct drm_device * dev)
1915 {
1916         struct drm_device_dma *dma = dev->dma;
1917         drm_radeon_private_t *dev_priv = dev->dev_private;
1918         int i;
1919
1920         dev_priv->last_buf = 0;
1921         for (i = 0; i < dma->buf_count; i++) {
1922                 struct drm_buf *buf = dma->buflist[i];
1923                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1924                 buf_priv->age = 0;
1925         }
1926 }
1927
1928 /* ================================================================
1929  * CP command submission
1930  */
1931
1932 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1933 {
1934         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1935         int i;
1936         u32 last_head = GET_RING_HEAD(dev_priv);
1937
1938         for (i = 0; i < dev_priv->usec_timeout; i++) {
1939                 u32 head = GET_RING_HEAD(dev_priv);
1940
1941                 ring->space = (head - ring->tail) * sizeof(u32);
1942                 if (ring->space <= 0)
1943                         ring->space += ring->size;
1944                 if (ring->space > n)
1945                         return 0;
1946
1947                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1948
1949                 if (head != last_head)
1950                         i = 0;
1951                 last_head = head;
1952
1953                 DRM_UDELAY(1);
1954         }
1955
1956         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1957 #if RADEON_FIFO_DEBUG
1958         radeon_status(dev_priv);
1959         DRM_ERROR("failed!\n");
1960 #endif
1961         return -EBUSY;
1962 }
1963
1964 static int radeon_cp_get_buffers(struct drm_device *dev,
1965                                  struct drm_file *file_priv,
1966                                  struct drm_dma * d)
1967 {
1968         int i;
1969         struct drm_buf *buf;
1970
1971         for (i = d->granted_count; i < d->request_count; i++) {
1972                 buf = radeon_freelist_get(dev);
1973                 if (!buf)
1974                         return -EBUSY;  /* NOTE: broken client */
1975
1976                 buf->file_priv = file_priv;
1977
1978                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1979                                      sizeof(buf->idx)))
1980                         return -EFAULT;
1981                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1982                                      sizeof(buf->total)))
1983                         return -EFAULT;
1984
1985                 d->granted_count++;
1986         }
1987         return 0;
1988 }
1989
1990 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1991 {
1992         struct drm_device_dma *dma = dev->dma;
1993         int ret = 0;
1994         struct drm_dma *d = data;
1995
1996         LOCK_TEST_WITH_RETURN(dev, file_priv);
1997
1998         /* Please don't send us buffers.
1999          */
2000         if (d->send_count != 0) {
2001                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2002                           DRM_CURRENTPID, d->send_count);
2003                 return -EINVAL;
2004         }
2005
2006         /* We'll send you buffers.
2007          */
2008         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2009                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2010                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2011                 return -EINVAL;
2012         }
2013
2014         d->granted_count = 0;
2015
2016         if (d->request_count) {
2017                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2018         }
2019
2020         return ret;
2021 }
2022
2023 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2024 {
2025         drm_radeon_private_t *dev_priv;
2026         int ret = 0;
2027
2028         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2029         if (dev_priv == NULL)
2030                 return -ENOMEM;
2031
2032         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2033         dev->dev_private = (void *)dev_priv;
2034         dev_priv->flags = flags;
2035
2036         switch (flags & RADEON_FAMILY_MASK) {
2037         case CHIP_R100:
2038         case CHIP_RV200:
2039         case CHIP_R200:
2040         case CHIP_R300:
2041         case CHIP_R350:
2042         case CHIP_R420:
2043         case CHIP_R423:
2044         case CHIP_RV410:
2045         case CHIP_RV515:
2046         case CHIP_R520:
2047         case CHIP_RV570:
2048         case CHIP_R580:
2049                 dev_priv->flags |= RADEON_HAS_HIERZ;
2050                 break;
2051         default:
2052                 /* all other chips have no hierarchical z buffer */
2053                 break;
2054         }
2055
2056         if (drm_device_is_agp(dev))
2057                 dev_priv->flags |= RADEON_IS_AGP;
2058         else if (drm_device_is_pcie(dev))
2059                 dev_priv->flags |= RADEON_IS_PCIE;
2060         else
2061                 dev_priv->flags |= RADEON_IS_PCI;
2062
2063         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2064                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2065                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2066         if (ret != 0)
2067                 goto error;
2068
2069         ret = drm_vblank_init(dev, 2);
2070         if (ret != 0)
2071                 goto error;
2072
2073         dev->max_vblank_count = 0x001fffff;
2074
2075         DRM_DEBUG("%s card detected\n",
2076                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" :
2077                     (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2078
2079         return ret;
2080
2081 error:
2082         radeon_driver_unload(dev);
2083         return ret;
2084 }
2085
2086 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2087  * have to find them.
2088  */
2089 int radeon_driver_firstopen(struct drm_device *dev)
2090 {
2091         int ret;
2092         drm_local_map_t *map;
2093         drm_radeon_private_t *dev_priv = dev->dev_private;
2094
2095         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2096
2097         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2098         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2099                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2100                          _DRM_WRITE_COMBINING, &map);
2101         if (ret != 0)
2102                 return ret;
2103
2104         return 0;
2105 }
2106
2107 int radeon_driver_unload(struct drm_device *dev)
2108 {
2109         drm_radeon_private_t *dev_priv = dev->dev_private;
2110
2111         DRM_DEBUG("\n");
2112
2113         drm_rmmap(dev, dev_priv->mmio);
2114
2115         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2116
2117         dev->dev_private = NULL;
2118         return 0;
2119 }
2120
2121 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2122 {
2123         int i;
2124         u32 *ring;
2125         int tail_aligned;
2126
2127         /* check if the ring is padded out to 16-dword alignment */
2128
2129         tail_aligned = dev_priv->ring.tail & 0xf;
2130         if (tail_aligned) {
2131                 int num_p2 = 16 - tail_aligned;
2132
2133                 ring = dev_priv->ring.start;
2134                 /* pad with some CP_PACKET2 */
2135                 for (i = 0; i < num_p2; i++)
2136                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2137
2138                 dev_priv->ring.tail += i;
2139
2140                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2141         }
2142
2143         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2144
2145         DRM_MEMORYBARRIER();
2146         GET_RING_HEAD( dev_priv );
2147
2148         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2149                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2150                 /* read from PCI bus to ensure correct posting */
2151                 RADEON_READ(R600_CP_RB_RPTR);
2152         } else {
2153                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2154                 /* read from PCI bus to ensure correct posting */
2155                 RADEON_READ(RADEON_CP_RB_RPTR);
2156         }
2157 }