sys/dev/e1000/e1000_80003es2lan.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  37  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  38  */
  39
  40 #include "e1000_api.h"
  41
  42 static s32  e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
  43 static s32  e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
  44 static s32  e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
  45 static s32  e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
  46 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
  47 static s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
  48 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
  49 static s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  50                                                    u32 offset,
  51                                                    u16 *data);
  52 static s32  e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  53                                                     u32 offset,
  54                                                     u16 data);
  55 static s32  e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
  56                                         u16 words, u16 *data);
  57 static s32  e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
  58 static s32  e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
  59 static s32  e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
  60 static s32  e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  61                                                u16 *duplex);
  62 static s32  e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
  63 static s32  e1000_init_hw_80003es2lan(struct e1000_hw *hw);
  64 static s32  e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  65 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  66 static s32  e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  67 static s32  e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  68 static s32  e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  69 static s32  e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
  70 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  71                                             u16 *data);
  72 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  73                                              u16 data);
  74 static s32  e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
  75 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  76 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  77 static s32  e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
  78 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  79
  80 /*
  81  * A table for the GG82563 cable length where the range is defined
  82  * with a lower bound at "index" and the upper bound at
  83  * "index + 5".
  84  */
  85 static const u16 e1000_gg82563_cable_length_table[] =
  86          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  87 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  88                 (sizeof(e1000_gg82563_cable_length_table) / \
  89                  sizeof(e1000_gg82563_cable_length_table[0]))
  90
  91 /**
  92  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  96 {
  97         struct e1000_phy_info *phy = &hw->phy;
  98         s32 ret_val = E1000_SUCCESS;
  99
 100         DEBUGFUNC("e1000_init_phy_params_80003es2lan");
 101
 102         if (hw->phy.media_type != e1000_media_type_copper) {
 103                 phy->type        = e1000_phy_none;
 104                 goto out;
 105         } else {
 106                 phy->ops.power_up = e1000_power_up_phy_copper;
 107                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 108         }
 109
 110         phy->addr                = 1;
 111         phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 112         phy->reset_delay_us      = 100;
 113         phy->type                = e1000_phy_gg82563;
 114
 115         phy->ops.acquire            = e1000_acquire_phy_80003es2lan;
 116         phy->ops.check_polarity     = e1000_check_polarity_m88;
 117         phy->ops.check_reset_block  = e1000_check_reset_block_generic;
 118         phy->ops.commit             = e1000_phy_sw_reset_generic;
 119         phy->ops.get_cfg_done       = e1000_get_cfg_done_80003es2lan;
 120         phy->ops.get_info           = e1000_get_phy_info_m88;
 121         phy->ops.release            = e1000_release_phy_80003es2lan;
 122         phy->ops.reset              = e1000_phy_hw_reset_generic;
 123         phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
 124
 125         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
 126         phy->ops.get_cable_length   = e1000_get_cable_length_80003es2lan;
 127         phy->ops.read_reg           = e1000_read_phy_reg_gg82563_80003es2lan;
 128         phy->ops.write_reg          = e1000_write_phy_reg_gg82563_80003es2lan;
 129
 130         phy->ops.cfg_on_link_up    = e1000_cfg_on_link_up_80003es2lan;
 131
 132         /* This can only be done after all function pointers are setup. */
 133         ret_val = e1000_get_phy_id(hw);
 134
 135         /* Verify phy id */
 136         if (phy->id != GG82563_E_PHY_ID) {
 137                 ret_val = -E1000_ERR_PHY;
 138                 goto out;
 139         }
 140
 141 out:
 142         return ret_val;
 143 }
 144
 145 /**
 146  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 147  *  @hw: pointer to the HW structure
 148  **/
 149 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 150 {
 151         struct e1000_nvm_info *nvm = &hw->nvm;
 152         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 153         u16 size;
 154
 155         DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
 156
 157         nvm->opcode_bits        = 8;
 158         nvm->delay_usec         = 1;
 159         switch (nvm->override) {
 160         case e1000_nvm_override_spi_large:
 161                 nvm->page_size    = 32;
 162                 nvm->address_bits = 16;
 163                 break;
 164         case e1000_nvm_override_spi_small:
 165                 nvm->page_size    = 8;
 166                 nvm->address_bits = 8;
 167                 break;
 168         default:
 169                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 170                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 171                 break;
 172         }
 173
 174         nvm->type               = e1000_nvm_eeprom_spi;
 175
 176         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 177                           E1000_EECD_SIZE_EX_SHIFT);
 178
 179         /*
 180          * Added to a constant, "size" becomes the left-shift value
 181          * for setting word_size.
 182          */
 183         size += NVM_WORD_SIZE_BASE_SHIFT;
 184
 185         /* EEPROM access above 16k is unsupported */
 186         if (size > 14)
 187                 size = 14;
 188         nvm->word_size  = 1 << size;
 189
 190         /* Function Pointers */
 191         nvm->ops.acquire           = e1000_acquire_nvm_80003es2lan;
 192         nvm->ops.read              = e1000_read_nvm_eerd;
 193         nvm->ops.release           = e1000_release_nvm_80003es2lan;
 194         nvm->ops.update            = e1000_update_nvm_checksum_generic;
 195         nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 196         nvm->ops.validate          = e1000_validate_nvm_checksum_generic;
 197         nvm->ops.write             = e1000_write_nvm_80003es2lan;
 198
 199         return E1000_SUCCESS;
 200 }
 201
 202 /**
 203  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 204  *  @hw: pointer to the HW structure
 205  **/
 206 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 207 {
 208         struct e1000_mac_info *mac = &hw->mac;
 209         s32 ret_val = E1000_SUCCESS;
 210
 211         DEBUGFUNC("e1000_init_mac_params_80003es2lan");
 212
 213         /* Set media type */
 214         switch (hw->device_id) {
 215         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 216                 hw->phy.media_type = e1000_media_type_internal_serdes;
 217                 break;
 218         default:
 219                 hw->phy.media_type = e1000_media_type_copper;
 220                 break;
 221         }
 222
 223         /* Set mta register count */
 224         mac->mta_reg_count = 128;
 225         /* Set rar entry count */
 226         mac->rar_entry_count = E1000_RAR_ENTRIES;
 227         /* Set if part includes ASF firmware */
 228         mac->asf_firmware_present = TRUE;
 229         /* Set if manageability features are enabled. */
 230         mac->arc_subsystem_valid =
 231                 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 232                         ? TRUE : FALSE;
 233
 234         /* Function pointers */
 235
 236         /* bus type/speed/width */
 237         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 238         /* reset */
 239         mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
 240         /* hw initialization */
 241         mac->ops.init_hw = e1000_init_hw_80003es2lan;
 242         /* link setup */
 243         mac->ops.setup_link = e1000_setup_link_generic;
 244         /* physical interface link setup */
 245         mac->ops.setup_physical_interface =
 246                 (hw->phy.media_type == e1000_media_type_copper)
 247                         ? e1000_setup_copper_link_80003es2lan
 248                         : e1000_setup_fiber_serdes_link_generic;
 249         /* check for link */
 250         switch (hw->phy.media_type) {
 251         case e1000_media_type_copper:
 252                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 253                 break;
 254         case e1000_media_type_fiber:
 255                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 256                 break;
 257         case e1000_media_type_internal_serdes:
 258                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 259                 break;
 260         default:
 261                 ret_val = -E1000_ERR_CONFIG;
 262                 goto out;
 263                 break;
 264         }
 265         /* check management mode */
 266         mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 267         /* multicast address update */
 268         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 269         /* writing VFTA */
 270         mac->ops.write_vfta = e1000_write_vfta_generic;
 271         /* clearing VFTA */
 272         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 273         /* setting MTA */
 274         mac->ops.mta_set = e1000_mta_set_generic;
 275         /* read mac address */
 276         mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
 277         /* ID LED init */
 278         mac->ops.id_led_init = e1000_id_led_init_generic;
 279         /* blink LED */
 280         mac->ops.blink_led = e1000_blink_led_generic;
 281         /* setup LED */
 282         mac->ops.setup_led = e1000_setup_led_generic;
 283         /* cleanup LED */
 284         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 285         /* turn on/off LED */
 286         mac->ops.led_on = e1000_led_on_generic;
 287         mac->ops.led_off = e1000_led_off_generic;
 288         /* clear hardware counters */
 289         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
 290         /* link info */
 291         mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
 292
 293 out:
 294         return ret_val;
 295 }
 296
 297 /**
 298  *  e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
 299  *  @hw: pointer to the HW structure
 300  *
 301  *  Called to initialize all function pointers and parameters.
 302  **/
 303 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
 304 {
 305         DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
 306
 307         hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
 308         hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
 309         hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
 310         e1000_get_bus_info_pcie_generic(hw);
 311 }
 312
 313 /**
 314  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 315  *  @hw: pointer to the HW structure
 316  *
 317  *  A wrapper to acquire access rights to the correct PHY.
 318  **/
 319 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 320 {
 321         u16 mask;
 322
 323         DEBUGFUNC("e1000_acquire_phy_80003es2lan");
 324
 325         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 326         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 327 }
 328
 329 /**
 330  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 331  *  @hw: pointer to the HW structure
 332  *
 333  *  A wrapper to release access rights to the correct PHY.
 334  **/
 335 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 336 {
 337         u16 mask;
 338
 339         DEBUGFUNC("e1000_release_phy_80003es2lan");
 340
 341         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 342         e1000_release_swfw_sync_80003es2lan(hw, mask);
 343 }
 344
 345
 346 /**
 347  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 348  *  @hw: pointer to the HW structure
 349  *
 350  *  Acquire the semaphore to access the Kumeran interface.
 351  *
 352  **/
 353 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 354 {
 355         u16 mask;
 356
 357         DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
 358
 359         mask = E1000_SWFW_CSR_SM;
 360
 361         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 362 }
 363
 364 /**
 365  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 366  *  @hw: pointer to the HW structure
 367  *
 368  *  Release the semaphore used to access the Kumeran interface
 369  **/
 370 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 371 {
 372         u16 mask;
 373
 374         DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
 375
 376         mask = E1000_SWFW_CSR_SM;
 377
 378         e1000_release_swfw_sync_80003es2lan(hw, mask);
 379 }
 380
 381 /**
 382  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 383  *  @hw: pointer to the HW structure
 384  *
 385  *  Acquire the semaphore to access the EEPROM.
 386  **/
 387 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 388 {
 389         s32 ret_val;
 390
 391         DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
 392
 393         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 394         if (ret_val)
 395                 goto out;
 396
 397         ret_val = e1000_acquire_nvm_generic(hw);
 398
 399         if (ret_val)
 400                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 401
 402 out:
 403         return ret_val;
 404 }
 405
 406 /**
 407  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 408  *  @hw: pointer to the HW structure
 409  *
 410  *  Release the semaphore used to access the EEPROM.
 411  **/
 412 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 413 {
 414         DEBUGFUNC("e1000_release_nvm_80003es2lan");
 415
 416         e1000_release_nvm_generic(hw);
 417         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 418 }
 419
 420 /**
 421  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 422  *  @hw: pointer to the HW structure
 423  *  @mask: specifies which semaphore to acquire
 424  *
 425  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 426  *  will also specify which port we're acquiring the lock for.
 427  **/
 428 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 429 {
 430         u32 swfw_sync;
 431         u32 swmask = mask;
 432         u32 fwmask = mask << 16;
 433         s32 ret_val = E1000_SUCCESS;
 434         s32 i = 0, timeout = 50;
 435
 436         DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
 437
 438         while (i < timeout) {
 439                 if (e1000_get_hw_semaphore_generic(hw)) {
 440                         ret_val = -E1000_ERR_SWFW_SYNC;
 441                         goto out;
 442                 }
 443
 444                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 445                 if (!(swfw_sync & (fwmask | swmask)))
 446                         break;
 447
 448                 /*
 449                  * Firmware currently using resource (fwmask)
 450                  * or other software thread using resource (swmask)
 451                  */
 452                 e1000_put_hw_semaphore_generic(hw);
 453                 msec_delay_irq(5);
 454                 i++;
 455         }
 456
 457         if (i == timeout) {
 458                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
 459                 ret_val = -E1000_ERR_SWFW_SYNC;
 460                 goto out;
 461         }
 462
 463         swfw_sync |= swmask;
 464         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 465
 466         e1000_put_hw_semaphore_generic(hw);
 467
 468 out:
 469         return ret_val;
 470 }
 471
 472 /**
 473  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 474  *  @hw: pointer to the HW structure
 475  *  @mask: specifies which semaphore to acquire
 476  *
 477  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 478  *  will also specify which port we're releasing the lock for.
 479  **/
 480 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 481 {
 482         u32 swfw_sync;
 483
 484         DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
 485
 486         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
 487                 ; /* Empty */
 488
 489         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 490         swfw_sync &= ~mask;
 491         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 492
 493         e1000_put_hw_semaphore_generic(hw);
 494 }
 495
 496 /**
 497  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 498  *  @hw: pointer to the HW structure
 499  *  @offset: offset of the register to read
 500  *  @data: pointer to the data returned from the operation
 501  *
 502  *  Read the GG82563 PHY register.
 503  **/
 504 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 505                                                   u32 offset, u16 *data)
 506 {
 507         s32 ret_val;
 508         u32 page_select;
 509         u16 temp;
 510
 511         DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
 512
 513         ret_val = e1000_acquire_phy_80003es2lan(hw);
 514         if (ret_val)
 515                 goto out;
 516
 517         /* Select Configuration Page */
 518         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 519                 page_select = GG82563_PHY_PAGE_SELECT;
 520         } else {
 521                 /*
 522                  * Use Alternative Page Select register to access
 523                  * registers 30 and 31
 524                  */
 525                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 526         }
 527
 528         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 529         ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
 530         if (ret_val) {
 531                 e1000_release_phy_80003es2lan(hw);
 532                 goto out;
 533         }
 534
 535         /*
 536          * The "ready" bit in the MDIC register may be incorrectly set
 537          * before the device has completed the "Page Select" MDI
 538          * transaction.  So we wait 200us after each MDI command...
 539          */
 540         usec_delay(200);
 541
 542         /* ...and verify the command was successful. */
 543         ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 544
 545         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 546                 ret_val = -E1000_ERR_PHY;
 547                 e1000_release_phy_80003es2lan(hw);
 548                 goto out;
 549         }
 550
 551         usec_delay(200);
 552
 553         ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 554                                            data);
 555
 556         usec_delay(200);
 557         e1000_release_phy_80003es2lan(hw);
 558
 559 out:
 560         return ret_val;
 561 }
 562
 563 /**
 564  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 565  *  @hw: pointer to the HW structure
 566  *  @offset: offset of the register to read
 567  *  @data: value to write to the register
 568  *
 569  *  Write to the GG82563 PHY register.
 570  **/
 571 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 572                                                    u32 offset, u16 data)
 573 {
 574         s32 ret_val;
 575         u32 page_select;
 576         u16 temp;
 577
 578         DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
 579
 580         ret_val = e1000_acquire_phy_80003es2lan(hw);
 581         if (ret_val)
 582                 goto out;
 583
 584         /* Select Configuration Page */
 585         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 586                 page_select = GG82563_PHY_PAGE_SELECT;
 587         } else {
 588                 /*
 589                  * Use Alternative Page Select register to access
 590                  * registers 30 and 31
 591                  */
 592                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 593         }
 594
 595         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 596         ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
 597         if (ret_val) {
 598                 e1000_release_phy_80003es2lan(hw);
 599                 goto out;
 600         }
 601
 602
 603         /*
 604          * The "ready" bit in the MDIC register may be incorrectly set
 605          * before the device has completed the "Page Select" MDI
 606          * transaction.  So we wait 200us after each MDI command...
 607          */
 608         usec_delay(200);
 609
 610         /* ...and verify the command was successful. */
 611         ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 612
 613         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 614                 ret_val = -E1000_ERR_PHY;
 615                 e1000_release_phy_80003es2lan(hw);
 616                 goto out;
 617         }
 618
 619         usec_delay(200);
 620
 621         ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 622                                           data);
 623
 624         usec_delay(200);
 625         e1000_release_phy_80003es2lan(hw);
 626
 627 out:
 628         return ret_val;
 629 }
 630
 631 /**
 632  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 633  *  @hw: pointer to the HW structure
 634  *  @offset: offset of the register to read
 635  *  @words: number of words to write
 636  *  @data: buffer of data to write to the NVM
 637  *
 638  *  Write "words" of data to the ESB2 NVM.
 639  **/
 640 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 641                             u16 words, u16 *data)
 642 {
 643         DEBUGFUNC("e1000_write_nvm_80003es2lan");
 644
 645         return e1000_write_nvm_spi(hw, offset, words, data);
 646 }
 647
 648 /**
 649  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Wait a specific amount of time for manageability processes to complete.
 653  *  This is a function pointer entry point called by the phy module.
 654  **/
 655 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 656 {
 657         s32 timeout = PHY_CFG_TIMEOUT;
 658         s32 ret_val = E1000_SUCCESS;
 659         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 660
 661         DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
 662
 663         if (hw->bus.func == 1)
 664                 mask = E1000_NVM_CFG_DONE_PORT_1;
 665
 666         while (timeout) {
 667                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
 668                         break;
 669                 msec_delay(1);
 670                 timeout--;
 671         }
 672         if (!timeout) {
 673                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 674                 ret_val = -E1000_ERR_RESET;
 675                 goto out;
 676         }
 677
 678 out:
 679         return ret_val;
 680 }
 681
 682 /**
 683  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 684  *  @hw: pointer to the HW structure
 685  *
 686  *  Force the speed and duplex settings onto the PHY.  This is a
 687  *  function pointer entry point called by the phy module.
 688  **/
 689 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 690 {
 691         s32 ret_val = E1000_SUCCESS;
 692         u16 phy_data;
 693         bool link;
 694
 695         DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
 696
 697         if (!(hw->phy.ops.read_reg))
 698                 goto out;
 699
 700         /*
 701          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 702          * forced whenever speed and duplex are forced.
 703          */
 704         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 705         if (ret_val)
 706                 goto out;
 707
 708         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 709         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 710         if (ret_val)
 711                 goto out;
 712
 713         DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
 714
 715         ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
 716         if (ret_val)
 717                 goto out;
 718
 719         e1000_phy_force_speed_duplex_setup(hw, &phy_data);
 720
 721         /* Reset the phy to commit changes. */
 722         phy_data |= MII_CR_RESET;
 723
 724         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
 725         if (ret_val)
 726                 goto out;
 727
 728         usec_delay(1);
 729
 730         if (hw->phy.autoneg_wait_to_complete) {
 731                 DEBUGOUT("Waiting for forced speed/duplex link "
 732                          "on GG82563 phy.\n");
 733
 734                 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 735                                                      100000, &link);
 736                 if (ret_val)
 737                         goto out;
 738
 739                 if (!link) {
 740                         /*
 741                          * We didn't get link.
 742                          * Reset the DSP and cross our fingers.
 743                          */
 744                         ret_val = e1000_phy_reset_dsp_generic(hw);
 745                         if (ret_val)
 746                                 goto out;
 747                 }
 748
 749                 /* Try once more */
 750                 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 751                                                      100000, &link);
 752                 if (ret_val)
 753                         goto out;
 754         }
 755
 756         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 757         if (ret_val)
 758                 goto out;
 759
 760         /*
 761          * Resetting the phy means we need to verify the TX_CLK corresponds
 762          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 763          */
 764         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 765         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 766                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 767         else
 768                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 769
 770         /*
 771          * In addition, we must re-enable CRS on Tx for both half and full
 772          * duplex.
 773          */
 774         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 775         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 776
 777 out:
 778         return ret_val;
 779 }
 780
 781 /**
 782  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 783  *  @hw: pointer to the HW structure
 784  *
 785  *  Find the approximate cable length as measured by the GG82563 PHY.
 786  *  This is a function pointer entry point called by the phy module.
 787  **/
 788 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 789 {
 790         struct e1000_phy_info *phy = &hw->phy;
 791         s32 ret_val = E1000_SUCCESS;
 792         u16 phy_data, index;
 793
 794         DEBUGFUNC("e1000_get_cable_length_80003es2lan");
 795
 796         if (!(hw->phy.ops.read_reg))
 797                 goto out;
 798
 799         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 800         if (ret_val)
 801                 goto out;
 802
 803         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 804
 805         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE + 5) {
 806                 ret_val = E1000_ERR_PHY;
 807                 goto out;
 808         }
 809
 810         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 811         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
 812
 813         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 814
 815 out:
 816         return ret_val;
 817 }
 818
 819 /**
 820  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 821  *  @hw: pointer to the HW structure
 822  *  @speed: pointer to speed buffer
 823  *  @duplex: pointer to duplex buffer
 824  *
 825  *  Retrieve the current speed and duplex configuration.
 826  **/
 827 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 828                                               u16 *duplex)
 829 {
 830         s32 ret_val;
 831
 832         DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
 833
 834         if (hw->phy.media_type == e1000_media_type_copper) {
 835                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
 836                                                                     speed,
 837                                                                     duplex);
 838                 hw->phy.ops.cfg_on_link_up(hw);
 839         } else {
 840                 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
 841                                                                   speed,
 842                                                                   duplex);
 843         }
 844
 845         return ret_val;
 846 }
 847
 848 /**
 849  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 850  *  @hw: pointer to the HW structure
 851  *
 852  *  Perform a global reset to the ESB2 controller.
 853  **/
 854 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 855 {
 856         u32 ctrl, icr;
 857         s32 ret_val;
 858
 859         DEBUGFUNC("e1000_reset_hw_80003es2lan");
 860
 861         /*
 862          * Prevent the PCI-E bus from sticking if there is no TLP connection
 863          * on the last TLP read/write transaction when MAC is reset.
 864          */
 865         ret_val = e1000_disable_pcie_master_generic(hw);
 866         if (ret_val)
 867                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 868
 869         DEBUGOUT("Masking off all interrupts\n");
 870         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 871
 872         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 873         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 874         E1000_WRITE_FLUSH(hw);
 875
 876         msec_delay(10);
 877
 878         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 879
 880         ret_val = e1000_acquire_phy_80003es2lan(hw);
 881         DEBUGOUT("Issuing a global reset to MAC\n");
 882         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 883         e1000_release_phy_80003es2lan(hw);
 884
 885         ret_val = e1000_get_auto_rd_done_generic(hw);
 886         if (ret_val)
 887                 /* We don't want to continue accessing MAC registers. */
 888                 goto out;
 889
 890         /* Clear any pending interrupt events. */
 891         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 892         icr = E1000_READ_REG(hw, E1000_ICR);
 893
 894         ret_val = e1000_check_alt_mac_addr_generic(hw);
 895
 896 out:
 897         return ret_val;
 898 }
 899
 900 /**
 901  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 902  *  @hw: pointer to the HW structure
 903  *
 904  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 905  **/
 906 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 907 {
 908         struct e1000_mac_info *mac = &hw->mac;
 909         u32 reg_data;
 910         s32 ret_val;
 911         u16 i;
 912
 913         DEBUGFUNC("e1000_init_hw_80003es2lan");
 914
 915         e1000_initialize_hw_bits_80003es2lan(hw);
 916
 917         /* Initialize identification LED */
 918         ret_val = mac->ops.id_led_init(hw);
 919         if (ret_val) {
 920                 DEBUGOUT("Error initializing identification LED\n");
 921                 /* This is not fatal and we should not stop init due to this */
 922         }
 923
 924         /* Disabling VLAN filtering */
 925         DEBUGOUT("Initializing the IEEE VLAN\n");
 926         mac->ops.clear_vfta(hw);
 927
 928         /* Setup the receive address. */
 929         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 930
 931         /* Zero out the Multicast HASH table */
 932         DEBUGOUT("Zeroing the MTA\n");
 933         for (i = 0; i < mac->mta_reg_count; i++)
 934                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 935
 936         /* Setup link and flow control */
 937         ret_val = mac->ops.setup_link(hw);
 938
 939         /* Set the transmit descriptor write-back policy */
 940         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 941         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 942                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 943         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 944
 945         /* ...for both queues. */
 946         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 947         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 948                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 949         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 950
 951         /* Enable retransmit on late collisions */
 952         reg_data = E1000_READ_REG(hw, E1000_TCTL);
 953         reg_data |= E1000_TCTL_RTLC;
 954         E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
 955
 956         /* Configure Gigabit Carry Extend Padding */
 957         reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
 958         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 959         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 960         E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
 961
 962         /* Configure Transmit Inter-Packet Gap */
 963         reg_data = E1000_READ_REG(hw, E1000_TIPG);
 964         reg_data &= ~E1000_TIPG_IPGT_MASK;
 965         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 966         E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
 967
 968         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 969         reg_data &= ~0x00100000;
 970         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 971
 972         /*
 973          * Clear all of the statistics registers (clear on read).  It is
 974          * important that we do this after we have tried to establish link
 975          * because the symbol error count will increment wildly if there
 976          * is no link.
 977          */
 978         e1000_clear_hw_cntrs_80003es2lan(hw);
 979
 980         return ret_val;
 981 }
 982
 983 /**
 984  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 985  *  @hw: pointer to the HW structure
 986  *
 987  *  Initializes required hardware-dependent bits needed for normal operation.
 988  **/
 989 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 990 {
 991         u32 reg;
 992
 993         DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
 994
 995         /* Transmit Descriptor Control 0 */
 996         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
 997         reg |= (1 << 22);
 998         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
 999
1000         /* Transmit Descriptor Control 1 */
1001         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1002         reg |= (1 << 22);
1003         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1004
1005         /* Transmit Arbitration Control 0 */
1006         reg = E1000_READ_REG(hw, E1000_TARC(0));
1007         reg &= ~(0xF << 27); /* 30:27 */
1008         if (hw->phy.media_type != e1000_media_type_copper)
1009                 reg &= ~(1 << 20);
1010         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1011
1012         /* Transmit Arbitration Control 1 */
1013         reg = E1000_READ_REG(hw, E1000_TARC(1));
1014         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1015                 reg &= ~(1 << 28);
1016         else
1017                 reg |= (1 << 28);
1018         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1019
1020         return;
1021 }
1022
1023 /**
1024  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1025  *  @hw: pointer to the HW structure
1026  *
1027  *  Setup some GG82563 PHY registers for obtaining link
1028  **/
1029 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1030 {
1031         struct e1000_phy_info *phy = &hw->phy;
1032         s32 ret_val;
1033         u32 ctrl_ext;
1034         u16 data;
1035
1036         DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1037
1038         if (!phy->reset_disable) {
1039                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1040                                              &data);
1041                 if (ret_val)
1042                         goto out;
1043
1044                 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1045                 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1046                 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1047
1048                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1049                                               data);
1050                 if (ret_val)
1051                         goto out;
1052
1053                 /*
1054                  * Options:
1055                  *   MDI/MDI-X = 0 (default)
1056                  *   0 - Auto for all speeds
1057                  *   1 - MDI mode
1058                  *   2 - MDI-X mode
1059                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1060                  */
1061                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1062                 if (ret_val)
1063                         goto out;
1064
1065                 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1066
1067                 switch (phy->mdix) {
1068                 case 1:
1069                         data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1070                         break;
1071                 case 2:
1072                         data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1073                         break;
1074                 case 0:
1075                 default:
1076                         data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1077                         break;
1078                 }
1079
1080                 /*
1081                  * Options:
1082                  *   disable_polarity_correction = 0 (default)
1083                  *       Automatic Correction for Reversed Cable Polarity
1084                  *   0 - Disabled
1085                  *   1 - Enabled
1086                  */
1087                 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1088                 if (phy->disable_polarity_correction)
1089                         data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1090
1091                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1092                 if (ret_val)
1093                         goto out;
1094
1095                 /* SW Reset the PHY so all changes take effect */
1096                 ret_val = hw->phy.ops.commit(hw);
1097                 if (ret_val) {
1098                         DEBUGOUT("Error Resetting the PHY\n");
1099                         goto out;
1100                 }
1101
1102         }
1103
1104         /* Bypass Rx and Tx FIFO's */
1105         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1106                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1107                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1108                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1109         if (ret_val)
1110                 goto out;
1111
1112         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1113                                       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1114                                       &data);
1115         if (ret_val)
1116                 goto out;
1117         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1118         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1119                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1120                                        data);
1121         if (ret_val)
1122                 goto out;
1123
1124         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1125         if (ret_val)
1126                 goto out;
1127
1128         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1129         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1130         if (ret_val)
1131                 goto out;
1132
1133         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1134         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1135         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1136
1137         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1138         if (ret_val)
1139                 goto out;
1140
1141         /*
1142          * Do not init these registers when the HW is in IAMT mode, since the
1143          * firmware will have already initialized them.  We only initialize
1144          * them if the HW is not in IAMT mode.
1145          */
1146         if (!(hw->mac.ops.check_mng_mode(hw))) {
1147                 /* Enable Electrical Idle on the PHY */
1148                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1149                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1150                                                 data);
1151                 if (ret_val)
1152                         goto out;
1153
1154                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1155                                                &data);
1156                 if (ret_val)
1157                         goto out;
1158
1159                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1160                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1161                                                 data);
1162                 if (ret_val)
1163                         goto out;
1164         }
1165
1166         /*
1167          * Workaround: Disable padding in Kumeran interface in the MAC
1168          * and in the PHY to avoid CRC errors.
1169          */
1170         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1171         if (ret_val)
1172                 goto out;
1173
1174         data |= GG82563_ICR_DIS_PADDING;
1175         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1176         if (ret_val)
1177                 goto out;
1178
1179 out:
1180         return ret_val;
1181 }
1182
1183 /**
1184  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1185  *  @hw: pointer to the HW structure
1186  *
1187  *  Essentially a wrapper for setting up all things "copper" related.
1188  *  This is a function pointer entry point called by the mac module.
1189  **/
1190 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1191 {
1192         u32 ctrl;
1193         s32 ret_val;
1194         u16 reg_data;
1195
1196         DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1197
1198         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1199         ctrl |= E1000_CTRL_SLU;
1200         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1201         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1202
1203         /*
1204          * Set the mac to wait the maximum time between each
1205          * iteration and increase the max iterations when
1206          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1207          */
1208         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1209                                                    0xFFFF);
1210         if (ret_val)
1211                 goto out;
1212         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1213                                                   &reg_data);
1214         if (ret_val)
1215                 goto out;
1216         reg_data |= 0x3F;
1217         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1218                                                    reg_data);
1219         if (ret_val)
1220                 goto out;
1221         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1222                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1223                                       &reg_data);
1224         if (ret_val)
1225                 goto out;
1226         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1227         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1228                                        E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1229                                        reg_data);
1230         if (ret_val)
1231                 goto out;
1232
1233         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1234         if (ret_val)
1235                 goto out;
1236
1237         ret_val = e1000_setup_copper_link_generic(hw);
1238
1239 out:
1240         return ret_val;
1241 }
1242
1243 /**
1244  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1245  *  @hw: pointer to the HW structure
1246  *  @duplex: current duplex setting
1247  *
1248  *  Configure the KMRN interface by applying last minute quirks for
1249  *  10/100 operation.
1250  **/
1251 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1252 {
1253         s32 ret_val = E1000_SUCCESS;
1254         u16 speed;
1255         u16 duplex;
1256
1257         DEBUGFUNC("e1000_configure_on_link_up");
1258
1259         if (hw->phy.media_type == e1000_media_type_copper) {
1260                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1261                                                                     &speed,
1262                                                                     &duplex);
1263                 if (ret_val)
1264                         goto out;
1265
1266                 if (speed == SPEED_1000)
1267                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1268                 else
1269                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1270         }
1271
1272 out:
1273         return ret_val;
1274 }
1275
1276 /**
1277  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1278  *  @hw: pointer to the HW structure
1279  *  @duplex: current duplex setting
1280  *
1281  *  Configure the KMRN interface by applying last minute quirks for
1282  *  10/100 operation.
1283  **/
1284 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1285 {
1286         s32 ret_val = E1000_SUCCESS;
1287         u32 tipg;
1288         u32 i = 0;
1289         u16 reg_data, reg_data2;
1290
1291         DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1292
1293         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1294         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1295                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1296                                        reg_data);
1297         if (ret_val)
1298                 goto out;
1299
1300         /* Configure Transmit Inter-Packet Gap */
1301         tipg = E1000_READ_REG(hw, E1000_TIPG);
1302         tipg &= ~E1000_TIPG_IPGT_MASK;
1303         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1304         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1305
1306
1307         do {
1308                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1309                                                &reg_data);
1310                 if (ret_val)
1311                         goto out;
1312
1313                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1314                                                &reg_data2);
1315                 if (ret_val)
1316                         goto out;
1317                 i++;
1318         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1319
1320         if (duplex == HALF_DUPLEX)
1321                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1322         else
1323                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1324
1325         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1326
1327 out:
1328         return ret_val;
1329 }
1330
1331 /**
1332  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1333  *  @hw: pointer to the HW structure
1334  *
1335  *  Configure the KMRN interface by applying last minute quirks for
1336  *  gigabit operation.
1337  **/
1338 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1339 {
1340         s32 ret_val = E1000_SUCCESS;
1341         u16 reg_data, reg_data2;
1342         u32 tipg;
1343         u32 i = 0;
1344
1345         DEBUGFUNC("e1000_configure_kmrn_for_1000");
1346
1347         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1348         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1349                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1350                                        reg_data);
1351         if (ret_val)
1352                 goto out;
1353
1354         /* Configure Transmit Inter-Packet Gap */
1355         tipg = E1000_READ_REG(hw, E1000_TIPG);
1356         tipg &= ~E1000_TIPG_IPGT_MASK;
1357         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1358         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1359
1360
1361         do {
1362                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1363                                                &reg_data);
1364                 if (ret_val)
1365                         goto out;
1366
1367                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1368                                                &reg_data2);
1369                 if (ret_val)
1370                         goto out;
1371                 i++;
1372         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1373
1374         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1375         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1376
1377 out:
1378         return ret_val;
1379 }
1380
1381 /**
1382  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1383  *  @hw: pointer to the HW structure
1384  *  @offset: register offset to be read
1385  *  @data: pointer to the read data
1386  *
1387  *  Acquire semaphore, then read the PHY register at offset
1388  *  using the kumeran interface.  The information retrieved is stored in data.
1389  *  Release the semaphore before exiting.
1390  **/
1391 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1392                                            u16 *data)
1393 {
1394         u32 kmrnctrlsta;
1395         s32 ret_val = E1000_SUCCESS;
1396
1397         DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1398
1399         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1400         if (ret_val)
1401                 goto out;
1402
1403         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1404                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1405         E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1406
1407         usec_delay(2);
1408
1409         kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1410         *data = (u16)kmrnctrlsta;
1411
1412         e1000_release_mac_csr_80003es2lan(hw);
1413
1414 out:
1415         return ret_val;
1416 }
1417
1418 /**
1419  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1420  *  @hw: pointer to the HW structure
1421  *  @offset: register offset to write to
1422  *  @data: data to write at register offset
1423  *
1424  *  Acquire semaphore, then write the data to PHY register
1425  *  at the offset using the kumeran interface.  Release semaphore
1426  *  before exiting.
1427  **/
1428 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1429                                             u16 data)
1430 {
1431         u32 kmrnctrlsta;
1432         s32 ret_val = E1000_SUCCESS;
1433
1434         DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1435
1436         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1437         if (ret_val)
1438                 goto out;
1439
1440         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1441                        E1000_KMRNCTRLSTA_OFFSET) | data;
1442         E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1443
1444         usec_delay(2);
1445
1446         e1000_release_mac_csr_80003es2lan(hw);
1447
1448 out:
1449         return ret_val;
1450 }
1451
1452 /**
1453  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1454  *  @hw: pointer to the HW structure
1455  **/
1456 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1457 {
1458         s32 ret_val = E1000_SUCCESS;
1459
1460         DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1461
1462         /*
1463          * If there's an alternate MAC address place it in RAR0
1464          * so that it will override the Si installed default perm
1465          * address.
1466          */
1467         ret_val = e1000_check_alt_mac_addr_generic(hw);
1468         if (ret_val)
1469                 goto out;
1470
1471         ret_val = e1000_read_mac_addr_generic(hw);
1472
1473 out:
1474         return ret_val;
1475 }
1476
1477 /**
1478  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1479  * @hw: pointer to the HW structure
1480  *
1481  * In the case of a PHY power down to save power, or to turn off link during a
1482  * driver unload, or wake on lan is not enabled, remove the link.
1483  **/
1484 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1485 {
1486         /* If the management interface is not enabled, then power down */
1487         if (!(hw->mac.ops.check_mng_mode(hw) ||
1488               hw->phy.ops.check_reset_block(hw)))
1489                 e1000_power_down_phy_copper(hw);
1490
1491         return;
1492 }
1493
1494 /**
1495  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1496  *  @hw: pointer to the HW structure
1497  *
1498  *  Clears the hardware counters by reading the counter registers.
1499  **/
1500 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1501 {
1502         DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1503
1504         e1000_clear_hw_cntrs_base_generic(hw);
1505
1506         E1000_READ_REG(hw, E1000_PRC64);
1507         E1000_READ_REG(hw, E1000_PRC127);
1508         E1000_READ_REG(hw, E1000_PRC255);
1509         E1000_READ_REG(hw, E1000_PRC511);
1510         E1000_READ_REG(hw, E1000_PRC1023);
1511         E1000_READ_REG(hw, E1000_PRC1522);
1512         E1000_READ_REG(hw, E1000_PTC64);
1513         E1000_READ_REG(hw, E1000_PTC127);
1514         E1000_READ_REG(hw, E1000_PTC255);
1515         E1000_READ_REG(hw, E1000_PTC511);
1516         E1000_READ_REG(hw, E1000_PTC1023);
1517         E1000_READ_REG(hw, E1000_PTC1522);
1518
1519         E1000_READ_REG(hw, E1000_ALGNERRC);
1520         E1000_READ_REG(hw, E1000_RXERRC);
1521         E1000_READ_REG(hw, E1000_TNCRS);
1522         E1000_READ_REG(hw, E1000_CEXTERR);
1523         E1000_READ_REG(hw, E1000_TSCTC);
1524         E1000_READ_REG(hw, E1000_TSCTFC);
1525
1526         E1000_READ_REG(hw, E1000_MGTPRC);
1527         E1000_READ_REG(hw, E1000_MGTPDC);
1528         E1000_READ_REG(hw, E1000_MGTPTC);
1529
1530         E1000_READ_REG(hw, E1000_IAC);
1531         E1000_READ_REG(hw, E1000_ICRXOC);
1532
1533         E1000_READ_REG(hw, E1000_ICRXPTC);
1534         E1000_READ_REG(hw, E1000_ICRXATC);
1535         E1000_READ_REG(hw, E1000_ICTXPTC);
1536         E1000_READ_REG(hw, E1000_ICTXATC);
1537         E1000_READ_REG(hw, E1000_ICTXQEC);
1538         E1000_READ_REG(hw, E1000_ICTXQMTC);
1539         E1000_READ_REG(hw, E1000_ICRXDMTC);
1540 }