sys/dev/e1000/e1000_82540.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82540EM Gigabit Ethernet Controller
  37  * 82540EP Gigabit Ethernet Controller
  38  * 82545EM Gigabit Ethernet Controller (Copper)
  39  * 82545EM Gigabit Ethernet Controller (Fiber)
  40  * 82545GM Gigabit Ethernet Controller
  41  * 82546EB Gigabit Ethernet Controller (Copper)
  42  * 82546EB Gigabit Ethernet Controller (Fiber)
  43  * 82546GB Gigabit Ethernet Controller
  44  */
  45
  46 #include "e1000_api.h"
  47
  48 static s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
  49 static s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
  50 static s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
  51 static s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
  52 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
  53 static s32  e1000_init_hw_82540(struct e1000_hw *hw);
  54 static s32  e1000_reset_hw_82540(struct e1000_hw *hw);
  55 static s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
  56 static s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
  57 static s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
  58 static s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
  59 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
  60 static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
  61
  62 /**
  63  * e1000_init_phy_params_82540 - Init PHY func ptrs.
  64  * @hw: pointer to the HW structure
  65  **/
  66 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
  67 {
  68         struct e1000_phy_info *phy = &hw->phy;
  69         s32 ret_val = E1000_SUCCESS;
  70
  71         phy->addr                      = 1;
  72         phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  73         phy->reset_delay_us            = 10000;
  74         phy->type                      = e1000_phy_m88;
  75
  76         /* Function Pointers */
  77         phy->ops.check_polarity        = e1000_check_polarity_m88;
  78         phy->ops.commit                = e1000_phy_sw_reset_generic;
  79         phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_m88;
  80         phy->ops.get_cable_length      = e1000_get_cable_length_m88;
  81         phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
  82         phy->ops.read_reg              = e1000_read_phy_reg_m88;
  83         phy->ops.reset                 = e1000_phy_hw_reset_generic;
  84         phy->ops.write_reg             = e1000_write_phy_reg_m88;
  85         phy->ops.get_info              = e1000_get_phy_info_m88;
  86         phy->ops.power_up              = e1000_power_up_phy_copper;
  87         phy->ops.power_down            = e1000_power_down_phy_copper_82540;
  88
  89         ret_val = e1000_get_phy_id(hw);
  90         if (ret_val)
  91                 goto out;
  92
  93         /* Verify phy id */
  94         switch (hw->mac.type) {
  95         case e1000_82540:
  96         case e1000_82545:
  97         case e1000_82545_rev_3:
  98         case e1000_82546:
  99         case e1000_82546_rev_3:
 100                 if (phy->id == M88E1011_I_PHY_ID)
 101                         break;
 102                 /* Fall Through */
 103         default:
 104                 ret_val = -E1000_ERR_PHY;
 105                 goto out;
 106                 break;
 107         }
 108
 109 out:
 110         return ret_val;
 111 }
 112
 113 /**
 114  * e1000_init_nvm_params_82540 - Init NVM func ptrs.
 115  * @hw: pointer to the HW structure
 116  **/
 117 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
 118 {
 119         struct e1000_nvm_info *nvm = &hw->nvm;
 120         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 121
 122         DEBUGFUNC("e1000_init_nvm_params_82540");
 123
 124         nvm->type               = e1000_nvm_eeprom_microwire;
 125         nvm->delay_usec         = 50;
 126         nvm->opcode_bits        = 3;
 127         switch (nvm->override) {
 128         case e1000_nvm_override_microwire_large:
 129                 nvm->address_bits       = 8;
 130                 nvm->word_size          = 256;
 131                 break;
 132         case e1000_nvm_override_microwire_small:
 133                 nvm->address_bits       = 6;
 134                 nvm->word_size          = 64;
 135                 break;
 136         default:
 137                 nvm->address_bits       = eecd & E1000_EECD_SIZE ? 8 : 6;
 138                 nvm->word_size          = eecd & E1000_EECD_SIZE ? 256 : 64;
 139                 break;
 140         }
 141
 142         /* Function Pointers */
 143         nvm->ops.acquire            = e1000_acquire_nvm_generic;
 144         nvm->ops.read               = e1000_read_nvm_microwire;
 145         nvm->ops.release            = e1000_release_nvm_generic;
 146         nvm->ops.update             = e1000_update_nvm_checksum_generic;
 147         nvm->ops.valid_led_default  = e1000_valid_led_default_generic;
 148         nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
 149         nvm->ops.write              = e1000_write_nvm_microwire;
 150
 151         return E1000_SUCCESS;
 152 }
 153
 154 /**
 155  * e1000_init_mac_params_82540 - Init MAC func ptrs.
 156  * @hw: pointer to the HW structure
 157  **/
 158 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
 159 {
 160         struct e1000_mac_info *mac = &hw->mac;
 161         s32 ret_val = E1000_SUCCESS;
 162
 163         DEBUGFUNC("e1000_init_mac_params_82540");
 164
 165         /* Set media type */
 166         switch (hw->device_id) {
 167         case E1000_DEV_ID_82545EM_FIBER:
 168         case E1000_DEV_ID_82545GM_FIBER:
 169         case E1000_DEV_ID_82546EB_FIBER:
 170         case E1000_DEV_ID_82546GB_FIBER:
 171                 hw->phy.media_type = e1000_media_type_fiber;
 172                 break;
 173         case E1000_DEV_ID_82545GM_SERDES:
 174         case E1000_DEV_ID_82546GB_SERDES:
 175                 hw->phy.media_type = e1000_media_type_internal_serdes;
 176                 break;
 177         default:
 178                 hw->phy.media_type = e1000_media_type_copper;
 179                 break;
 180         }
 181
 182         /* Set mta register count */
 183         mac->mta_reg_count = 128;
 184         /* Set rar entry count */
 185         mac->rar_entry_count = E1000_RAR_ENTRIES;
 186
 187         /* Function pointers */
 188
 189         /* bus type/speed/width */
 190         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 191         /* function id */
 192         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 193         /* reset */
 194         mac->ops.reset_hw = e1000_reset_hw_82540;
 195         /* hw initialization */
 196         mac->ops.init_hw = e1000_init_hw_82540;
 197         /* link setup */
 198         mac->ops.setup_link = e1000_setup_link_generic;
 199         /* physical interface setup */
 200         mac->ops.setup_physical_interface =
 201                 (hw->phy.media_type == e1000_media_type_copper)
 202                         ? e1000_setup_copper_link_82540
 203                         : e1000_setup_fiber_serdes_link_82540;
 204         /* check for link */
 205         switch (hw->phy.media_type) {
 206         case e1000_media_type_copper:
 207                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 208                 break;
 209         case e1000_media_type_fiber:
 210                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 211                 break;
 212         case e1000_media_type_internal_serdes:
 213                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 214                 break;
 215         default:
 216                 ret_val = -E1000_ERR_CONFIG;
 217                 goto out;
 218                 break;
 219         }
 220         /* link info */
 221         mac->ops.get_link_up_info =
 222                 (hw->phy.media_type == e1000_media_type_copper)
 223                         ? e1000_get_speed_and_duplex_copper_generic
 224                         : e1000_get_speed_and_duplex_fiber_serdes_generic;
 225         /* multicast address update */
 226         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 227         /* writing VFTA */
 228         mac->ops.write_vfta = e1000_write_vfta_generic;
 229         /* clearing VFTA */
 230         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 231         /* setting MTA */
 232         mac->ops.mta_set = e1000_mta_set_generic;
 233         /* read mac address */
 234         mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
 235         /* ID LED init */
 236         mac->ops.id_led_init = e1000_id_led_init_generic;
 237         /* setup LED */
 238         mac->ops.setup_led = e1000_setup_led_generic;
 239         /* cleanup LED */
 240         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 241         /* turn on/off LED */
 242         mac->ops.led_on = e1000_led_on_generic;
 243         mac->ops.led_off = e1000_led_off_generic;
 244         /* clear hardware counters */
 245         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
 246
 247 out:
 248         return ret_val;
 249 }
 250
 251 /**
 252  * e1000_init_function_pointers_82540 - Init func ptrs.
 253  * @hw: pointer to the HW structure
 254  *
 255  * Called to initialize all function pointers and parameters.
 256  **/
 257 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
 258 {
 259         DEBUGFUNC("e1000_init_function_pointers_82540");
 260
 261         hw->mac.ops.init_params = e1000_init_mac_params_82540;
 262         hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
 263         hw->phy.ops.init_params = e1000_init_phy_params_82540;
 264 }
 265
 266 /**
 267  *  e1000_reset_hw_82540 - Reset hardware
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  This resets the hardware into a known state.
 271  **/
 272 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
 273 {
 274         u32 ctrl, icr, manc;
 275         s32 ret_val = E1000_SUCCESS;
 276
 277         DEBUGFUNC("e1000_reset_hw_82540");
 278
 279         DEBUGOUT("Masking off all interrupts\n");
 280         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 281
 282         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 283         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 284         E1000_WRITE_FLUSH(hw);
 285
 286         /*
 287          * Delay to allow any outstanding PCI transactions to complete
 288          * before resetting the device.
 289          */
 290         msec_delay(10);
 291
 292         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 293
 294         DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
 295         switch (hw->mac.type) {
 296         case e1000_82545_rev_3:
 297         case e1000_82546_rev_3:
 298                 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
 299                 break;
 300         default:
 301                 /*
 302                  * These controllers can't ack the 64-bit write when
 303                  * issuing the reset, so we use IO-mapping as a
 304                  * workaround to issue the reset.
 305                  */
 306                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 307                 break;
 308         }
 309
 310         /* Wait for EEPROM reload */
 311         msec_delay(5);
 312
 313         /* Disable HW ARPs on ASF enabled adapters */
 314         manc = E1000_READ_REG(hw, E1000_MANC);
 315         manc &= ~E1000_MANC_ARP_EN;
 316         E1000_WRITE_REG(hw, E1000_MANC, manc);
 317
 318         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 319         icr = E1000_READ_REG(hw, E1000_ICR);
 320
 321         return ret_val;
 322 }
 323
 324 /**
 325  *  e1000_init_hw_82540 - Initialize hardware
 326  *  @hw: pointer to the HW structure
 327  *
 328  *  This inits the hardware readying it for operation.
 329  **/
 330 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
 331 {
 332         struct e1000_mac_info *mac = &hw->mac;
 333         u32 txdctl, ctrl_ext;
 334         s32 ret_val = E1000_SUCCESS;
 335         u16 i;
 336
 337         DEBUGFUNC("e1000_init_hw_82540");
 338
 339         /* Initialize identification LED */
 340         ret_val = mac->ops.id_led_init(hw);
 341         if (ret_val) {
 342                 DEBUGOUT("Error initializing identification LED\n");
 343                 /* This is not fatal and we should not stop init due to this */
 344         }
 345
 346         /* Disabling VLAN filtering */
 347         DEBUGOUT("Initializing the IEEE VLAN\n");
 348         if (mac->type < e1000_82545_rev_3)
 349                 E1000_WRITE_REG(hw, E1000_VET, 0);
 350
 351         mac->ops.clear_vfta(hw);
 352
 353         /* Setup the receive address. */
 354         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 355
 356         /* Zero out the Multicast HASH table */
 357         DEBUGOUT("Zeroing the MTA\n");
 358         for (i = 0; i < mac->mta_reg_count; i++) {
 359                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 360                 /*
 361                  * Avoid back to back register writes by adding the register
 362                  * read (flush).  This is to protect against some strange
 363                  * bridge configurations that may issue Memory Write Block
 364                  * (MWB) to our register space.  The *_rev_3 hardware at
 365                  * least doesn't respond correctly to every other dword in an
 366                  * MWB to our register space.
 367                  */
 368                 E1000_WRITE_FLUSH(hw);
 369         }
 370
 371         if (mac->type < e1000_82545_rev_3)
 372                 e1000_pcix_mmrbc_workaround_generic(hw);
 373
 374         /* Setup link and flow control */
 375         ret_val = mac->ops.setup_link(hw);
 376
 377         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 378         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 379                  E1000_TXDCTL_FULL_TX_DESC_WB;
 380         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 381
 382         /*
 383          * Clear all of the statistics registers (clear on read).  It is
 384          * important that we do this after we have tried to establish link
 385          * because the symbol error count will increment wildly if there
 386          * is no link.
 387          */
 388         e1000_clear_hw_cntrs_82540(hw);
 389
 390         if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
 391             (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
 392                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 393                 /*
 394                  * Relaxed ordering must be disabled to avoid a parity
 395                  * error crash in a PCI slot.
 396                  */
 397                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
 398                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 399         }
 400
 401         return ret_val;
 402 }
 403
 404 /**
 405  *  e1000_setup_copper_link_82540 - Configure copper link settings
 406  *  @hw: pointer to the HW structure
 407  *
 408  *  Calls the appropriate function to configure the link for auto-neg or forced
 409  *  speed and duplex.  Then we check for link, once link is established calls
 410  *  to configure collision distance and flow control are called.  If link is
 411  *  not established, we return -E1000_ERR_PHY (-2).
 412  **/
 413 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
 414 {
 415         u32 ctrl;
 416         s32 ret_val = E1000_SUCCESS;
 417         u16 data;
 418
 419         DEBUGFUNC("e1000_setup_copper_link_82540");
 420
 421         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 422         ctrl |= E1000_CTRL_SLU;
 423         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 424         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 425
 426         ret_val = e1000_set_phy_mode_82540(hw);
 427         if (ret_val)
 428                 goto out;
 429
 430         if (hw->mac.type == e1000_82545_rev_3 ||
 431             hw->mac.type == e1000_82546_rev_3) {
 432                 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
 433                 if (ret_val)
 434                         goto out;
 435                 data |= 0x00000008;
 436                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
 437                 if (ret_val)
 438                         goto out;
 439         }
 440
 441         ret_val = e1000_copper_link_setup_m88(hw);
 442         if (ret_val)
 443                 goto out;
 444
 445         ret_val = e1000_setup_copper_link_generic(hw);
 446
 447 out:
 448         return ret_val;
 449 }
 450
 451 /**
 452  *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
 453  *  @hw: pointer to the HW structure
 454  *
 455  *  Set the output amplitude to the value in the EEPROM and adjust the VCO
 456  *  speed to improve Bit Error Rate (BER) performance.  Configures collision
 457  *  distance and flow control for fiber and serdes links.  Upon successful
 458  *  setup, poll for link.
 459  **/
 460 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
 461 {
 462         struct e1000_mac_info *mac = &hw->mac;
 463         s32 ret_val = E1000_SUCCESS;
 464
 465         DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
 466
 467         switch (mac->type) {
 468         case e1000_82545_rev_3:
 469         case e1000_82546_rev_3:
 470                 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
 471                         /*
 472                          * If we're on serdes media, adjust the output
 473                          * amplitude to value set in the EEPROM.
 474                          */
 475                         ret_val = e1000_adjust_serdes_amplitude_82540(hw);
 476                         if (ret_val)
 477                                 goto out;
 478                 }
 479                 /* Adjust VCO speed to improve BER performance */
 480                 ret_val = e1000_set_vco_speed_82540(hw);
 481                 if (ret_val)
 482                         goto out;
 483         default:
 484                 break;
 485         }
 486
 487         ret_val = e1000_setup_fiber_serdes_link_generic(hw);
 488
 489 out:
 490         return ret_val;
 491 }
 492
 493 /**
 494  *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
 495  *  @hw: pointer to the HW structure
 496  *
 497  *  Adjust the SERDES output amplitude based on the EEPROM settings.
 498  **/
 499 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
 500 {
 501         s32 ret_val = E1000_SUCCESS;
 502         u16 nvm_data;
 503
 504         DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
 505
 506         ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
 507         if (ret_val)
 508                 goto out;
 509
 510         if (nvm_data != NVM_RESERVED_WORD) {
 511                 /* Adjust serdes output amplitude only. */
 512                 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
 513                 ret_val = hw->phy.ops.write_reg(hw,
 514                                              M88E1000_PHY_EXT_CTRL,
 515                                              nvm_data);
 516                 if (ret_val)
 517                         goto out;
 518         }
 519
 520 out:
 521         return ret_val;
 522 }
 523
 524 /**
 525  *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
 526  *  @hw: pointer to the HW structure
 527  *
 528  *  Set the VCO speed to improve Bit Error Rate (BER) performance.
 529  **/
 530 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
 531 {
 532         s32  ret_val = E1000_SUCCESS;
 533         u16 default_page = 0;
 534         u16 phy_data;
 535
 536         DEBUGFUNC("e1000_set_vco_speed_82540");
 537
 538         /* Set PHY register 30, page 5, bit 8 to 0 */
 539
 540         ret_val = hw->phy.ops.read_reg(hw,
 541                                     M88E1000_PHY_PAGE_SELECT,
 542                                     &default_page);
 543         if (ret_val)
 544                 goto out;
 545
 546         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
 547         if (ret_val)
 548                 goto out;
 549
 550         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 551         if (ret_val)
 552                 goto out;
 553
 554         phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
 555         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 556         if (ret_val)
 557                 goto out;
 558
 559         /* Set PHY register 30, page 4, bit 11 to 1 */
 560
 561         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
 562         if (ret_val)
 563                 goto out;
 564
 565         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 566         if (ret_val)
 567                 goto out;
 568
 569         phy_data |= M88E1000_PHY_VCO_REG_BIT11;
 570         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 571         if (ret_val)
 572                 goto out;
 573
 574         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
 575                                       default_page);
 576
 577 out:
 578         return ret_val;
 579 }
 580
 581 /**
 582  *  e1000_set_phy_mode_82540 - Set PHY to class A mode
 583  *  @hw: pointer to the HW structure
 584  *
 585  *  Sets the PHY to class A mode and assumes the following operations will
 586  *  follow to enable the new class mode:
 587  *    1.  Do a PHY soft reset.
 588  *    2.  Restart auto-negotiation or force link.
 589  **/
 590 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
 591 {
 592         struct e1000_phy_info *phy = &hw->phy;
 593         s32 ret_val = E1000_SUCCESS;
 594         u16 nvm_data;
 595
 596         DEBUGFUNC("e1000_set_phy_mode_82540");
 597
 598         if (hw->mac.type != e1000_82545_rev_3)
 599                 goto out;
 600
 601         ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
 602         if (ret_val) {
 603                 ret_val = -E1000_ERR_PHY;
 604                 goto out;
 605         }
 606
 607         if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
 608                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
 609                                               0x000B);
 610                 if (ret_val) {
 611                         ret_val = -E1000_ERR_PHY;
 612                         goto out;
 613                 }
 614                 ret_val = hw->phy.ops.write_reg(hw,
 615                                               M88E1000_PHY_GEN_CONTROL,
 616                                               0x8104);
 617                 if (ret_val) {
 618                         ret_val = -E1000_ERR_PHY;
 619                         goto out;
 620                 }
 621
 622                 phy->reset_disable = FALSE;
 623         }
 624
 625 out:
 626         return ret_val;
 627 }
 628
 629 /**
 630  * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
 631  * @hw: pointer to the HW structure
 632  *
 633  * In the case of a PHY power down to save power, or to turn off link during a
 634  * driver unload, or wake on lan is not enabled, remove the link.
 635  **/
 636 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
 637 {
 638         /* If the management interface is not enabled, then power down */
 639         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
 640                 e1000_power_down_phy_copper(hw);
 641
 642         return;
 643 }
 644
 645 /**
 646  *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
 647  *  @hw: pointer to the HW structure
 648  *
 649  *  Clears the hardware counters by reading the counter registers.
 650  **/
 651 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
 652 {
 653         DEBUGFUNC("e1000_clear_hw_cntrs_82540");
 654
 655         e1000_clear_hw_cntrs_base_generic(hw);
 656
 657         E1000_READ_REG(hw, E1000_PRC64);
 658         E1000_READ_REG(hw, E1000_PRC127);
 659         E1000_READ_REG(hw, E1000_PRC255);
 660         E1000_READ_REG(hw, E1000_PRC511);
 661         E1000_READ_REG(hw, E1000_PRC1023);
 662         E1000_READ_REG(hw, E1000_PRC1522);
 663         E1000_READ_REG(hw, E1000_PTC64);
 664         E1000_READ_REG(hw, E1000_PTC127);
 665         E1000_READ_REG(hw, E1000_PTC255);
 666         E1000_READ_REG(hw, E1000_PTC511);
 667         E1000_READ_REG(hw, E1000_PTC1023);
 668         E1000_READ_REG(hw, E1000_PTC1522);
 669
 670         E1000_READ_REG(hw, E1000_ALGNERRC);
 671         E1000_READ_REG(hw, E1000_RXERRC);
 672         E1000_READ_REG(hw, E1000_TNCRS);
 673         E1000_READ_REG(hw, E1000_CEXTERR);
 674         E1000_READ_REG(hw, E1000_TSCTC);
 675         E1000_READ_REG(hw, E1000_TSCTFC);
 676
 677         E1000_READ_REG(hw, E1000_MGTPRC);
 678         E1000_READ_REG(hw, E1000_MGTPDC);
 679         E1000_READ_REG(hw, E1000_MGTPTC);
 680 }
 681
 682 /**
 683  *  e1000_read_mac_addr_82540 - Read device MAC address
 684  *  @hw: pointer to the HW structure
 685  *
 686  *  Reads the device MAC address from the EEPROM and stores the value.
 687  *  Since devices with two ports use the same EEPROM, we increment the
 688  *  last bit in the MAC address for the second port.
 689  *
 690  *  This version is being used over generic because of customer issues
 691  *  with VmWare and Virtual Box when using generic. It seems in
 692  *  the emulated 82545, RAR[0] does NOT have a valid address after a
 693  *  reset, this older method works and using this breaks nothing for
 694  *  these legacy adapters.
 695  **/
 696 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
 697 {
 698         s32  ret_val = E1000_SUCCESS;
 699         u16 offset, nvm_data, i;
 700
 701         DEBUGFUNC("e1000_read_mac_addr");
 702
 703         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
 704                 offset = i >> 1;
 705                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 706                 if (ret_val) {
 707                         DEBUGOUT("NVM Read Error\n");
 708                         goto out;
 709                 }
 710                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
 711                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
 712         }
 713
 714         /* Flip last bit of mac address if we're on second port */
 715         if (hw->bus.func == E1000_FUNC_1)
 716                 hw->mac.perm_addr[5] ^= 1;
 717
 718         for (i = 0; i < ETH_ADDR_LEN; i++)
 719                 hw->mac.addr[i] = hw->mac.perm_addr[i];
 720
 721 out:
 722         return ret_val;
 723 }