sys/dev/e1000/e1000_ich8lan.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82562G 10/100 Network Connection
  37  * 82562G-2 10/100 Network Connection
  38  * 82562GT 10/100 Network Connection
  39  * 82562GT-2 10/100 Network Connection
  40  * 82562V 10/100 Network Connection
  41  * 82562V-2 10/100 Network Connection
  42  * 82566DC-2 Gigabit Network Connection
  43  * 82566DC Gigabit Network Connection
  44  * 82566DM-2 Gigabit Network Connection
  45  * 82566DM Gigabit Network Connection
  46  * 82566MC Gigabit Network Connection
  47  * 82566MM Gigabit Network Connection
  48  * 82567LM Gigabit Network Connection
  49  * 82567LF Gigabit Network Connection
  50  * 82567V Gigabit Network Connection
  51  * 82567LM-2 Gigabit Network Connection
  52  * 82567LF-2 Gigabit Network Connection
  53  * 82567V-2 Gigabit Network Connection
  54  * 82567LF-3 Gigabit Network Connection
  55  * 82567LM-3 Gigabit Network Connection
  56  * 82567LM-4 Gigabit Network Connection
  57  * 82577LM Gigabit Network Connection
  58  * 82577LC Gigabit Network Connection
  59  * 82578DM Gigabit Network Connection
  60  * 82578DC Gigabit Network Connection
  61  */
  62
  63 #include "e1000_api.h"
  64
  65 static s32  e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
  66 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
  67 static s32  e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
  68 static s32  e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
  69 static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  70 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  71 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  72 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  73 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  74 static s32  e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
  75 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  76                                             bool active);
  77 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  78                                             bool active);
  79 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  80                                    u16 words, u16 *data);
  81 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  82                                     u16 words, u16 *data);
  83 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  84 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  85 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  86                                             u16 *data);
  87 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  88 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  89 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  90 static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  91 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  92 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  93 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  94                                            u16 *speed, u16 *duplex);
  95 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  96 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  97 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  98 static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
  99 static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 100 static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 101 static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 102 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 103 static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 104 static s32  e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
 105 static s32  e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
 106 static s32  e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
 107 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 108 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 109 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 110                                           u32 offset, u8 *data);
 111 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 112                                           u8 size, u16 *data);
 113 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 114                                           u32 offset, u16 *data);
 115 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 116                                                  u32 offset, u8 byte);
 117 static s32  e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
 118                                            u32 offset, u8 data);
 119 static s32  e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 120                                            u8 size, u16 data);
 121 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 122 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 123
 124 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 125 /* Offset 04h HSFSTS */
 126 union ich8_hws_flash_status {
 127         struct ich8_hsfsts {
 128                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 129                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 130                 u16 dael       :1; /* bit 2 Direct Access error Log */
 131                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 132                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 133                 u16 reserved1  :2; /* bit 13:6 Reserved */
 134                 u16 reserved2  :6; /* bit 13:6 Reserved */
 135                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 136                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 137         } hsf_status;
 138         u16 regval;
 139 };
 140
 141 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 142 /* Offset 06h FLCTL */
 143 union ich8_hws_flash_ctrl {
 144         struct ich8_hsflctl {
 145                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 146                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 147                 u16 reserved   :5;   /* 7:3 Reserved  */
 148                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 149                 u16 flockdn    :6;   /* 15:10 Reserved */
 150         } hsf_ctrl;
 151         u16 regval;
 152 };
 153
 154 /* ICH Flash Region Access Permissions */
 155 union ich8_hws_flash_regacc {
 156         struct ich8_flracc {
 157                 u32 grra      :8; /* 0:7 GbE region Read Access */
 158                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 159                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 160                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 161         } hsf_flregacc;
 162         u16 regval;
 163 };
 164
 165 /**
 166  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 167  *  @hw: pointer to the HW structure
 168  *
 169  *  Initialize family-specific PHY parameters and function pointers.
 170  **/
 171 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 172 {
 173         struct e1000_phy_info *phy = &hw->phy;
 174         s32 ret_val = E1000_SUCCESS;
 175
 176         DEBUGFUNC("e1000_init_phy_params_pchlan");
 177
 178         phy->addr                     = 1;
 179         phy->reset_delay_us           = 100;
 180
 181         phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
 182         phy->ops.check_polarity       = e1000_check_polarity_ife;
 183         phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
 184         phy->ops.force_speed_duplex   = e1000_phy_force_speed_duplex_ife;
 185         phy->ops.get_cable_length     = e1000_get_cable_length_igp_2;
 186         phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
 187         phy->ops.get_info             = e1000_get_phy_info_ich8lan;
 188         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 189         phy->ops.release              = e1000_release_swflag_ich8lan;
 190         phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
 191         phy->ops.set_d0_lplu_state    = e1000_set_d0_lplu_state_ich8lan;
 192         phy->ops.set_d3_lplu_state    = e1000_set_d3_lplu_state_ich8lan;
 193         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 194         phy->ops.power_up             = e1000_power_up_phy_copper;
 195         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 196         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 197
 198         phy->id = e1000_phy_unknown;
 199         e1000_get_phy_id(hw);
 200         phy->type = e1000_get_phy_type_from_id(phy->id);
 201
 202         if (phy->type == e1000_phy_82577) {
 203                 phy->ops.check_polarity = e1000_check_polarity_82577;
 204                 phy->ops.force_speed_duplex =
 205                         e1000_phy_force_speed_duplex_82577;
 206                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 207                 phy->ops.get_info = e1000_get_phy_info_82577;
 208                 phy->ops.commit = e1000_phy_sw_reset_generic;
 209         }
 210
 211         return ret_val;
 212 }
 213
 214 /**
 215  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 216  *  @hw: pointer to the HW structure
 217  *
 218  *  Initialize family-specific PHY parameters and function pointers.
 219  **/
 220 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 221 {
 222         struct e1000_phy_info *phy = &hw->phy;
 223         s32 ret_val = E1000_SUCCESS;
 224         u16 i = 0;
 225
 226         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 227
 228         phy->addr                     = 1;
 229         phy->reset_delay_us           = 100;
 230
 231         phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
 232         phy->ops.check_polarity       = e1000_check_polarity_ife;
 233         phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
 234         phy->ops.force_speed_duplex   = e1000_phy_force_speed_duplex_ife;
 235         phy->ops.get_cable_length     = e1000_get_cable_length_igp_2;
 236         phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
 237         phy->ops.get_info             = e1000_get_phy_info_ich8lan;
 238         phy->ops.read_reg             = e1000_read_phy_reg_igp;
 239         phy->ops.release              = e1000_release_swflag_ich8lan;
 240         phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
 241         phy->ops.set_d0_lplu_state    = e1000_set_d0_lplu_state_ich8lan;
 242         phy->ops.set_d3_lplu_state    = e1000_set_d3_lplu_state_ich8lan;
 243         phy->ops.write_reg            = e1000_write_phy_reg_igp;
 244         phy->ops.power_up             = e1000_power_up_phy_copper;
 245         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 246
 247         /*
 248          * We may need to do this twice - once for IGP and if that fails,
 249          * we'll set BM func pointers and try again
 250          */
 251         ret_val = e1000_determine_phy_address(hw);
 252         if (ret_val) {
 253                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 254                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 255                 ret_val = e1000_determine_phy_address(hw);
 256                 if (ret_val) {
 257                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 258                         goto out;
 259                 }
 260         }
 261
 262         phy->id = 0;
 263         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 264                (i++ < 100)) {
 265                 msec_delay(1);
 266                 ret_val = e1000_get_phy_id(hw);
 267                 if (ret_val)
 268                         goto out;
 269         }
 270
 271         /* Verify phy id */
 272         switch (phy->id) {
 273         case IGP03E1000_E_PHY_ID:
 274                 phy->type = e1000_phy_igp_3;
 275                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 276                 break;
 277         case IFE_E_PHY_ID:
 278         case IFE_PLUS_E_PHY_ID:
 279         case IFE_C_E_PHY_ID:
 280                 phy->type = e1000_phy_ife;
 281                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 282                 break;
 283         case BME1000_E_PHY_ID:
 284                 phy->type = e1000_phy_bm;
 285                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 286                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 287                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 288                 phy->ops.commit = e1000_phy_sw_reset_generic;
 289                 break;
 290         default:
 291                 ret_val = -E1000_ERR_PHY;
 292                 goto out;
 293         }
 294
 295 out:
 296         return ret_val;
 297 }
 298
 299 /**
 300  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Initialize family-specific NVM parameters and function
 304  *  pointers.
 305  **/
 306 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 307 {
 308         struct e1000_nvm_info *nvm = &hw->nvm;
 309         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 310         u32 gfpreg, sector_base_addr, sector_end_addr;
 311         s32 ret_val = E1000_SUCCESS;
 312         u16 i;
 313
 314         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 315
 316         /* Can't read flash registers if the register set isn't mapped. */
 317         if (!hw->flash_address) {
 318                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 319                 ret_val = -E1000_ERR_CONFIG;
 320                 goto out;
 321         }
 322
 323         nvm->type = e1000_nvm_flash_sw;
 324
 325         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 326
 327         /*
 328          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 329          * Add 1 to sector_end_addr since this sector is included in
 330          * the overall size.
 331          */
 332         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 333         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 334
 335         /* flash_base_addr is byte-aligned */
 336         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 337
 338         /*
 339          * find total size of the NVM, then cut in half since the total
 340          * size represents two separate NVM banks.
 341          */
 342         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 343                                   << FLASH_SECTOR_ADDR_SHIFT;
 344         nvm->flash_bank_size /= 2;
 345         /* Adjust to word count */
 346         nvm->flash_bank_size /= sizeof(u16);
 347
 348         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 349
 350         /* Clear shadow ram */
 351         for (i = 0; i < nvm->word_size; i++) {
 352                 dev_spec->shadow_ram[i].modified = FALSE;
 353                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 354         }
 355
 356         /* Function Pointers */
 357         nvm->ops.acquire       = e1000_acquire_swflag_ich8lan;
 358         nvm->ops.read          = e1000_read_nvm_ich8lan;
 359         nvm->ops.release       = e1000_release_swflag_ich8lan;
 360         nvm->ops.update        = e1000_update_nvm_checksum_ich8lan;
 361         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 362         nvm->ops.validate      = e1000_validate_nvm_checksum_ich8lan;
 363         nvm->ops.write         = e1000_write_nvm_ich8lan;
 364
 365 out:
 366         return ret_val;
 367 }
 368
 369 /**
 370  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 371  *  @hw: pointer to the HW structure
 372  *
 373  *  Initialize family-specific MAC parameters and function
 374  *  pointers.
 375  **/
 376 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 377 {
 378         struct e1000_mac_info *mac = &hw->mac;
 379         u16 pci_cfg;
 380
 381         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 382
 383         /* Set media type function pointer */
 384         hw->phy.media_type = e1000_media_type_copper;
 385
 386         /* Set mta register count */
 387         mac->mta_reg_count = 32;
 388         /* Set rar entry count */
 389         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 390         if (mac->type == e1000_ich8lan)
 391                 mac->rar_entry_count--;
 392         /* Set if part includes ASF firmware */
 393         mac->asf_firmware_present = TRUE;
 394         /* Set if manageability features are enabled. */
 395         mac->arc_subsystem_valid = TRUE;
 396
 397         /* Function pointers */
 398
 399         /* bus type/speed/width */
 400         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 401         /* function id */
 402         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 403         /* reset */
 404         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 405         /* hw initialization */
 406         mac->ops.init_hw = e1000_init_hw_ich8lan;
 407         /* link setup */
 408         mac->ops.setup_link = e1000_setup_link_ich8lan;
 409         /* physical interface setup */
 410         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 411         /* check for link */
 412         mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 413         /* check management mode */
 414         mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 415         /* link info */
 416         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 417         /* multicast address update */
 418         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 419         /* setting MTA */
 420         mac->ops.mta_set = e1000_mta_set_generic;
 421         /* clear hardware counters */
 422         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 423
 424         /* LED operations */
 425         switch (mac->type) {
 426         case e1000_ich8lan:
 427         case e1000_ich9lan:
 428         case e1000_ich10lan:
 429                 /* ID LED init */
 430                 mac->ops.id_led_init = e1000_id_led_init_generic;
 431                 /* blink LED */
 432                 mac->ops.blink_led = e1000_blink_led_generic;
 433                 /* setup LED */
 434                 mac->ops.setup_led = e1000_setup_led_generic;
 435                 /* cleanup LED */
 436                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 437                 /* turn on/off LED */
 438                 mac->ops.led_on = e1000_led_on_ich8lan;
 439                 mac->ops.led_off = e1000_led_off_ich8lan;
 440                 break;
 441         case e1000_pchlan:
 442                 /* save PCH revision_id */
 443                 e1000_read_pci_cfg(hw, 0x2, &pci_cfg);
 444                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 445                 /* ID LED init */
 446                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 447                 /* setup LED */
 448                 mac->ops.setup_led = e1000_setup_led_pchlan;
 449                 /* cleanup LED */
 450                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 451                 /* turn on/off LED */
 452                 mac->ops.led_on = e1000_led_on_pchlan;
 453                 mac->ops.led_off = e1000_led_off_pchlan;
 454                 break;
 455         default:
 456                 break;
 457         }
 458
 459         /* Enable PCS Lock-loss workaround for ICH8 */
 460         if (mac->type == e1000_ich8lan)
 461                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
 462
 463
 464         return E1000_SUCCESS;
 465 }
 466
 467 /**
 468  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
 469  *  @hw: pointer to the HW structure
 470  *
 471  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
 472  **/
 473 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
 474 {
 475         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
 476
 477         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
 478         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
 479         switch (hw->mac.type) {
 480         case e1000_ich8lan:
 481         case e1000_ich9lan:
 482         case e1000_ich10lan:
 483                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
 484                 break;
 485         case e1000_pchlan:
 486                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
 487                 break;
 488         default:
 489                 break;
 490         }
 491 }
 492
 493 /**
 494  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 495  *  @hw: pointer to the HW structure
 496  *
 497  *  Acquires the software control flag for performing NVM and PHY
 498  *  operations.  This is a function pointer entry point only called by
 499  *  read/write routines for the PHY and NVM parts.
 500  **/
 501 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 502 {
 503         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 504         s32 ret_val = E1000_SUCCESS;
 505
 506         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
 507
 508         while (timeout) {
 509                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 510
 511                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
 512                         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 513                         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 514
 515                         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 516                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 517                                 break;
 518                 }
 519                 msec_delay_irq(1);
 520                 timeout--;
 521         }
 522
 523         if (!timeout) {
 524                 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
 525                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 526                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 527                 ret_val = -E1000_ERR_CONFIG;
 528                 goto out;
 529         }
 530
 531 out:
 532         return ret_val;
 533 }
 534
 535 /**
 536  *  e1000_release_swflag_ich8lan - Release software control flag
 537  *  @hw: pointer to the HW structure
 538  *
 539  *  Releases the software control flag for performing NVM and PHY operations.
 540  *  This is a function pointer entry point only called by read/write
 541  *  routines for the PHY and NVM parts.
 542  **/
 543 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 544 {
 545         u32 extcnf_ctrl;
 546
 547         DEBUGFUNC("e1000_release_swflag_ich8lan");
 548
 549         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 550         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 551         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 552
 553         return;
 554 }
 555
 556 /**
 557  *  e1000_check_mng_mode_ich8lan - Checks management mode
 558  *  @hw: pointer to the HW structure
 559  *
 560  *  This checks if the adapter has manageability enabled.
 561  *  This is a function pointer entry point only called by read/write
 562  *  routines for the PHY and NVM parts.
 563  **/
 564 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 565 {
 566         u32 fwsm;
 567
 568         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
 569
 570         fwsm = E1000_READ_REG(hw, E1000_FWSM);
 571
 572         return (fwsm & E1000_FWSM_MODE_MASK) ==
 573                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 574 }
 575
 576 /**
 577  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 578  *  @hw: pointer to the HW structure
 579  *
 580  *  Checks if firmware is blocking the reset of the PHY.
 581  *  This is a function pointer entry point only called by
 582  *  reset routines.
 583  **/
 584 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 585 {
 586         u32 fwsm;
 587
 588         DEBUGFUNC("e1000_check_reset_block_ich8lan");
 589
 590         fwsm = E1000_READ_REG(hw, E1000_FWSM);
 591
 592         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
 593                                                 : E1000_BLK_PHY_RESET;
 594 }
 595
 596 /**
 597  *  e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
 598  *  @hw: pointer to the HW structure
 599  **/
 600 s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
 601 {
 602         if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
 603                 return E1000_SUCCESS;
 604
 605         return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444);
 606 }
 607
 608 /**
 609  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 610  *  done after every PHY reset.
 611  **/
 612 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 613 {
 614         s32 ret_val = E1000_SUCCESS;
 615
 616         if (hw->mac.type != e1000_pchlan)
 617                 return ret_val;
 618
 619         /* Hanksville M Phy init for IEEE. */
 620         if ((hw->revision_id == 2) &&
 621             (hw->phy.type == e1000_phy_82577) &&
 622             ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
 623                 hw->phy.ops.write_reg(hw, 0x10, 0x8823);
 624                 hw->phy.ops.write_reg(hw, 0x11, 0x0018);
 625                 hw->phy.ops.write_reg(hw, 0x10, 0x8824);
 626                 hw->phy.ops.write_reg(hw, 0x11, 0x0016);
 627                 hw->phy.ops.write_reg(hw, 0x10, 0x8825);
 628                 hw->phy.ops.write_reg(hw, 0x11, 0x001A);
 629                 hw->phy.ops.write_reg(hw, 0x10, 0x888C);
 630                 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
 631                 hw->phy.ops.write_reg(hw, 0x10, 0x888D);
 632                 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
 633                 hw->phy.ops.write_reg(hw, 0x10, 0x888E);
 634                 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
 635                 hw->phy.ops.write_reg(hw, 0x10, 0x8827);
 636                 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
 637                 hw->phy.ops.write_reg(hw, 0x10, 0x8835);
 638                 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
 639                 hw->phy.ops.write_reg(hw, 0x10, 0x8834);
 640                 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
 641                 hw->phy.ops.write_reg(hw, 0x10, 0x8833);
 642                 hw->phy.ops.write_reg(hw, 0x11, 0x0002);
 643         }
 644
 645         if (((hw->phy.type == e1000_phy_82577) &&
 646              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 647             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
 648                 /* Disable generation of early preamble */
 649                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
 650                 if (ret_val)
 651                         return ret_val;
 652
 653                 /* Preamble tuning for SSC */
 654                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
 655                 if (ret_val)
 656                         return ret_val;
 657         }
 658
 659         if (hw->phy.type == e1000_phy_82578) {
 660                 if (hw->revision_id < 3) {
 661                         /* PHY config */
 662                         ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
 663                                                         0x66C0);
 664                         if (ret_val)
 665                                 return ret_val;
 666
 667                         /* PHY config */
 668                         ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
 669                                                         0xFFFF);
 670                         if (ret_val)
 671                                 return ret_val;
 672                 }
 673
 674                 /*
 675                  * Return registers to default by doing a soft reset then
 676                  * writing 0x3140 to the control register.
 677                  */
 678                 if (hw->phy.revision < 2) {
 679                         e1000_phy_sw_reset_generic(hw);
 680                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
 681                                                         0x3140);
 682                 }
 683         }
 684
 685         if ((hw->revision_id == 2) &&
 686             (hw->phy.type == e1000_phy_82577) &&
 687             ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
 688                 /*
 689                  * Workaround for OEM (GbE) not operating after reset -
 690                  * restart AN (twice)
 691                  */
 692                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
 693                 if (ret_val)
 694                         return ret_val;
 695                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
 696                 if (ret_val)
 697                         return ret_val;
 698         }
 699
 700         /* Select page 0 */
 701         ret_val = hw->phy.ops.acquire(hw);
 702         if (ret_val)
 703                 return ret_val;
 704         hw->phy.addr = 1;
 705         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
 706         hw->phy.ops.release(hw);
 707
 708         return ret_val;
 709 }
 710
 711 /**
 712  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
 713  *  @hw: pointer to the HW structure
 714  *
 715  *  Check the appropriate indication the MAC has finished configuring the
 716  *  PHY after a software reset.
 717  **/
 718 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
 719 {
 720         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 721
 722         DEBUGFUNC("e1000_lan_init_done_ich8lan");
 723
 724         /* Wait for basic configuration completes before proceeding */
 725         do {
 726                 data = E1000_READ_REG(hw, E1000_STATUS);
 727                 data &= E1000_STATUS_LAN_INIT_DONE;
 728                 usec_delay(100);
 729         } while ((!data) && --loop);
 730
 731         /*
 732          * If basic configuration is incomplete before the above loop
 733          * count reaches 0, loading the configuration from NVM will
 734          * leave the PHY in a bad state possibly resulting in no link.
 735          */
 736         if (loop == 0)
 737                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
 738
 739         /* Clear the Init Done bit for the next init event */
 740         data = E1000_READ_REG(hw, E1000_STATUS);
 741         data &= ~E1000_STATUS_LAN_INIT_DONE;
 742         E1000_WRITE_REG(hw, E1000_STATUS, data);
 743 }
 744
 745 /**
 746  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 747  *  @hw: pointer to the HW structure
 748  *
 749  *  Resets the PHY
 750  *  This is a function pointer entry point called by drivers
 751  *  or other shared routines.
 752  **/
 753 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 754 {
 755         struct e1000_phy_info *phy = &hw->phy;
 756         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 757         s32 ret_val;
 758         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 759
 760         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
 761
 762         ret_val = e1000_phy_hw_reset_generic(hw);
 763         if (ret_val)
 764                 goto out;
 765
 766         /* Allow time for h/w to get to a quiescent state after reset */
 767         msec_delay(10);
 768
 769         if (hw->mac.type == e1000_pchlan) {
 770                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
 771                 if (ret_val)
 772                         goto out;
 773         }
 774
 775         /*
 776          * Initialize the PHY from the NVM on ICH platforms.  This
 777          * is needed due to an issue where the NVM configuration is
 778          * not properly autoloaded after power transitions.
 779          * Therefore, after each PHY reset, we will load the
 780          * configuration data out of the NVM manually.
 781          */
 782         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 783                 /* Check if SW needs configure the PHY */
 784                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 785                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
 786                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 787                 else
 788                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 789
 790                 data = E1000_READ_REG(hw, E1000_FEXTNVM);
 791                 if (!(data & sw_cfg_mask))
 792                         goto out;
 793
 794                 /* Wait for basic configuration completes before proceeding */
 795                 e1000_lan_init_done_ich8lan(hw);
 796
 797                 /*
 798                  * Make sure HW does not configure LCD from PHY
 799                  * extended configuration before SW configuration
 800                  */
 801                 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 802                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 803                         goto out;
 804
 805                 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
 806                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 807                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 808                 if (!cnf_size)
 809                         goto out;
 810
 811                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 812                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 813
 814                 /* Configure LCD from extended configuration region. */
 815
 816                 /* cnf_base_addr is in DWORD */
 817                 word_addr = (u16)(cnf_base_addr << 1);
 818
 819                 for (i = 0; i < cnf_size; i++) {
 820                         ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
 821                                                    &reg_data);
 822                         if (ret_val)
 823                                 goto out;
 824
 825                         ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
 826                                                    1, &reg_addr);
 827                         if (ret_val)
 828                                 goto out;
 829
 830                         /* Save off the PHY page for future writes. */
 831                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 832                                 phy_page = reg_data;
 833                                 continue;
 834                         }
 835
 836                         reg_addr |= phy_page;
 837
 838                         ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data);
 839                         if (ret_val)
 840                                 goto out;
 841                 }
 842         }
 843
 844 out:
 845         return ret_val;
 846 }
 847
 848 /**
 849  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 850  *  @hw: pointer to the HW structure
 851  *
 852  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 853  **/
 854 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 855 {
 856         s32 ret_val = -E1000_ERR_PHY_TYPE;
 857
 858         DEBUGFUNC("e1000_get_phy_info_ich8lan");
 859
 860         switch (hw->phy.type) {
 861         case e1000_phy_ife:
 862                 ret_val = e1000_get_phy_info_ife_ich8lan(hw);
 863                 break;
 864         case e1000_phy_igp_3:
 865         case e1000_phy_bm:
 866         case e1000_phy_82578:
 867         case e1000_phy_82577:
 868                 ret_val = e1000_get_phy_info_igp(hw);
 869                 break;
 870         default:
 871                 break;
 872         }
 873
 874         return ret_val;
 875 }
 876
 877 /**
 878  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 879  *  @hw: pointer to the HW structure
 880  *
 881  *  Populates "phy" structure with various feature states.
 882  *  This function is only called by other family-specific
 883  *  routines.
 884  **/
 885 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 886 {
 887         struct e1000_phy_info *phy = &hw->phy;
 888         s32 ret_val;
 889         u16 data;
 890         bool link;
 891
 892         DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
 893
 894         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 895         if (ret_val)
 896                 goto out;
 897
 898         if (!link) {
 899                 DEBUGOUT("Phy info is only valid if link is up\n");
 900                 ret_val = -E1000_ERR_CONFIG;
 901                 goto out;
 902         }
 903
 904         ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 905         if (ret_val)
 906                 goto out;
 907         phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
 908                                    ? FALSE : TRUE;
 909
 910         if (phy->polarity_correction) {
 911                 ret_val = e1000_check_polarity_ife(hw);
 912                 if (ret_val)
 913                         goto out;
 914         } else {
 915                 /* Polarity is forced */
 916                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 917                                       ? e1000_rev_polarity_reversed
 918                                       : e1000_rev_polarity_normal;
 919         }
 920
 921         ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
 922         if (ret_val)
 923                 goto out;
 924
 925         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
 926
 927         /* The following parameters are undefined for 10/100 operation. */
 928         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 929         phy->local_rx = e1000_1000t_rx_status_undefined;
 930         phy->remote_rx = e1000_1000t_rx_status_undefined;
 931
 932 out:
 933         return ret_val;
 934 }
 935
 936 /**
 937  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 938  *  @hw: pointer to the HW structure
 939  *  @active: TRUE to enable LPLU, FALSE to disable
 940  *
 941  *  Sets the LPLU D0 state according to the active flag.  When
 942  *  activating LPLU this function also disables smart speed
 943  *  and vice versa.  LPLU will not be activated unless the
 944  *  device autonegotiation advertisement meets standards of
 945  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 946  *  This is a function pointer entry point only called by
 947  *  PHY setup routines.
 948  **/
 949 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 950 {
 951         struct e1000_phy_info *phy = &hw->phy;
 952         u32 phy_ctrl;
 953         s32 ret_val = E1000_SUCCESS;
 954         u16 data;
 955
 956         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
 957
 958         if (phy->type == e1000_phy_ife)
 959                 goto out;
 960
 961         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
 962
 963         if (active) {
 964                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 965                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 966
 967                 if (phy->type != e1000_phy_igp_3)
 968                         goto out;
 969
 970                 /*
 971                  * Call gig speed drop workaround on LPLU before accessing
 972                  * any PHY registers
 973                  */
 974                 if (hw->mac.type == e1000_ich8lan)
 975                         e1000_gig_downshift_workaround_ich8lan(hw);
 976
 977                 /* When LPLU is enabled, we should disable SmartSpeed */
 978                 ret_val = phy->ops.read_reg(hw,
 979                                             IGP01E1000_PHY_PORT_CONFIG,
 980                                             &data);
 981                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 982                 ret_val = phy->ops.write_reg(hw,
 983                                              IGP01E1000_PHY_PORT_CONFIG,
 984                                              data);
 985                 if (ret_val)
 986                         goto out;
 987         } else {
 988                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 989                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 990
 991                 if (phy->type != e1000_phy_igp_3)
 992                         goto out;
 993
 994                 /*
 995                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 996                  * during Dx states where the power conservation is most
 997                  * important.  During driver activity we should enable
 998                  * SmartSpeed, so performance is maintained.
 999                  */
1000                 if (phy->smart_speed == e1000_smart_speed_on) {
1001                         ret_val = phy->ops.read_reg(hw,
1002                                                     IGP01E1000_PHY_PORT_CONFIG,
1003                                                     &data);
1004                         if (ret_val)
1005                                 goto out;
1006
1007                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1008                         ret_val = phy->ops.write_reg(hw,
1009                                                      IGP01E1000_PHY_PORT_CONFIG,
1010                                                      data);
1011                         if (ret_val)
1012                                 goto out;
1013                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1014                         ret_val = phy->ops.read_reg(hw,
1015                                                     IGP01E1000_PHY_PORT_CONFIG,
1016                                                     &data);
1017                         if (ret_val)
1018                                 goto out;
1019
1020                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1021                         ret_val = phy->ops.write_reg(hw,
1022                                                      IGP01E1000_PHY_PORT_CONFIG,
1023                                                      data);
1024                         if (ret_val)
1025                                 goto out;
1026                 }
1027         }
1028
1029 out:
1030         return ret_val;
1031 }
1032
1033 /**
1034  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1035  *  @hw: pointer to the HW structure
1036  *  @active: TRUE to enable LPLU, FALSE to disable
1037  *
1038  *  Sets the LPLU D3 state according to the active flag.  When
1039  *  activating LPLU this function also disables smart speed
1040  *  and vice versa.  LPLU will not be activated unless the
1041  *  device autonegotiation advertisement meets standards of
1042  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1043  *  This is a function pointer entry point only called by
1044  *  PHY setup routines.
1045  **/
1046 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1047 {
1048         struct e1000_phy_info *phy = &hw->phy;
1049         u32 phy_ctrl;
1050         s32 ret_val = E1000_SUCCESS;
1051         u16 data;
1052
1053         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
1054
1055         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
1056
1057         if (!active) {
1058                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1059                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1060
1061                 if (phy->type != e1000_phy_igp_3)
1062                         goto out;
1063
1064                 /*
1065                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1066                  * during Dx states where the power conservation is most
1067                  * important.  During driver activity we should enable
1068                  * SmartSpeed, so performance is maintained.
1069                  */
1070                 if (phy->smart_speed == e1000_smart_speed_on) {
1071                         ret_val = phy->ops.read_reg(hw,
1072                                                     IGP01E1000_PHY_PORT_CONFIG,
1073                                                     &data);
1074                         if (ret_val)
1075                                 goto out;
1076
1077                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1078                         ret_val = phy->ops.write_reg(hw,
1079                                                      IGP01E1000_PHY_PORT_CONFIG,
1080                                                      data);
1081                         if (ret_val)
1082                                 goto out;
1083                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1084                         ret_val = phy->ops.read_reg(hw,
1085                                                     IGP01E1000_PHY_PORT_CONFIG,
1086                                                     &data);
1087                         if (ret_val)
1088                                 goto out;
1089
1090                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1091                         ret_val = phy->ops.write_reg(hw,
1092                                                      IGP01E1000_PHY_PORT_CONFIG,
1093                                                      data);
1094                         if (ret_val)
1095                                 goto out;
1096                 }
1097         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1098                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1099                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1100                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1101                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1102
1103                 if (phy->type != e1000_phy_igp_3)
1104                         goto out;
1105
1106                 /*
1107                  * Call gig speed drop workaround on LPLU before accessing
1108                  * any PHY registers
1109                  */
1110                 if (hw->mac.type == e1000_ich8lan)
1111                         e1000_gig_downshift_workaround_ich8lan(hw);
1112
1113                 /* When LPLU is enabled, we should disable SmartSpeed */
1114                 ret_val = phy->ops.read_reg(hw,
1115                                             IGP01E1000_PHY_PORT_CONFIG,
1116                                             &data);
1117                 if (ret_val)
1118                         goto out;
1119
1120                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1121                 ret_val = phy->ops.write_reg(hw,
1122                                              IGP01E1000_PHY_PORT_CONFIG,
1123                                              data);
1124         }
1125
1126 out:
1127         return ret_val;
1128 }
1129
1130 /**
1131  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1132  *  @hw: pointer to the HW structure
1133  *  @bank:  pointer to the variable that returns the active bank
1134  *
1135  *  Reads signature byte from the NVM using the flash access registers.
1136  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1137  **/
1138 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1139 {
1140         u32 eecd;
1141         struct e1000_nvm_info *nvm = &hw->nvm;
1142         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1143         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1144         u8 sig_byte = 0;
1145         s32 ret_val = E1000_SUCCESS;
1146
1147         switch (hw->mac.type) {
1148         case e1000_ich8lan:
1149         case e1000_ich9lan:
1150                 eecd = E1000_READ_REG(hw, E1000_EECD);
1151                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1152                     E1000_EECD_SEC1VAL_VALID_MASK) {
1153                         if (eecd & E1000_EECD_SEC1VAL)
1154                                 *bank = 1;
1155                         else
1156                                 *bank = 0;
1157
1158                         goto out;
1159                 }
1160                 DEBUGOUT("Unable to determine valid NVM bank via EEC - "
1161                          "reading flash signature\n");
1162                 /* fall-thru */
1163         default:
1164                 /* set bank to 0 in case flash read fails */
1165                 *bank = 0;
1166
1167                 /* Check bank 0 */
1168                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1169                                                         &sig_byte);
1170                 if (ret_val)
1171                         goto out;
1172                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1173                         E1000_ICH_NVM_SIG_VALUE) {
1174                         *bank = 0;
1175                         goto out;
1176                 }
1177
1178                 /* Check bank 1 */
1179                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1180                                                         bank1_offset,
1181                                                         &sig_byte);
1182                 if (ret_val)
1183                         goto out;
1184                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1185                         E1000_ICH_NVM_SIG_VALUE) {
1186                         *bank = 1;
1187                         goto out;
1188                 }
1189
1190                 DEBUGOUT("ERROR: No valid NVM bank present\n");
1191                 ret_val = -E1000_ERR_NVM;
1192                 break;
1193         }
1194 out:
1195         return ret_val;
1196 }
1197
1198 /**
1199  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1200  *  @hw: pointer to the HW structure
1201  *  @offset: The offset (in bytes) of the word(s) to read.
1202  *  @words: Size of data to read in words
1203  *  @data: Pointer to the word(s) to read at offset.
1204  *
1205  *  Reads a word(s) from the NVM using the flash access registers.
1206  **/
1207 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1208                                   u16 *data)
1209 {
1210         struct e1000_nvm_info *nvm = &hw->nvm;
1211         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1212         u32 act_offset;
1213         s32 ret_val = E1000_SUCCESS;
1214         u32 bank = 0;
1215         u16 i, word;
1216
1217         DEBUGFUNC("e1000_read_nvm_ich8lan");
1218
1219         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1220             (words == 0)) {
1221                 DEBUGOUT("nvm parameter(s) out of bounds\n");
1222                 ret_val = -E1000_ERR_NVM;
1223                 goto out;
1224         }
1225
1226         ret_val = nvm->ops.acquire(hw);
1227         if (ret_val)
1228                 goto out;
1229
1230         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1231         if (ret_val != E1000_SUCCESS)
1232                 goto release;
1233
1234         act_offset = (bank) ? nvm->flash_bank_size : 0;
1235         act_offset += offset;
1236
1237         for (i = 0; i < words; i++) {
1238                 if ((dev_spec->shadow_ram) &&
1239                     (dev_spec->shadow_ram[offset+i].modified)) {
1240                         data[i] = dev_spec->shadow_ram[offset+i].value;
1241                 } else {
1242                         ret_val = e1000_read_flash_word_ich8lan(hw,
1243                                                                 act_offset + i,
1244                                                                 &word);
1245                         if (ret_val)
1246                                 break;
1247                         data[i] = word;
1248                 }
1249         }
1250
1251 release:
1252         nvm->ops.release(hw);
1253
1254 out:
1255         if (ret_val)
1256                 DEBUGOUT1("NVM read error: %d\n", ret_val);
1257
1258         return ret_val;
1259 }
1260
1261 /**
1262  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1263  *  @hw: pointer to the HW structure
1264  *
1265  *  This function does initial flash setup so that a new read/write/erase cycle
1266  *  can be started.
1267  **/
1268 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1269 {
1270         union ich8_hws_flash_status hsfsts;
1271         s32 ret_val = -E1000_ERR_NVM;
1272         s32 i = 0;
1273
1274         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1275
1276         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1277
1278         /* Check if the flash descriptor is valid */
1279         if (hsfsts.hsf_status.fldesvalid == 0) {
1280                 DEBUGOUT("Flash descriptor invalid.  "
1281                          "SW Sequencing must be used.");
1282                 goto out;
1283         }
1284
1285         /* Clear FCERR and DAEL in hw status by writing 1 */
1286         hsfsts.hsf_status.flcerr = 1;
1287         hsfsts.hsf_status.dael = 1;
1288
1289         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1290
1291         /*
1292          * Either we should have a hardware SPI cycle in progress
1293          * bit to check against, in order to start a new cycle or
1294          * FDONE bit should be changed in the hardware so that it
1295          * is 1 after hardware reset, which can then be used as an
1296          * indication whether a cycle is in progress or has been
1297          * completed.
1298          */
1299
1300         if (hsfsts.hsf_status.flcinprog == 0) {
1301                 /*
1302                  * There is no cycle running at present,
1303                  * so we can start a cycle.
1304                  * Begin by setting Flash Cycle Done.
1305                  */
1306                 hsfsts.hsf_status.flcdone = 1;
1307                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1308                 ret_val = E1000_SUCCESS;
1309         } else {
1310                 /*
1311                  * Otherwise poll for sometime so the current
1312                  * cycle has a chance to end before giving up.
1313                  */
1314                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1315                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1316                                                               ICH_FLASH_HSFSTS);
1317                         if (hsfsts.hsf_status.flcinprog == 0) {
1318                                 ret_val = E1000_SUCCESS;
1319                                 break;
1320                         }
1321                         usec_delay(1);
1322                 }
1323                 if (ret_val == E1000_SUCCESS) {
1324                         /*
1325                          * Successful in waiting for previous cycle to timeout,
1326                          * now set the Flash Cycle Done.
1327                          */
1328                         hsfsts.hsf_status.flcdone = 1;
1329                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
1330                                                 hsfsts.regval);
1331                 } else {
1332                         DEBUGOUT("Flash controller busy, cannot get access");
1333                 }
1334         }
1335
1336 out:
1337         return ret_val;
1338 }
1339
1340 /**
1341  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1342  *  @hw: pointer to the HW structure
1343  *  @timeout: maximum time to wait for completion
1344  *
1345  *  This function starts a flash cycle and waits for its completion.
1346  **/
1347 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1348 {
1349         union ich8_hws_flash_ctrl hsflctl;
1350         union ich8_hws_flash_status hsfsts;
1351         s32 ret_val = -E1000_ERR_NVM;
1352         u32 i = 0;
1353
1354         DEBUGFUNC("e1000_flash_cycle_ich8lan");
1355
1356         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1357         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1358         hsflctl.hsf_ctrl.flcgo = 1;
1359         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1360
1361         /* wait till FDONE bit is set to 1 */
1362         do {
1363                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1364                 if (hsfsts.hsf_status.flcdone == 1)
1365                         break;
1366                 usec_delay(1);
1367         } while (i++ < timeout);
1368
1369         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1370                 ret_val = E1000_SUCCESS;
1371
1372         return ret_val;
1373 }
1374
1375 /**
1376  *  e1000_read_flash_word_ich8lan - Read word from flash
1377  *  @hw: pointer to the HW structure
1378  *  @offset: offset to data location
1379  *  @data: pointer to the location for storing the data
1380  *
1381  *  Reads the flash word at offset into data.  Offset is converted
1382  *  to bytes before read.
1383  **/
1384 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1385                                          u16 *data)
1386 {
1387         s32 ret_val;
1388
1389         DEBUGFUNC("e1000_read_flash_word_ich8lan");
1390
1391         if (!data) {
1392                 ret_val = -E1000_ERR_NVM;
1393                 goto out;
1394         }
1395
1396         /* Must convert offset into bytes. */
1397         offset <<= 1;
1398
1399         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1400
1401 out:
1402         return ret_val;
1403 }
1404
1405 /**
1406  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1407  *  @hw: pointer to the HW structure
1408  *  @offset: The offset of the byte to read.
1409  *  @data: Pointer to a byte to store the value read.
1410  *
1411  *  Reads a single byte from the NVM using the flash access registers.
1412  **/
1413 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1414                                          u8 *data)
1415 {
1416         s32 ret_val = E1000_SUCCESS;
1417         u16 word = 0;
1418
1419         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1420         if (ret_val)
1421                 goto out;
1422
1423         *data = (u8)word;
1424
1425 out:
1426         return ret_val;
1427 }
1428
1429 /**
1430  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1431  *  @hw: pointer to the HW structure
1432  *  @offset: The offset (in bytes) of the byte or word to read.
1433  *  @size: Size of data to read, 1=byte 2=word
1434  *  @data: Pointer to the word to store the value read.
1435  *
1436  *  Reads a byte or word from the NVM using the flash access registers.
1437  **/
1438 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1439                                          u8 size, u16 *data)
1440 {
1441         union ich8_hws_flash_status hsfsts;
1442         union ich8_hws_flash_ctrl hsflctl;
1443         u32 flash_linear_addr;
1444         u32 flash_data = 0;
1445         s32 ret_val = -E1000_ERR_NVM;
1446         u8 count = 0;
1447
1448         DEBUGFUNC("e1000_read_flash_data_ich8lan");
1449
1450         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1451                 goto out;
1452
1453         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1454                             hw->nvm.flash_base_addr;
1455
1456         do {
1457                 usec_delay(1);
1458                 /* Steps */
1459                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1460                 if (ret_val != E1000_SUCCESS)
1461                         break;
1462
1463                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1464                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1465                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1466                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1467                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1468
1469                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1470
1471                 ret_val = e1000_flash_cycle_ich8lan(hw,
1472                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1473
1474                 /*
1475                  * Check if FCERR is set to 1, if set to 1, clear it
1476                  * and try the whole sequence a few more times, else
1477                  * read in (shift in) the Flash Data0, the order is
1478                  * least significant byte first msb to lsb
1479                  */
1480                 if (ret_val == E1000_SUCCESS) {
1481                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1482                         if (size == 1)
1483                                 *data = (u8)(flash_data & 0x000000FF);
1484                         else if (size == 2)
1485                                 *data = (u16)(flash_data & 0x0000FFFF);
1486                         break;
1487                 } else {
1488                         /*
1489                          * If we've gotten here, then things are probably
1490                          * completely hosed, but if the error condition is
1491                          * detected, it won't hurt to give it another try...
1492                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1493                          */
1494                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1495                                                               ICH_FLASH_HSFSTS);
1496                         if (hsfsts.hsf_status.flcerr == 1) {
1497                                 /* Repeat for some time before giving up. */
1498                                 continue;
1499                         } else if (hsfsts.hsf_status.flcdone == 0) {
1500                                 DEBUGOUT("Timeout error - flash cycle "
1501                                          "did not complete.");
1502                                 break;
1503                         }
1504                 }
1505         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1506
1507 out:
1508         return ret_val;
1509 }
1510
1511 /**
1512  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1513  *  @hw: pointer to the HW structure
1514  *  @offset: The offset (in bytes) of the word(s) to write.
1515  *  @words: Size of data to write in words
1516  *  @data: Pointer to the word(s) to write at offset.
1517  *
1518  *  Writes a byte or word to the NVM using the flash access registers.
1519  **/
1520 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1521                                    u16 *data)
1522 {
1523         struct e1000_nvm_info *nvm = &hw->nvm;
1524         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1525         s32 ret_val = E1000_SUCCESS;
1526         u16 i;
1527
1528         DEBUGFUNC("e1000_write_nvm_ich8lan");
1529
1530         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1531             (words == 0)) {
1532                 DEBUGOUT("nvm parameter(s) out of bounds\n");
1533                 ret_val = -E1000_ERR_NVM;
1534                 goto out;
1535         }
1536
1537         ret_val = nvm->ops.acquire(hw);
1538         if (ret_val)
1539                 goto out;
1540
1541         for (i = 0; i < words; i++) {
1542                 dev_spec->shadow_ram[offset+i].modified = TRUE;
1543                 dev_spec->shadow_ram[offset+i].value = data[i];
1544         }
1545
1546         nvm->ops.release(hw);
1547
1548 out:
1549         return ret_val;
1550 }
1551
1552 /**
1553  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1554  *  @hw: pointer to the HW structure
1555  *
1556  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1557  *  which writes the checksum to the shadow ram.  The changes in the shadow
1558  *  ram are then committed to the EEPROM by processing each bank at a time
1559  *  checking for the modified bit and writing only the pending changes.
1560  *  After a successful commit, the shadow ram is cleared and is ready for
1561  *  future writes.
1562  **/
1563 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1564 {
1565         struct e1000_nvm_info *nvm = &hw->nvm;
1566         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1567         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1568         s32 ret_val;
1569         u16 data;
1570
1571         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1572
1573         ret_val = e1000_update_nvm_checksum_generic(hw);
1574         if (ret_val)
1575                 goto out;
1576
1577         if (nvm->type != e1000_nvm_flash_sw)
1578                 goto out;
1579
1580         ret_val = nvm->ops.acquire(hw);
1581         if (ret_val)
1582                 goto out;
1583
1584         /*
1585          * We're writing to the opposite bank so if we're on bank 1,
1586          * write to bank 0 etc.  We also need to erase the segment that
1587          * is going to be written
1588          */
1589         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1590         if (ret_val != E1000_SUCCESS) {
1591                 nvm->ops.release(hw);
1592                 goto out;
1593         }
1594
1595         if (bank == 0) {
1596                 new_bank_offset = nvm->flash_bank_size;
1597                 old_bank_offset = 0;
1598                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1599                 if (ret_val) {
1600                         nvm->ops.release(hw);
1601                         goto out;
1602                 }
1603         } else {
1604                 old_bank_offset = nvm->flash_bank_size;
1605                 new_bank_offset = 0;
1606                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1607                 if (ret_val) {
1608                         nvm->ops.release(hw);
1609                         goto out;
1610                 }
1611         }
1612
1613         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1614                 /*
1615                  * Determine whether to write the value stored
1616                  * in the other NVM bank or a modified value stored
1617                  * in the shadow RAM
1618                  */
1619                 if (dev_spec->shadow_ram[i].modified) {
1620                         data = dev_spec->shadow_ram[i].value;
1621                 } else {
1622                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1623                                                                 old_bank_offset,
1624                                                                 &data);
1625                         if (ret_val)
1626                                 break;
1627                 }
1628
1629                 /*
1630                  * If the word is 0x13, then make sure the signature bits
1631                  * (15:14) are 11b until the commit has completed.
1632                  * This will allow us to write 10b which indicates the
1633                  * signature is valid.  We want to do this after the write
1634                  * has completed so that we don't mark the segment valid
1635                  * while the write is still in progress
1636                  */
1637                 if (i == E1000_ICH_NVM_SIG_WORD)
1638                         data |= E1000_ICH_NVM_SIG_MASK;
1639
1640                 /* Convert offset to bytes. */
1641                 act_offset = (i + new_bank_offset) << 1;
1642
1643                 usec_delay(100);
1644                 /* Write the bytes to the new bank. */
1645                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1646                                                                act_offset,
1647                                                                (u8)data);
1648                 if (ret_val)
1649                         break;
1650
1651                 usec_delay(100);
1652                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1653                                                           act_offset + 1,
1654                                                           (u8)(data >> 8));
1655                 if (ret_val)
1656                         break;
1657         }
1658
1659         /*
1660          * Don't bother writing the segment valid bits if sector
1661          * programming failed.
1662          */
1663         if (ret_val) {
1664                 DEBUGOUT("Flash commit failed.\n");
1665                 nvm->ops.release(hw);
1666                 goto out;
1667         }
1668
1669         /*
1670          * Finally validate the new segment by setting bit 15:14
1671          * to 10b in word 0x13 , this can be done without an
1672          * erase as well since these bits are 11 to start with
1673          * and we need to change bit 14 to 0b
1674          */
1675         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1676         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1677         if (ret_val) {
1678                 nvm->ops.release(hw);
1679                 goto out;
1680         }
1681         data &= 0xBFFF;
1682         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1683                                                        act_offset * 2 + 1,
1684                                                        (u8)(data >> 8));
1685         if (ret_val) {
1686                 nvm->ops.release(hw);
1687                 goto out;
1688         }
1689
1690         /*
1691          * And invalidate the previously valid segment by setting
1692          * its signature word (0x13) high_byte to 0b. This can be
1693          * done without an erase because flash erase sets all bits
1694          * to 1's. We can write 1's to 0's without an erase
1695          */
1696         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1697         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1698         if (ret_val) {
1699                 nvm->ops.release(hw);
1700                 goto out;
1701         }
1702
1703         /* Great!  Everything worked, we can now clear the cached entries. */
1704         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1705                 dev_spec->shadow_ram[i].modified = FALSE;
1706                 dev_spec->shadow_ram[i].value = 0xFFFF;
1707         }
1708
1709         nvm->ops.release(hw);
1710
1711         /*
1712          * Reload the EEPROM, or else modifications will not appear
1713          * until after the next adapter reset.
1714          */
1715         nvm->ops.reload(hw);
1716         msec_delay(10);
1717
1718 out:
1719         if (ret_val)
1720                 DEBUGOUT1("NVM update error: %d\n", ret_val);
1721
1722         return ret_val;
1723 }
1724
1725 /**
1726  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1727  *  @hw: pointer to the HW structure
1728  *
1729  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1730  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1731  *  calculated, in which case we need to calculate the checksum and set bit 6.
1732  **/
1733 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1734 {
1735         s32 ret_val = E1000_SUCCESS;
1736         u16 data;
1737
1738         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1739
1740         /*
1741          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1742          * needs to be fixed.  This bit is an indication that the NVM
1743          * was prepared by OEM software and did not calculate the
1744          * checksum...a likely scenario.
1745          */
1746         ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
1747         if (ret_val)
1748                 goto out;
1749
1750         if ((data & 0x40) == 0) {
1751                 data |= 0x40;
1752                 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
1753                 if (ret_val)
1754                         goto out;
1755                 ret_val = hw->nvm.ops.update(hw);
1756                 if (ret_val)
1757                         goto out;
1758         }
1759
1760         ret_val = e1000_validate_nvm_checksum_generic(hw);
1761
1762 out:
1763         return ret_val;
1764 }
1765
1766 /**
1767  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1768  *  @hw: pointer to the HW structure
1769  *  @offset: The offset (in bytes) of the byte/word to read.
1770  *  @size: Size of data to read, 1=byte 2=word
1771  *  @data: The byte(s) to write to the NVM.
1772  *
1773  *  Writes one/two bytes to the NVM using the flash access registers.
1774  **/
1775 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1776                                           u8 size, u16 data)
1777 {
1778         union ich8_hws_flash_status hsfsts;
1779         union ich8_hws_flash_ctrl hsflctl;
1780         u32 flash_linear_addr;
1781         u32 flash_data = 0;
1782         s32 ret_val = -E1000_ERR_NVM;
1783         u8 count = 0;
1784
1785         DEBUGFUNC("e1000_write_ich8_data");
1786
1787         if (size < 1 || size > 2 || data > size * 0xff ||
1788             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1789                 goto out;
1790
1791         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1792                             hw->nvm.flash_base_addr;
1793
1794         do {
1795                 usec_delay(1);
1796                 /* Steps */
1797                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1798                 if (ret_val != E1000_SUCCESS)
1799                         break;
1800
1801                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1802                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1803                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1804                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1805                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1806
1807                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1808
1809                 if (size == 1)
1810                         flash_data = (u32)data & 0x00FF;
1811                 else
1812                         flash_data = (u32)data;
1813
1814                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
1815
1816                 /*
1817                  * check if FCERR is set to 1 , if set to 1, clear it
1818                  * and try the whole sequence a few more times else done
1819                  */
1820                 ret_val = e1000_flash_cycle_ich8lan(hw,
1821                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1822                 if (ret_val == E1000_SUCCESS)
1823                         break;
1824
1825                 /*
1826                  * If we're here, then things are most likely
1827                  * completely hosed, but if the error condition
1828                  * is detected, it won't hurt to give it another
1829                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1830                  */
1831                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1832                 if (hsfsts.hsf_status.flcerr == 1) {
1833                         /* Repeat for some time before giving up. */
1834                         continue;
1835                 } else if (hsfsts.hsf_status.flcdone == 0) {
1836                         DEBUGOUT("Timeout error - flash cycle "
1837                                  "did not complete.");
1838                         break;
1839                 }
1840         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1841
1842 out:
1843         return ret_val;
1844 }
1845
1846 /**
1847  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1848  *  @hw: pointer to the HW structure
1849  *  @offset: The index of the byte to read.
1850  *  @data: The byte to write to the NVM.
1851  *
1852  *  Writes a single byte to the NVM using the flash access registers.
1853  **/
1854 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1855                                           u8 data)
1856 {
1857         u16 word = (u16)data;
1858
1859         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1860
1861         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1862 }
1863
1864 /**
1865  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1866  *  @hw: pointer to the HW structure
1867  *  @offset: The offset of the byte to write.
1868  *  @byte: The byte to write to the NVM.
1869  *
1870  *  Writes a single byte to the NVM using the flash access registers.
1871  *  Goes through a retry algorithm before giving up.
1872  **/
1873 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1874                                                 u32 offset, u8 byte)
1875 {
1876         s32 ret_val;
1877         u16 program_retries;
1878
1879         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
1880
1881         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1882         if (ret_val == E1000_SUCCESS)
1883                 goto out;
1884
1885         for (program_retries = 0; program_retries < 100; program_retries++) {
1886                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
1887                 usec_delay(100);
1888                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1889                 if (ret_val == E1000_SUCCESS)
1890                         break;
1891         }
1892         if (program_retries == 100) {
1893                 ret_val = -E1000_ERR_NVM;
1894                 goto out;
1895         }
1896
1897 out:
1898         return ret_val;
1899 }
1900
1901 /**
1902  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1903  *  @hw: pointer to the HW structure
1904  *  @bank: 0 for first bank, 1 for second bank, etc.
1905  *
1906  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1907  *  bank N is 4096 * N + flash_reg_addr.
1908  **/
1909 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1910 {
1911         struct e1000_nvm_info *nvm = &hw->nvm;
1912         union ich8_hws_flash_status hsfsts;
1913         union ich8_hws_flash_ctrl hsflctl;
1914         u32 flash_linear_addr;
1915         /* bank size is in 16bit words - adjust to bytes */
1916         u32 flash_bank_size = nvm->flash_bank_size * 2;
1917         s32 ret_val = E1000_SUCCESS;
1918         s32 count = 0;
1919         s32 j, iteration, sector_size;
1920
1921         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
1922
1923         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1924
1925         /*
1926          * Determine HW Sector size: Read BERASE bits of hw flash status
1927          * register
1928          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1929          *     consecutive sectors.  The start index for the nth Hw sector
1930          *     can be calculated as = bank * 4096 + n * 256
1931          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1932          *     The start index for the nth Hw sector can be calculated
1933          *     as = bank * 4096
1934          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1935          *     (ich9 only, otherwise error condition)
1936          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1937          */
1938         switch (hsfsts.hsf_status.berasesz) {
1939         case 0:
1940                 /* Hw sector size 256 */
1941                 sector_size = ICH_FLASH_SEG_SIZE_256;
1942                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1943                 break;
1944         case 1:
1945                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1946                 iteration = 1;
1947                 break;
1948         case 2:
1949                 sector_size = ICH_FLASH_SEG_SIZE_8K;
1950                 iteration = 1;
1951                 break;
1952         case 3:
1953                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1954                 iteration = 1;
1955                 break;
1956         default:
1957                 ret_val = -E1000_ERR_NVM;
1958                 goto out;
1959         }
1960
1961         /* Start with the base address, then add the sector offset. */
1962         flash_linear_addr = hw->nvm.flash_base_addr;
1963         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1964
1965         for (j = 0; j < iteration ; j++) {
1966                 do {
1967                         /* Steps */
1968                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1969                         if (ret_val)
1970                                 goto out;
1971
1972                         /*
1973                          * Write a value 11 (block Erase) in Flash
1974                          * Cycle field in hw flash control
1975                          */
1976                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
1977                                                               ICH_FLASH_HSFCTL);
1978                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1979                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
1980                                                 hsflctl.regval);
1981
1982                         /*
1983                          * Write the last 24 bits of an index within the
1984                          * block into Flash Linear address field in Flash
1985                          * Address.
1986                          */
1987                         flash_linear_addr += (j * sector_size);
1988                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
1989                                               flash_linear_addr);
1990
1991                         ret_val = e1000_flash_cycle_ich8lan(hw,
1992                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1993                         if (ret_val == E1000_SUCCESS)
1994                                 break;
1995
1996                         /*
1997                          * Check if FCERR is set to 1.  If 1,
1998                          * clear it and try the whole sequence
1999                          * a few more times else Done
2000                          */
2001                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2002                                                       ICH_FLASH_HSFSTS);
2003                         if (hsfsts.hsf_status.flcerr == 1)
2004                                 /* repeat for some time before giving up */
2005                                 continue;
2006                         else if (hsfsts.hsf_status.flcdone == 0)
2007                                 goto out;
2008                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2009         }
2010
2011 out:
2012         return ret_val;
2013 }
2014
2015 /**
2016  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2017  *  @hw: pointer to the HW structure
2018  *  @data: Pointer to the LED settings
2019  *
2020  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2021  *  settings is all 0's or F's, set the LED default to a valid LED default
2022  *  setting.
2023  **/
2024 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2025 {
2026         s32 ret_val;
2027
2028         DEBUGFUNC("e1000_valid_led_default_ich8lan");
2029
2030         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2031         if (ret_val) {
2032                 DEBUGOUT("NVM Read Error\n");
2033                 goto out;
2034         }
2035
2036         if (*data == ID_LED_RESERVED_0000 ||
2037             *data == ID_LED_RESERVED_FFFF)
2038                 *data = ID_LED_DEFAULT_ICH8LAN;
2039
2040 out:
2041         return ret_val;
2042 }
2043
2044 /**
2045  *  e1000_id_led_init_pchlan - store LED configurations
2046  *  @hw: pointer to the HW structure
2047  *
2048  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2049  *  the PHY LED configuration register.
2050  *
2051  *  PCH also does not have an "always on" or "always off" mode which
2052  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2053  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
2054  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2055  *  link based on logic in e1000_led_[on|off]_pchlan().
2056  **/
2057 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2058 {
2059         struct e1000_mac_info *mac = &hw->mac;
2060         s32 ret_val;
2061         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2062         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2063         u16 data, i, temp, shift;
2064
2065         DEBUGFUNC("e1000_id_led_init_pchlan");
2066
2067         /* Get default ID LED modes */
2068         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2069         if (ret_val)
2070                 goto out;
2071
2072         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
2073         mac->ledctl_mode1 = mac->ledctl_default;
2074         mac->ledctl_mode2 = mac->ledctl_default;
2075
2076         for (i = 0; i < 4; i++) {
2077                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2078                 shift = (i * 5);
2079                 switch (temp) {
2080                 case ID_LED_ON1_DEF2:
2081                 case ID_LED_ON1_ON2:
2082                 case ID_LED_ON1_OFF2:
2083                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2084                         mac->ledctl_mode1 |= (ledctl_on << shift);
2085                         break;
2086                 case ID_LED_OFF1_DEF2:
2087                 case ID_LED_OFF1_ON2:
2088                 case ID_LED_OFF1_OFF2:
2089                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2090                         mac->ledctl_mode1 |= (ledctl_off << shift);
2091                         break;
2092                 default:
2093                         /* Do nothing */
2094                         break;
2095                 }
2096                 switch (temp) {
2097                 case ID_LED_DEF1_ON2:
2098                 case ID_LED_ON1_ON2:
2099                 case ID_LED_OFF1_ON2:
2100                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2101                         mac->ledctl_mode2 |= (ledctl_on << shift);
2102                         break;
2103                 case ID_LED_DEF1_OFF2:
2104                 case ID_LED_ON1_OFF2:
2105                 case ID_LED_OFF1_OFF2:
2106                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2107                         mac->ledctl_mode2 |= (ledctl_off << shift);
2108                         break;
2109                 default:
2110                         /* Do nothing */
2111                         break;
2112                 }
2113         }
2114
2115 out:
2116         return ret_val;
2117 }
2118
2119 /**
2120  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2121  *  @hw: pointer to the HW structure
2122  *
2123  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2124  *  register, so the the bus width is hard coded.
2125  **/
2126 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2127 {
2128         struct e1000_bus_info *bus = &hw->bus;
2129         s32 ret_val;
2130
2131         DEBUGFUNC("e1000_get_bus_info_ich8lan");
2132
2133         ret_val = e1000_get_bus_info_pcie_generic(hw);
2134
2135         /*
2136          * ICH devices are "PCI Express"-ish.  They have
2137          * a configuration space, but do not contain
2138          * PCI Express Capability registers, so bus width
2139          * must be hardcoded.
2140          */
2141         if (bus->width == e1000_bus_width_unknown)
2142                 bus->width = e1000_bus_width_pcie_x1;
2143
2144         return ret_val;
2145 }
2146
2147 /**
2148  *  e1000_reset_hw_ich8lan - Reset the hardware
2149  *  @hw: pointer to the HW structure
2150  *
2151  *  Does a full reset of the hardware which includes a reset of the PHY and
2152  *  MAC.
2153  **/
2154 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2155 {
2156         u32 ctrl, icr, kab;
2157         s32 ret_val;
2158
2159         DEBUGFUNC("e1000_reset_hw_ich8lan");
2160
2161         /*
2162          * Prevent the PCI-E bus from sticking if there is no TLP connection
2163          * on the last TLP read/write transaction when MAC is reset.
2164          */
2165         ret_val = e1000_disable_pcie_master_generic(hw);
2166         if (ret_val)
2167                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2168
2169         DEBUGOUT("Masking off all interrupts\n");
2170         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2171
2172         /*
2173          * Disable the Transmit and Receive units.  Then delay to allow
2174          * any pending transactions to complete before we hit the MAC
2175          * with the global reset.
2176          */
2177         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2178         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2179         E1000_WRITE_FLUSH(hw);
2180
2181         msec_delay(10);
2182
2183         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2184         if (hw->mac.type == e1000_ich8lan) {
2185                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2186                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
2187                 /* Set Packet Buffer Size to 16k. */
2188                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
2189         }
2190
2191         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2192
2193         if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
2194                 /* Clear PHY Reset Asserted bit */
2195                 if (hw->mac.type >= e1000_pchlan) {
2196                         u32 status = E1000_READ_REG(hw, E1000_STATUS);
2197                         E1000_WRITE_REG(hw, E1000_STATUS, status &
2198                                         ~E1000_STATUS_PHYRA);
2199                 }
2200
2201                 /*
2202                  * PHY HW reset requires MAC CORE reset at the same
2203                  * time to make sure the interface between MAC and the
2204                  * external PHY is reset.
2205                  */
2206                 ctrl |= E1000_CTRL_PHY_RST;
2207         }
2208         ret_val = e1000_acquire_swflag_ich8lan(hw);
2209         DEBUGOUT("Issuing a global reset to ich8lan\n");
2210         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
2211         msec_delay(20);
2212
2213         if (!ret_val)
2214                 e1000_release_swflag_ich8lan(hw);
2215
2216         if (ctrl & E1000_CTRL_PHY_RST)
2217                 ret_val = hw->phy.ops.get_cfg_done(hw);
2218
2219         if (hw->mac.type >= e1000_ich10lan) {
2220                 e1000_lan_init_done_ich8lan(hw);
2221         } else {
2222                 ret_val = e1000_get_auto_rd_done_generic(hw);
2223                 if (ret_val) {
2224                         /*
2225                          * When auto config read does not complete, do not
2226                          * return with an error. This can happen in situations
2227                          * where there is no eeprom and prevents getting link.
2228                          */
2229                         DEBUGOUT("Auto Read Done did not complete\n");
2230                 }
2231         }
2232
2233         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2234         icr = E1000_READ_REG(hw, E1000_ICR);
2235
2236         kab = E1000_READ_REG(hw, E1000_KABGTXD);
2237         kab |= E1000_KABGTXD_BGSQLBIAS;
2238         E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
2239
2240         if (hw->mac.type == e1000_pchlan)
2241                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2242
2243         return ret_val;
2244 }
2245
2246 /**
2247  *  e1000_init_hw_ich8lan - Initialize the hardware
2248  *  @hw: pointer to the HW structure
2249  *
2250  *  Prepares the hardware for transmit and receive by doing the following:
2251  *   - initialize hardware bits
2252  *   - initialize LED identification
2253  *   - setup receive address registers
2254  *   - setup flow control
2255  *   - setup transmit descriptors
2256  *   - clear statistics
2257  **/
2258 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2259 {
2260         struct e1000_mac_info *mac = &hw->mac;
2261         u32 ctrl_ext, txdctl, snoop;
2262         s32 ret_val;
2263         u16 i;
2264
2265         DEBUGFUNC("e1000_init_hw_ich8lan");
2266
2267         e1000_initialize_hw_bits_ich8lan(hw);
2268
2269         /* Initialize identification LED */
2270         ret_val = mac->ops.id_led_init(hw);
2271         if (ret_val)
2272                 /* This is not fatal and we should not stop init due to this */
2273                 DEBUGOUT("Error initializing identification LED\n");
2274
2275         /* Setup the receive address. */
2276         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2277
2278         /* Zero out the Multicast HASH table */
2279         DEBUGOUT("Zeroing the MTA\n");
2280         for (i = 0; i < mac->mta_reg_count; i++)
2281                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2282
2283         /*
2284          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2285          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2286          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2287          */
2288         if (hw->phy.type == e1000_phy_82578) {
2289                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2290                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2291                 if (ret_val)
2292                         return ret_val;
2293         }
2294
2295         /* Setup link and flow control */
2296         ret_val = mac->ops.setup_link(hw);
2297
2298         /* Set the transmit descriptor write-back policy for both queues */
2299         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2300         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2301                  E1000_TXDCTL_FULL_TX_DESC_WB;
2302         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2303                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2304         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
2305         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
2306         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2307                  E1000_TXDCTL_FULL_TX_DESC_WB;
2308         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2309                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2310         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
2311
2312         /*
2313          * ICH8 has opposite polarity of no_snoop bits.
2314          * By default, we should use snoop behavior.
2315          */
2316         if (mac->type == e1000_ich8lan)
2317                 snoop = PCIE_ICH8_SNOOP_ALL;
2318         else
2319                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2320         e1000_set_pcie_no_snoop_generic(hw, snoop);
2321
2322         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2323         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2324         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2325
2326         /*
2327          * Clear all of the statistics registers (clear on read).  It is
2328          * important that we do this after we have tried to establish link
2329          * because the symbol error count will increment wildly if there
2330          * is no link.
2331          */
2332         e1000_clear_hw_cntrs_ich8lan(hw);
2333
2334         return ret_val;
2335 }
2336 /**
2337  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2338  *  @hw: pointer to the HW structure
2339  *
2340  *  Sets/Clears required hardware bits necessary for correctly setting up the
2341  *  hardware for transmit and receive.
2342  **/
2343 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2344 {
2345         u32 reg;
2346
2347         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
2348
2349         /* Extended Device Control */
2350         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2351         reg |= (1 << 22);
2352         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2353         if (hw->mac.type >= e1000_pchlan)
2354                 reg |= E1000_CTRL_EXT_PHYPDEN;
2355         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2356
2357         /* Transmit Descriptor Control 0 */
2358         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
2359         reg |= (1 << 22);
2360         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
2361
2362         /* Transmit Descriptor Control 1 */
2363         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2364         reg |= (1 << 22);
2365         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2366
2367         /* Transmit Arbitration Control 0 */
2368         reg = E1000_READ_REG(hw, E1000_TARC(0));
2369         if (hw->mac.type == e1000_ich8lan)
2370                 reg |= (1 << 28) | (1 << 29);
2371         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2372         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2373
2374         /* Transmit Arbitration Control 1 */
2375         reg = E1000_READ_REG(hw, E1000_TARC(1));
2376         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2377                 reg &= ~(1 << 28);
2378         else
2379                 reg |= (1 << 28);
2380         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2381         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2382
2383         /* Device Status */
2384         if (hw->mac.type == e1000_ich8lan) {
2385                 reg = E1000_READ_REG(hw, E1000_STATUS);
2386                 reg &= ~(1 << 31);
2387                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2388         }
2389
2390         return;
2391 }
2392
2393 /**
2394  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2395  *  @hw: pointer to the HW structure
2396  *
2397  *  Determines which flow control settings to use, then configures flow
2398  *  control.  Calls the appropriate media-specific link configuration
2399  *  function.  Assuming the adapter has a valid link partner, a valid link
2400  *  should be established.  Assumes the hardware has previously been reset
2401  *  and the transmitter and receiver are not enabled.
2402  **/
2403 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2404 {
2405         s32 ret_val = E1000_SUCCESS;
2406
2407         DEBUGFUNC("e1000_setup_link_ich8lan");
2408
2409         if (hw->phy.ops.check_reset_block(hw))
2410                 goto out;
2411
2412         /*
2413          * ICH parts do not have a word in the NVM to determine
2414          * the default flow control setting, so we explicitly
2415          * set it to full.
2416          */
2417         if (hw->fc.requested_mode == e1000_fc_default)
2418                 hw->fc.requested_mode = e1000_fc_full;
2419
2420         /*
2421          * Save off the requested flow control mode for use later.  Depending
2422          * on the link partner's capabilities, we may or may not use this mode.
2423          */
2424         hw->fc.current_mode = hw->fc.requested_mode;
2425
2426         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
2427                 hw->fc.current_mode);
2428
2429         /* Continue to configure the copper link. */
2430         ret_val = hw->mac.ops.setup_physical_interface(hw);
2431         if (ret_val)
2432                 goto out;
2433
2434         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2435         if ((hw->phy.type == e1000_phy_82578) ||
2436             (hw->phy.type == e1000_phy_82577)) {
2437                 ret_val = hw->phy.ops.write_reg(hw,
2438                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2439                                              hw->fc.pause_time);
2440                 if (ret_val)
2441                         goto out;
2442         }
2443
2444         ret_val = e1000_set_fc_watermarks_generic(hw);
2445
2446 out:
2447         return ret_val;
2448 }
2449
2450 /**
2451  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2452  *  @hw: pointer to the HW structure
2453  *
2454  *  Configures the kumeran interface to the PHY to wait the appropriate time
2455  *  when polling the PHY, then call the generic setup_copper_link to finish
2456  *  configuring the copper link.
2457  **/
2458 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2459 {
2460         u32 ctrl;
2461         s32 ret_val;
2462         u16 reg_data;
2463
2464         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2465
2466         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2467         ctrl |= E1000_CTRL_SLU;
2468         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2469         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2470
2471         /*
2472          * Set the mac to wait the maximum time between each iteration
2473          * and increase the max iterations when polling the phy;
2474          * this fixes erroneous timeouts at 10Mbps.
2475          */
2476         ret_val = e1000_write_kmrn_reg_generic(hw,
2477                                                E1000_KMRNCTRLSTA_TIMEOUTS,
2478                                                0xFFFF);
2479         if (ret_val)
2480                 goto out;
2481         ret_val = e1000_read_kmrn_reg_generic(hw,
2482                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
2483                                               &reg_data);
2484         if (ret_val)
2485                 goto out;
2486         reg_data |= 0x3F;
2487         ret_val = e1000_write_kmrn_reg_generic(hw,
2488                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
2489                                                reg_data);
2490         if (ret_val)
2491                 goto out;
2492
2493         switch (hw->phy.type) {
2494         case e1000_phy_igp_3:
2495                 ret_val = e1000_copper_link_setup_igp(hw);
2496                 if (ret_val)
2497                         goto out;
2498                 break;
2499         case e1000_phy_bm:
2500         case e1000_phy_82578:
2501                 ret_val = e1000_copper_link_setup_m88(hw);
2502                 if (ret_val)
2503                         goto out;
2504                 break;
2505         case e1000_phy_82577:
2506                 ret_val = e1000_copper_link_setup_82577(hw);
2507                 if (ret_val)
2508                         goto out;
2509                 break;
2510         case e1000_phy_ife:
2511                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2512                                                &reg_data);
2513                 if (ret_val)
2514                         goto out;
2515
2516                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2517
2518                 switch (hw->phy.mdix) {
2519                 case 1:
2520                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2521                         break;
2522                 case 2:
2523                         reg_data |= IFE_PMC_FORCE_MDIX;
2524                         break;
2525                 case 0:
2526                 default:
2527                         reg_data |= IFE_PMC_AUTO_MDIX;
2528                         break;
2529                 }
2530                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2531                                                 reg_data);
2532                 if (ret_val)
2533                         goto out;
2534                 break;
2535         default:
2536                 break;
2537         }
2538         ret_val = e1000_setup_copper_link_generic(hw);
2539
2540 out:
2541         return ret_val;
2542 }
2543
2544 /**
2545  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2546  *  @hw: pointer to the HW structure
2547  *  @speed: pointer to store current link speed
2548  *  @duplex: pointer to store the current link duplex
2549  *
2550  *  Calls the generic get_speed_and_duplex to retrieve the current link
2551  *  information and then calls the Kumeran lock loss workaround for links at
2552  *  gigabit speeds.
2553  **/
2554 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2555                                           u16 *duplex)
2556 {
2557         s32 ret_val;
2558
2559         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2560
2561         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2562         if (ret_val)
2563                 goto out;
2564
2565         if ((hw->mac.type == e1000_ich8lan) &&
2566             (hw->phy.type == e1000_phy_igp_3) &&
2567             (*speed == SPEED_1000)) {
2568                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2569         }
2570
2571 out:
2572         return ret_val;
2573 }
2574
2575 /**
2576  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2577  *  @hw: pointer to the HW structure
2578  *
2579  *  Work-around for 82566 Kumeran PCS lock loss:
2580  *  On link status change (i.e. PCI reset, speed change) and link is up and
2581  *  speed is gigabit-
2582  *    0) if workaround is optionally disabled do nothing
2583  *    1) wait 1ms for Kumeran link to come up
2584  *    2) check Kumeran Diagnostic register PCS lock loss bit
2585  *    3) if not set the link is locked (all is good), otherwise...
2586  *    4) reset the PHY
2587  *    5) repeat up to 10 times
2588  *  Note: this is only called for IGP3 copper when speed is 1gb.
2589  **/
2590 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2591 {
2592         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2593         u32 phy_ctrl;
2594         s32 ret_val = E1000_SUCCESS;
2595         u16 i, data;
2596         bool link;
2597
2598         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
2599
2600         if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
2601                 goto out;
2602
2603         /*
2604          * Make sure link is up before proceeding.  If not just return.
2605          * Attempting this while link is negotiating fouled up link
2606          * stability
2607          */
2608         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2609         if (!link) {
2610                 ret_val = E1000_SUCCESS;
2611                 goto out;
2612         }
2613
2614         for (i = 0; i < 10; i++) {
2615                 /* read once to clear */
2616                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2617                 if (ret_val)
2618                         goto out;
2619                 /* and again to get new status */
2620                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2621                 if (ret_val)
2622                         goto out;
2623
2624                 /* check for PCS lock */
2625                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2626                         ret_val = E1000_SUCCESS;
2627                         goto out;
2628                 }
2629
2630                 /* Issue PHY reset */
2631                 hw->phy.ops.reset(hw);
2632                 msec_delay_irq(5);
2633         }
2634         /* Disable GigE link negotiation */
2635         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2636         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2637                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2638         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2639
2640         /*
2641          * Call gig speed drop workaround on Gig disable before accessing
2642          * any PHY registers
2643          */
2644         e1000_gig_downshift_workaround_ich8lan(hw);
2645
2646         /* unable to acquire PCS lock */
2647         ret_val = -E1000_ERR_PHY;
2648
2649 out:
2650         return ret_val;
2651 }
2652
2653 /**
2654  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2655  *  @hw: pointer to the HW structure
2656  *  @state: boolean value used to set the current Kumeran workaround state
2657  *
2658  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2659  *  /disabled - FALSE).
2660  **/
2661 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2662                                                  bool state)
2663 {
2664         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2665
2666         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
2667
2668         if (hw->mac.type != e1000_ich8lan) {
2669                 DEBUGOUT("Workaround applies to ICH8 only.\n");
2670                 return;
2671         }
2672
2673         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2674
2675         return;
2676 }
2677
2678 /**
2679  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2680  *  @hw: pointer to the HW structure
2681  *
2682  *  Workaround for 82566 power-down on D3 entry:
2683  *    1) disable gigabit link
2684  *    2) write VR power-down enable
2685  *    3) read it back
2686  *  Continue if successful, else issue LCD reset and repeat
2687  **/
2688 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2689 {
2690         u32 reg;
2691         u16 data;
2692         u8  retry = 0;
2693
2694         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
2695
2696         if (hw->phy.type != e1000_phy_igp_3)
2697                 goto out;
2698
2699         /* Try the workaround twice (if needed) */
2700         do {
2701                 /* Disable link */
2702                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2703                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2704                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2705                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
2706
2707                 /*
2708                  * Call gig speed drop workaround on Gig disable before
2709                  * accessing any PHY registers
2710                  */
2711                 if (hw->mac.type == e1000_ich8lan)
2712                         e1000_gig_downshift_workaround_ich8lan(hw);
2713
2714                 /* Write VR power-down enable */
2715                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2716                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2717                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
2718                                    data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2719
2720                 /* Read it back and test */
2721                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2722                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2723                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2724                         break;
2725
2726                 /* Issue PHY reset and repeat at most one more time */
2727                 reg = E1000_READ_REG(hw, E1000_CTRL);
2728                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2729                 retry++;
2730         } while (retry);
2731
2732 out:
2733         return;
2734 }
2735
2736 /**
2737  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2738  *  @hw: pointer to the HW structure
2739  *
2740  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2741  *  LPLU, Gig disable, MDIC PHY reset):
2742  *    1) Set Kumeran Near-end loopback
2743  *    2) Clear Kumeran Near-end loopback
2744  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2745  **/
2746 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2747 {
2748         s32 ret_val = E1000_SUCCESS;
2749         u16 reg_data;
2750
2751         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
2752
2753         if ((hw->mac.type != e1000_ich8lan) ||
2754             (hw->phy.type != e1000_phy_igp_3))
2755                 goto out;
2756
2757         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2758                                               &reg_data);
2759         if (ret_val)
2760                 goto out;
2761         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2762         ret_val = e1000_write_kmrn_reg_generic(hw,
2763                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
2764                                                reg_data);
2765         if (ret_val)
2766                 goto out;
2767         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2768         ret_val = e1000_write_kmrn_reg_generic(hw,
2769                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
2770                                                reg_data);
2771 out:
2772         return;
2773 }
2774
2775 /**
2776  *  e1000_disable_gig_wol_ich8lan - disable gig during WoL
2777  *  @hw: pointer to the HW structure
2778  *
2779  *  During S0 to Sx transition, it is possible the link remains at gig
2780  *  instead of negotiating to a lower speed.  Before going to Sx, set
2781  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2782  *  to a lower speed.
2783  *
2784  *  Should only be called for applicable parts.
2785  **/
2786 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2787 {
2788         u32 phy_ctrl;
2789
2790         switch (hw->mac.type) {
2791         case e1000_ich9lan:
2792         case e1000_ich10lan:
2793         case e1000_pchlan:
2794                 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2795                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2796                             E1000_PHY_CTRL_GBE_DISABLE;
2797                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2798
2799                 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2800                 if (hw->mac.type == e1000_pchlan)
2801                         usec_delay(500);
2802         default:
2803                 break;
2804         }
2805
2806         return;
2807 }
2808
2809 /**
2810  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2811  *  @hw: pointer to the HW structure
2812  *
2813  *  Return the LED back to the default configuration.
2814  **/
2815 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2816 {
2817         s32 ret_val = E1000_SUCCESS;
2818
2819         DEBUGFUNC("e1000_cleanup_led_ich8lan");
2820
2821         if (hw->phy.type == e1000_phy_ife)
2822                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2823                                               0);
2824         else
2825                 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2826
2827         return ret_val;
2828 }
2829
2830 /**
2831  *  e1000_led_on_ich8lan - Turn LEDs on
2832  *  @hw: pointer to the HW structure
2833  *
2834  *  Turn on the LEDs.
2835  **/
2836 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2837 {
2838         s32 ret_val = E1000_SUCCESS;
2839
2840         DEBUGFUNC("e1000_led_on_ich8lan");
2841
2842         if (hw->phy.type == e1000_phy_ife)
2843                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2844                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2845         else
2846                 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2847
2848         return ret_val;
2849 }
2850
2851 /**
2852  *  e1000_led_off_ich8lan - Turn LEDs off
2853  *  @hw: pointer to the HW structure
2854  *
2855  *  Turn off the LEDs.
2856  **/
2857 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2858 {
2859         s32 ret_val = E1000_SUCCESS;
2860
2861         DEBUGFUNC("e1000_led_off_ich8lan");
2862
2863         if (hw->phy.type == e1000_phy_ife)
2864                 ret_val = hw->phy.ops.write_reg(hw,
2865                                IFE_PHY_SPECIAL_CONTROL_LED,
2866                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2867         else
2868                 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2869
2870         return ret_val;
2871 }
2872
2873 /**
2874  *  e1000_setup_led_pchlan - Configures SW controllable LED
2875  *  @hw: pointer to the HW structure
2876  *
2877  *  This prepares the SW controllable LED for use.
2878  **/
2879 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2880 {
2881         DEBUGFUNC("e1000_setup_led_pchlan");
2882
2883         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
2884                                         (u16)hw->mac.ledctl_mode1);
2885 }
2886
2887 /**
2888  *  e1000_cleanup_led_pchlan - Restore the default LED operation
2889  *  @hw: pointer to the HW structure
2890  *
2891  *  Return the LED back to the default configuration.
2892  **/
2893 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2894 {
2895         DEBUGFUNC("e1000_cleanup_led_pchlan");
2896
2897         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
2898                                         (u16)hw->mac.ledctl_default);
2899 }
2900
2901 /**
2902  *  e1000_led_on_pchlan - Turn LEDs on
2903  *  @hw: pointer to the HW structure
2904  *
2905  *  Turn on the LEDs.
2906  **/
2907 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2908 {
2909         u16 data = (u16)hw->mac.ledctl_mode2;
2910         u32 i, led;
2911
2912         DEBUGFUNC("e1000_led_on_pchlan");
2913
2914         /*
2915          * If no link, then turn LED on by setting the invert bit
2916          * for each LED that's mode is "link_up" in ledctl_mode2.
2917          */
2918         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2919                 for (i = 0; i < 3; i++) {
2920                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2921                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2922                             E1000_LEDCTL_MODE_LINK_UP)
2923                                 continue;
2924                         if (led & E1000_PHY_LED0_IVRT)
2925                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2926                         else
2927                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2928                 }
2929         }
2930
2931         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
2932 }
2933
2934 /**
2935  *  e1000_led_off_pchlan - Turn LEDs off
2936  *  @hw: pointer to the HW structure
2937  *
2938  *  Turn off the LEDs.
2939  **/
2940 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2941 {
2942         u16 data = (u16)hw->mac.ledctl_mode1;
2943         u32 i, led;
2944
2945         DEBUGFUNC("e1000_led_off_pchlan");
2946
2947         /*
2948          * If no link, then turn LED off by clearing the invert bit
2949          * for each LED that's mode is "link_up" in ledctl_mode1.
2950          */
2951         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2952                 for (i = 0; i < 3; i++) {
2953                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2954                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2955                             E1000_LEDCTL_MODE_LINK_UP)
2956                                 continue;
2957                         if (led & E1000_PHY_LED0_IVRT)
2958                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2959                         else
2960                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2961                 }
2962         }
2963
2964         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
2965 }
2966
2967 /**
2968  *  e1000_get_cfg_done_ich8lan - Read config done bit
2969  *  @hw: pointer to the HW structure
2970  *
2971  *  Read the management control register for the config done bit for
2972  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2973  *  to read the config done bit, so an error is *ONLY* logged and returns
2974  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2975  *  would not be able to be reset or change link.
2976  **/
2977 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2978 {
2979         s32 ret_val = E1000_SUCCESS;
2980         u32 bank = 0;
2981
2982         if (hw->mac.type >= e1000_pchlan) {
2983                 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2984
2985                 if (status & E1000_STATUS_PHYRA) {
2986                         E1000_WRITE_REG(hw, E1000_STATUS, status &
2987                                         ~E1000_STATUS_PHYRA);
2988                 } else
2989                         DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
2990         }
2991
2992         e1000_get_cfg_done_generic(hw);
2993
2994         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2995         if ((hw->mac.type != e1000_ich10lan) &&
2996             (hw->mac.type != e1000_pchlan)) {
2997                 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2998                     (hw->phy.type == e1000_phy_igp_3)) {
2999                         e1000_phy_init_script_igp3(hw);
3000                 }
3001         } else {
3002                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3003                         /* Maybe we should do a basic PHY config */
3004                         DEBUGOUT("EEPROM not present\n");
3005                         ret_val = -E1000_ERR_CONFIG;
3006                 }
3007         }
3008
3009         return ret_val;
3010 }
3011
3012 /**
3013  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3014  * @hw: pointer to the HW structure
3015  *
3016  * In the case of a PHY power down to save power, or to turn off link during a
3017  * driver unload, or wake on lan is not enabled, remove the link.
3018  **/
3019 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3020 {
3021         /* If the management interface is not enabled, then power down */
3022         if (!(hw->mac.ops.check_mng_mode(hw) ||
3023               hw->phy.ops.check_reset_block(hw)))
3024                 e1000_power_down_phy_copper(hw);
3025
3026         return;
3027 }
3028
3029 /**
3030  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3031  *  @hw: pointer to the HW structure
3032  *
3033  *  Clears hardware counters specific to the silicon family and calls
3034  *  clear_hw_cntrs_generic to clear all general purpose counters.
3035  **/
3036 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3037 {
3038         u16 phy_data;
3039
3040         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
3041
3042         e1000_clear_hw_cntrs_base_generic(hw);
3043
3044         E1000_READ_REG(hw, E1000_ALGNERRC);
3045         E1000_READ_REG(hw, E1000_RXERRC);
3046         E1000_READ_REG(hw, E1000_TNCRS);
3047         E1000_READ_REG(hw, E1000_CEXTERR);
3048         E1000_READ_REG(hw, E1000_TSCTC);
3049         E1000_READ_REG(hw, E1000_TSCTFC);
3050
3051         E1000_READ_REG(hw, E1000_MGTPRC);
3052         E1000_READ_REG(hw, E1000_MGTPDC);
3053         E1000_READ_REG(hw, E1000_MGTPTC);
3054
3055         E1000_READ_REG(hw, E1000_IAC);
3056         E1000_READ_REG(hw, E1000_ICRXOC);
3057
3058         /* Clear PHY statistics registers */
3059         if ((hw->phy.type == e1000_phy_82578) ||
3060             (hw->phy.type == e1000_phy_82577)) {
3061                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3062                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3063                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3064                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3065                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3066                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3067                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3068                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3069                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3070                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3071                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3072                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3073                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3074                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3075         }
3076 }
3077