2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
72 #include <machine/resource.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <dev/fxp/if_fxpreg.h>
81 #include <dev/fxp/if_fxpvar.h>
82 #include <dev/fxp/rcvbundl.h>
84 MODULE_DEPEND(fxp, pci, 1, 1, 1);
85 MODULE_DEPEND(fxp, ether, 1, 1, 1);
86 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
87 #include "miibus_if.h"
90 * NOTE! On the Alpha, we have an alignment constraint. The
91 * card DMAs the packet immediately following the RFA. However,
92 * the first thing in the packet is a 14-byte Ethernet header.
93 * This means that the packet is misaligned. To compensate,
94 * we actually offset the RFA 2 bytes into the cluster. This
95 * alignes the packet after the Ethernet header at a 32-bit
96 * boundary. HOWEVER! This means that the RFA is misaligned!
98 #define RFA_ALIGNMENT_FUDGE 2
101 * Set initial transmit threshold at 64 (512 bytes). This is
102 * increased by 64 (512 bytes) at a time, to maximum of 192
103 * (1536 bytes), if an underrun occurs.
105 static int tx_threshold = 64;
108 * The configuration byte map has several undefined fields which
109 * must be one or must be zero. Set up a template for these bits
110 * only, (assuming a 82557 chip) leaving the actual configuration
113 * See struct fxp_cb_config for the bit definitions.
115 static u_char fxp_cb_config_template[] = {
116 0x0, 0x0, /* cb_status */
117 0x0, 0x0, /* cb_command */
118 0x0, 0x0, 0x0, 0x0, /* link_addr */
144 * Claim various Intel PCI device identifiers for this driver. The
145 * sub-vendor and sub-device field are extensively used to identify
146 * particular variants, but we don't currently differentiate between
149 static struct fxp_ident fxp_ident_table[] = {
150 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
151 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
152 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
153 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
154 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
156 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
157 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
158 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
160 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
161 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
162 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
163 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
164 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
165 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
166 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
167 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
168 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
169 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
170 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
171 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
172 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
173 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
174 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
175 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
176 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
177 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
178 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
179 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
180 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
181 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
182 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
183 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
184 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
185 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
186 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
187 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
188 { 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" },
189 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
190 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
191 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
192 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
193 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
194 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
198 #ifdef FXP_IP_CSUM_WAR
199 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
201 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
204 static int fxp_probe(device_t dev);
205 static int fxp_attach(device_t dev);
206 static int fxp_detach(device_t dev);
207 static int fxp_shutdown(device_t dev);
208 static int fxp_suspend(device_t dev);
209 static int fxp_resume(device_t dev);
211 static struct fxp_ident *fxp_find_ident(device_t dev);
212 static void fxp_intr(void *xsc);
213 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
214 struct mbuf *m, uint16_t status, int pos);
215 static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
216 uint8_t statack, int count);
217 static void fxp_init(void *xsc);
218 static void fxp_init_body(struct fxp_softc *sc);
219 static void fxp_tick(void *xsc);
220 static void fxp_start(struct ifnet *ifp);
221 static void fxp_start_body(struct ifnet *ifp);
222 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
223 static void fxp_txeof(struct fxp_softc *sc);
224 static void fxp_stop(struct fxp_softc *sc);
225 static void fxp_release(struct fxp_softc *sc);
226 static int fxp_ioctl(struct ifnet *ifp, u_long command,
228 static void fxp_watchdog(struct fxp_softc *sc);
229 static void fxp_add_rfabuf(struct fxp_softc *sc,
231 static void fxp_discard_rfabuf(struct fxp_softc *sc,
233 static int fxp_new_rfabuf(struct fxp_softc *sc,
235 static int fxp_mc_addrs(struct fxp_softc *sc);
236 static void fxp_mc_setup(struct fxp_softc *sc);
237 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
239 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
241 static void fxp_autosize_eeprom(struct fxp_softc *sc);
242 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
243 int offset, int words);
244 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
245 int offset, int words);
246 static int fxp_ifmedia_upd(struct ifnet *ifp);
247 static void fxp_ifmedia_sts(struct ifnet *ifp,
248 struct ifmediareq *ifmr);
249 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
250 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
251 struct ifmediareq *ifmr);
252 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
253 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
255 static void fxp_load_ucode(struct fxp_softc *sc);
256 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
258 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
259 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
260 static void fxp_scb_wait(struct fxp_softc *sc);
261 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
262 static void fxp_dma_wait(struct fxp_softc *sc,
263 volatile uint16_t *status, bus_dma_tag_t dmat,
266 static device_method_t fxp_methods[] = {
267 /* Device interface */
268 DEVMETHOD(device_probe, fxp_probe),
269 DEVMETHOD(device_attach, fxp_attach),
270 DEVMETHOD(device_detach, fxp_detach),
271 DEVMETHOD(device_shutdown, fxp_shutdown),
272 DEVMETHOD(device_suspend, fxp_suspend),
273 DEVMETHOD(device_resume, fxp_resume),
276 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
277 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
282 static driver_t fxp_driver = {
285 sizeof(struct fxp_softc),
288 static devclass_t fxp_devclass;
290 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
291 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
293 static struct resource_spec fxp_res_spec_mem[] = {
294 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
295 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
299 static struct resource_spec fxp_res_spec_io[] = {
300 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
301 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
306 * Wait for the previous command to be accepted (but not necessarily
310 fxp_scb_wait(struct fxp_softc *sc)
318 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
321 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL);
322 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1);
323 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
324 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
325 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
326 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
331 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
334 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
335 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
338 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
342 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
343 bus_dma_tag_t dmat, bus_dmamap_t map)
347 for (i = 10000; i > 0; i--) {
349 bus_dmamap_sync(dmat, map,
350 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
351 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
355 device_printf(sc->dev, "DMA timeout\n");
358 static struct fxp_ident *
359 fxp_find_ident(device_t dev)
363 struct fxp_ident *ident;
365 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
366 devid = pci_get_device(dev);
367 revid = pci_get_revid(dev);
368 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
369 if (ident->devid == devid &&
370 (ident->revid == revid || ident->revid == -1)) {
379 * Return identification string if this device is ours.
382 fxp_probe(device_t dev)
384 struct fxp_ident *ident;
386 ident = fxp_find_ident(dev);
388 device_set_desc(dev, ident->name);
389 return (BUS_PROBE_DEFAULT);
395 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
402 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
404 *addr = segs->ds_addr;
408 fxp_attach(device_t dev)
410 struct fxp_softc *sc;
411 struct fxp_cb_tx *tcbp;
416 uint16_t data, myea[ETHER_ADDR_LEN / 2];
417 u_char eaddr[ETHER_ADDR_LEN];
418 int i, pmc, prefer_iomap;
422 sc = device_get_softc(dev);
424 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
426 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
427 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
428 fxp_serial_ifmedia_sts);
430 ifp = sc->ifp = if_alloc(IFT_ETHER);
432 device_printf(dev, "can not if_alloc()\n");
438 * Enable bus mastering.
440 pci_enable_busmaster(dev);
441 val = pci_read_config(dev, PCIR_COMMAND, 2);
444 * Figure out which we should try first - memory mapping or i/o mapping?
445 * We default to memory mapping. Then we accept an override from the
446 * command line. Then we check to see which one is enabled.
449 resource_int_value(device_get_name(dev), device_get_unit(dev),
450 "prefer_iomap", &prefer_iomap);
452 sc->fxp_spec = fxp_res_spec_io;
454 sc->fxp_spec = fxp_res_spec_mem;
456 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
458 if (sc->fxp_spec == fxp_res_spec_mem)
459 sc->fxp_spec = fxp_res_spec_io;
461 sc->fxp_spec = fxp_res_spec_mem;
462 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
465 device_printf(dev, "could not allocate resources\n");
471 device_printf(dev, "using %s space register mapping\n",
472 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
476 * Put CU/RU idle state and prepare full reset.
478 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
480 /* Full reset and disable interrupts. */
481 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
483 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
486 * Find out how large of an SEEPROM we have.
488 fxp_autosize_eeprom(sc);
491 * Find out the chip revision; lump all 82557 revs together.
493 sc->ident = fxp_find_ident(dev);
494 if (sc->ident->ich > 0) {
495 /* Assume ICH controllers are 82559. */
496 sc->revision = FXP_REV_82559_A0;
498 fxp_read_eeprom(sc, &data, 5, 1);
499 if ((data >> 8) == 1)
500 sc->revision = FXP_REV_82557;
502 sc->revision = pci_get_revid(dev);
506 * Check availability of WOL. 82559ER does not support WOL.
508 if (sc->revision >= FXP_REV_82558_A4 &&
509 sc->revision != FXP_REV_82559S_A) {
510 fxp_read_eeprom(sc, &data, 10, 1);
511 if ((data & 0x20) != 0 &&
512 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
513 sc->flags |= FXP_FLAG_WOLCAP;
516 /* Receiver lock-up workaround detection. */
517 fxp_read_eeprom(sc, &data, 3, 1);
518 if ((data & 0x03) != 0x03) {
519 sc->flags |= FXP_FLAG_RXBUG;
520 device_printf(dev, "Enabling Rx lock-up workaround\n");
524 * Determine whether we must use the 503 serial interface.
526 fxp_read_eeprom(sc, &data, 6, 1);
527 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
528 && (data & FXP_PHY_SERIAL_ONLY))
529 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
531 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
533 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
534 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
535 "FXP driver receive interrupt microcode bundling delay");
536 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
538 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
539 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
540 "FXP driver receive interrupt microcode bundle size limit");
541 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
542 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
543 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
545 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
546 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
547 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0,
548 "FXP flow control disabled");
551 * Pull in device tunables.
553 sc->tunable_int_delay = TUNABLE_INT_DELAY;
554 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
555 sc->tunable_noflow = 1;
556 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
557 "int_delay", &sc->tunable_int_delay);
558 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
559 "bundle_max", &sc->tunable_bundle_max);
560 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
561 "noflow", &sc->tunable_noflow);
565 * Enable workarounds for certain chip revision deficiencies.
567 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
568 * some systems based a normal 82559 design, have a defect where
569 * the chip can cause a PCI protocol violation if it receives
570 * a CU_RESUME command when it is entering the IDLE state. The
571 * workaround is to disable Dynamic Standby Mode, so the chip never
572 * deasserts CLKRUN#, and always remains in an active state.
574 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
576 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
577 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
578 fxp_read_eeprom(sc, &data, 10, 1);
579 if (data & 0x02) { /* STB enable */
584 "Disabling dynamic standby mode in EEPROM\n");
586 fxp_write_eeprom(sc, &data, 10, 1);
587 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
589 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
590 fxp_read_eeprom(sc, &data, i, 1);
593 i = (1 << sc->eeprom_size) - 1;
594 cksum = 0xBABA - cksum;
595 fxp_read_eeprom(sc, &data, i, 1);
596 fxp_write_eeprom(sc, &cksum, i, 1);
598 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
602 * If the user elects to continue, try the software
603 * workaround, as it is better than nothing.
605 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
611 * If we are not a 82557 chip, we can enable extended features.
613 if (sc->revision != FXP_REV_82557) {
615 * If MWI is enabled in the PCI configuration, and there
616 * is a valid cacheline size (8 or 16 dwords), then tell
617 * the board to turn on MWI.
619 if (val & PCIM_CMD_MWRICEN &&
620 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
621 sc->flags |= FXP_FLAG_MWI_ENABLE;
623 /* turn on the extended TxCB feature */
624 sc->flags |= FXP_FLAG_EXT_TXCB;
626 /* enable reception of long frames for VLAN */
627 sc->flags |= FXP_FLAG_LONG_PKT_EN;
629 /* a hack to get long VLAN frames on a 82557 */
630 sc->flags |= FXP_FLAG_SAVE_BAD;
633 /* For 82559 or later chips, Rx checksum offload is supported. */
634 if (sc->revision >= FXP_REV_82559_A0)
635 sc->flags |= FXP_FLAG_82559_RXCSUM;
637 * Enable use of extended RFDs and TCBs for 82550
638 * and later chips. Note: we need extended TXCB support
639 * too, but that's already enabled by the code above.
640 * Be careful to do this only on the right devices.
642 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
643 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
644 || sc->revision == FXP_REV_82551_10) {
645 sc->rfa_size = sizeof (struct fxp_rfa);
646 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
647 sc->flags |= FXP_FLAG_EXT_RFA;
648 /* Use extended RFA instead of 82559 checksum mode. */
649 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
651 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
652 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
656 * Allocate DMA tags and DMA safe memory.
658 sc->maxtxseg = FXP_NTXSEG;
659 sc->maxsegsize = MCLBYTES;
660 if (sc->flags & FXP_FLAG_EXT_RFA) {
662 sc->maxsegsize = FXP_TSO_SEGSIZE;
664 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
665 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
666 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
667 sc->maxtxseg, sc->maxsegsize, 0,
668 busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
670 device_printf(dev, "could not create TX DMA tag\n");
674 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
675 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
676 MCLBYTES, 1, MCLBYTES, 0,
677 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
679 device_printf(dev, "could not create RX DMA tag\n");
683 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
684 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
685 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
686 busdma_lock_mutex, &Giant, &sc->fxp_stag);
688 device_printf(dev, "could not create stats DMA tag\n");
692 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
693 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
695 device_printf(dev, "could not allocate stats DMA memory\n");
698 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
699 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
701 device_printf(dev, "could not load the stats DMA buffer\n");
705 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
706 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
707 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
708 busdma_lock_mutex, &Giant, &sc->cbl_tag);
710 device_printf(dev, "could not create TxCB DMA tag\n");
714 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
715 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
717 device_printf(dev, "could not allocate TxCB DMA memory\n");
721 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
722 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
723 &sc->fxp_desc.cbl_addr, 0);
725 device_printf(dev, "could not load TxCB DMA buffer\n");
729 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
730 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
731 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
732 busdma_lock_mutex, &Giant, &sc->mcs_tag);
735 "could not create multicast setup DMA tag\n");
739 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
740 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->mcs_map);
743 "could not allocate multicast setup DMA memory\n");
746 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
747 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
750 "can't load the multicast setup DMA buffer\n");
755 * Pre-allocate the TX DMA maps and setup the pointers to
756 * the TX command blocks.
758 txp = sc->fxp_desc.tx_list;
759 tcbp = sc->fxp_desc.cbl_list;
760 for (i = 0; i < FXP_NTXCB; i++) {
761 txp[i].tx_cb = tcbp + i;
762 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
764 device_printf(dev, "can't create DMA map for TX\n");
768 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
770 device_printf(dev, "can't create spare DMA map\n");
775 * Pre-allocate our receive buffers.
777 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
778 for (i = 0; i < FXP_NRFABUFS; i++) {
779 rxp = &sc->fxp_desc.rx_list[i];
780 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
782 device_printf(dev, "can't create DMA map for RX\n");
785 if (fxp_new_rfabuf(sc, rxp) != 0) {
789 fxp_add_rfabuf(sc, rxp);
795 fxp_read_eeprom(sc, myea, 0, 3);
796 eaddr[0] = myea[0] & 0xff;
797 eaddr[1] = myea[0] >> 8;
798 eaddr[2] = myea[1] & 0xff;
799 eaddr[3] = myea[1] >> 8;
800 eaddr[4] = myea[2] & 0xff;
801 eaddr[5] = myea[2] >> 8;
803 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
804 pci_get_vendor(dev), pci_get_device(dev),
805 pci_get_subvendor(dev), pci_get_subdevice(dev),
807 fxp_read_eeprom(sc, &data, 10, 1);
808 device_printf(dev, "Dynamic Standby mode is %s\n",
809 data & 0x02 ? "enabled" : "disabled");
813 * If this is only a 10Mbps device, then there is no MII, and
814 * the PHY will use a serial interface instead.
816 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
817 * doesn't have a programming interface of any sort. The
818 * media is sensed automatically based on how the link partner
819 * is configured. This is, in essence, manual configuration.
821 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
822 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
823 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
825 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
827 device_printf(dev, "MII without any PHY!\n");
833 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
834 ifp->if_init = fxp_init;
836 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
837 ifp->if_ioctl = fxp_ioctl;
838 ifp->if_start = fxp_start;
840 ifp->if_capabilities = ifp->if_capenable = 0;
842 /* Enable checksum offload/TSO for 82550 or better chips */
843 if (sc->flags & FXP_FLAG_EXT_RFA) {
844 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
845 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
846 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
849 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
850 ifp->if_capabilities |= IFCAP_RXCSUM;
851 ifp->if_capenable |= IFCAP_RXCSUM;
854 if (sc->flags & FXP_FLAG_WOLCAP) {
855 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
856 ifp->if_capenable |= IFCAP_WOL_MAGIC;
859 #ifdef DEVICE_POLLING
860 /* Inform the world we support polling. */
861 ifp->if_capabilities |= IFCAP_POLLING;
865 * Attach the interface.
867 ether_ifattach(ifp, eaddr);
870 * Tell the upper layer(s) we support long frames.
871 * Must appear after the call to ether_ifattach() because
872 * ether_ifattach() sets ifi_hdrlen to the default value.
874 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
875 ifp->if_capabilities |= IFCAP_VLAN_MTU;
876 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
877 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
878 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
880 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
885 * Let the system queue as many packets as we have available
888 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
889 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
890 IFQ_SET_READY(&ifp->if_snd);
893 * Hook our interrupt after all initialization is complete.
895 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
896 NULL, fxp_intr, sc, &sc->ih);
898 device_printf(dev, "could not setup irq\n");
899 ether_ifdetach(sc->ifp);
904 * Configure hardware to reject magic frames otherwise
905 * system will hang on recipt of magic frames.
907 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
909 /* Clear wakeup events. */
910 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
923 * Release all resources. The softc lock should not be held and the
924 * interrupt should already be torn down.
927 fxp_release(struct fxp_softc *sc)
933 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
934 KASSERT(sc->ih == NULL,
935 ("fxp_release() called with intr handle still active"));
937 device_delete_child(sc->dev, sc->miibus);
938 bus_generic_detach(sc->dev);
939 ifmedia_removeall(&sc->sc_media);
940 if (sc->fxp_desc.cbl_list) {
941 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
942 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
946 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
947 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
950 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
951 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
953 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
954 if (sc->fxp_rxmtag) {
955 for (i = 0; i < FXP_NRFABUFS; i++) {
956 rxp = &sc->fxp_desc.rx_list[i];
957 if (rxp->rx_mbuf != NULL) {
958 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
959 BUS_DMASYNC_POSTREAD);
960 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
961 m_freem(rxp->rx_mbuf);
963 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
965 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
966 bus_dma_tag_destroy(sc->fxp_rxmtag);
968 if (sc->fxp_txmtag) {
969 for (i = 0; i < FXP_NTXCB; i++) {
970 txp = &sc->fxp_desc.tx_list[i];
971 if (txp->tx_mbuf != NULL) {
972 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
973 BUS_DMASYNC_POSTWRITE);
974 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
975 m_freem(txp->tx_mbuf);
977 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
979 bus_dma_tag_destroy(sc->fxp_txmtag);
982 bus_dma_tag_destroy(sc->fxp_stag);
984 bus_dma_tag_destroy(sc->cbl_tag);
986 bus_dma_tag_destroy(sc->mcs_tag);
990 mtx_destroy(&sc->sc_mtx);
997 fxp_detach(device_t dev)
999 struct fxp_softc *sc = device_get_softc(dev);
1001 #ifdef DEVICE_POLLING
1002 if (sc->ifp->if_capenable & IFCAP_POLLING)
1003 ether_poll_deregister(sc->ifp);
1008 * Stop DMA and drop transmit queue, but disable interrupts first.
1010 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1013 callout_drain(&sc->stat_ch);
1016 * Close down routes etc.
1018 ether_ifdetach(sc->ifp);
1021 * Unhook interrupt before dropping lock. This is to prevent
1022 * races with fxp_intr().
1024 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1027 /* Release our allocated resources. */
1033 * Device shutdown routine. Called at system shutdown after sync. The
1034 * main purpose of this routine is to shut off receiver DMA so that
1035 * kernel memory doesn't get clobbered during warmboot.
1038 fxp_shutdown(device_t dev)
1042 * Make sure that DMA is disabled prior to reboot. Not doing
1043 * do could allow DMA to corrupt kernel memory during the
1044 * reboot before the driver initializes.
1046 return (fxp_suspend(dev));
1050 * Device suspend routine. Stop the interface and save some PCI
1051 * settings in case the BIOS doesn't restore them properly on
1055 fxp_suspend(device_t dev)
1057 struct fxp_softc *sc = device_get_softc(dev);
1065 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1066 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1067 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1068 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1070 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1071 sc->flags |= FXP_FLAG_WOL;
1072 /* Reconfigure hardware to accept magic frames. */
1075 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1086 * Device resume routine. re-enable busmastering, and restart the interface if
1090 fxp_resume(device_t dev)
1092 struct fxp_softc *sc = device_get_softc(dev);
1093 struct ifnet *ifp = sc->ifp;
1099 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1100 sc->flags &= ~FXP_FLAG_WOL;
1101 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1102 /* Disable PME and clear PME status. */
1103 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1104 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1105 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1106 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1107 CSR_READ_1(sc, FXP_CSR_PMDR));
1110 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1113 /* reinitialize interface if necessary */
1114 if (ifp->if_flags & IFF_UP)
1124 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1132 for (x = 1 << (length - 1); x; x >>= 1) {
1134 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1136 reg = FXP_EEPROM_EECS;
1137 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1139 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1141 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1147 * Read from the serial EEPROM. Basically, you manually shift in
1148 * the read opcode (one bit at a time) and then shift in the address,
1149 * and then you shift out the data (all of this one bit at a time).
1150 * The word size is 16 bits, so you have to provide the address for
1151 * every 16 bits of data.
1154 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1159 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1161 * Shift in read opcode.
1163 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1168 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1170 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1172 reg = FXP_EEPROM_EECS;
1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1175 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1179 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1181 if (autosize && reg == 0) {
1182 sc->eeprom_size = data;
1190 reg = FXP_EEPROM_EECS;
1191 for (x = 1 << 15; x; x >>= 1) {
1192 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1194 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1196 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1199 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1206 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1211 * Erase/write enable.
1213 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1214 fxp_eeprom_shiftin(sc, 0x4, 3);
1215 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1216 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1219 * Shift in write opcode, address, data.
1221 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1222 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1223 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1224 fxp_eeprom_shiftin(sc, data, 16);
1225 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1228 * Wait for EEPROM to finish up.
1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1232 for (i = 0; i < 1000; i++) {
1233 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1237 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1240 * Erase/write disable.
1242 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1243 fxp_eeprom_shiftin(sc, 0x4, 3);
1244 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1245 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1252 * Figure out EEPROM size.
1254 * 559's can have either 64-word or 256-word EEPROMs, the 558
1255 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1256 * talks about the existance of 16 to 256 word EEPROMs.
1258 * The only known sizes are 64 and 256, where the 256 version is used
1259 * by CardBus cards to store CIS information.
1261 * The address is shifted in msb-to-lsb, and after the last
1262 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1263 * after which follows the actual data. We try to detect this zero, by
1264 * probing the data-out bit in the EEPROM control register just after
1265 * having shifted in a bit. If the bit is zero, we assume we've
1266 * shifted enough address bits. The data-out should be tri-state,
1267 * before this, which should translate to a logical one.
1270 fxp_autosize_eeprom(struct fxp_softc *sc)
1273 /* guess maximum size of 256 words */
1274 sc->eeprom_size = 8;
1277 (void) fxp_eeprom_getword(sc, 0, 1);
1281 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1285 for (i = 0; i < words; i++)
1286 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1290 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1294 for (i = 0; i < words; i++)
1295 fxp_eeprom_putword(sc, offset + i, data[i]);
1299 * Grab the softc lock and call the real fxp_start_body() routine
1302 fxp_start(struct ifnet *ifp)
1304 struct fxp_softc *sc = ifp->if_softc;
1307 fxp_start_body(ifp);
1312 * Start packet transmission on the interface.
1313 * This routine must be called with the softc lock held, and is an
1314 * internal entry point only.
1317 fxp_start_body(struct ifnet *ifp)
1319 struct fxp_softc *sc = ifp->if_softc;
1320 struct mbuf *mb_head;
1323 FXP_LOCK_ASSERT(sc, MA_OWNED);
1325 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1329 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1332 * We're finished if there is nothing more to add to the list or if
1333 * we're all filled up with buffers to transmit.
1334 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1335 * a NOP command when needed.
1338 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1339 sc->tx_queued < FXP_NTXCB - 1) {
1342 * Grab a packet to transmit.
1344 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1345 if (mb_head == NULL)
1348 if (fxp_encap(sc, &mb_head)) {
1349 if (mb_head == NULL)
1351 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1352 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1356 * Pass packet to bpf if there is a listener.
1358 BPF_MTAP(ifp, mb_head);
1362 * We're finished. If we added to the list, issue a RESUME to get DMA
1363 * going again if suspended.
1366 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1369 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1371 * Set a 5 second timer just in case we don't hear
1372 * from the card again.
1374 sc->watchdog_timer = 5;
1379 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1384 struct fxp_cb_tx *cbp;
1386 bus_dma_segment_t segs[FXP_NTXSEG];
1387 int error, i, nseg, tcp_payload;
1389 FXP_LOCK_ASSERT(sc, MA_OWNED);
1395 * Get pointer to next available tx desc.
1397 txp = sc->fxp_desc.tx_last->tx_next;
1400 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1401 * Ethernet Controller Family Open Source Software
1402 * Developer Manual says:
1403 * Using software parsing is only allowed with legal
1404 * TCP/IP or UDP/IP packets.
1406 * For all other datagrams, hardware parsing must
1408 * Software parsing appears to truncate ICMP and
1409 * fragmented UDP packets that contain one to three
1410 * bytes in the second (and final) mbuf of the packet.
1412 if (sc->flags & FXP_FLAG_EXT_RFA)
1413 txp->tx_cb->ipcb_ip_activation_high =
1414 FXP_IPCB_HARDWAREPARSING_ENABLE;
1418 * Deal with TCP/IP checksum offload. Note that
1419 * in order for TCP checksum offload to work,
1420 * the pseudo header checksum must have already
1421 * been computed and stored in the checksum field
1422 * in the TCP header. The stack should have
1423 * already done this for us.
1425 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1426 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1427 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1428 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1430 #ifdef FXP_IP_CSUM_WAR
1432 * XXX The 82550 chip appears to have trouble
1433 * dealing with IP header checksums in very small
1434 * datagrams, namely fragments from 1 to 3 bytes
1435 * in size. For example, say you want to transmit
1436 * a UDP packet of 1473 bytes. The packet will be
1437 * fragmented over two IP datagrams, the latter
1438 * containing only one byte of data. The 82550 will
1439 * botch the header checksum on the 1-byte fragment.
1440 * As long as the datagram contains 4 or more bytes
1441 * of data, you're ok.
1443 * The following code attempts to work around this
1444 * problem: if the datagram is less than 38 bytes
1445 * in size (14 bytes ether header, 20 bytes IP header,
1446 * plus 4 bytes of data), we punt and compute the IP
1447 * header checksum by hand. This workaround doesn't
1448 * work very well, however, since it can be fooled
1449 * by things like VLAN tags and IP options that make
1450 * the header sizes/offsets vary.
1453 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1454 if (m->m_pkthdr.len < 38) {
1456 m->m_data += ETHER_HDR_LEN;
1457 ip = mtod(m, struct ip *);
1458 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1459 m->m_data -= ETHER_HDR_LEN;
1460 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1462 txp->tx_cb->ipcb_ip_activation_high =
1463 FXP_IPCB_HARDWAREPARSING_ENABLE;
1464 txp->tx_cb->ipcb_ip_schedule |=
1465 FXP_IPCB_IP_CHECKSUM_ENABLE;
1471 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1473 * 82550/82551 requires ethernet/IP/TCP headers must be
1474 * contained in the first active transmit buffer.
1476 struct ether_header *eh;
1478 uint32_t ip_off, poff;
1480 if (M_WRITABLE(*m_head) == 0) {
1481 /* Get a writable copy. */
1482 m = m_dup(*m_head, M_DONTWAIT);
1490 ip_off = sizeof(struct ether_header);
1491 m = m_pullup(*m_head, ip_off);
1496 eh = mtod(m, struct ether_header *);
1497 /* Check the existence of VLAN tag. */
1498 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1499 ip_off = sizeof(struct ether_vlan_header);
1500 m = m_pullup(m, ip_off);
1506 m = m_pullup(m, ip_off + sizeof(struct ip));
1511 ip = (struct ip *)(mtod(m, char *) + ip_off);
1512 poff = ip_off + (ip->ip_hl << 2);
1513 m = m_pullup(m, poff + sizeof(struct tcphdr));
1518 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1519 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
1526 * Since 82550/82551 doesn't modify IP length and pseudo
1527 * checksum in the first frame driver should compute it.
1530 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1531 (tcp->th_off << 2));
1532 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1533 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1534 m->m_pkthdr.tso_segsz));
1535 /* Compute total TCP payload. */
1536 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1537 tcp_payload -= tcp->th_off << 2;
1541 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1543 if (error == EFBIG) {
1544 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg);
1551 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1552 *m_head, segs, &nseg, 0);
1558 } else if (error != 0)
1566 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1567 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1570 for (i = 0; i < nseg; i++) {
1572 * If this is an 82550/82551, then we're using extended
1573 * TxCBs _and_ we're using checksum offload. This means
1574 * that the TxCB is really an IPCB. One major difference
1575 * between the two is that with plain extended TxCBs,
1576 * the bottom half of the TxCB contains two entries from
1577 * the TBD array, whereas IPCBs contain just one entry:
1578 * one entry (8 bytes) has been sacrificed for the TCP/IP
1579 * checksum offload control bits. So to make things work
1580 * right, we have to start filling in the TBD array
1581 * starting from a different place depending on whether
1582 * the chip is an 82550/82551 or not.
1584 if (sc->flags & FXP_FLAG_EXT_RFA) {
1585 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1586 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1588 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1589 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1592 if (sc->flags & FXP_FLAG_EXT_RFA) {
1593 /* Configure dynamic TBD for 82550/82551. */
1594 cbp->tbd_number = 0xFF;
1595 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1597 cbp->tbd_number = nseg;
1598 /* Configure TSO. */
1599 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1600 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1601 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1602 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1603 FXP_IPCB_IP_CHECKSUM_ENABLE |
1604 FXP_IPCB_TCP_PACKET |
1605 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1607 /* Configure VLAN hardware tag insertion. */
1608 if ((m->m_flags & M_VLANTAG) != 0) {
1609 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1610 txp->tx_cb->ipcb_ip_activation_high |=
1611 FXP_IPCB_INSERTVLAN_ENABLE;
1615 txp->tx_cb->cb_status = 0;
1616 txp->tx_cb->byte_count = 0;
1617 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1618 txp->tx_cb->cb_command =
1619 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1622 txp->tx_cb->cb_command =
1623 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1624 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1625 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1626 txp->tx_cb->tx_threshold = tx_threshold;
1629 * Advance the end of list forward.
1634 * On platforms which can't access memory in 16-bit
1635 * granularities, we must prevent the card from DMA'ing
1636 * up the status while we update the command field.
1637 * This could cause us to overwrite the completion status.
1638 * XXX This is probably bogus and we're _not_ looking
1639 * for atomicity here.
1641 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1642 htole16(FXP_CB_COMMAND_S));
1644 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1645 #endif /*__alpha__*/
1646 sc->fxp_desc.tx_last = txp;
1649 * Advance the beginning of the list forward if there are
1650 * no other packets queued (when nothing is queued, tx_first
1651 * sits on the last TxCB that was sent out).
1653 if (sc->tx_queued == 0)
1654 sc->fxp_desc.tx_first = txp;
1661 #ifdef DEVICE_POLLING
1662 static poll_handler_t fxp_poll;
1665 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1667 struct fxp_softc *sc = ifp->if_softc;
1672 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1677 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1679 if (cmd == POLL_AND_CHECK_STATUS) {
1682 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1683 if (tmp == 0xff || tmp == 0) {
1685 return (rx_npkts); /* nothing to do */
1688 /* ack what we can */
1690 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1693 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1697 #endif /* DEVICE_POLLING */
1700 * Process interface interrupts.
1705 struct fxp_softc *sc = xsc;
1706 struct ifnet *ifp = sc->ifp;
1710 if (sc->suspended) {
1715 #ifdef DEVICE_POLLING
1716 if (ifp->if_capenable & IFCAP_POLLING) {
1721 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1723 * It should not be possible to have all bits set; the
1724 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1725 * all bits are set, this may indicate that the card has
1726 * been physically ejected, so ignore it.
1728 if (statack == 0xff) {
1734 * First ACK all the interrupts in this pass.
1736 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1737 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1738 fxp_intr_body(sc, ifp, statack, -1);
1744 fxp_txeof(struct fxp_softc *sc)
1750 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1751 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1752 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1753 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1754 txp = txp->tx_next) {
1755 if (txp->tx_mbuf != NULL) {
1756 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1757 BUS_DMASYNC_POSTWRITE);
1758 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1759 m_freem(txp->tx_mbuf);
1760 txp->tx_mbuf = NULL;
1761 /* clear this to reset csum offload bits */
1762 txp->tx_cb->tbd[0].tb_addr = 0;
1765 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1767 sc->fxp_desc.tx_first = txp;
1768 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1770 if (sc->tx_queued == 0)
1771 sc->watchdog_timer = 0;
1775 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1776 uint16_t status, int pos)
1778 struct ether_header *eh;
1781 int32_t hlen, len, pktlen, temp32;
1782 uint16_t csum, *opts;
1784 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1785 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1786 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1787 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1788 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1789 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1790 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1791 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1792 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1794 m->m_pkthdr.csum_data = 0xffff;
1800 pktlen = m->m_pkthdr.len;
1801 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1803 eh = mtod(m, struct ether_header *);
1804 if (eh->ether_type != htons(ETHERTYPE_IP))
1806 ip = (struct ip *)(eh + 1);
1807 if (ip->ip_v != IPVERSION)
1810 hlen = ip->ip_hl << 2;
1811 pktlen -= sizeof(struct ether_header);
1812 if (hlen < sizeof(struct ip))
1814 if (ntohs(ip->ip_len) < hlen)
1816 if (ntohs(ip->ip_len) != pktlen)
1818 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1819 return; /* can't handle fragmented packet */
1823 if (pktlen < (hlen + sizeof(struct tcphdr)))
1827 if (pktlen < (hlen + sizeof(struct udphdr)))
1829 uh = (struct udphdr *)((caddr_t)ip + hlen);
1830 if (uh->uh_sum == 0)
1831 return; /* no checksum */
1836 /* Extract computed checksum. */
1837 csum = be16dec(mtod(m, char *) + pos);
1838 /* checksum fixup for IP options */
1839 len = hlen - sizeof(struct ip);
1841 opts = (uint16_t *)(ip + 1);
1842 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1843 temp32 = csum - *opts;
1844 temp32 = (temp32 >> 16) + (temp32 & 65535);
1845 csum = temp32 & 65535;
1848 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1849 m->m_pkthdr.csum_data = csum;
1853 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1858 struct fxp_rfa *rfa;
1859 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1864 FXP_LOCK_ASSERT(sc, MA_OWNED);
1868 #ifdef DEVICE_POLLING
1869 /* Pick up a deferred RNR condition if `count' ran out last time. */
1870 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1871 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1877 * Free any finished transmit mbuf chains.
1879 * Handle the CNA event likt a CXTNO event. It used to
1880 * be that this event (control unit not ready) was not
1881 * encountered, but it is now with the SMPng modifications.
1882 * The exact sequence of events that occur when the interface
1883 * is brought up are different now, and if this event
1884 * goes unhandled, the configuration/rxfilter setup sequence
1885 * can stall for several seconds. The result is that no
1886 * packets go out onto the wire for about 5 to 10 seconds
1887 * after the interface is ifconfig'ed for the first time.
1889 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1893 * Try to start more packets transmitting.
1895 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1896 fxp_start_body(ifp);
1899 * Just return if nothing happened on the receive side.
1901 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1905 * Process receiver interrupts. If a no-resource (RNR)
1906 * condition exists, get whatever packets we can and
1907 * re-start the receiver.
1909 * When using polling, we do not process the list to completion,
1910 * so when we get an RNR interrupt we must defer the restart
1911 * until we hit the last buffer with the C bit set.
1912 * If we run out of cycles and rfa_headm has the C bit set,
1913 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1914 * that the info will be used in the subsequent polling cycle.
1917 rxp = sc->fxp_desc.rx_head;
1919 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1920 RFA_ALIGNMENT_FUDGE);
1921 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1922 BUS_DMASYNC_POSTREAD);
1924 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1925 if (count >= 0 && count-- == 0) {
1927 /* Defer RNR processing until the next time. */
1928 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1933 #endif /* DEVICE_POLLING */
1935 status = le16toh(rfa->rfa_status);
1936 if ((status & FXP_RFA_STATUS_C) == 0)
1940 * Advance head forward.
1942 sc->fxp_desc.rx_head = rxp->rx_next;
1945 * Add a new buffer to the receive chain.
1946 * If this fails, the old buffer is recycled
1949 if (fxp_new_rfabuf(sc, rxp) == 0) {
1953 * Fetch packet length (the top 2 bits of
1954 * actual_size are flags set by the controller
1955 * upon completion), and drop the packet in case
1956 * of bogus length or CRC errors.
1958 total_len = le16toh(rfa->actual_size) & 0x3fff;
1959 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1960 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1961 /* Adjust for appended checksum bytes. */
1964 if (total_len < sizeof(struct ether_header) ||
1965 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1966 sc->rfa_size || status & FXP_RFA_STATUS_CRC) {
1971 m->m_pkthdr.len = m->m_len = total_len;
1972 m->m_pkthdr.rcvif = ifp;
1974 /* Do IP checksum checking. */
1975 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1976 fxp_rxcsum(sc, ifp, m, status, total_len);
1977 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1978 (status & FXP_RFA_STATUS_VLAN) != 0) {
1979 m->m_pkthdr.ether_vtag =
1980 ntohs(rfa->rfax_vlan_id);
1981 m->m_flags |= M_VLANTAG;
1984 * Drop locks before calling if_input() since it
1985 * may re-enter fxp_start() in the netisr case.
1986 * This would result in a lock reversal. Better
1987 * performance might be obtained by chaining all
1988 * packets received, dropping the lock, and then
1989 * calling if_input() on each one.
1992 (*ifp->if_input)(ifp, m);
1995 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1998 /* Reuse RFA and loaded DMA map. */
2000 fxp_discard_rfabuf(sc, rxp);
2002 fxp_add_rfabuf(sc, rxp);
2006 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2007 sc->fxp_desc.rx_head->rx_addr);
2008 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2014 * Update packet in/out/collision statistics. The i82557 doesn't
2015 * allow you to access these counters without doing a fairly
2016 * expensive DMA to get _all_ of the statistics it maintains, so
2017 * we do this operation here only once per second. The statistics
2018 * counters in the kernel are updated from the previous dump-stats
2019 * DMA and then a new dump-stats DMA is started. The on-chip
2020 * counters are zeroed when the DMA completes. If we can't start
2021 * the DMA immediately, we don't wait - we just prepare to read
2022 * them again next time.
2027 struct fxp_softc *sc = xsc;
2028 struct ifnet *ifp = sc->ifp;
2029 struct fxp_stats *sp = sc->fxp_stats;
2031 FXP_LOCK_ASSERT(sc, MA_OWNED);
2032 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
2033 ifp->if_opackets += le32toh(sp->tx_good);
2034 ifp->if_collisions += le32toh(sp->tx_total_collisions);
2036 ifp->if_ipackets += le32toh(sp->rx_good);
2037 sc->rx_idle_secs = 0;
2038 } else if (sc->flags & FXP_FLAG_RXBUG) {
2040 * Receiver's been idle for another second.
2045 le32toh(sp->rx_crc_errors) +
2046 le32toh(sp->rx_alignment_errors) +
2047 le32toh(sp->rx_rnr_errors) +
2048 le32toh(sp->rx_overrun_errors);
2050 * If any transmit underruns occured, bump up the transmit
2051 * threshold by another 512 bytes (64 * 8).
2053 if (sp->tx_underruns) {
2054 ifp->if_oerrors += le32toh(sp->tx_underruns);
2055 if (tx_threshold < 192)
2060 * Release any xmit buffers that have completed DMA. This isn't
2061 * strictly necessary to do here, but it's advantagous for mbufs
2062 * with external storage to be released in a timely manner rather
2063 * than being defered for a potentially long time. This limits
2064 * the delay to a maximum of one second.
2069 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2070 * then assume the receiver has locked up and attempt to clear
2071 * the condition by reprogramming the multicast filter. This is
2072 * a work-around for a bug in the 82557 where the receiver locks
2073 * up if it gets certain types of garbage in the syncronization
2074 * bits prior to the packet header. This bug is supposed to only
2075 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2076 * mode as well (perhaps due to a 10/100 speed transition).
2078 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2079 sc->rx_idle_secs = 0;
2080 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2085 * If there is no pending command, start another stats
2086 * dump. Otherwise punt for now.
2088 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2090 * Start another stats dump.
2092 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2093 BUS_DMASYNC_PREREAD);
2094 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2097 * A previous command is still waiting to be accepted.
2098 * Just zero our copy of the stats and wait for the
2099 * next timer event to update them.
2102 sp->tx_underruns = 0;
2103 sp->tx_total_collisions = 0;
2106 sp->rx_crc_errors = 0;
2107 sp->rx_alignment_errors = 0;
2108 sp->rx_rnr_errors = 0;
2109 sp->rx_overrun_errors = 0;
2111 if (sc->miibus != NULL)
2112 mii_tick(device_get_softc(sc->miibus));
2115 * Check that chip hasn't hung.
2120 * Schedule another timeout one second from now.
2122 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2126 * Stop the interface. Cancels the statistics updater and resets
2130 fxp_stop(struct fxp_softc *sc)
2132 struct ifnet *ifp = sc->ifp;
2136 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2137 sc->watchdog_timer = 0;
2140 * Cancel stats updater.
2142 callout_stop(&sc->stat_ch);
2145 * Preserve PCI configuration, configure, IA/multicast
2146 * setup and put RU and CU into idle state.
2148 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2150 /* Disable interrupts. */
2151 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2154 * Release any xmit buffers.
2156 txp = sc->fxp_desc.tx_list;
2158 for (i = 0; i < FXP_NTXCB; i++) {
2159 if (txp[i].tx_mbuf != NULL) {
2160 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2161 BUS_DMASYNC_POSTWRITE);
2162 bus_dmamap_unload(sc->fxp_txmtag,
2164 m_freem(txp[i].tx_mbuf);
2165 txp[i].tx_mbuf = NULL;
2166 /* clear this to reset csum offload bits */
2167 txp[i].tx_cb->tbd[0].tb_addr = 0;
2171 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2172 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2177 * Watchdog/transmission transmit timeout handler. Called when a
2178 * transmission is started on the interface, but no interrupt is
2179 * received before the timeout. This usually indicates that the
2180 * card has wedged for some reason.
2183 fxp_watchdog(struct fxp_softc *sc)
2186 FXP_LOCK_ASSERT(sc, MA_OWNED);
2188 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2191 device_printf(sc->dev, "device timeout\n");
2192 sc->ifp->if_oerrors++;
2198 * Acquire locks and then call the real initialization function. This
2199 * is necessary because ether_ioctl() calls if_init() and this would
2200 * result in mutex recursion if the mutex was held.
2205 struct fxp_softc *sc = xsc;
2213 * Perform device initialization. This routine must be called with the
2217 fxp_init_body(struct fxp_softc *sc)
2219 struct ifnet *ifp = sc->ifp;
2220 struct fxp_cb_config *cbp;
2221 struct fxp_cb_ias *cb_ias;
2222 struct fxp_cb_tx *tcbp;
2226 FXP_LOCK_ASSERT(sc, MA_OWNED);
2228 * Cancel any pending I/O
2233 * Issue software reset, which also unloads the microcode.
2235 sc->flags &= ~FXP_FLAG_UCODE;
2236 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2239 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2242 * Initialize base of CBL and RFA memory. Loading with zero
2243 * sets it up for regular linear addressing.
2245 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2246 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2249 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2252 * Initialize base of dump-stats buffer.
2255 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
2256 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2257 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2260 * Attempt to load microcode if requested.
2261 * For ICH based controllers do not load microcode.
2263 if (sc->ident->ich == 0) {
2264 if (ifp->if_flags & IFF_LINK0 &&
2265 (sc->flags & FXP_FLAG_UCODE) == 0)
2270 * Set IFF_ALLMULTI status. It's needed in configure action
2276 * We temporarily use memory that contains the TxCB list to
2277 * construct the config CB. The TxCB list memory is rebuilt
2280 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2283 * This bcopy is kind of disgusting, but there are a bunch of must be
2284 * zero and must be one bits in this structure and this is the easiest
2285 * way to initialize them all to proper values.
2287 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2290 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2292 cbp->link_addr = 0xffffffff; /* (no) next command */
2293 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2294 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2295 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2296 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2297 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2298 cbp->type_enable = 0; /* actually reserved */
2299 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2300 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2301 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2302 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2303 cbp->dma_mbce = 0; /* (disable) dma max counters */
2304 cbp->late_scb = 0; /* (don't) defer SCB update */
2305 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2306 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2307 cbp->ci_int = 1; /* interrupt on CU idle */
2308 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2309 cbp->ext_stats_dis = 1; /* disable extended counters */
2310 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2311 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2312 cbp->disc_short_rx = !prm; /* discard short packets */
2313 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2314 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2315 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2316 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2317 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2318 cbp->csma_dis = 0; /* (don't) disable link */
2319 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2320 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2321 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2322 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2323 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2324 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2325 cbp->nsai = 1; /* (don't) disable source addr insert */
2326 cbp->preamble_length = 2; /* (7 byte) preamble */
2327 cbp->loopback = 0; /* (don't) loopback */
2328 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2329 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2330 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2331 cbp->promiscuous = prm; /* promiscuous mode */
2332 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2333 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2334 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2335 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2336 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2338 cbp->stripping = !prm; /* truncate rx packet to byte count */
2339 cbp->padding = 1; /* (do) pad short tx packets */
2340 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2341 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2342 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2343 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2344 cbp->force_fdx = 0; /* (don't) force full duplex */
2345 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2346 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2347 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
2348 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2349 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2350 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2352 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) {
2354 * The 82557 has no hardware flow control, the values
2355 * below are the defaults for the chip.
2357 cbp->fc_delay_lsb = 0;
2358 cbp->fc_delay_msb = 0x40;
2359 cbp->pri_fc_thresh = 3;
2361 cbp->rx_fc_restop = 0;
2362 cbp->rx_fc_restart = 0;
2364 cbp->pri_fc_loc = 1;
2366 cbp->fc_delay_lsb = 0x1f;
2367 cbp->fc_delay_msb = 0x01;
2368 cbp->pri_fc_thresh = 3;
2369 cbp->tx_fc_dis = 0; /* enable transmit FC */
2370 cbp->rx_fc_restop = 1; /* enable FC restop frames */
2371 cbp->rx_fc_restart = 1; /* enable FC restart frames */
2372 cbp->fc_filter = !prm; /* drop FC frames to host */
2373 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2377 * Start the config command/DMA.
2380 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2381 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2382 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2383 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2384 /* ...and wait for it to complete. */
2385 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2388 * Now initialize the station address. Temporarily use the TxCB
2389 * memory area like we did above for the config CB.
2391 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2392 cb_ias->cb_status = 0;
2393 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2394 cb_ias->link_addr = 0xffffffff;
2395 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2398 * Start the IAS (Individual Address Setup) command/DMA.
2401 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2403 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2404 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2405 /* ...and wait for it to complete. */
2406 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2409 * Initialize the multicast address list.
2414 * Initialize transmit control block (TxCB) list.
2416 txp = sc->fxp_desc.tx_list;
2417 tcbp = sc->fxp_desc.cbl_list;
2418 bzero(tcbp, FXP_TXCB_SZ);
2419 for (i = 0; i < FXP_NTXCB; i++) {
2420 txp[i].tx_mbuf = NULL;
2421 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2422 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2423 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2424 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2425 if (sc->flags & FXP_FLAG_EXT_TXCB)
2426 tcbp[i].tbd_array_addr =
2427 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2429 tcbp[i].tbd_array_addr =
2430 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2431 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2434 * Set the suspend flag on the first TxCB and start the control
2435 * unit. It will execute the NOP and then suspend.
2437 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2438 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2439 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2440 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2444 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2445 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2448 * Initialize receiver buffer area - RFA.
2451 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2452 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2455 * Set current media.
2457 if (sc->miibus != NULL)
2458 mii_mediachg(device_get_softc(sc->miibus));
2460 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2461 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2464 * Enable interrupts.
2466 #ifdef DEVICE_POLLING
2468 * ... but only do that if we are not polling. And because (presumably)
2469 * the default is interrupts on, we need to disable them explicitly!
2471 if (ifp->if_capenable & IFCAP_POLLING )
2472 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2474 #endif /* DEVICE_POLLING */
2475 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2478 * Start stats updater.
2480 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2484 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2491 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2494 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2498 * Change media according to request.
2501 fxp_ifmedia_upd(struct ifnet *ifp)
2503 struct fxp_softc *sc = ifp->if_softc;
2504 struct mii_data *mii;
2506 mii = device_get_softc(sc->miibus);
2508 if (mii->mii_instance) {
2509 struct mii_softc *miisc;
2510 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2511 mii_phy_reset(miisc);
2519 * Notify the world which media we're using.
2522 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2524 struct fxp_softc *sc = ifp->if_softc;
2525 struct mii_data *mii;
2527 mii = device_get_softc(sc->miibus);
2530 ifmr->ifm_active = mii->mii_media_active;
2531 ifmr->ifm_status = mii->mii_media_status;
2533 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2534 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2535 sc->cu_resume_bug = 1;
2537 sc->cu_resume_bug = 0;
2542 * Add a buffer to the end of the RFA buffer list.
2543 * Return 0 if successful, 1 for failure. A failure results in
2544 * reusing the RFA buffer.
2545 * The RFA struct is stuck at the beginning of mbuf cluster and the
2546 * data pointer is fixed up to point just past it.
2549 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2552 struct fxp_rfa *rfa;
2553 bus_dmamap_t tmp_map;
2556 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2561 * Move the data pointer up so that the incoming data packet
2562 * will be 32-bit aligned.
2564 m->m_data += RFA_ALIGNMENT_FUDGE;
2567 * Get a pointer to the base of the mbuf cluster and move
2568 * data start past it.
2570 rfa = mtod(m, struct fxp_rfa *);
2571 m->m_data += sc->rfa_size;
2572 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2574 rfa->rfa_status = 0;
2575 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2576 rfa->actual_size = 0;
2577 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2581 * Initialize the rest of the RFA. Note that since the RFA
2582 * is misaligned, we cannot store values directly. We're thus
2583 * using the le32enc() function which handles endianness and
2584 * is also alignment-safe.
2586 le32enc(&rfa->link_addr, 0xffffffff);
2587 le32enc(&rfa->rbd_addr, 0xffffffff);
2589 /* Map the RFA into DMA memory. */
2590 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2591 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2598 if (rxp->rx_mbuf != NULL)
2599 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2600 tmp_map = sc->spare_map;
2601 sc->spare_map = rxp->rx_map;
2602 rxp->rx_map = tmp_map;
2605 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2606 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2611 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2613 struct fxp_rfa *p_rfa;
2614 struct fxp_rx *p_rx;
2617 * If there are other buffers already on the list, attach this
2618 * one to the end by fixing up the tail to point to this one.
2620 if (sc->fxp_desc.rx_head != NULL) {
2621 p_rx = sc->fxp_desc.rx_tail;
2622 p_rfa = (struct fxp_rfa *)
2623 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2624 p_rx->rx_next = rxp;
2625 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2626 p_rfa->rfa_control = 0;
2627 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2628 BUS_DMASYNC_PREWRITE);
2630 rxp->rx_next = NULL;
2631 sc->fxp_desc.rx_head = rxp;
2633 sc->fxp_desc.rx_tail = rxp;
2637 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2640 struct fxp_rfa *rfa;
2643 m->m_data = m->m_ext.ext_buf;
2645 * Move the data pointer up so that the incoming data packet
2646 * will be 32-bit aligned.
2648 m->m_data += RFA_ALIGNMENT_FUDGE;
2651 * Get a pointer to the base of the mbuf cluster and move
2652 * data start past it.
2654 rfa = mtod(m, struct fxp_rfa *);
2655 m->m_data += sc->rfa_size;
2656 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2658 rfa->rfa_status = 0;
2659 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2660 rfa->actual_size = 0;
2663 * Initialize the rest of the RFA. Note that since the RFA
2664 * is misaligned, we cannot store values directly. We're thus
2665 * using the le32enc() function which handles endianness and
2666 * is also alignment-safe.
2668 le32enc(&rfa->link_addr, 0xffffffff);
2669 le32enc(&rfa->rbd_addr, 0xffffffff);
2671 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2676 fxp_miibus_readreg(device_t dev, int phy, int reg)
2678 struct fxp_softc *sc = device_get_softc(dev);
2682 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2683 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2685 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2690 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2692 return (value & 0xffff);
2696 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2698 struct fxp_softc *sc = device_get_softc(dev);
2701 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2702 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2705 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2710 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2715 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2717 struct fxp_softc *sc = ifp->if_softc;
2718 struct ifreq *ifr = (struct ifreq *)data;
2719 struct mii_data *mii;
2720 int flag, mask, error = 0, reinit;
2726 * If interface is marked up and not running, then start it.
2727 * If it is marked down and running, stop it.
2728 * XXX If it's up then re-initialize it. This is so flags
2729 * such as IFF_PROMISC are handled.
2731 if (ifp->if_flags & IFF_UP) {
2732 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2733 ((ifp->if_flags ^ sc->if_flags) &
2734 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0)
2736 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2739 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2742 sc->if_flags = ifp->if_flags;
2748 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2754 if (sc->miibus != NULL) {
2755 mii = device_get_softc(sc->miibus);
2756 error = ifmedia_ioctl(ifp, ifr,
2757 &mii->mii_media, command);
2759 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2765 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2766 #ifdef DEVICE_POLLING
2767 if (mask & IFCAP_POLLING) {
2768 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2769 error = ether_poll_register(fxp_poll, ifp);
2773 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2774 FXP_SCB_INTR_DISABLE);
2775 ifp->if_capenable |= IFCAP_POLLING;
2778 error = ether_poll_deregister(ifp);
2779 /* Enable interrupts in any case */
2781 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2782 ifp->if_capenable &= ~IFCAP_POLLING;
2788 if ((mask & IFCAP_TXCSUM) != 0 &&
2789 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2790 ifp->if_capenable ^= IFCAP_TXCSUM;
2791 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2792 ifp->if_hwassist |= FXP_CSUM_FEATURES;
2794 ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2796 if ((mask & IFCAP_RXCSUM) != 0 &&
2797 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2798 ifp->if_capenable ^= IFCAP_RXCSUM;
2799 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2802 if ((mask & IFCAP_TSO4) != 0 &&
2803 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2804 ifp->if_capenable ^= IFCAP_TSO4;
2805 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2806 ifp->if_hwassist |= CSUM_TSO;
2808 ifp->if_hwassist &= ~CSUM_TSO;
2810 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2811 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2812 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2813 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2814 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2815 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2816 if (sc->revision != FXP_REV_82557)
2817 flag = FXP_FLAG_LONG_PKT_EN;
2818 else /* a hack to get long frames on the old chip */
2819 flag = FXP_FLAG_SAVE_BAD;
2821 if (ifp->if_flags & IFF_UP)
2824 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2825 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2826 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2829 if (reinit > 0 && ifp->if_flags & IFF_UP)
2832 VLAN_CAPABILITIES(ifp);
2836 error = ether_ioctl(ifp, command, data);
2842 * Fill in the multicast address list and return number of entries.
2845 fxp_mc_addrs(struct fxp_softc *sc)
2847 struct fxp_cb_mcs *mcsp = sc->mcsp;
2848 struct ifnet *ifp = sc->ifp;
2849 struct ifmultiaddr *ifma;
2853 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2854 if_maddr_rlock(ifp);
2855 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2856 if (ifma->ifma_addr->sa_family != AF_LINK)
2858 if (nmcasts >= MAXMCADDR) {
2859 ifp->if_flags |= IFF_ALLMULTI;
2863 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2864 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2867 if_maddr_runlock(ifp);
2869 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2874 * Program the multicast filter.
2876 * We have an artificial restriction that the multicast setup command
2877 * must be the first command in the chain, so we take steps to ensure
2878 * this. By requiring this, it allows us to keep up the performance of
2879 * the pre-initialized command ring (esp. link pointers) by not actually
2880 * inserting the mcsetup command in the ring - i.e. its link pointer
2881 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2882 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2883 * lead into the regular TxCB ring when it completes.
2886 fxp_mc_setup(struct fxp_softc *sc)
2888 struct fxp_cb_mcs *mcsp;
2891 FXP_LOCK_ASSERT(sc, MA_OWNED);
2894 mcsp->cb_status = 0;
2895 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2896 mcsp->link_addr = 0xffffffff;
2900 * Wait until command unit is idle. This should never be the
2901 * case when nothing is queued, but make sure anyway.
2904 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
2905 FXP_SCB_CUS_IDLE && --count)
2908 device_printf(sc->dev, "command queue timeout\n");
2913 * Start the multicast setup command.
2916 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
2917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2918 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2919 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2920 /* ...and wait for it to complete. */
2921 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
2924 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2925 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2926 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2927 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2928 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2929 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2930 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
2932 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
2938 u_short int_delay_offset;
2939 u_short bundle_max_offset;
2941 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2942 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2943 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2944 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2945 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2946 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2947 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2948 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2949 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2950 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2951 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
2952 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
2953 { 0, NULL, 0, 0, 0 }
2957 fxp_load_ucode(struct fxp_softc *sc)
2960 struct fxp_cb_ucode *cbp;
2963 for (uc = ucode_table; uc->ucode != NULL; uc++)
2964 if (sc->revision == uc->revision)
2966 if (uc->ucode == NULL)
2968 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2970 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2971 cbp->link_addr = 0xffffffff; /* (no) next command */
2972 for (i = 0; i < uc->length; i++)
2973 cbp->ucode[i] = htole32(uc->ucode[i]);
2974 if (uc->int_delay_offset)
2975 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
2976 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
2977 if (uc->bundle_max_offset)
2978 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
2979 htole16(sc->tunable_bundle_max);
2981 * Download the ucode to the chip.
2984 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2986 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2987 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2988 /* ...and wait for it to complete. */
2989 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2990 device_printf(sc->dev,
2991 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2992 sc->tunable_int_delay,
2993 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2994 sc->flags |= FXP_FLAG_UCODE;
2998 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3002 value = *(int *)arg1;
3003 error = sysctl_handle_int(oidp, &value, 0, req);
3004 if (error || !req->newptr)
3006 if (value < low || value > high)
3008 *(int *)arg1 = value;
3013 * Interrupt delay is expressed in microseconds, a multiplier is used
3014 * to convert this to the appropriate clock ticks before using.
3017 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3019 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3023 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3025 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));