2 /* $OpenBSD: if_iwnreg.h,v 1.9 2007/11/27 20:59:40 damien Exp $ */
6 * Damien Bergamini <damien.bergamini@free.fr>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #define IWN_TX_RING_COUNT 256
24 #define IWN_RX_RING_COUNT 64
26 #define IWN_NTXQUEUES 16
27 #define IWN_NTXCHAINS 2
30 * Rings must be aligned on a 256-byte boundary.
32 #define IWN_RING_DMA_ALIGN 256
34 /* maximum scatter/gather */
35 #define IWN_MAX_SCATTER 20
37 /* Rx buffers must be large enough to hold a full 4K A-MPDU */
38 #define IWN_RBUF_SIZE (4 * 1024)
41 * Control and status registers.
43 #define IWN_HWCONFIG 0x000
44 #define IWN_INTR_MIT 0x004
45 #define IWN_INTR 0x008
46 #define IWN_MASK 0x00c
47 #define IWN_INTR_STATUS 0x010
48 #define IWN_RESET 0x020
49 #define IWN_GPIO_CTL 0x024
50 #define IWN_EEPROM_CTL 0x02c
51 #define IWN_UCODE_CLR 0x05c
52 #define IWN_CHICKEN 0x100
53 #define IWN_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
54 #define IWN_MEM_WADDR 0x410
55 #define IWN_MEM_WDATA 0x418
56 #define IWN_WRITE_MEM_ADDR 0x444
57 #define IWN_READ_MEM_ADDR 0x448
58 #define IWN_WRITE_MEM_DATA 0x44c
59 #define IWN_READ_MEM_DATA 0x450
60 #define IWN_TX_WIDX 0x460
62 #define IWN_KW_BASE 0x197c
63 #define IWN_TX_BASE(qid) (0x19d0 + (qid) * 4)
64 #define IWN_RW_WIDX_PTR 0x1bc0
65 #define IWN_RX_BASE 0x1bc4
66 #define IWN_RX_WIDX 0x1bc8
67 #define IWN_RX_CONFIG 0x1c00
68 #define IWN_RX_STATUS 0x1c44
69 #define IWN_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
70 #define IWN_TX_STATUS 0x1eb0
72 #define IWN_SRAM_BASE 0xa02c00
73 #define IWN_TX_ACTIVE (IWN_SRAM_BASE + 0x01c)
74 #define IWN_QUEUE_RIDX(qid) (IWN_SRAM_BASE + 0x064 + (qid) * 4)
75 #define IWN_SELECT_QCHAIN (IWN_SRAM_BASE + 0x0d0)
76 #define IWN_QUEUE_INTR_MASK (IWN_SRAM_BASE + 0x0e4)
77 #define IWN_TXQ_STATUS(qid) (IWN_SRAM_BASE + 0x104 + (qid) * 4)
80 * NIC internal memory offsets.
82 #define IWN_CLOCK_CTL 0x3000
83 #define IWN_MEM_CLOCK2 0x3008
84 #define IWN_MEM_POWER 0x300c
85 #define IWN_MEM_PCIDEV 0x3010
86 #define IWN_MEM_UCODE_CTL 0x3400
87 #define IWN_MEM_UCODE_SRC 0x3404
88 #define IWN_MEM_UCODE_DST 0x3408
89 #define IWN_MEM_UCODE_SIZE 0x340c
90 #define IWN_MEM_TEXT_BASE 0x3490
91 #define IWN_MEM_TEXT_SIZE 0x3494
92 #define IWN_MEM_DATA_BASE 0x3498
93 #define IWN_MEM_DATA_SIZE 0x349c
94 #define IWN_MEM_UCODE_BASE 0x3800
97 /* possible flags for register IWN_HWCONFIG */
98 #define IWN_HW_EEPROM_LOCKED (1 << 21)
100 /* possible flags for registers IWN_READ_MEM_ADDR/IWN_WRITE_MEM_ADDR */
101 #define IWN_MEM_4 ((sizeof (uint32_t) - 1) << 24)
103 /* possible values for IWN_MEM_UCODE_DST */
104 #define IWN_FW_TEXT 0x00000000
106 /* possible flags for register IWN_RESET */
107 #define IWN_NEVO_RESET (1 << 0)
108 #define IWN_SW_RESET (1 << 7)
109 #define IWN_MASTER_DISABLED (1 << 8)
110 #define IWN_STOP_MASTER (1 << 9)
112 /* possible flags for register IWN_GPIO_CTL */
113 #define IWN_GPIO_CLOCK (1 << 0)
114 #define IWN_GPIO_INIT (1 << 2)
115 #define IWN_GPIO_MAC (1 << 3)
116 #define IWN_GPIO_SLEEP (1 << 4)
117 #define IWN_GPIO_PWR_STATUS 0x07000000
118 #define IWN_GPIO_PWR_SLEEP (4 << 24)
119 #define IWN_GPIO_RF_ENABLED (1 << 27)
121 /* possible flags for register IWN_CHICKEN */
122 #define IWN_CHICKEN_DISLOS (1 << 29)
124 /* possible flags for register IWN_UCODE_CLR */
125 #define IWN_RADIO_OFF (1 << 1)
126 #define IWN_DISABLE_CMD (1 << 2)
127 #define IWN_CTEMP_STOP_RF (1 << 3)
129 /* possible flags for IWN_RX_STATUS */
130 #define IWN_RX_IDLE (1 << 24)
132 /* possible flags for register IWN_UC_CTL */
133 #define IWN_UC_ENABLE (1 << 30)
134 #define IWN_UC_RUN (1 << 31)
136 /* possible flags for register IWN_INTR */
137 #define IWN_ALIVE_INTR (1 << 0)
138 #define IWN_WAKEUP_INTR (1 << 1)
139 #define IWN_SW_RX_INTR (1 << 3)
140 #define IWN_CT_REACHED (1 << 6)
141 #define IWN_RF_TOGGLED (1 << 7)
142 #define IWN_SW_ERROR (1 << 25)
143 #define IWN_TX_INTR (1 << 27)
144 #define IWN_HW_ERROR (1 << 29)
145 #define IWN_RX_INTR (1 << 31)
147 #define IWN_INTR_BITS "\20\1ALIVE\2WAKEUP\3SW_RX\6CT_REACHED\7RF_TOGGLED" \
148 "\32SW_ERROR\34TX_INTR\36HW_ERROR\40RX_INTR"
150 #define IWN_INTR_MASK \
151 (IWN_SW_ERROR | IWN_HW_ERROR | IWN_TX_INTR | IWN_RX_INTR | \
152 IWN_ALIVE_INTR | IWN_WAKEUP_INTR | IWN_SW_RX_INTR | \
153 IWN_CT_REACHED | IWN_RF_TOGGLED)
155 /* possible flags for register IWN_INTR_STATUS */
156 #define IWN_STATUS_TXQ(x) (1 << (x))
157 #define IWN_STATUS_RXQ(x) (1 << ((x) + 16))
158 #define IWN_STATUS_PRI (1 << 30)
159 /* shortcuts for the above */
160 #define IWN_TX_STATUS_INTR \
161 (IWN_STATUS_TXQ(0) | IWN_STATUS_TXQ(1) | IWN_STATUS_TXQ(6))
162 #define IWN_RX_STATUS_INTR \
163 (IWN_STATUS_RXQ(0) | IWN_STATUS_RXQ(1) | IWN_STATUS_RXQ(2) | \
166 /* possible flags for register IWN_TX_STATUS */
167 #define IWN_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16))
169 /* possible flags/masks for register IWN_EEPROM_CTL */
170 #define IWN_EEPROM_READY (1 << 0)
171 #define IWN_EEPROM_MSK (1 << 1)
173 /* possible flags for register IWN_TXQ_STATUS */
174 #define IWN_TXQ_STATUS_ACTIVE 0x0007fc01
176 /* possible flags for register IWN_MEM_POWER */
177 #define IWN_POWER_RESET (1 << 26)
179 /* possible flags for register IWN_MEM_TEXT_SIZE */
180 #define IWN_FW_UPDATED (1 << 31)
182 /* possible flags for device-specific PCI register 0xe8 */
183 #define IWN_DIS_NOSNOOP (1 << 11)
185 /* possible flags for device-specific PCI register 0xf0 */
186 #define IWN_ENA_L1 (1 << 1)
189 #define IWN_TX_WINDOW 64
191 uint16_t len[IWN_NTXQUEUES][512]; /* 16KB total */
192 uint16_t closed_count;
193 uint16_t closed_rx_count;
194 uint16_t finished_count;
195 uint16_t finished_rx_count;
196 uint32_t reserved[2];
205 } __packed segs[IWN_MAX_SCATTER / 2];
206 /* pad to 128 bytes */
210 #define IWN_SET_DESC_NSEGS(d, x) \
211 (d)->flags = htole32(((x) & 0x1f) << 24)
213 /* set a segment physical address and length in a Tx descriptor */
214 #define IWN_SET_DESC_SEG(d, n, addr, size) do { \
216 (d)->segs[(n) / 2].w2 |= \
217 htole32(((addr) & 0xffff) << 16); \
218 (d)->segs[(n) / 2].w3 = \
219 htole32((((addr) >> 16) & 0xffff) | (size) << 20); \
221 (d)->segs[(n) / 2].w1 = htole32(addr); \
222 (d)->segs[(n) / 2].w2 = htole32((size) << 4); \
229 #define IWN_UC_READY 1
230 #define IWN_ADD_NODE_DONE 24
231 #define IWN_TX_DONE 28
232 #define IWN_START_SCAN 130
233 #define IWN_STOP_SCAN 132
234 #define IWN_RX_STATISTICS 156
235 #define IWN_BEACON_STATISTICS 157
236 #define IWN_STATE_CHANGED 161
237 #define IWN_BEACON_MISSED 162
238 #define IWN_AMPDU_RX_START 192
239 #define IWN_AMPDU_RX_DONE 193
240 #define IWN_RX_DONE 195
247 /* possible Rx status flags */
248 #define IWN_RX_NO_CRC_ERR (1 << 0)
249 #define IWN_RX_NO_OVFL_ERR (1 << 1)
250 /* shortcut for the above */
251 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
255 #define IWN_CMD_CONFIGURE 0x10 /* REPLY_RXON */
256 #define IWN_CMD_ASSOCIATE 0x11 /* REPLY_RXON_ASSOC */
257 #define IWN_CMD_EDCA_PARAMS 0x13 /* REPLY_QOS_PARAM */
258 #define IWN_CMD_TSF 0x14 /* REPLY_RXON_TIMING */
259 #define IWN_CMD_ADD_NODE 0x18 /* REPLY_ADD_STA */
260 #define IWN_CMD_TX_DATA 0x1c /* REPLY_TX */
261 #define IWN_CMD_TX_LINK_QUALITY 0x4e /* REPLY_TX_LINK_QUALITY_CMD */
262 #define IWN_CMD_SET_LED 0x48 /* REPLY_LEDS_CMD */
263 #define IWN_CMD_SET_POWER_MODE 0x77 /* POWER_TABLE_CMD */
264 #define IWN_CMD_SCAN 0x80 /* REPLY_SCAN_CMD */
265 #define IWN_CMD_TXPOWER 0x97 /* REPLY_TX_PWR_TABLE_CMD */
266 #define IWN_CMD_BLUETOOTH 0x9b /* REPLY_BT_CONFIG */
267 #define IWN_CMD_GET_STATISTICS 0x9c /* REPLY_STATISTICS_CMD */
268 #define IWN_CMD_SET_CRITICAL_TEMP 0xa4 /* REPLY_CT_KILL_CONFIG_CMD */
269 #define IWN_SENSITIVITY 0xa8 /* SENSITIVITY_CMD */
270 #define IWN_PHY_CALIB 0xb0 /* REPLY_PHY_CALIBRATION_CMD */
277 /* structure for command IWN_CMD_CONFIGURE (aka RXON) */
279 uint8_t myaddr[IEEE80211_ADDR_LEN];
281 uint8_t bssid[IEEE80211_ADDR_LEN];
283 uint8_t wlap[IEEE80211_ADDR_LEN];
286 #define IWN_MODE_HOSTAP 1
287 #define IWN_MODE_STA 3
288 #define IWN_MODE_IBSS 4
289 #define IWN_MODE_MONITOR 6
290 uint8_t unused4; /* air propagation */
292 #define IWN_RXCHAIN_VALID 0x000e /* which antennae are valid */
293 #define IWN_RXCHAIN_VALID_S 1
294 #define IWN_RXCHAIN_FORCE 0x0070
295 #define IWN_RXCHAIN_FORCE_S 4
296 #define IWN_RXCHAIN_FORCE_MIMO 0x0380
297 #define IWN_RXCHAIN_FORCE_MIMO_S 7
298 #define IWN_RXCHAIN_CNT 0x0c00
299 #define IWN_RXCHAIN_CNT_S 10
300 #define IWN_RXCHAIN_MIMO_CNT 0x3000
301 #define IWN_RXCHAIN_MIMO_CNT_S 12
302 #define IWN_RXCHAIN_MIMO_FORCE 0x4000
303 #define IWN_RXCHAIN_MIMO_FORCE_S 14
304 uint8_t ofdm_mask; /* basic rates */
305 uint8_t cck_mask; /* basic rates */
308 #define IWN_CONFIG_24GHZ 0x00000001 /* band */
309 #define IWN_CONFIG_CCK 0x00000002 /* modulation */
310 #define IWN_CONFIG_AUTO 0x00000004 /* 2.4-only auto-detect */
311 #define IWN_CONFIG_HTPROT 0x00000008 /* xmit with HT protection */
312 #define IWN_CONFIG_SHSLOT 0x00000010 /* short slot time */
313 #define IWN_CONFIG_SHPREAMBLE 0x00000020 /* short premable */
314 #define IWN_CONFIG_NODIVERSITY 0x00000080 /* disable antenna diversity */
315 #define IWN_CONFIG_ANTENNA_A 0x00000100
316 #define IWN_CONFIG_ANTENNA_B 0x00000200
317 #define IWN_CONFIG_RADAR 0x00001000 /* enable radar detect */
318 #define IWN_CONFIG_NARROW 0x00002000 /* MKK narrow band select */
319 #define IWN_CONFIG_TSF 0x00008000
320 #define IWN_CONFIG_HT 0x06400000
321 #define IWN_CONFIG_HT20 0x02000000
322 #define IWN_CONFIG_HT40U 0x04000000
323 #define IWN_CONFIG_HT40D 0x04400000
325 #define IWN_FILTER_PROMISC (1 << 0) /* pass all data frames */
326 #define IWN_FILTER_CTL (1 << 1) /* pass ctl+mgt frames */
327 #define IWN_FILTER_MULTICAST (1 << 2) /* pass multi-cast frames */
328 #define IWN_FILTER_NODECRYPT (1 << 3) /* pass unicast undecrypted */
329 #define IWN_FILTER_BSS (1 << 5) /* station is associated */
330 #define IWN_FILTER_ALLBEACONS (1 << 6) /* pass overlapping bss beacons
331 (must be associated) */
332 uint16_t chan; /* IEEE channel # of control/primary */
333 uint8_t ht_single_mask; /* single-stream basic rates */
334 uint8_t ht_dual_mask; /* dual-stream basic rates */
337 /* structure for command IWN_CMD_ASSOCIATE */
346 /* structure for command IWN_CMD_EDCA_PARAMS */
347 struct iwn_edca_params {
349 #define IWN_EDCA_UPDATE (1 << 0)
350 #define IWN_EDCA_TXOP (1 << 4)
358 } __packed ac[EDCA_NUM_AC];
361 /* structure for command IWN_CMD_TSF */
371 /* structure for command IWN_CMD_ADD_NODE */
372 struct iwn_node_info {
374 #define IWN_NODE_UPDATE (1 << 0)
375 uint8_t reserved1[3];
376 uint8_t macaddr[IEEE80211_ADDR_LEN];
380 #define IWN_ID_BROADCAST 31
382 #define IWN_FLAG_SET_KEY (1 << 0)
385 uint8_t tsc2; /* TKIP TSC2 */
389 uint8_t key[IEEE80211_KEYBUF_SIZE];
391 #define IWN_MAXRXAMPDU_S 19
392 #define IWN_MPDUDENSITY_S 23
395 uint8_t rate; /* legacy rate/MCS */
396 #define IWN_RATE_MCS 0x08 /* or'd to indicate MCS */
398 #define IWN_RFLAG_HT (1 << 0) /* use HT modulation */
399 #define IWN_RFLAG_CCK (1 << 1) /* use CCK modulation */
400 #define IWN_RFLAG_HT40 (1 << 3) /* use dual-stream */
401 #define IWN_RFLAG_SGI (1 << 5) /* use short GI */
402 #define IWN_RFLAG_ANT_A (1 << 6) /* start on antenna port A */
403 #define IWN_RFLAG_ANT_B (1 << 7) /* start on antenna port B */
406 uint16_t add_imm_start;
410 /* structure for command IWN_CMD_TX_DATA */
411 struct iwn_cmd_data {
415 #define IWN_TX_NEED_RTS (1 << 1)
416 #define IWN_TX_NEED_CTS (1 << 2)
417 #define IWN_TX_NEED_ACK (1 << 3)
418 #define IWN_TX_USE_NODE_RATE (1 << 4)
419 #define IWN_TX_FULL_TXOP (1 << 7)
420 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
421 #define IWN_TX_AUTO_SEQ (1 << 13)
422 #define IWN_TX_INSERT_TSTAMP (1 << 16)
423 #define IWN_TX_NEED_PADDING (1 << 20)
433 #define IWN_CIPHER_WEP40 1
434 #define IWN_CIPHER_CCMP 2
435 #define IWN_CIPHER_TKIP 3
436 #define IWN_CIPHER_WEP104 9
440 uint8_t key[IEEE80211_KEYBUF_SIZE];
444 #define IWN_LIFETIME_INFINITE 0xffffffff
455 /* structure for command IWN_CMD_TX_LINK_QUALITY */
456 #define IWN_MAX_TX_RETRIES 16
457 struct iwn_cmd_link_quality {
462 uint8_t mimo; /* MIMO delimiter */
463 uint8_t ssmask; /* single stream antenna mask */
464 uint8_t dsmask; /* dual stream antenna mask */
465 uint8_t ridx[EDCA_NUM_AC];/* starting rate index */
466 uint16_t ampdu_limit; /* tx aggregation time limit */
467 uint8_t ampdu_disable;
468 uint8_t ampdu_max; /* frame count limit */
472 #define IWN_RATE_CCK1 0
473 #define IWN_RATE_CCK11 3
474 #define IWN_RATE_OFDM6 4
475 #define IWN_RATE_OFDM54 11
478 } table[IWN_MAX_TX_RETRIES];
482 /* structure for command IWN_CMD_SET_LED */
484 uint32_t unit; /* multiplier (in usecs) */
486 #define IWN_LED_ACTIVITY 1
487 #define IWN_LED_LINK 2
494 /* structure for command IWN_CMD_SET_POWER_MODE */
497 #define IWN_POWER_CAM 0 /* constantly awake mode */
507 /* structures for command IWN_CMD_SCAN */
508 struct iwn_scan_essid {
511 uint8_t data[IEEE80211_NWID_LEN];
514 struct iwn_scan_hdr {
519 uint16_t plcp_threshold;
520 uint16_t crc_threshold;
522 uint32_t max_svc; /* background scans */
523 uint32_t pause_svc; /* background scans */
527 /* followed by a struct iwn_cmd_data */
528 /* followed by an array of 4x struct iwn_scan_essid */
529 /* followed by probe request body */
530 /* followed by nchan x struct iwn_scan_chan */
533 struct iwn_scan_chan {
535 #define IWN_CHAN_ACTIVE (1 << 0)
536 #define IWN_CHAN_DIRECT (1 << 1)
541 uint16_t active; /* msecs */
542 uint16_t passive; /* msecs */
545 /* structure for command IWN_CMD_TXPOWER */
546 #define IWN_RIDX_MAX 32
547 struct iwn_cmd_txpower {
553 uint8_t rf_gain[IWN_NTXCHAINS];
554 uint8_t dsp_gain[IWN_NTXCHAINS];
555 } power[IWN_RIDX_MAX + 1];
558 /* structure for command IWN_CMD_BLUETOOTH */
559 struct iwn_bluetooth {
568 /* structure for command IWN_CMD_SET_CRITICAL_TEMP */
569 struct iwn_critical_temp {
573 /* degK <-> degC conversion macros */
574 #define IWN_CTOK(c) ((c) + 273)
575 #define IWN_KTOC(k) ((k) - 273)
576 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
579 /* structure for command IWN_SENSITIVITY */
580 struct iwn_sensitivity_cmd {
582 #define IWN_SENSITIVITY_DEFAULTTBL 0
583 #define IWN_SENSITIVITY_WORKTBL 1
586 uint16_t energy_ofdm;
587 uint16_t corr_ofdm_x1;
588 uint16_t corr_ofdm_mrc_x1;
589 uint16_t corr_cck_mrc_x4;
590 uint16_t corr_ofdm_x4;
591 uint16_t corr_ofdm_mrc_x4;
592 uint16_t corr_barker;
593 uint16_t corr_barker_mrc;
594 uint16_t corr_cck_x4;
595 uint16_t energy_ofdm_th;
598 /* structure for command IWN_PHY_CALIB */
599 struct iwn_phy_calib_cmd {
601 #define IWN_SET_DIFF_GAIN 7
606 #define IWN_GAIN_SET (1 << 2)
612 /* structure for IWN_UC_READY notification */
613 #define IWN_NATTEN_GROUPS 5
614 struct iwn_ucode_info {
621 #define IWN_UCODE_RUNTIME 0
622 #define IWN_UCODE_INIT 9
630 /* the following fields are for UCODE_INIT only */
636 int32_t atten[IWN_NATTEN_GROUPS][IWN_NTXCHAINS];
639 /* structure for IWN_TX_DONE notification */
652 #define IWN_TX_SUCCESS 0x00
653 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */
654 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
655 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
656 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
657 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
658 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
661 /* structure for IWN_BEACON_MISSED notification */
662 struct iwn_beacon_missed {
663 uint32_t consecutive;
669 /* structure for IWN_AMPDU_RX_DONE notification */
670 struct iwn_rx_ampdu {
675 /* structure for IWN_RX_DONE and IWN_AMPDU_RX_START notifications */
679 #define IWN_STAT_MAXLEN 20
690 #define IWN_RSSI_TO_DBM 44
692 uint8_t reserved2[22];
700 /* structure for IWN_START_SCAN notification */
701 struct iwn_start_scan {
710 /* structure for IWN_STOP_SCAN notification */
711 struct iwn_stop_scan {
719 /* structure for IWN_{RX,BEACON}_STATISTICS notification */
720 struct iwn_rx_phy_stats {
729 uint32_t bad_fina_sync;
730 uint32_t sfd_timeout;
731 uint32_t fina_timeout;
743 struct iwn_rx_general_stats {
750 uint32_t missed_beacons;
751 uint32_t adc_saturated; /* time in 0.8us */
752 uint32_t ina_searched; /* time in 0.8us */
761 struct iwn_rx_ht_phy_stats {
768 uint32_t good_ampdu_crc32;
774 struct iwn_rx_stats {
775 struct iwn_rx_phy_stats ofdm;
776 struct iwn_rx_phy_stats cck;
777 struct iwn_rx_general_stats general;
778 struct iwn_rx_ht_phy_stats ht;
781 struct iwn_tx_stats {
783 uint32_t rx_detected;
787 uint32_t cts_timeout;
788 uint32_t ack_timeout;
794 uint32_t cts_collision;
795 uint32_t ack_collision;
798 uint32_t query_ampdu;
800 uint32_t query_ampdu_frag;
801 uint32_t query_mismatch;
806 uint32_t reserved[2];
809 struct iwn_general_stats {
812 uint32_t burst_check;
814 uint32_t reserved1[4];
823 uint32_t reserved2[2];
825 uint32_t reserved3[3];
830 struct iwn_rx_stats rx;
831 struct iwn_tx_stats tx;
832 struct iwn_general_stats general;
836 /* firmware image header */
837 struct iwn_firmware_hdr {
839 uint32_t main_textsz;
840 uint32_t main_datasz;
841 uint32_t init_textsz;
842 uint32_t init_datasz;
843 uint32_t boot_textsz;
846 #define IWN_FW_MAIN_TEXT_MAXSZ (96 * 1024)
847 #define IWN_FW_MAIN_DATA_MAXSZ (40 * 1024)
848 #define IWN_FW_INIT_TEXT_MAXSZ (96 * 1024)
849 #define IWN_FW_INIT_DATA_MAXSZ (40 * 1024)
850 #define IWN_FW_BOOT_TEXT_MAXSZ 1024
854 * Offsets into EEPROM.
856 #define IWN_EEPROM_MAC 0x015
857 #define IWN_EEPROM_DOMAIN 0x060
858 #define IWN_EEPROM_BAND1 0x063
859 #define IWN_EEPROM_BAND2 0x072
860 #define IWN_EEPROM_BAND3 0x080
861 #define IWN_EEPROM_BAND4 0x08d
862 #define IWN_EEPROM_BAND5 0x099
863 #define IWN_EEPROM_BAND6 0x0a0
864 #define IWN_EEPROM_BAND7 0x0a8
865 #define IWN_EEPROM_MAXPOW 0x0e8
866 #define IWN_EEPROM_VOLTAGE 0x0e9
867 #define IWN_EEPROM_BANDS 0x0ea
869 struct iwn_eeprom_chan {
871 #define IWN_EEPROM_CHAN_VALID (1 << 0)
872 #define IWN_EEPROM_CHAN_IBSS (1 << 1) /* adhoc permitted */
873 /* NB: bit 2 is reserved */
874 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) /* active/passive scan */
875 #define IWN_EEPROM_CHAN_RADAR (1 << 4) /* DFS required */
876 #define IWN_EEPROM_CHAN_WIDE (1 << 5) /* HT40 */
877 #define IWN_EEPROM_CHAN_NARROW (1 << 6) /* HT20 */
882 #define IWN_NSAMPLES 3
883 struct iwn_eeprom_chan_samples {
890 } samples[IWN_NTXCHAINS][IWN_NSAMPLES];
894 struct iwn_eeprom_band {
895 uint8_t lo; /* low channel number */
896 uint8_t hi; /* high channel number */
897 struct iwn_eeprom_chan_samples chans[2];
900 #define IWN_MAX_PWR_INDEX 107
903 * RF Tx gain values from highest to lowest power (values obtained from
904 * the reference driver.)
906 static const uint8_t iwn_rf_gain_2ghz[IWN_MAX_PWR_INDEX + 1] = {
907 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
908 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
909 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
910 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
911 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
912 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
913 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
914 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
916 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
919 static const uint8_t iwn_rf_gain_5ghz[IWN_MAX_PWR_INDEX + 1] = {
920 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
921 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
922 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
923 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
924 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
925 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
926 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
927 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
928 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
929 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
933 * DSP pre-DAC gain values from highest to lowest power (values obtained
934 * from the reference driver.)
936 static const uint8_t iwn_dsp_gain_2ghz[IWN_MAX_PWR_INDEX + 1] = {
937 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
938 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
939 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
940 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
941 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
942 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
943 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
944 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
945 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
946 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
949 static const uint8_t iwn_dsp_gain_5ghz[IWN_MAX_PWR_INDEX + 1] = {
950 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
951 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
952 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
953 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
954 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
955 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
956 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
957 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
958 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
959 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
962 #define IWN_READ(sc, reg) \
963 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
965 #define IWN_WRITE(sc, reg, val) \
966 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
968 #define IWN_WRITE_REGION_4(sc, offset, datap, count) \
969 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \