2 * Copyright (c) 2007 Bruce M. Simpson.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _SIBA_SIBAVAR_H_
30 #define _SIBA_SIBAVAR_H_
35 device_t sc_dev; /* Device ID */
36 struct resource *sc_mem; /* Memory window on nexus */
38 bus_space_tag_t sc_bt;
39 bus_space_handle_t sc_bh;
47 struct resource_list sdi_rl;
48 /*devhandle_t sdi_devhandle; XXX*/
49 /*struct rman sdi_intr_rman;*/
51 /* Accessors are needed for ivars below. */
55 uint8_t sdi_idx; /* core index on bus */
56 uint8_t sdi_irq; /* TODO */
59 #define siba_read_2(sc, core, reg) \
60 bus_space_read_2((sc)->sc_bt, (sc)->sc_bh, \
61 (core * SIBA_CORE_LEN) + (reg))
63 #define siba_read_4(sc, core, reg) \
64 bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, \
65 (core * SIBA_CORE_LEN) + (reg))
67 #define siba_write_2(sc, core, reg, val) \
68 bus_space_write_2((sc)->sc_bt, (sc)->sc_bh, \
69 (core * SIBA_CORE_LEN) + (reg), (val))
71 #define siba_write_4(sc, core, reg, val) \
72 bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, \
73 (core * SIBA_CORE_LEN) + (reg), (val))
75 enum siba_device_ivars {
82 #define SIBA_ACCESSOR(var, ivar, type) \
83 __BUS_ACCESSOR(siba, var, SIBA, ivar, type)
85 SIBA_ACCESSOR(vendor, VENDOR, uint16_t)
86 SIBA_ACCESSOR(device, DEVICE, uint16_t)
87 SIBA_ACCESSOR(revid, REVID, uint8_t)
88 SIBA_ACCESSOR(core_index, CORE_INDEX, uint8_t)
92 #endif /* _SIBA_SIBAVAR_H_ */