2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
31 * that this driver still in its early stage, and possible of rewrite are
32 * pretty much guaranteed. There are supposedly several distinct parent/child
33 * busses to make this "perfect", but as for now and for the sake of
34 * simplicity, everything is gobble up within single source.
37 * 1) HDA Controller support
38 * 2) HDA Codecs support, which may include
42 * 3) Widget parser - the real magic of why this driver works on so
43 * many hardwares with minimal vendor specific quirk. The original
44 * parser was written using Ruby and can be found at
45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
46 * ruby parser take the verbose dmesg dump as its input. Refer to
47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
48 * interesting documents, especially UAA (Universal Audio Architecture).
49 * 4) Possible vendor specific support.
50 * (snd_hda_intel, snd_hda_ati, etc..)
52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
53 * Compaq V3000 with Conexant HDA.
55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
57 * * This driver is a collaborative effort made by: *
59 * * Stephane E. Potvin <sepotvin@videotron.ca> *
60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
61 * * Wesley Morgan <morganw@chemikals.org> *
62 * * Daniel Eischen <deischen@FreeBSD.org> *
63 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
64 * * Ariff Abdullah <ariff@FreeBSD.org> *
65 * * Alexander Motin <mav@FreeBSD.org> *
67 * * ....and various people from freebsd-multimedia@FreeBSD.org *
69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
72 #ifdef HAVE_KERNEL_OPTION_HEADERS
76 #include <dev/sound/pcm/sound.h>
77 #include <dev/pci/pcireg.h>
78 #include <dev/pci/pcivar.h>
80 #include <sys/ctype.h>
81 #include <sys/taskqueue.h>
83 #include <dev/sound/pci/hda/hdac_private.h>
84 #include <dev/sound/pci/hda/hdac_reg.h>
85 #include <dev/sound/pci/hda/hda_reg.h>
86 #include <dev/sound/pci/hda/hdac.h>
90 #define HDA_DRV_TEST_REV "20090624_0136"
92 SND_DECLARE_FILE("$FreeBSD$");
94 #define HDA_BOOTVERBOSE(stmt) do { \
95 if (bootverbose != 0 || snd_verbose > 3) { \
100 #define HDA_BOOTHVERBOSE(stmt) do { \
101 if (snd_verbose > 3) { \
107 #undef HDAC_INTR_EXTRA
108 #define HDAC_INTR_EXTRA 1
111 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
112 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
113 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
114 #define hdac_lockowned(sc) mtx_owned((sc)->lock)
116 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
117 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
118 (fl) == 0xffffffff || \
119 (((fl) & 0xffff0000) == 0xffff0000 && \
120 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
121 (((fl) & 0x0000ffff) == 0x0000ffff && \
122 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
123 #define HDA_MATCH_ALL 0xffffffff
124 #define HDAC_INVALID 0xffffffff
126 /* Default controller / jack sense poll: 250ms */
127 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
130 * Make room for possible 4096 playback/record channels, in 100 years to come.
132 #define HDAC_TRIGGER_NONE 0x00000000
133 #define HDAC_TRIGGER_PLAY 0x00000fff
134 #define HDAC_TRIGGER_REC 0x00fff000
135 #define HDAC_TRIGGER_UNSOL 0x80000000
137 #define HDA_MODEL_CONSTRUCT(vendor, model) \
138 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
140 /* Controller models */
143 #define INTEL_VENDORID 0x8086
144 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
145 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
146 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
147 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
148 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
149 #define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)
150 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)
151 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b)
152 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
155 #define NVIDIA_VENDORID 0x10de
156 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
157 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
158 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
159 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
160 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
161 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
162 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
163 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
164 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774)
165 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775)
166 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776)
167 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777)
168 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc)
169 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd)
170 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0)
171 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1)
172 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2)
173 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3)
174 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
177 #define ATI_VENDORID 0x1002
178 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
179 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
180 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b)
181 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919)
182 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f)
183 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00)
184 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08)
185 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10)
186 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18)
187 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20)
188 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28)
189 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30)
190 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38)
191 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40)
192 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48)
193 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
196 #define VIA_VENDORID 0x1106
197 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
198 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
201 #define SIS_VENDORID 0x1039
202 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
203 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
206 #define ULI_VENDORID 0x10b9
207 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461)
208 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff)
213 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
216 #define HP_VENDORID 0x103c
217 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
218 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
219 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
220 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
221 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
222 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
223 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
224 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801)
225 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802)
226 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
227 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
228 #define HP_NX6325_SUBVENDORX 0x103c30b0
231 #define DELL_VENDORID 0x1028
232 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9)
233 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
234 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227)
235 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228)
236 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
237 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
238 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
239 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
242 #define CLEVO_VENDORID 0x1558
243 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
244 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
247 #define ACER_VENDORID 0x1025
248 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
249 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127)
250 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f)
251 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133)
252 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
253 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b)
254 #define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f)
255 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
258 #define ASUS_VENDORID 0x1043
259 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
260 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
261 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
262 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
263 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
264 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339)
265 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
266 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
267 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
268 #define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f)
269 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
270 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
271 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
272 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
273 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
274 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
275 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
278 #define IBM_VENDORID 0x1014
279 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
280 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
283 #define LENOVO_VENDORID 0x17aa
284 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
285 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e)
286 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
287 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
290 #define SAMSUNG_VENDORID 0x144d
291 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
292 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
295 #define MEDION_VENDORID 0x161f
296 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
297 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
299 /* Apple Computer Inc. */
300 #define APPLE_VENDORID 0x106b
301 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
304 #define SONY_VENDORID 0x104d
305 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc)
306 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff)
309 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
310 * instead of their own, which is beyond my comprehension
311 * (see HDA_CODEC_STAC9221 below).
313 #define APPLE_INTEL_MAC 0x76808384
316 #define LG_VENDORID 0x1854
317 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
318 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
320 /* Fujitsu Siemens */
321 #define FS_VENDORID 0x1734
322 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
323 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd)
324 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
326 /* Fujitsu Limited */
327 #define FL_VENDORID 0x10cf
328 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326)
329 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d)
330 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff)
333 #define TOSHIBA_VENDORID 0x1179
334 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
335 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
336 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
338 /* Micro-Star International (MSI) */
339 #define MSI_VENDORID 0x1462
340 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
341 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a)
342 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
344 /* Giga-Byte Technology */
345 #define GB_VENDORID 0x1458
346 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022)
347 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff)
350 #define UNIWILL_VENDORID 0x1584
351 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
352 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
355 /* Misc constants.. */
356 #define HDA_AMP_VOL_DEFAULT (-1)
357 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
358 #define HDA_AMP_MUTE_NONE (0)
359 #define HDA_AMP_MUTE_LEFT (1 << 0)
360 #define HDA_AMP_MUTE_RIGHT (1 << 1)
361 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
363 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
364 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
366 #define HDA_ADC_MONITOR (1 << 0)
368 #define HDA_CTL_OUT 1
371 #define HDA_GPIO_MAX 8
372 /* 0 - 7 = GPIO , 8 = Flush */
373 #define HDA_QUIRK_GPIO0 (1 << 0)
374 #define HDA_QUIRK_GPIO1 (1 << 1)
375 #define HDA_QUIRK_GPIO2 (1 << 2)
376 #define HDA_QUIRK_GPIO3 (1 << 3)
377 #define HDA_QUIRK_GPIO4 (1 << 4)
378 #define HDA_QUIRK_GPIO5 (1 << 5)
379 #define HDA_QUIRK_GPIO6 (1 << 6)
380 #define HDA_QUIRK_GPIO7 (1 << 7)
381 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
383 /* 9 - 25 = anything else */
384 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
385 #define HDA_QUIRK_FIXEDRATE (1 << 10)
386 #define HDA_QUIRK_FORCESTEREO (1 << 11)
387 #define HDA_QUIRK_EAPDINV (1 << 12)
388 #define HDA_QUIRK_DMAPOS (1 << 13)
389 #define HDA_QUIRK_SENSEINV (1 << 14)
391 /* 26 - 31 = vrefs */
392 #define HDA_QUIRK_IVREF50 (1 << 26)
393 #define HDA_QUIRK_IVREF80 (1 << 27)
394 #define HDA_QUIRK_IVREF100 (1 << 28)
395 #define HDA_QUIRK_OVREF50 (1 << 29)
396 #define HDA_QUIRK_OVREF80 (1 << 30)
397 #define HDA_QUIRK_OVREF100 (1 << 31)
399 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
401 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
403 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
405 #if __FreeBSD_version < 600000
406 #define taskqueue_drain(...)
409 static const struct {
412 } hdac_quirks_tab[] = {
413 { "gpio0", HDA_QUIRK_GPIO0 },
414 { "gpio1", HDA_QUIRK_GPIO1 },
415 { "gpio2", HDA_QUIRK_GPIO2 },
416 { "gpio3", HDA_QUIRK_GPIO3 },
417 { "gpio4", HDA_QUIRK_GPIO4 },
418 { "gpio5", HDA_QUIRK_GPIO5 },
419 { "gpio6", HDA_QUIRK_GPIO6 },
420 { "gpio7", HDA_QUIRK_GPIO7 },
421 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
422 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
423 { "fixedrate", HDA_QUIRK_FIXEDRATE },
424 { "forcestereo", HDA_QUIRK_FORCESTEREO },
425 { "eapdinv", HDA_QUIRK_EAPDINV },
426 { "dmapos", HDA_QUIRK_DMAPOS },
427 { "senseinv", HDA_QUIRK_SENSEINV },
428 { "ivref50", HDA_QUIRK_IVREF50 },
429 { "ivref80", HDA_QUIRK_IVREF80 },
430 { "ivref100", HDA_QUIRK_IVREF100 },
431 { "ovref50", HDA_QUIRK_OVREF50 },
432 { "ovref80", HDA_QUIRK_OVREF80 },
433 { "ovref100", HDA_QUIRK_OVREF100 },
434 { "ivref", HDA_QUIRK_IVREF },
435 { "ovref", HDA_QUIRK_OVREF },
436 { "vref", HDA_QUIRK_VREF },
438 #define HDAC_QUIRKS_TAB_LEN \
439 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
441 #define HDA_BDL_MIN 2
442 #define HDA_BDL_MAX 256
443 #define HDA_BDL_DEFAULT HDA_BDL_MIN
445 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
446 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
448 #define HDA_BUFSZ_MIN 4096
449 #define HDA_BUFSZ_MAX 65536
450 #define HDA_BUFSZ_DEFAULT 16384
452 #define HDA_PARSE_MAXDEPTH 10
454 #define HDAC_UNSOLTAG_EVENT_HP 0x00
456 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
458 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red",
459 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D",
462 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD",
463 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in",
464 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"};
466 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"};
469 static uint32_t hdac_fmt[] = {
470 SND_FORMAT(AFMT_S16_LE, 2, 0),
474 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
476 #define HDAC_NO_MSI 1
477 #define HDAC_NO_64BIT 2
479 static const struct {
484 { HDA_INTEL_82801F, "Intel 82801F", 0 },
485 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 },
486 { HDA_INTEL_82801G, "Intel 82801G", 0 },
487 { HDA_INTEL_82801H, "Intel 82801H", 0 },
488 { HDA_INTEL_82801I, "Intel 82801I", 0 },
489 { HDA_INTEL_82801J, "Intel 82801J", 0 },
490 { HDA_INTEL_PCH, "Intel PCH", 0 },
491 { HDA_INTEL_SCH, "Intel SCH", 0 },
492 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI },
493 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI },
494 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 },
495 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 },
496 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 },
497 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 },
498 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 },
499 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 },
500 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 },
501 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 },
502 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT },
503 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT },
504 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT },
505 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT },
506 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 },
507 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 },
508 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 },
509 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 },
510 { HDA_ATI_SB450, "ATI SB450", 0 },
511 { HDA_ATI_SB600, "ATI SB600", 0 },
512 { HDA_ATI_RS600, "ATI RS600", 0 },
513 { HDA_ATI_RS690, "ATI RS690", 0 },
514 { HDA_ATI_RS780, "ATI RS780", 0 },
515 { HDA_ATI_R600, "ATI R600", 0 },
516 { HDA_ATI_RV610, "ATI RV610", 0 },
517 { HDA_ATI_RV620, "ATI RV620", 0 },
518 { HDA_ATI_RV630, "ATI RV630", 0 },
519 { HDA_ATI_RV635, "ATI RV635", 0 },
520 { HDA_ATI_RV710, "ATI RV710", 0 },
521 { HDA_ATI_RV730, "ATI RV730", 0 },
522 { HDA_ATI_RV740, "ATI RV740", 0 },
523 { HDA_ATI_RV770, "ATI RV770", 0 },
524 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 },
525 { HDA_SIS_966, "SiS 966", 0 },
526 { HDA_ULI_M5461, "ULI M5461", 0 },
528 { HDA_INTEL_ALL, "Intel (Unknown)" },
529 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
530 { HDA_ATI_ALL, "ATI (Unknown)" },
531 { HDA_VIA_ALL, "VIA (Unknown)" },
532 { HDA_SIS_ALL, "SiS (Unknown)" },
533 { HDA_ULI_ALL, "ULI (Unknown)" },
535 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
537 static const struct {
542 } hdac_pcie_snoop[] = {
543 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
544 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
545 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
547 #define HDAC_PCIESNOOP_LEN \
548 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
550 static const struct {
557 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
558 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
559 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
560 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
561 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
562 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
563 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
564 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
565 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
566 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
567 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
568 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
569 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
570 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
571 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
572 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
573 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
574 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
575 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
576 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
577 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
578 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
579 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
580 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
581 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
582 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
583 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
584 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
585 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
586 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
587 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
588 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
589 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
590 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
591 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
593 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
595 /* All codecs you can eat... */
596 #define HDA_CODEC_CONSTRUCT(vendor, id) \
597 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
600 #define REALTEK_VENDORID 0x10ec
601 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
602 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
603 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267)
604 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
605 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269)
606 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272)
607 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
608 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662)
609 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663)
610 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
611 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
612 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
613 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
614 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
615 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
616 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
617 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889)
618 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
621 #define ANALOGDEVICES_VENDORID 0x11d4
622 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a)
623 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882)
624 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883)
625 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884)
626 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a)
627 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b)
628 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
629 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
630 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)
631 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
632 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987)
633 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
634 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
635 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a)
636 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b)
637 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
640 #define CMEDIA_VENDORID 0x434d
641 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
642 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
645 #define SIGMATEL_VENDORID 0x8384
646 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)
647 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)
648 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614)
649 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615)
650 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616)
651 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617)
652 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
653 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619)
654 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620)
655 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621)
656 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622)
657 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623)
658 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624)
659 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625)
660 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626)
661 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
662 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628)
663 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629)
664 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634)
665 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636)
666 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638)
667 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639)
668 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645)
669 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646)
670 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662)
671 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
672 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
673 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682)
674 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
675 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
676 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691)
677 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698)
678 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699)
679 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0)
680 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1)
681 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2)
682 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3)
683 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880)
684 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882)
685 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
688 #define IDT_VENDORID 0x111d
689 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603)
690 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604)
691 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605)
692 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608)
693 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674)
694 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675)
695 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676)
696 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0)
697 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2)
698 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6)
699 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4)
700 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5)
701 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff)
704 #define SII_VENDORID 0x1095
705 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390)
706 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)
707 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)
710 #define AGERE_VENDORID 0x11c1
711 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)
714 #define CONEXANT_VENDORID 0x14f1
715 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
716 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
717 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051)
718 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
721 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
722 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
723 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
724 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
725 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
726 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
727 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
728 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
729 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
730 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
731 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
732 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
733 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720)
734 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721)
735 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722)
736 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723)
737 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724)
738 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725)
739 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726)
740 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727)
741 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397)
742 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397)
743 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397)
744 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397)
745 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397)
746 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397)
747 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397)
748 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397)
749 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398)
750 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398)
751 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398)
752 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398)
753 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398)
754 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398)
755 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398)
756 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398)
757 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
760 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c)
761 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919)
762 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a)
763 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01)
764 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff)
767 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002)
768 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006)
769 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007)
770 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067)
771 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001)
772 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff)
775 #define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801)
776 #define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802)
777 #define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803)
778 #define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)
779 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff)
782 static const struct {
786 { HDA_CODEC_ALC260, "Realtek ALC260" },
787 { HDA_CODEC_ALC262, "Realtek ALC262" },
788 { HDA_CODEC_ALC267, "Realtek ALC267" },
789 { HDA_CODEC_ALC268, "Realtek ALC268" },
790 { HDA_CODEC_ALC269, "Realtek ALC269" },
791 { HDA_CODEC_ALC272, "Realtek ALC272" },
792 { HDA_CODEC_ALC660, "Realtek ALC660" },
793 { HDA_CODEC_ALC662, "Realtek ALC662" },
794 { HDA_CODEC_ALC663, "Realtek ALC663" },
795 { HDA_CODEC_ALC861, "Realtek ALC861" },
796 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
797 { HDA_CODEC_ALC880, "Realtek ALC880" },
798 { HDA_CODEC_ALC882, "Realtek ALC882" },
799 { HDA_CODEC_ALC883, "Realtek ALC883" },
800 { HDA_CODEC_ALC885, "Realtek ALC885" },
801 { HDA_CODEC_ALC888, "Realtek ALC888" },
802 { HDA_CODEC_ALC889, "Realtek ALC889" },
803 { HDA_CODEC_AD1882, "Analog Devices AD1882" },
804 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" },
805 { HDA_CODEC_AD1883, "Analog Devices AD1883" },
806 { HDA_CODEC_AD1884, "Analog Devices AD1884" },
807 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" },
808 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
809 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
810 { HDA_CODEC_AD1984, "Analog Devices AD1984" },
811 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" },
812 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" },
813 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
814 { HDA_CODEC_AD1987, "Analog Devices AD1987" },
815 { HDA_CODEC_AD1988, "Analog Devices AD1988A" },
816 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
817 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" },
818 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
819 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" },
820 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" },
821 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" },
822 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" },
823 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" },
824 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
825 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" },
826 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" },
827 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
828 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" },
829 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
830 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
831 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" },
832 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" },
833 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" },
834 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" },
835 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" },
836 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" },
837 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" },
838 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" },
839 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" },
840 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" },
841 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" },
842 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
843 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" },
844 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" },
845 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" },
846 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" },
847 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" },
848 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" },
849 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" },
850 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" },
851 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" },
852 { HDA_CODEC_IDT92HD005, "IDT 92HD005" },
853 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" },
854 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" },
855 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" },
856 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" },
857 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" },
858 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" },
859 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" },
860 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" },
861 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" },
862 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" },
863 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" },
864 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" },
865 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" },
866 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" },
867 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" },
868 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" },
869 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" },
870 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" },
871 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" },
872 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" },
873 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
874 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
875 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
876 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
877 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
878 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
879 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
880 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
881 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
882 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
883 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
884 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
885 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" },
886 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" },
887 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" },
888 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" },
889 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" },
890 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" },
891 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" },
892 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" },
893 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" },
894 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" },
895 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" },
896 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" },
897 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" },
898 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" },
899 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" },
900 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" },
901 { HDA_CODEC_VT1702_0, "VIA VT1702_0" },
902 { HDA_CODEC_VT1702_1, "VIA VT1702_1" },
903 { HDA_CODEC_VT1702_2, "VIA VT1702_2" },
904 { HDA_CODEC_VT1702_3, "VIA VT1702_3" },
905 { HDA_CODEC_VT1702_4, "VIA VT1702_4" },
906 { HDA_CODEC_VT1702_5, "VIA VT1702_5" },
907 { HDA_CODEC_VT1702_6, "VIA VT1702_6" },
908 { HDA_CODEC_VT1702_7, "VIA VT1702_7" },
909 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" },
910 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" },
911 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" },
912 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" },
913 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" },
914 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" },
915 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" },
916 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" },
917 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" },
918 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" },
919 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" },
920 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" },
921 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" },
922 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" },
923 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" },
925 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
926 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
927 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
928 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
929 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" },
930 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" },
931 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
932 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
933 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" },
934 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" },
935 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" },
936 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" },
938 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
941 /****************************************************************************
942 * Function prototypes
943 ****************************************************************************/
944 static void hdac_intr_handler(void *);
945 static int hdac_reset(struct hdac_softc *, int);
946 static int hdac_get_capabilities(struct hdac_softc *);
947 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
948 static int hdac_dma_alloc(struct hdac_softc *,
949 struct hdac_dma *, bus_size_t);
950 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
951 static int hdac_mem_alloc(struct hdac_softc *);
952 static void hdac_mem_free(struct hdac_softc *);
953 static int hdac_irq_alloc(struct hdac_softc *);
954 static void hdac_irq_free(struct hdac_softc *);
955 static void hdac_corb_init(struct hdac_softc *);
956 static void hdac_rirb_init(struct hdac_softc *);
957 static void hdac_corb_start(struct hdac_softc *);
958 static void hdac_rirb_start(struct hdac_softc *);
959 static void hdac_scan_codecs(struct hdac_softc *);
960 static void hdac_probe_codec(struct hdac_codec *);
961 static void hdac_probe_function(struct hdac_codec *, nid_t);
962 static int hdac_pcmchannel_setup(struct hdac_chan *);
964 static void hdac_attach2(void *);
966 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
968 static void hdac_command_send_internal(struct hdac_softc *,
969 struct hdac_command_list *, int);
971 static int hdac_probe(device_t);
972 static int hdac_attach(device_t);
973 static int hdac_detach(device_t);
974 static int hdac_suspend(device_t);
975 static int hdac_resume(device_t);
976 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
977 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
979 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
980 nid_t, int, int, int);
981 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
982 nid_t, nid_t, int, int, int, int, int, int);
983 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
985 static int hdac_rirb_flush(struct hdac_softc *sc);
986 static int hdac_unsolq_flush(struct hdac_softc *sc);
988 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf);
990 #define hdac_command(a1, a2, a3) \
991 hdac_command_sendone_internal(a1, a2, a3)
993 #define hdac_codec_id(c) \
994 ((uint32_t)((c == NULL) ? 0x00000000 : \
995 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \
996 ((uint32_t)(c)->device_id & 0x0000ffff))))
999 hdac_codec_name(struct hdac_codec *codec)
1004 id = hdac_codec_id(codec);
1006 for (i = 0; i < HDAC_CODECS_LEN; i++) {
1007 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
1008 return (hdac_codecs[i].name);
1011 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
1015 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
1017 static char *ossname[] = SOUND_DEVICE_NAMES;
1021 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1022 if (mask & (1 << i)) {
1024 strlcat(buf, ", ", len);
1025 strlcat(buf, ossname[i], len);
1032 static struct hdac_audio_ctl *
1033 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
1035 if (devinfo == NULL ||
1036 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
1037 index == NULL || devinfo->function.audio.ctl == NULL ||
1038 devinfo->function.audio.ctlcnt < 1 ||
1039 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
1041 return (&devinfo->function.audio.ctl[(*index)++]);
1044 static struct hdac_audio_ctl *
1045 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir,
1048 struct hdac_audio_ctl *ctl;
1051 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
1055 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
1056 if (ctl->enable == 0)
1058 if (ctl->widget->nid != nid)
1060 if (dir && ctl->ndir != dir)
1062 if (index >= 0 && ctl->ndir == HDA_CTL_IN &&
1063 ctl->dir == ctl->ndir && ctl->index != index)
1066 if (found == cnt || cnt <= 0)
1074 * Jack detection (Speaker/HP redirection) event handler.
1077 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
1079 struct hdac_audio_as *as;
1080 struct hdac_softc *sc;
1081 struct hdac_widget *w;
1082 struct hdac_audio_ctl *ctl;
1087 if (devinfo == NULL || devinfo->codec == NULL ||
1088 devinfo->codec->sc == NULL)
1091 sc = devinfo->codec->sc;
1092 cad = devinfo->codec->cad;
1093 as = devinfo->function.audio.as;
1094 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
1095 if (as[i].hpredir < 0)
1098 w = hdac_widget_get(devinfo, as[i].pins[15]);
1099 if (w == NULL || w->enable == 0 || w->type !=
1100 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1103 res = hdac_command(sc,
1104 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad);
1107 device_printf(sc->dev,
1108 "Pin sense: nid=%d res=0x%08x\n",
1109 as[i].pins[15], res);
1112 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
1113 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV)
1116 /* (Un)Mute headphone pin. */
1117 ctl = hdac_audio_ctl_amp_get(devinfo,
1118 as[i].pins[15], HDA_CTL_IN, -1, 1);
1119 if (ctl != NULL && ctl->mute) {
1120 /* If pin has muter - use it. */
1121 val = (res != 0) ? 0 : 1;
1122 if (val != ctl->forcemute) {
1123 ctl->forcemute = val;
1124 hdac_audio_ctl_amp_set(ctl,
1125 HDA_AMP_MUTE_DEFAULT,
1126 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
1129 /* If there is no muter - disable pin output. */
1130 w = hdac_widget_get(devinfo, as[i].pins[15]);
1131 if (w != NULL && w->type ==
1132 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1134 val = w->wclass.pin.ctrl |
1135 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1137 val = w->wclass.pin.ctrl &
1138 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1139 if (val != w->wclass.pin.ctrl) {
1140 w->wclass.pin.ctrl = val;
1142 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1143 w->nid, w->wclass.pin.ctrl), cad);
1147 /* (Un)Mute other pins. */
1148 for (j = 0; j < 15; j++) {
1149 if (as[i].pins[j] <= 0)
1151 ctl = hdac_audio_ctl_amp_get(devinfo,
1152 as[i].pins[j], HDA_CTL_IN, -1, 1);
1153 if (ctl != NULL && ctl->mute) {
1154 /* If pin has muter - use it. */
1155 val = (res != 0) ? 1 : 0;
1156 if (val == ctl->forcemute)
1158 ctl->forcemute = val;
1159 hdac_audio_ctl_amp_set(ctl,
1160 HDA_AMP_MUTE_DEFAULT,
1161 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
1164 /* If there is no muter - disable pin output. */
1165 w = hdac_widget_get(devinfo, as[i].pins[j]);
1166 if (w != NULL && w->type ==
1167 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1169 val = w->wclass.pin.ctrl &
1170 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1172 val = w->wclass.pin.ctrl |
1173 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1174 if (val != w->wclass.pin.ctrl) {
1175 w->wclass.pin.ctrl = val;
1177 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1178 w->nid, w->wclass.pin.ctrl), cad);
1186 * Callback for poll based jack detection.
1189 hdac_jack_poll_callback(void *arg)
1191 struct hdac_devinfo *devinfo = arg;
1192 struct hdac_softc *sc;
1194 if (devinfo == NULL || devinfo->codec == NULL ||
1195 devinfo->codec->sc == NULL)
1197 sc = devinfo->codec->sc;
1199 if (sc->poll_ival == 0) {
1203 hdac_hp_switch_handler(devinfo);
1204 callout_reset(&sc->poll_jack, sc->poll_ival,
1205 hdac_jack_poll_callback, devinfo);
1210 * Jack detection initializer.
1213 hdac_hp_switch_init(struct hdac_devinfo *devinfo)
1215 struct hdac_softc *sc = devinfo->codec->sc;
1216 struct hdac_audio_as *as = devinfo->function.audio.as;
1217 struct hdac_widget *w;
1219 int i, enable = 0, poll = 0;
1222 id = hdac_codec_id(devinfo->codec);
1223 cad = devinfo->codec->cad;
1224 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
1225 if (as[i].hpredir < 0)
1228 w = hdac_widget_get(devinfo, as[i].pins[15]);
1229 if (w == NULL || w->enable == 0 || w->type !=
1230 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1232 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 ||
1233 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) {
1234 device_printf(sc->dev,
1235 "No jack detection support at pin %d\n",
1240 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) {
1242 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
1243 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
1244 HDAC_UNSOLTAG_EVENT_HP), cad);
1248 device_printf(sc->dev,
1249 "Enabling headphone/speaker "
1250 "audio routing switching:\n");
1251 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n",
1252 i, w->nid, (poll != 0) ? "POLL" : "UNSOL");
1256 hdac_hp_switch_handler(devinfo);
1258 callout_reset(&sc->poll_jack, 1,
1259 hdac_jack_poll_callback, devinfo);
1265 * Unsolicited messages handler.
1268 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1270 struct hdac_softc *sc;
1271 struct hdac_devinfo *devinfo = NULL;
1274 if (codec == NULL || codec->sc == NULL)
1280 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag);
1283 for (i = 0; i < codec->num_fgs; i++) {
1284 if (codec->fgs[i].node_type ==
1285 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
1286 devinfo = &codec->fgs[i];
1291 if (devinfo == NULL)
1295 case HDAC_UNSOLTAG_EVENT_HP:
1296 hdac_hp_switch_handler(devinfo);
1299 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag);
1305 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1307 /* XXX to be removed */
1308 #ifdef HDAC_INTR_EXTRA
1312 if (!(ch->flags & HDAC_CHN_RUNNING))
1315 /* XXX to be removed */
1316 #ifdef HDAC_INTR_EXTRA
1317 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1320 /* XXX to be removed */
1321 #ifdef HDAC_INTR_EXTRA
1323 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1324 device_printf(ch->pdevinfo->dev,
1325 "PCMDIR_%s intr triggered beyond stream boundary:"
1327 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1331 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1332 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1334 /* XXX to be removed */
1335 #ifdef HDAC_INTR_EXTRA
1336 if (res & HDAC_SDSTS_BCIS) {
1339 /* XXX to be removed */
1340 #ifdef HDAC_INTR_EXTRA
1347 /****************************************************************************
1348 * void hdac_intr_handler(void *)
1350 * Interrupt handler. Processes interrupts received from the hdac.
1351 ****************************************************************************/
1353 hdac_intr_handler(void *context)
1355 struct hdac_softc *sc;
1358 struct hdac_rirb *rirb_base;
1362 sc = (struct hdac_softc *)context;
1365 if (sc->polling != 0) {
1370 /* Do we have anything to do? */
1371 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1372 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1379 /* Was this a controller interrupt? */
1380 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1381 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1382 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1383 /* Get as many responses that we can */
1384 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1385 HDAC_WRITE_1(&sc->mem,
1386 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1387 if (hdac_rirb_flush(sc) != 0)
1388 trigger |= HDAC_TRIGGER_UNSOL;
1389 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1391 /* XXX to be removed */
1392 /* Clear interrupt and exit */
1393 #ifdef HDAC_INTR_EXTRA
1394 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1398 if (intsts & HDAC_INTSTS_SIS_MASK) {
1399 for (i = 0; i < sc->num_chans; i++) {
1400 if ((intsts & (1 << (sc->chans[i].off >> 5))) &&
1401 hdac_stream_intr(sc, &sc->chans[i]) != 0)
1402 trigger |= (1 << i);
1404 /* XXX to be removed */
1405 #ifdef HDAC_INTR_EXTRA
1406 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1407 HDAC_INTSTS_SIS_MASK);
1413 for (i = 0; i < sc->num_chans; i++) {
1414 if (trigger & (1 << i))
1415 chn_intr(sc->chans[i].c);
1417 if (trigger & HDAC_TRIGGER_UNSOL)
1418 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1421 /****************************************************************************
1422 * int hdac_reset(hdac_softc *, int)
1424 * Reset the hdac to a quiescent and known state.
1425 ****************************************************************************/
1427 hdac_reset(struct hdac_softc *sc, int wakeup)
1433 * Stop all Streams DMA engine
1435 for (i = 0; i < sc->num_iss; i++)
1436 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1437 for (i = 0; i < sc->num_oss; i++)
1438 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1439 for (i = 0; i < sc->num_bss; i++)
1440 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1443 * Stop Control DMA engines.
1445 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1446 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1449 * Reset DMA position buffer.
1451 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1452 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1455 * Reset the controller. The reset must remain asserted for
1456 * a minimum of 100us.
1458 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1459 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1462 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1463 if (!(gctl & HDAC_GCTL_CRST))
1467 if (gctl & HDAC_GCTL_CRST) {
1468 device_printf(sc->dev, "Unable to put hdac in reset\n");
1472 /* If wakeup is not requested - leave the controller in reset state. */
1477 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1478 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1481 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1482 if (gctl & HDAC_GCTL_CRST)
1486 if (!(gctl & HDAC_GCTL_CRST)) {
1487 device_printf(sc->dev, "Device stuck in reset\n");
1492 * Wait for codecs to finish their own reset sequence. The delay here
1493 * should be of 250us but for some reasons, on it's not enough on my
1494 * computer. Let's use twice as much as necessary to make sure that
1495 * it's reset properly.
1503 /****************************************************************************
1504 * int hdac_get_capabilities(struct hdac_softc *);
1506 * Retreive the general capabilities of the hdac;
1507 * Number of Input Streams
1508 * Number of Output Streams
1509 * Number of bidirectional Streams
1511 * CORB and RIRB sizes
1512 ****************************************************************************/
1514 hdac_get_capabilities(struct hdac_softc *sc)
1517 uint8_t corbsize, rirbsize;
1519 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1520 sc->num_iss = HDAC_GCAP_ISS(gcap);
1521 sc->num_oss = HDAC_GCAP_OSS(gcap);
1522 sc->num_bss = HDAC_GCAP_BSS(gcap);
1524 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1526 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1527 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1528 HDAC_CORBSIZE_CORBSZCAP_256)
1529 sc->corb_size = 256;
1530 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1531 HDAC_CORBSIZE_CORBSZCAP_16)
1533 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1534 HDAC_CORBSIZE_CORBSZCAP_2)
1537 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1538 __func__, corbsize);
1542 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1543 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1544 HDAC_RIRBSIZE_RIRBSZCAP_256)
1545 sc->rirb_size = 256;
1546 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1547 HDAC_RIRBSIZE_RIRBSZCAP_16)
1549 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1550 HDAC_RIRBSIZE_RIRBSZCAP_2)
1553 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1554 __func__, rirbsize);
1559 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
1560 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
1561 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
1562 sc->num_iss, sc->num_oss, sc->num_bss);
1569 /****************************************************************************
1572 * This function is called by bus_dmamap_load when the mapping has been
1573 * established. We just record the physical address of the mapping into
1574 * the struct hdac_dma passed in.
1575 ****************************************************************************/
1577 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1579 struct hdac_dma *dma;
1582 dma = (struct hdac_dma *)callback_arg;
1583 dma->dma_paddr = segs[0].ds_addr;
1588 /****************************************************************************
1589 * int hdac_dma_alloc
1591 * This function allocate and setup a dma region (struct hdac_dma).
1592 * It must be freed by a corresponding hdac_dma_free.
1593 ****************************************************************************/
1595 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1600 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1601 bzero(dma, sizeof(*dma));
1606 result = bus_dma_tag_create(
1607 bus_get_dma_tag(sc->dev), /* parent */
1608 HDAC_DMA_ALIGNMENT, /* alignment */
1610 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1611 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1612 BUS_SPACE_MAXADDR, /* highaddr */
1613 NULL, /* filtfunc */
1614 NULL, /* fistfuncarg */
1615 roundsz, /* maxsize */
1617 roundsz, /* maxsegsz */
1619 NULL, /* lockfunc */
1620 NULL, /* lockfuncarg */
1621 &dma->dma_tag); /* dmat */
1623 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1625 goto hdac_dma_alloc_fail;
1629 * Allocate DMA memory
1631 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1632 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1633 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1636 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1638 goto hdac_dma_alloc_fail;
1641 dma->dma_size = roundsz;
1646 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1647 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1648 if (result != 0 || dma->dma_paddr == 0) {
1651 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1653 goto hdac_dma_alloc_fail;
1657 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1658 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1663 hdac_dma_alloc_fail:
1664 hdac_dma_free(sc, dma);
1670 /****************************************************************************
1671 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1673 * Free a struct dhac_dma that has been previously allocated via the
1674 * hdac_dma_alloc function.
1675 ****************************************************************************/
1677 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1679 if (dma->dma_map != NULL) {
1682 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1683 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1685 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1687 if (dma->dma_vaddr != NULL) {
1688 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1689 dma->dma_vaddr = NULL;
1691 dma->dma_map = NULL;
1692 if (dma->dma_tag != NULL) {
1693 bus_dma_tag_destroy(dma->dma_tag);
1694 dma->dma_tag = NULL;
1699 /****************************************************************************
1700 * int hdac_mem_alloc(struct hdac_softc *)
1702 * Allocate all the bus resources necessary to speak with the physical
1704 ****************************************************************************/
1706 hdac_mem_alloc(struct hdac_softc *sc)
1708 struct hdac_mem *mem;
1711 mem->mem_rid = PCIR_BAR(0);
1712 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1713 &mem->mem_rid, RF_ACTIVE);
1714 if (mem->mem_res == NULL) {
1715 device_printf(sc->dev,
1716 "%s: Unable to allocate memory resource\n", __func__);
1719 mem->mem_tag = rman_get_bustag(mem->mem_res);
1720 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1725 /****************************************************************************
1726 * void hdac_mem_free(struct hdac_softc *)
1728 * Free up resources previously allocated by hdac_mem_alloc.
1729 ****************************************************************************/
1731 hdac_mem_free(struct hdac_softc *sc)
1733 struct hdac_mem *mem;
1736 if (mem->mem_res != NULL)
1737 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1739 mem->mem_res = NULL;
1742 /****************************************************************************
1743 * int hdac_irq_alloc(struct hdac_softc *)
1745 * Allocate and setup the resources necessary for interrupt handling.
1746 ****************************************************************************/
1748 hdac_irq_alloc(struct hdac_softc *sc)
1750 struct hdac_irq *irq;
1756 if ((sc->flags & HDAC_F_MSI) &&
1757 (result = pci_msi_count(sc->dev)) == 1 &&
1758 pci_alloc_msi(sc->dev, &result) == 0)
1761 sc->flags &= ~HDAC_F_MSI;
1763 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1764 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1765 if (irq->irq_res == NULL) {
1766 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1768 goto hdac_irq_alloc_fail;
1770 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
1771 NULL, hdac_intr_handler, sc, &irq->irq_handle);
1773 device_printf(sc->dev,
1774 "%s: Unable to setup interrupt handler (%x)\n",
1776 goto hdac_irq_alloc_fail;
1781 hdac_irq_alloc_fail:
1787 /****************************************************************************
1788 * void hdac_irq_free(struct hdac_softc *)
1790 * Free up resources previously allocated by hdac_irq_alloc.
1791 ****************************************************************************/
1793 hdac_irq_free(struct hdac_softc *sc)
1795 struct hdac_irq *irq;
1798 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1799 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1800 if (irq->irq_res != NULL)
1801 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1803 if (irq->irq_rid == 0x1)
1804 pci_release_msi(sc->dev);
1805 irq->irq_handle = NULL;
1806 irq->irq_res = NULL;
1810 /****************************************************************************
1811 * void hdac_corb_init(struct hdac_softc *)
1813 * Initialize the corb registers for operations but do not start it up yet.
1814 * The CORB engine must not be running when this function is called.
1815 ****************************************************************************/
1817 hdac_corb_init(struct hdac_softc *sc)
1822 /* Setup the CORB size. */
1823 switch (sc->corb_size) {
1825 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1828 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1831 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1834 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1836 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1838 /* Setup the CORB Address in the hdac */
1839 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1840 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1841 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1843 /* Set the WP and RP */
1845 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1846 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1848 * The HDA specification indicates that the CORBRPRST bit will always
1849 * read as zero. Unfortunately, it seems that at least the 82801G
1850 * doesn't reset the bit to zero, which stalls the corb engine.
1851 * manually reset the bit to zero before continuing.
1853 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1855 /* Enable CORB error reporting */
1857 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1861 /****************************************************************************
1862 * void hdac_rirb_init(struct hdac_softc *)
1864 * Initialize the rirb registers for operations but do not start it up yet.
1865 * The RIRB engine must not be running when this function is called.
1866 ****************************************************************************/
1868 hdac_rirb_init(struct hdac_softc *sc)
1873 /* Setup the RIRB size. */
1874 switch (sc->rirb_size) {
1876 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1879 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1882 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1885 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1887 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1889 /* Setup the RIRB Address in the hdac */
1890 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1891 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1892 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1894 /* Setup the WP and RP */
1896 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1898 /* Setup the interrupt threshold */
1899 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1901 /* Enable Overrun and response received reporting */
1903 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1904 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1906 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1911 * Make sure that the Host CPU cache doesn't contain any dirty
1912 * cache lines that falls in the rirb. If I understood correctly, it
1913 * should be sufficient to do this only once as the rirb is purely
1914 * read-only from now on.
1916 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1917 BUS_DMASYNC_PREREAD);
1921 /****************************************************************************
1922 * void hdac_corb_start(hdac_softc *)
1924 * Startup the corb DMA engine
1925 ****************************************************************************/
1927 hdac_corb_start(struct hdac_softc *sc)
1931 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1932 corbctl |= HDAC_CORBCTL_CORBRUN;
1933 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1936 /****************************************************************************
1937 * void hdac_rirb_start(hdac_softc *)
1939 * Startup the rirb DMA engine
1940 ****************************************************************************/
1942 hdac_rirb_start(struct hdac_softc *sc)
1946 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1947 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1948 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1952 /****************************************************************************
1953 * void hdac_scan_codecs(struct hdac_softc *, int)
1955 * Scan the bus for available codecs, starting with num.
1956 ****************************************************************************/
1958 hdac_scan_codecs(struct hdac_softc *sc)
1960 struct hdac_codec *codec;
1964 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1965 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1966 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1967 /* We have found a codec. */
1968 codec = (struct hdac_codec *)malloc(sizeof(*codec),
1969 M_HDAC, M_ZERO | M_NOWAIT);
1970 if (codec == NULL) {
1971 device_printf(sc->dev,
1972 "Unable to allocate memory for codec\n");
1975 codec->commands = NULL;
1976 codec->responses_received = 0;
1977 codec->verbs_sent = 0;
1980 sc->codecs[i] = codec;
1981 hdac_probe_codec(codec);
1984 /* All codecs have been probed, now try to attach drivers to them */
1985 /* bus_generic_attach(sc->dev); */
1988 /****************************************************************************
1989 * void hdac_probe_codec(struct hdac_softc *, int)
1991 * Probe a the given codec_id for available function groups.
1992 ****************************************************************************/
1994 hdac_probe_codec(struct hdac_codec *codec)
1996 struct hdac_softc *sc = codec->sc;
1997 uint32_t vendorid, revisionid, subnode;
2001 nid_t cad = codec->cad;
2004 device_printf(sc->dev, "Probing codec #%d...\n", cad);
2006 vendorid = hdac_command(sc,
2007 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
2009 revisionid = hdac_command(sc,
2010 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
2012 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
2013 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
2014 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
2015 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
2017 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) {
2018 device_printf(sc->dev, "Codec #%d is not responding!"
2019 " Probing aborted.\n", cad);
2023 device_printf(sc->dev, "HDA Codec #%d: %s\n",
2024 cad, hdac_codec_name(codec));
2026 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n",
2027 hdac_codec_id(codec));
2028 device_printf(sc->dev, " Vendor: 0x%04x\n",
2030 device_printf(sc->dev, " Device: 0x%04x\n",
2032 device_printf(sc->dev, " Revision: 0x%02x\n",
2033 codec->revision_id);
2034 device_printf(sc->dev, " Stepping: 0x%02x\n",
2035 codec->stepping_id);
2036 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
2039 subnode = hdac_command(sc,
2040 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
2042 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
2043 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
2046 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n",
2047 startnode, endnode);
2050 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) *
2051 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO);
2052 if (codec->fgs == NULL) {
2053 device_printf(sc->dev, "%s: Unable to allocate function groups\n",
2058 for (i = startnode; i < endnode; i++)
2059 hdac_probe_function(codec, i);
2064 * Probe codec function and add it to the list.
2067 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
2069 struct hdac_softc *sc = codec->sc;
2070 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs];
2071 uint32_t fctgrptype;
2073 nid_t cad = codec->cad;
2075 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
2076 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
2079 devinfo->node_type = fctgrptype;
2080 devinfo->codec = codec;
2082 res = hdac_command(sc,
2083 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
2085 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
2086 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
2087 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
2090 device_printf(sc->dev,
2091 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n",
2092 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio":
2093 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem":
2094 "unknown", nid, devinfo->startnode, devinfo->endnode,
2098 if (devinfo->nodecnt > 0)
2099 devinfo->widget = (struct hdac_widget *)malloc(
2100 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
2103 devinfo->widget = NULL;
2105 if (devinfo->widget == NULL) {
2106 device_printf(sc->dev, "unable to allocate widgets!\n");
2107 devinfo->endnode = devinfo->startnode;
2108 devinfo->nodecnt = 0;
2116 hdac_widget_connection_parse(struct hdac_widget *w)
2118 struct hdac_softc *sc = w->devinfo->codec->sc;
2120 int i, j, max, ents, entnum;
2121 nid_t cad = w->devinfo->codec->cad;
2123 nid_t cnid, addcnid, prevcnid;
2127 res = hdac_command(sc,
2128 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
2130 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
2135 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
2136 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
2139 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
2140 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
2141 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
2142 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
2143 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
2145 for (i = 0; i < ents; i += entnum) {
2146 res = hdac_command(sc,
2147 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
2148 for (j = 0; j < entnum; j++) {
2149 cnid = CONN_CNID(res, entnum, j);
2151 if (w->nconns < ents)
2152 device_printf(sc->dev,
2153 "%s: nid=%d WARNING: zero cnid "
2154 "entnum=%d j=%d index=%d "
2155 "entries=%d found=%d res=0x%08x\n",
2156 __func__, nid, entnum, j, i,
2157 ents, w->nconns, res);
2161 if (cnid < w->devinfo->startnode ||
2162 cnid >= w->devinfo->endnode) {
2164 device_printf(sc->dev,
2165 "GHOST: nid=%d j=%d "
2166 "entnum=%d index=%d res=0x%08x\n",
2167 nid, j, entnum, i, res);
2170 if (CONN_RANGE(res, entnum, j) == 0)
2172 else if (prevcnid == 0 || prevcnid >= cnid) {
2173 device_printf(sc->dev,
2174 "%s: WARNING: Invalid child range "
2175 "nid=%d index=%d j=%d entnum=%d "
2176 "prevcnid=%d cnid=%d res=0x%08x\n",
2177 __func__, nid, i, j, entnum, prevcnid,
2181 addcnid = prevcnid + 1;
2182 while (addcnid <= cnid) {
2183 if (w->nconns > max) {
2184 device_printf(sc->dev,
2185 "Adding %d (nid=%d): "
2186 "Max connection reached! max=%d\n",
2187 addcnid, nid, max + 1);
2190 w->connsenable[w->nconns] = 1;
2191 w->conns[w->nconns++] = addcnid++;
2202 hdac_widget_pin_patch(uint32_t config, const char *str)
2205 char *key, *value, *rest, *bad;
2208 strlcpy(buf, str, sizeof(buf));
2210 while ((key = strsep(&rest, "=")) != NULL) {
2211 value = strsep(&rest, " \t");
2214 ival = strtol(value, &bad, 10);
2215 if (strcmp(key, "seq") == 0) {
2216 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK;
2217 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) &
2218 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK);
2219 } else if (strcmp(key, "as") == 0) {
2220 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK;
2221 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) &
2222 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK);
2223 } else if (strcmp(key, "misc") == 0) {
2224 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK;
2225 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) &
2226 HDA_CONFIG_DEFAULTCONF_MISC_MASK);
2227 } else if (strcmp(key, "color") == 0) {
2228 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK;
2230 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) &
2231 HDA_CONFIG_DEFAULTCONF_COLOR_MASK);
2233 for (i = 0; i < 16; i++) {
2234 if (strcasecmp(HDA_COLORS[i], value) == 0) {
2235 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT);
2239 } else if (strcmp(key, "ctype") == 0) {
2240 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK;
2241 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) &
2242 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK);
2243 } else if (strcmp(key, "device") == 0) {
2244 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2246 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) &
2247 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK);
2250 for (i = 0; i < 16; i++) {
2251 if (strcasecmp(HDA_DEVS[i], value) == 0) {
2252 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT);
2256 } else if (strcmp(key, "loc") == 0) {
2257 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK;
2258 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) &
2259 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK);
2260 } else if (strcmp(key, "conn") == 0) {
2261 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2263 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) &
2264 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2267 for (i = 0; i < 4; i++) {
2268 if (strcasecmp(HDA_CONNS[i], value) == 0) {
2269 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT);
2279 hdac_widget_pin_getconfig(struct hdac_widget *w)
2281 struct hdac_softc *sc;
2282 uint32_t config, orig, id;
2285 const char *res = NULL, *patch = NULL;
2287 sc = w->devinfo->codec->sc;
2288 cad = w->devinfo->codec->cad;
2290 id = hdac_codec_id(w->devinfo->codec);
2292 config = hdac_command(sc,
2293 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2298 hdac_dump_pin_config(w, orig);
2301 /* XXX: Old patches require complete review.
2302 * Now they may create more problem then solve due to
2303 * incorrect associations.
2305 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2308 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2309 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2312 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2313 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2318 } else if (id == HDA_CODEC_ALC880 &&
2319 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2320 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2326 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2327 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2329 case 25: /* XXX MIC2 */
2330 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2331 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2333 case 26: /* LINE1 */
2334 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2335 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2337 case 27: /* XXX LINE2 */
2338 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2339 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2342 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2343 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2346 } else if (id == HDA_CODEC_ALC883 &&
2347 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2348 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2351 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2352 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2353 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2354 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2357 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2358 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2359 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2360 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2363 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor ==
2364 HP_V3000_SUBVENDOR) {
2367 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2368 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2371 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2372 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2373 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2377 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2378 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2379 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2380 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2383 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor ==
2384 HP_DV5000_SUBVENDOR) {
2388 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2389 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2392 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2393 ASUS_W6F_SUBVENDOR) {
2396 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2397 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2398 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2399 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2406 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2408 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2409 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2412 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2413 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2414 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2415 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2418 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2419 UNIWILL_9075_SUBVENDOR) {
2422 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2423 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2424 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2425 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2431 if (id == HDA_CODEC_AD1986A &&
2432 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2433 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR ||
2434 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) {
2436 case 26: /* Headphones with redirection */
2437 patch = "as=1 seq=15";
2439 case 28: /* 5.1 out => 2.0 out + 1 input */
2440 patch = "device=Line-in as=8 seq=1";
2442 case 29: /* Can't use this as input, as the only available mic
2443 * preamplifier is busy by front panel mic (nid 31).
2444 * If you want to use this rear connector as mic input,
2445 * you have to disable the front panel one. */
2448 case 31: /* Lot of inputs configured with as=15 and unusable */
2449 patch = "as=8 seq=3";
2452 patch = "as=8 seq=4";
2455 patch = "as=8 seq=5";
2458 patch = "as=8 seq=6";
2461 } else if (id == HDA_CODEC_ALC260 &&
2462 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) {
2465 patch = "seq=15 device=Headphones";
2468 } else if (id == HDA_CODEC_ALC268) {
2469 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) {
2471 case 20: /* Headphones Jack */
2472 patch = "as=1 seq=15";
2479 config = hdac_widget_pin_patch(config, patch);
2481 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid);
2482 if (resource_string_value(device_get_name(sc->dev),
2483 device_get_unit(sc->dev), buf, &res) == 0) {
2484 if (strncmp(res, "0x", 2) == 0) {
2485 config = strtol(res + 2, NULL, 16);
2487 config = hdac_widget_pin_patch(config, res);
2493 device_printf(sc->dev,
2494 "Patching pin config nid=%u 0x%08x -> 0x%08x\n",
2502 hdac_widget_pin_getcaps(struct hdac_widget *w)
2504 struct hdac_softc *sc;
2505 uint32_t caps, orig, id;
2508 sc = w->devinfo->codec->sc;
2509 cad = w->devinfo->codec->cad;
2511 id = hdac_codec_id(w->devinfo->codec);
2513 caps = hdac_command(sc,
2514 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2519 device_printf(sc->dev,
2520 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n",
2528 hdac_widget_pin_parse(struct hdac_widget *w)
2530 struct hdac_softc *sc = w->devinfo->codec->sc;
2531 uint32_t config, pincap;
2533 nid_t cad = w->devinfo->codec->cad;
2537 config = hdac_widget_pin_getconfig(w);
2538 w->wclass.pin.config = config;
2540 pincap = hdac_widget_pin_getcaps(w);
2541 w->wclass.pin.cap = pincap;
2543 w->wclass.pin.ctrl = hdac_command(sc,
2544 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad);
2546 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2547 w->param.eapdbtl = hdac_command(sc,
2548 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2549 w->param.eapdbtl &= 0x7;
2550 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2552 w->param.eapdbtl = HDAC_INVALID;
2554 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >>
2555 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT];
2557 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >>
2558 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT;
2559 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >>
2560 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT;
2562 strlcat(w->name, ": ", sizeof(w->name));
2563 strlcat(w->name, devstr, sizeof(w->name));
2564 strlcat(w->name, " (", sizeof(w->name));
2565 if (conn == 0 && color != 0 && color != 15) {
2566 strlcat(w->name, HDA_COLORS[color], sizeof(w->name));
2567 strlcat(w->name, " ", sizeof(w->name));
2569 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name));
2570 strlcat(w->name, ")", sizeof(w->name));
2574 hdac_widget_getcaps(struct hdac_widget *w, int *waspin)
2576 struct hdac_softc *sc;
2577 uint32_t caps, orig, id;
2578 nid_t cad, nid, beeper = -1;
2580 sc = w->devinfo->codec->sc;
2581 cad = w->devinfo->codec->cad;
2583 id = hdac_codec_id(w->devinfo->codec);
2585 caps = hdac_command(sc,
2586 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2590 /* On some codecs beeper is an input pin, but it is not recordable
2591 alone. Also most of BIOSes does not declare beeper pin.
2592 Change beeper pin node type to beeper to help parser. */
2595 case HDA_CODEC_AD1882:
2596 case HDA_CODEC_AD1883:
2597 case HDA_CODEC_AD1984:
2598 case HDA_CODEC_AD1984A:
2599 case HDA_CODEC_AD1984B:
2600 case HDA_CODEC_AD1987:
2601 case HDA_CODEC_AD1988:
2602 case HDA_CODEC_AD1988B:
2603 case HDA_CODEC_AD1989B:
2606 case HDA_CODEC_ALC260:
2609 case HDA_CODEC_ALC262:
2610 case HDA_CODEC_ALC268:
2611 case HDA_CODEC_ALC880:
2612 case HDA_CODEC_ALC882:
2613 case HDA_CODEC_ALC883:
2614 case HDA_CODEC_ALC885:
2615 case HDA_CODEC_ALC888:
2616 case HDA_CODEC_ALC889:
2620 if (nid == beeper) {
2621 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
2622 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
2623 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
2629 device_printf(sc->dev,
2630 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n",
2639 hdac_widget_parse(struct hdac_widget *w)
2641 struct hdac_softc *sc = w->devinfo->codec->sc;
2644 nid_t cad = w->devinfo->codec->cad;
2647 wcap = hdac_widget_getcaps(w, &w->waspin);
2649 w->param.widget_cap = wcap;
2650 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2653 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2654 typestr = "audio output";
2656 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2657 typestr = "audio input";
2659 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2660 typestr = "audio mixer";
2662 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2663 typestr = "audio selector";
2665 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2668 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2669 typestr = "power widget";
2671 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2672 typestr = "volume widget";
2674 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2675 typestr = "beep widget";
2677 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2678 typestr = "vendor widget";
2681 typestr = "unknown type";
2685 strlcpy(w->name, typestr, sizeof(w->name));
2687 hdac_widget_connection_parse(w);
2689 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2690 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2691 w->param.outamp_cap =
2693 HDA_CMD_GET_PARAMETER(cad, nid,
2694 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2696 w->param.outamp_cap =
2697 w->devinfo->function.audio.outamp_cap;
2699 w->param.outamp_cap = 0;
2701 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2702 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2703 w->param.inamp_cap =
2705 HDA_CMD_GET_PARAMETER(cad, nid,
2706 HDA_PARAM_INPUT_AMP_CAP), cad);
2708 w->param.inamp_cap =
2709 w->devinfo->function.audio.inamp_cap;
2711 w->param.inamp_cap = 0;
2713 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2714 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2715 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2716 cap = hdac_command(sc,
2717 HDA_CMD_GET_PARAMETER(cad, nid,
2718 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2719 w->param.supp_stream_formats = (cap != 0) ? cap :
2720 w->devinfo->function.audio.supp_stream_formats;
2721 cap = hdac_command(sc,
2722 HDA_CMD_GET_PARAMETER(cad, nid,
2723 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2724 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2725 w->devinfo->function.audio.supp_pcm_size_rate;
2727 w->param.supp_stream_formats =
2728 w->devinfo->function.audio.supp_stream_formats;
2729 w->param.supp_pcm_size_rate =
2730 w->devinfo->function.audio.supp_pcm_size_rate;
2733 w->param.supp_stream_formats = 0;
2734 w->param.supp_pcm_size_rate = 0;
2737 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2738 hdac_widget_pin_parse(w);
2741 static struct hdac_widget *
2742 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2744 if (devinfo == NULL || devinfo->widget == NULL ||
2745 nid < devinfo->startnode || nid >= devinfo->endnode)
2747 return (&devinfo->widget[nid - devinfo->startnode]);
2751 hda_poll_channel(struct hdac_chan *ch)
2754 volatile uint32_t ptr;
2756 if (!(ch->flags & HDAC_CHN_RUNNING))
2759 sz = ch->blksz * ch->blkcnt;
2760 if (ch->dmapos != NULL)
2761 ptr = *(ch->dmapos);
2763 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2764 ch->off + HDAC_SDLPIB);
2767 ptr &= ~(ch->blksz - 1);
2768 delta = (sz + ptr - ch->prevptr) % sz;
2770 if (delta < ch->blksz)
2779 hda_poll_callback(void *arg)
2781 struct hdac_softc *sc = arg;
2789 if (sc->polling == 0) {
2795 for (i = 0; i < sc->num_chans; i++) {
2796 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0)
2799 if (hda_poll_channel(&sc->chans[i]))
2800 trigger |= (1 << i);
2805 callout_reset(&sc->poll_hda, sc->poll_ticks,
2806 hda_poll_callback, sc);
2810 for (i = 0; i < sc->num_chans; i++) {
2811 if (trigger & (1 << i))
2812 chn_intr(sc->chans[i].c);
2817 hdac_rirb_flush(struct hdac_softc *sc)
2819 struct hdac_rirb *rirb_base, *rirb;
2820 struct hdac_codec *codec;
2821 struct hdac_command_list *commands;
2827 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2828 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2830 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2831 BUS_DMASYNC_POSTREAD);
2836 while (sc->rirb_rp != rirbwp) {
2838 sc->rirb_rp %= sc->rirb_size;
2839 rirb = &rirb_base[sc->rirb_rp];
2840 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2841 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2842 sc->codecs[cad] == NULL)
2844 resp = rirb->response;
2845 codec = sc->codecs[cad];
2846 commands = codec->commands;
2847 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2848 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2849 ((resp >> 26) & 0xffff);
2850 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2851 } else if (commands != NULL && commands->num_commands > 0 &&
2852 codec->responses_received < commands->num_commands)
2853 commands->responses[codec->responses_received++] =
2862 hdac_unsolq_flush(struct hdac_softc *sc)
2868 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2869 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2870 while (sc->unsolq_rp != sc->unsolq_wp) {
2871 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2872 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2873 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2874 hdac_unsolicited_handler(sc->codecs[cad], tag);
2877 sc->unsolq_st = HDAC_UNSOLQ_READY;
2884 hdac_poll_callback(void *arg)
2886 struct hdac_softc *sc = arg;
2891 if (sc->polling == 0 || sc->poll_ival == 0) {
2895 if (hdac_rirb_flush(sc) != 0)
2896 hdac_unsolq_flush(sc);
2897 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2902 hdac_poll_reinit(struct hdac_softc *sc)
2904 int i, pollticks, min = 1000000;
2905 struct hdac_chan *ch;
2907 for (i = 0; i < sc->num_chans; i++) {
2908 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0)
2911 pollticks = ((uint64_t)hz * ch->blksz) /
2912 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b));
2916 if (pollticks < 1) {
2918 device_printf(sc->dev,
2919 "%s: pollticks=%d < 1 !\n",
2920 __func__, pollticks);
2924 if (min > pollticks)
2928 device_printf(sc->dev,
2929 "%s: pollticks %d -> %d\n",
2930 __func__, sc->poll_ticks, min);
2932 sc->poll_ticks = min;
2934 callout_stop(&sc->poll_hda);
2936 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc);
2940 hdac_stream_stop(struct hdac_chan *ch)
2942 struct hdac_softc *sc = ch->devinfo->codec->sc;
2945 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2946 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2948 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2950 ch->flags &= ~HDAC_CHN_RUNNING;
2952 if (sc->polling != 0)
2953 hdac_poll_reinit(sc);
2955 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2956 ctl &= ~(1 << (ch->off >> 5));
2957 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2961 hdac_stream_start(struct hdac_chan *ch)
2963 struct hdac_softc *sc = ch->devinfo->codec->sc;
2966 ch->flags |= HDAC_CHN_RUNNING;
2968 if (sc->polling != 0)
2969 hdac_poll_reinit(sc);
2971 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2972 ctl |= 1 << (ch->off >> 5);
2973 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2975 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2976 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2978 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2982 hdac_stream_reset(struct hdac_chan *ch)
2984 struct hdac_softc *sc = ch->devinfo->codec->sc;
2989 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2990 ctl |= HDAC_SDCTL_SRST;
2991 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2993 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2994 if (ctl & HDAC_SDCTL_SRST)
2998 if (!(ctl & HDAC_SDCTL_SRST)) {
2999 device_printf(sc->dev, "timeout in reset\n");
3001 ctl &= ~HDAC_SDCTL_SRST;
3002 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3005 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3006 if (!(ctl & HDAC_SDCTL_SRST))
3010 if (ctl & HDAC_SDCTL_SRST)
3011 device_printf(sc->dev, "can't reset!\n");
3015 hdac_stream_setid(struct hdac_chan *ch)
3017 struct hdac_softc *sc = ch->devinfo->codec->sc;
3020 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
3021 ctl &= ~HDAC_SDCTL2_STRM_MASK;
3022 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
3023 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
3027 hdac_bdl_setup(struct hdac_chan *ch)
3029 struct hdac_softc *sc = ch->devinfo->codec->sc;
3030 struct hdac_bdle *bdle;
3032 uint32_t blksz, blkcnt;
3035 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
3036 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
3039 blkcnt = ch->blkcnt;
3041 for (i = 0; i < blkcnt; i++, bdle++) {
3042 bdle->addrl = (uint32_t)addr;
3043 bdle->addrh = (uint32_t)(addr >> 32);
3049 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
3050 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
3051 addr = ch->bdl_dma.dma_paddr;
3052 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
3053 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
3054 if (ch->dmapos != NULL &&
3055 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
3056 addr = sc->pos_dma.dma_paddr;
3057 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
3058 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
3059 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
3064 hdac_bdl_alloc(struct hdac_chan *ch)
3066 struct hdac_softc *sc = ch->devinfo->codec->sc;
3069 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
3070 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
3072 device_printf(sc->dev, "can't alloc bdl\n");
3080 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
3081 int index, int lmute, int rmute,
3082 int left, int right, int dir)
3089 if (left != right || lmute != rmute) {
3090 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
3091 (lmute << 7) | left;
3093 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
3094 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
3095 (rmute << 7) | right;
3097 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
3098 (lmute << 7) | left;
3101 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
3105 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
3106 int left, int right)
3108 struct hdac_softc *sc;
3112 sc = ctl->widget->devinfo->codec->sc;
3113 cad = ctl->widget->devinfo->codec->cad;
3114 nid = ctl->widget->nid;
3116 /* Save new values if valid. */
3117 if (mute != HDA_AMP_MUTE_DEFAULT)
3119 if (left != HDA_AMP_VOL_DEFAULT)
3121 if (right != HDA_AMP_VOL_DEFAULT)
3123 /* Prepare effective values */
3124 if (ctl->forcemute) {
3130 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
3131 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
3135 /* Apply effective values */
3136 if (ctl->dir & HDA_CTL_OUT)
3137 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
3138 lmute, rmute, left, right, 0);
3139 if (ctl->dir & HDA_CTL_IN)
3140 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
3141 lmute, rmute, left, right, 1);
3145 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
3147 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
3149 hdac_command(w->devinfo->codec->sc,
3150 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
3151 w->nid, index), w->devinfo->codec->cad);
3156 /****************************************************************************
3157 * uint32_t hdac_command_sendone_internal
3159 * Wrapper function that sends only one command to a given codec
3160 ****************************************************************************/
3162 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
3164 struct hdac_command_list cl;
3165 uint32_t response = HDAC_INVALID;
3167 if (!hdac_lockowned(sc))
3168 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
3169 cl.num_commands = 1;
3171 cl.responses = &response;
3173 hdac_command_send_internal(sc, &cl, cad);
3178 /****************************************************************************
3179 * hdac_command_send_internal
3181 * Send a command list to the codec via the corb. We queue as much verbs as
3182 * we can and msleep on the codec. When the interrupt get the responses
3183 * back from the rirb, it will wake us up so we can queue the remaining verbs
3185 ****************************************************************************/
3187 hdac_command_send_internal(struct hdac_softc *sc,
3188 struct hdac_command_list *commands, nid_t cad)
3190 struct hdac_codec *codec;
3195 struct hdac_rirb *rirb_base;
3197 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
3198 commands->num_commands < 1)
3201 codec = sc->codecs[cad];
3202 codec->commands = commands;
3203 codec->responses_received = 0;
3204 codec->verbs_sent = 0;
3205 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
3206 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
3209 if (codec->verbs_sent != commands->num_commands) {
3210 /* Queue as many verbs as possible */
3211 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
3213 bus_dmamap_sync(sc->corb_dma.dma_tag,
3214 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
3216 while (codec->verbs_sent != commands->num_commands &&
3217 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
3219 sc->corb_wp %= sc->corb_size;
3221 commands->verbs[codec->verbs_sent++];
3224 /* Send the verbs to the codecs */
3226 bus_dmamap_sync(sc->corb_dma.dma_tag,
3227 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
3229 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
3233 while (hdac_rirb_flush(sc) == 0 && --timeout)
3235 } while ((codec->verbs_sent != commands->num_commands ||
3236 codec->responses_received != commands->num_commands) && --retry);
3239 device_printf(sc->dev,
3240 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
3241 __func__, commands->num_commands, codec->verbs_sent,
3242 codec->responses_received);
3244 codec->commands = NULL;
3245 codec->responses_received = 0;
3246 codec->verbs_sent = 0;
3248 hdac_unsolq_flush(sc);
3252 /****************************************************************************
3254 ****************************************************************************/
3256 /****************************************************************************
3257 * int hdac_probe(device_t)
3259 * Probe for the presence of an hdac. If none is found, check for a generic
3260 * match using the subclass of the device.
3261 ****************************************************************************/
3263 hdac_probe(device_t dev)
3267 uint16_t class, subclass;
3270 model = (uint32_t)pci_get_device(dev) << 16;
3271 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
3272 class = pci_get_class(dev);
3273 subclass = pci_get_subclass(dev);
3275 bzero(desc, sizeof(desc));
3277 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
3278 if (hdac_devices[i].model == model) {
3279 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3280 result = BUS_PROBE_DEFAULT;
3283 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
3284 class == PCIC_MULTIMEDIA &&
3285 subclass == PCIS_MULTIMEDIA_HDA) {
3286 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3287 result = BUS_PROBE_GENERIC;
3291 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3292 subclass == PCIS_MULTIMEDIA_HDA) {
3293 strlcpy(desc, "Generic", sizeof(desc));
3294 result = BUS_PROBE_GENERIC;
3296 if (result != ENXIO) {
3297 strlcat(desc, " High Definition Audio Controller",
3299 device_set_desc_copy(dev, desc);
3306 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3307 struct pcm_channel *c, int dir)
3309 struct hdac_pcm_devinfo *pdevinfo = data;
3310 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3311 struct hdac_softc *sc = devinfo->codec->sc;
3312 struct hdac_chan *ch;
3313 int i, ord = 0, chid;
3317 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec;
3318 ch = &sc->chans[chid];
3319 for (i = 0; i < sc->num_chans && i < chid; i++) {
3320 if (ch->dir == sc->chans[i].dir)
3323 if (dir == PCMDIR_PLAY) {
3324 ch->off = (sc->num_iss + ord) << 5;
3329 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3330 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3331 ch->pcmrates[0] = 48000;
3332 ch->pcmrates[1] = 0;
3334 if (sc->pos_dma.dma_vaddr != NULL)
3335 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3336 (sc->streamcnt * 8));
3339 ch->sid = ++sc->streamcnt;
3343 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt;
3344 ch->blkcnt = pdevinfo->chan_blkcnt;
3347 if (hdac_bdl_alloc(ch) != 0) {
3352 if (sndbuf_alloc(ch->b, sc->chan_dmat,
3353 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0,
3354 pdevinfo->chan_size) != 0)
3361 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3363 struct hdac_chan *ch = data;
3366 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3367 if (format == ch->caps.fmtlist[i]) {
3377 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3379 struct hdac_chan *ch = data;
3380 uint32_t spd = 0, threshold;
3383 for (i = 0; ch->pcmrates[i] != 0; i++) {
3384 spd = ch->pcmrates[i];
3385 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3386 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3387 if (speed < threshold)
3391 if (spd == 0) /* impossible */
3400 hdac_stream_setup(struct hdac_chan *ch)
3402 struct hdac_softc *sc = ch->devinfo->codec->sc;
3403 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as];
3404 struct hdac_widget *w;
3405 int i, chn, totalchn, c;
3406 nid_t cad = ch->devinfo->codec->cad;
3410 device_printf(ch->pdevinfo->dev,
3411 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n",
3412 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3416 if (ch->fmt & AFMT_S16_LE)
3417 fmt |= ch->bit16 << 4;
3418 else if (ch->fmt & AFMT_S32_LE)
3419 fmt |= ch->bit32 << 4;
3423 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3424 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3425 fmt |= hda_rate_tab[i].base;
3426 fmt |= hda_rate_tab[i].mul;
3427 fmt |= hda_rate_tab[i].div;
3432 totalchn = AFMT_CHANNEL(ch->fmt);
3436 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3438 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN;
3439 if (ch->fmt & AFMT_AC3)
3440 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO;
3443 for (i = 0; ch->io[i] != -1; i++) {
3444 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3448 if (as->hpredir >= 0 && i == as->pincnt)
3451 device_printf(ch->pdevinfo->dev,
3452 "PCMDIR_%s: Stream setup nid=%d: "
3453 "fmt=0x%04x, dfmt=0x%04x\n",
3454 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3455 ch->io[i], fmt, dfmt);
3458 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3459 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
3461 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt),
3464 /* If HP redirection is enabled, but failed to use same
3465 DAC make last DAC one to duplicate first one. */
3466 if (as->hpredir >= 0 && i == as->pincnt) {
3468 } else if (chn >= totalchn) {
3469 /* This is until OSS will support multichannel.
3470 Should be: c = 0; to disable unused DAC */
3473 c = (ch->sid << 4) | chn;
3476 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad);
3478 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ?
3484 hdac_channel_setfragments(kobj_t obj, void *data,
3485 uint32_t blksz, uint32_t blkcnt)
3487 struct hdac_chan *ch = data;
3488 struct hdac_softc *sc = ch->devinfo->codec->sc;
3490 blksz &= HDA_BLK_ALIGN;
3492 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3493 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3494 if (blksz < HDA_BLK_MIN)
3495 blksz = HDA_BLK_MIN;
3496 if (blkcnt > HDA_BDL_MAX)
3497 blkcnt = HDA_BDL_MAX;
3498 if (blkcnt < HDA_BDL_MIN)
3499 blkcnt = HDA_BDL_MIN;
3501 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3502 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3504 else if ((blksz >> 1) >= HDA_BLK_MIN)
3510 if ((sndbuf_getblksz(ch->b) != blksz ||
3511 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3512 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3513 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3514 __func__, blksz, blkcnt);
3516 ch->blksz = sndbuf_getblksz(ch->b);
3517 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3523 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3525 struct hdac_chan *ch = data;
3527 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt);
3533 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3535 struct hdac_devinfo *devinfo = ch->devinfo;
3536 struct hdac_widget *w;
3537 nid_t cad = devinfo->codec->cad;
3540 hdac_stream_stop(ch);
3542 for (i = 0; ch->io[i] != -1; i++) {
3543 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3546 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
3548 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0),
3552 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3558 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3562 hdac_stream_stop(ch);
3563 hdac_stream_reset(ch);
3565 hdac_stream_setid(ch);
3566 hdac_stream_setup(ch);
3567 hdac_stream_start(ch);
3571 hdac_channel_trigger(kobj_t obj, void *data, int go)
3573 struct hdac_chan *ch = data;
3574 struct hdac_softc *sc = ch->devinfo->codec->sc;
3576 if (!PCMTRIG_COMMON(go))
3582 hdac_channel_start(sc, ch);
3586 hdac_channel_stop(sc, ch);
3597 hdac_channel_getptr(kobj_t obj, void *data)
3599 struct hdac_chan *ch = data;
3600 struct hdac_softc *sc = ch->devinfo->codec->sc;
3604 if (sc->polling != 0)
3606 else if (ch->dmapos != NULL)
3607 ptr = *(ch->dmapos);
3609 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3613 * Round to available space and force 128 bytes aligment.
3615 ptr %= ch->blksz * ch->blkcnt;
3616 ptr &= HDA_BLK_ALIGN;
3621 static struct pcmchan_caps *
3622 hdac_channel_getcaps(kobj_t obj, void *data)
3624 return (&((struct hdac_chan *)data)->caps);
3627 static kobj_method_t hdac_channel_methods[] = {
3628 KOBJMETHOD(channel_init, hdac_channel_init),
3629 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3630 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3631 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3632 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments),
3633 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3634 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3635 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3638 CHANNEL_DECLARE(hdac_channel);
3641 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3643 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3644 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3645 struct hdac_softc *sc = devinfo->codec->sc;
3646 struct hdac_widget *w, *cw;
3647 struct hdac_audio_ctl *ctl;
3648 uint32_t mask, recmask, id;
3649 int i, j, softpcmvol;
3653 /* Make sure that in case of soft volume it won't stay muted. */
3654 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3655 pdevinfo->left[i] = 100;
3656 pdevinfo->right[i] = 100;
3661 id = hdac_codec_id(devinfo->codec);
3663 /* Declate EAPD as ogain control. */
3664 if (pdevinfo->play >= 0) {
3665 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3666 w = hdac_widget_get(devinfo, i);
3667 if (w == NULL || w->enable == 0)
3669 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3670 w->param.eapdbtl == HDAC_INVALID ||
3671 w->bindas != sc->chans[pdevinfo->play].as)
3673 mask |= SOUND_MASK_OGAIN;
3678 /* Declare volume controls assigned to this association. */
3681 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3682 if (ctl->enable == 0)
3684 if ((pdevinfo->play >= 0 &&
3685 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
3686 (pdevinfo->rec >= 0 &&
3687 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
3688 (ctl->widget->bindas == -2 && pdevinfo->index == 0))
3689 mask |= ctl->ossmask;
3692 /* Declare record sources available to this association. */
3693 if (pdevinfo->rec >= 0) {
3694 struct hdac_chan *ch = &sc->chans[pdevinfo->rec];
3695 for (i = 0; ch->io[i] != -1; i++) {
3696 w = hdac_widget_get(devinfo, ch->io[i]);
3697 if (w == NULL || w->enable == 0)
3699 for (j = 0; j < w->nconns; j++) {
3700 if (w->connsenable[j] == 0)
3702 cw = hdac_widget_get(devinfo, w->conns[j]);
3703 if (cw == NULL || cw->enable == 0)
3705 if (cw->bindas != sc->chans[pdevinfo->rec].as &&
3708 recmask |= cw->ossmask;
3713 /* Declare soft PCM volume if needed. */
3714 if (pdevinfo->play >= 0) {
3716 if ((mask & SOUND_MASK_PCM) == 0 ||
3717 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) {
3719 mask |= SOUND_MASK_PCM;
3723 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3724 if (ctl->enable == 0)
3726 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as &&
3727 (ctl->widget->bindas != -2 || pdevinfo->index != 0))
3729 if (!(ctl->ossmask & SOUND_MASK_PCM))
3736 if (softpcmvol == 1 || ctl == NULL) {
3737 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL);
3739 device_printf(pdevinfo->dev,
3740 "%s Soft PCM volume\n",
3741 (softpcmvol == 1) ? "Forcing" : "Enabling");
3746 /* Declare master volume if needed. */
3747 if (pdevinfo->play >= 0) {
3748 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) ==
3750 mask |= SOUND_MASK_VOLUME;
3751 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3753 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3756 device_printf(pdevinfo->dev,
3757 "Forcing master volume with PCM\n");
3762 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3763 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3765 mix_setrecdevs(m, recmask);
3766 mix_setdevs(m, mask);
3774 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3775 unsigned left, unsigned right)
3777 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3778 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3779 struct hdac_softc *sc = devinfo->codec->sc;
3780 struct hdac_widget *w;
3781 struct hdac_audio_ctl *ctl;
3787 /* Save new values. */
3788 pdevinfo->left[dev] = left;
3789 pdevinfo->right[dev] = right;
3791 /* 'ogain' is the special case implemented with EAPD. */
3792 if (dev == SOUND_MIXER_OGAIN) {
3795 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3796 w = hdac_widget_get(devinfo, i);
3797 if (w == NULL || w->enable == 0)
3799 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3800 w->param.eapdbtl == HDAC_INVALID)
3804 if (i >= devinfo->endnode) {
3808 orig = w->param.eapdbtl;
3810 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3812 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3813 if (orig != w->param.eapdbtl) {
3816 val = w->param.eapdbtl;
3817 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3818 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3820 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3821 w->nid, val), devinfo->codec->cad);
3824 return (left | (left << 8));
3827 /* Recalculate all controls related to this OSS device. */
3829 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3830 if (ctl->enable == 0 ||
3831 !(ctl->ossmask & (1 << dev)))
3833 if (!((pdevinfo->play >= 0 &&
3834 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
3835 (pdevinfo->rec >= 0 &&
3836 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
3837 ctl->widget->bindas == -2))
3842 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) {
3843 if (ctl->ossmask & (1 << j)) {
3844 lvol = lvol * pdevinfo->left[j] / 100;
3845 rvol = rvol * pdevinfo->right[j] / 100;
3848 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0;
3849 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0;
3850 lvol = (lvol * ctl->step + 50) / 100;
3851 rvol = (rvol * ctl->step + 50) / 100;
3852 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3856 return (left | (right << 8));
3860 * Commutate specified record source.
3863 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth)
3865 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3866 struct hdac_widget *w, *cw;
3867 struct hdac_audio_ctl *ctl;
3872 if (depth > HDA_PARSE_MAXDEPTH)
3875 w = hdac_widget_get(devinfo, nid);
3876 if (w == NULL || w->enable == 0)
3879 for (i = 0; i < w->nconns; i++) {
3880 if (w->connsenable[i] == 0)
3882 cw = hdac_widget_get(devinfo, w->conns[i]);
3883 if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
3885 /* Call recursively to trace signal to it's source if needed. */
3886 if ((src & cw->ossmask) != 0) {
3887 if (cw->ossdev < 0) {
3888 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src,
3889 w->conns[i], depth + 1);
3894 /* We have two special cases: mixers and others (selectors). */
3895 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
3896 ctl = hdac_audio_ctl_amp_get(devinfo,
3897 w->nid, HDA_CTL_IN, i, 1);
3900 /* If we have input control on this node mute them
3901 * according to requested sources. */
3902 muted = (src & cw->ossmask) ? 0 : 1;
3903 if (muted != ctl->forcemute) {
3904 ctl->forcemute = muted;
3905 hdac_audio_ctl_amp_set(ctl,
3906 HDA_AMP_MUTE_DEFAULT,
3907 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
3910 device_printf(pdevinfo->dev,
3911 "Recsel (%s): nid %d source %d %s\n",
3912 hdac_audio_ctl_ossmixer_mask2allname(
3913 src, buf, sizeof(buf)),
3914 nid, i, muted?"mute":"unmute");
3919 if ((src & cw->ossmask) == 0)
3921 /* If we found requested source - select it and exit. */
3922 hdac_widget_connection_select(w, i);
3924 device_printf(pdevinfo->dev,
3925 "Recsel (%s): nid %d source %d select\n",
3926 hdac_audio_ctl_ossmixer_mask2allname(
3927 src, buf, sizeof(buf)),
3937 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3939 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3940 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3941 struct hdac_widget *w;
3942 struct hdac_softc *sc = devinfo->codec->sc;
3943 struct hdac_chan *ch;
3945 uint32_t ret = 0xffffffff;
3949 /* Commutate requested recsrc for each ADC. */
3950 ch = &sc->chans[pdevinfo->rec];
3951 for (i = 0; ch->io[i] != -1; i++) {
3952 w = hdac_widget_get(devinfo, ch->io[i]);
3953 if (w == NULL || w->enable == 0)
3955 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0);
3960 return ((ret == 0xffffffff)? 0 : ret);
3963 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3964 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3965 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3966 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3969 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3972 hdac_unsolq_task(void *context, int pending)
3974 struct hdac_softc *sc;
3976 sc = (struct hdac_softc *)context;
3979 hdac_unsolq_flush(sc);
3983 /****************************************************************************
3984 * int hdac_attach(device_t)
3986 * Attach the device into the kernel. Interrupts usually won't be enabled
3987 * when this function is called. Setup everything that doesn't require
3988 * interrupts and defer probing of codecs until interrupts are enabled.
3989 ****************************************************************************/
3991 hdac_attach(device_t dev)
3993 struct hdac_softc *sc;
3997 uint16_t class, subclass;
4001 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV);
4003 model = (uint32_t)pci_get_device(dev) << 16;
4004 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
4005 class = pci_get_class(dev);
4006 subclass = pci_get_subclass(dev);
4008 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
4009 if (hdac_devices[i].model == model) {
4013 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
4014 class == PCIC_MULTIMEDIA &&
4015 subclass == PCIS_MULTIMEDIA_HDA) {
4021 sc = device_get_softc(dev);
4022 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
4024 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
4025 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
4026 vendor = pci_get_vendor(dev);
4028 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
4029 /* Screw nx6325 - subdevice/subvendor swapped */
4030 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
4033 callout_init(&sc->poll_hda, CALLOUT_MPSAFE);
4034 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE);
4035 callout_init(&sc->poll_jack, CALLOUT_MPSAFE);
4037 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
4039 sc->poll_ticks = 1000000;
4040 sc->poll_ival = HDAC_POLL_INTERVAL;
4041 if (resource_int_value(device_get_name(dev),
4042 device_get_unit(dev), "polling", &i) == 0 && i != 0)
4048 for (i = 0; i < HDAC_CODEC_MAX; i++)
4049 sc->codecs[i] = NULL;
4051 pci_enable_busmaster(dev);
4053 if (vendor == INTEL_VENDORID) {
4055 v = pci_read_config(dev, 0x44, 1);
4056 pci_write_config(dev, 0x44, v & 0xf8, 1);
4058 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
4059 pci_read_config(dev, 0x44, 1));
4063 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI))
4064 sc->flags &= ~HDAC_F_MSI;
4066 sc->flags |= HDAC_F_MSI;
4067 if (resource_int_value(device_get_name(dev),
4068 device_get_unit(dev), "msi", &i) == 0) {
4070 sc->flags &= ~HDAC_F_MSI;
4072 sc->flags |= HDAC_F_MSI;
4075 #if defined(__i386__) || defined(__amd64__)
4076 sc->flags |= HDAC_F_DMA_NOCACHE;
4078 if (resource_int_value(device_get_name(dev),
4079 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
4081 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4084 * Try to enable PCIe snoop to avoid messing around with
4085 * uncacheable DMA attribute. Since PCIe snoop register
4086 * config is pretty much vendor specific, there are no
4087 * general solutions on how to enable it, forcing us (even
4088 * Microsoft) to enable uncacheable or write combined DMA
4091 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
4093 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
4094 if (hdac_pcie_snoop[i].vendor != vendor)
4096 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4097 if (hdac_pcie_snoop[i].reg == 0x00)
4099 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
4100 if ((v & hdac_pcie_snoop[i].enable) ==
4101 hdac_pcie_snoop[i].enable)
4103 v &= hdac_pcie_snoop[i].mask;
4104 v |= hdac_pcie_snoop[i].enable;
4105 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
4106 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
4107 if ((v & hdac_pcie_snoop[i].enable) !=
4108 hdac_pcie_snoop[i].enable) {
4111 "WARNING: Failed to enable PCIe "
4114 #if defined(__i386__) || defined(__amd64__)
4115 sc->flags |= HDAC_F_DMA_NOCACHE;
4120 #if defined(__i386__) || defined(__amd64__)
4125 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
4126 (sc->flags & HDAC_F_DMA_NOCACHE) ?
4127 "Uncacheable" : "PCIe snoop", vendor);
4130 /* Allocate resources */
4131 result = hdac_mem_alloc(sc);
4133 goto hdac_attach_fail;
4134 result = hdac_irq_alloc(sc);
4136 goto hdac_attach_fail;
4138 /* Get Capabilities */
4139 result = hdac_get_capabilities(sc);
4141 goto hdac_attach_fail;
4143 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT))
4144 sc->support_64bit = 0;
4146 /* Allocate CORB and RIRB dma memory */
4147 result = hdac_dma_alloc(sc, &sc->corb_dma,
4148 sc->corb_size * sizeof(uint32_t));
4150 goto hdac_attach_fail;
4151 result = hdac_dma_alloc(sc, &sc->rirb_dma,
4152 sc->rirb_size * sizeof(struct hdac_rirb));
4154 goto hdac_attach_fail;
4156 result = bus_dma_tag_create(
4157 bus_get_dma_tag(sc->dev), /* parent */
4158 HDAC_DMA_ALIGNMENT, /* alignment */
4160 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
4161 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
4162 BUS_SPACE_MAXADDR, /* highaddr */
4163 NULL, /* filtfunc */
4164 NULL, /* fistfuncarg */
4165 HDA_BUFSZ_MAX, /* maxsize */
4167 HDA_BUFSZ_MAX, /* maxsegsz */
4169 NULL, /* lockfunc */
4170 NULL, /* lockfuncarg */
4171 &sc->chan_dmat); /* dmat */
4173 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
4175 goto hdac_attach_fail;
4178 /* Quiesce everything */
4180 device_printf(dev, "Reset controller...\n");
4184 /* Initialize the CORB and RIRB */
4188 /* Defer remaining of initialization until interrupts are enabled */
4189 sc->intrhook.ich_func = hdac_attach2;
4190 sc->intrhook.ich_arg = (void *)sc;
4191 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
4192 sc->intrhook.ich_func = NULL;
4193 hdac_attach2((void *)sc);
4200 hdac_dma_free(sc, &sc->rirb_dma);
4201 hdac_dma_free(sc, &sc->corb_dma);
4203 snd_mtxfree(sc->lock);
4210 hdac_audio_parse(struct hdac_devinfo *devinfo)
4212 struct hdac_codec *codec = devinfo->codec;
4213 struct hdac_softc *sc = codec->sc;
4214 struct hdac_widget *w;
4219 cad = devinfo->codec->cad;
4222 res = hdac_command(sc,
4223 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
4224 devinfo->function.audio.gpio = res;
4227 device_printf(sc->dev, "GPIO: 0x%08x "
4228 "NumGPIO=%d NumGPO=%d "
4229 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
4230 devinfo->function.audio.gpio,
4231 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
4232 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
4233 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
4234 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
4235 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
4238 res = hdac_command(sc,
4239 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
4241 devinfo->function.audio.supp_stream_formats = res;
4243 res = hdac_command(sc,
4244 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
4246 devinfo->function.audio.supp_pcm_size_rate = res;
4248 res = hdac_command(sc,
4249 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
4251 devinfo->function.audio.outamp_cap = res;
4253 res = hdac_command(sc,
4254 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
4256 devinfo->function.audio.inamp_cap = res;
4258 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4259 w = hdac_widget_get(devinfo, i);
4261 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
4263 w->devinfo = devinfo;
4270 w->param.eapdbtl = HDAC_INVALID;
4271 hdac_widget_parse(w);
4277 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
4279 struct hdac_softc *sc = devinfo->codec->sc;
4280 struct hdac_audio_ctl *ctls;
4281 struct hdac_widget *w, *cw;
4282 int i, j, cnt, max, ocap, icap;
4283 int mute, offset, step, size;
4285 /* XXX This is redundant */
4287 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4288 w = hdac_widget_get(devinfo, i);
4289 if (w == NULL || w->enable == 0)
4291 if (w->param.outamp_cap != 0)
4293 if (w->param.inamp_cap != 0) {
4295 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4296 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4297 for (j = 0; j < w->nconns; j++) {
4298 cw = hdac_widget_get(devinfo,
4300 if (cw == NULL || cw->enable == 0)
4312 devinfo->function.audio.ctlcnt = max;
4317 ctls = (struct hdac_audio_ctl *)malloc(
4318 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
4322 device_printf(sc->dev, "unable to allocate ctls!\n");
4323 devinfo->function.audio.ctlcnt = 0;
4328 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4330 device_printf(sc->dev, "%s: Ctl overflow!\n",
4334 w = hdac_widget_get(devinfo, i);
4335 if (w == NULL || w->enable == 0)
4337 ocap = w->param.outamp_cap;
4338 icap = w->param.inamp_cap;
4340 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4341 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4342 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4343 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4344 /*if (offset > step) {
4346 device_printf(sc->dev,
4347 "BUGGY outamp: nid=%d "
4348 "[offset=%d > step=%d]\n",
4349 w->nid, offset, step);
4353 ctls[cnt].enable = 1;
4354 ctls[cnt].widget = w;
4355 ctls[cnt].mute = mute;
4356 ctls[cnt].step = step;
4357 ctls[cnt].size = size;
4358 ctls[cnt].offset = offset;
4359 ctls[cnt].left = offset;
4360 ctls[cnt].right = offset;
4361 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
4363 ctls[cnt].ndir = HDA_CTL_IN;
4365 ctls[cnt].ndir = HDA_CTL_OUT;
4366 ctls[cnt++].dir = HDA_CTL_OUT;
4370 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4371 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4372 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4373 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4374 /*if (offset > step) {
4376 device_printf(sc->dev,
4377 "BUGGY inamp: nid=%d "
4378 "[offset=%d > step=%d]\n",
4379 w->nid, offset, step);
4384 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4385 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4386 for (j = 0; j < w->nconns; j++) {
4388 device_printf(sc->dev,
4389 "%s: Ctl overflow!\n",
4393 cw = hdac_widget_get(devinfo,
4395 if (cw == NULL || cw->enable == 0)
4397 ctls[cnt].enable = 1;
4398 ctls[cnt].widget = w;
4399 ctls[cnt].childwidget = cw;
4400 ctls[cnt].index = j;
4401 ctls[cnt].mute = mute;
4402 ctls[cnt].step = step;
4403 ctls[cnt].size = size;
4404 ctls[cnt].offset = offset;
4405 ctls[cnt].left = offset;
4406 ctls[cnt].right = offset;
4407 ctls[cnt].ndir = HDA_CTL_IN;
4408 ctls[cnt++].dir = HDA_CTL_IN;
4413 device_printf(sc->dev,
4414 "%s: Ctl overflow!\n",
4418 ctls[cnt].enable = 1;
4419 ctls[cnt].widget = w;
4420 ctls[cnt].mute = mute;
4421 ctls[cnt].step = step;
4422 ctls[cnt].size = size;
4423 ctls[cnt].offset = offset;
4424 ctls[cnt].left = offset;
4425 ctls[cnt].right = offset;
4427 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4428 ctls[cnt].ndir = HDA_CTL_OUT;
4430 ctls[cnt].ndir = HDA_CTL_IN;
4431 ctls[cnt++].dir = HDA_CTL_IN;
4437 devinfo->function.audio.ctl = ctls;
4441 hdac_audio_as_parse(struct hdac_devinfo *devinfo)
4443 struct hdac_softc *sc = devinfo->codec->sc;
4444 struct hdac_audio_as *as;
4445 struct hdac_widget *w;
4446 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir;
4448 /* Count present associations */
4450 for (j = 1; j < 16; j++) {
4451 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4452 w = hdac_widget_get(devinfo, i);
4453 if (w == NULL || w->enable == 0)
4455 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4457 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config)
4461 if (j != 15) /* There could be many 1-pin assocs #15 */
4466 devinfo->function.audio.ascnt = max;
4471 as = (struct hdac_audio_as *)malloc(
4472 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT);
4476 device_printf(sc->dev, "unable to allocate assocs!\n");
4477 devinfo->function.audio.ascnt = 0;
4481 for (i = 0; i < max; i++) {
4487 /* Scan associations skipping as=0. */
4489 for (j = 1; j < 16; j++) {
4492 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4493 w = hdac_widget_get(devinfo, i);
4494 if (w == NULL || w->enable == 0)
4496 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4498 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config);
4499 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config);
4504 ("%s: Associations owerflow (%d of %d)",
4505 __func__, cnt, max));
4506 type = w->wclass.pin.config &
4507 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4508 /* Get pin direction. */
4509 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT ||
4510 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4511 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4512 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT ||
4513 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT)
4517 /* If this is a first pin - create new association. */
4518 if (as[cnt].pincnt == 0) {
4525 /* Check association correctness. */
4526 if (as[cnt].pins[seq] != 0) {
4527 device_printf(sc->dev, "%s: Duplicate pin %d (%d) "
4528 "in association %d! Disabling association.\n",
4529 __func__, seq, w->nid, j);
4532 if (dir != as[cnt].dir) {
4533 device_printf(sc->dev, "%s: Pin %d has wrong "
4534 "direction for association %d! Disabling "
4536 __func__, w->nid, j);
4539 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
4540 as[cnt].digital = 0;
4541 /* Headphones with seq=15 may mean redirection. */
4542 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT &&
4545 as[cnt].pins[seq] = w->nid;
4547 /* Association 15 is a multiple unassociated pins. */
4551 if (j != 15 && as[cnt].pincnt > 0) {
4552 if (hpredir && as[cnt].pincnt > 1)
4553 as[cnt].hpredir = first;
4558 device_printf(sc->dev,
4559 "%d associations found:\n", max);
4560 for (i = 0; i < max; i++) {
4561 device_printf(sc->dev,
4562 "Association %d (%d) %s%s:\n",
4563 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out",
4564 as[i].enable?"":" (disabled)");
4565 for (j = 0; j < 16; j++) {
4566 if (as[i].pins[j] == 0)
4568 device_printf(sc->dev,
4569 " Pin nid=%d seq=%d\n",
4575 devinfo->function.audio.as = as;
4578 static const struct {
4581 uint32_t set, unset;
4584 * XXX Force stereo quirk. Monoural recording / playback
4585 * on few codecs (especially ALC880) seems broken or
4586 * perhaps unsupported.
4588 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4589 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4590 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4591 HDA_QUIRK_GPIO0, 0 },
4592 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660,
4593 HDA_QUIRK_GPIO0, 0 },
4594 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4595 HDA_QUIRK_GPIO0, 0 },
4596 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4597 HDA_QUIRK_GPIO0, 0 },
4598 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4599 HDA_QUIRK_GPIO0, 0 },
4600 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4601 HDA_QUIRK_GPIO0, 0 },
4602 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4603 HDA_QUIRK_EAPDINV, 0 },
4604 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A,
4605 HDA_QUIRK_EAPDINV, 0 },
4606 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4607 HDA_QUIRK_OVREF, 0 },
4608 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4609 HDA_QUIRK_OVREF, 0 },
4610 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4611 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4612 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4613 HDA_QUIRK_GPIO1, 0 },
4614 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4615 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 },
4616 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4617 HDA_QUIRK_EAPDINV, 0 },
4618 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885,
4619 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0},
4620 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4621 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4622 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X,
4623 HDA_QUIRK_GPIO0, 0 },
4624 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X,
4625 HDA_QUIRK_GPIO2, 0 },
4626 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X,
4627 HDA_QUIRK_GPIO0, 0 },
4628 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4629 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4630 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4631 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4632 { HDA_MATCH_ALL, HDA_CODEC_CX20549,
4633 0, HDA_QUIRK_FORCESTEREO }
4635 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4638 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4640 struct hdac_widget *w;
4641 uint32_t id, subvendor;
4644 id = hdac_codec_id(devinfo->codec);
4645 subvendor = devinfo->codec->sc->pci_subvendor;
4650 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4651 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4652 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4654 if (hdac_quirks[i].set != 0)
4655 devinfo->function.audio.quirks |=
4657 if (hdac_quirks[i].unset != 0)
4658 devinfo->function.audio.quirks &=
4659 ~(hdac_quirks[i].unset);
4664 case HDA_CODEC_ALC883:
4666 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4667 * Clear vref cap for jack connectivity.
4669 w = hdac_widget_get(devinfo, 24);
4670 if (w != NULL && w->enable != 0 && w->type ==
4671 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4672 (w->wclass.pin.config &
4673 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4674 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4675 w->wclass.pin.cap &= ~(
4676 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4677 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4678 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4679 w = hdac_widget_get(devinfo, 25);
4680 if (w != NULL && w->enable != 0 && w->type ==
4681 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4682 (w->wclass.pin.config &
4683 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4684 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4685 w->wclass.pin.cap &= ~(
4686 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4687 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4688 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4690 * nid: 26 = Line-in, leave it alone.
4694 case HDA_CODEC_AD1983:
4696 * This codec has several possible usages, but none
4697 * fit the parser best. Help parser to choose better.
4699 /* Disable direct unmixed playback to get pcm volume. */
4700 w = hdac_widget_get(devinfo, 5);
4702 w->connsenable[0] = 0;
4703 w = hdac_widget_get(devinfo, 6);
4705 w->connsenable[0] = 0;
4706 w = hdac_widget_get(devinfo, 11);
4708 w->connsenable[0] = 0;
4709 /* Disable mic and line selectors. */
4710 w = hdac_widget_get(devinfo, 12);
4712 w->connsenable[1] = 0;
4713 w = hdac_widget_get(devinfo, 13);
4715 w->connsenable[1] = 0;
4716 /* Disable recording from mono playback mix. */
4717 w = hdac_widget_get(devinfo, 20);
4719 w->connsenable[3] = 0;
4721 case HDA_CODEC_AD1986A:
4723 * This codec has overcomplicated input mixing.
4724 * Make some cleaning there.
4726 /* Disable input mono mixer. Not needed and not supported. */
4727 w = hdac_widget_get(devinfo, 43);
4730 /* Disable any with any input mixing mesh. Use separately. */
4731 w = hdac_widget_get(devinfo, 39);
4734 w = hdac_widget_get(devinfo, 40);
4737 w = hdac_widget_get(devinfo, 41);
4740 w = hdac_widget_get(devinfo, 42);
4743 /* Disable duplicate mixer node connector. */
4744 w = hdac_widget_get(devinfo, 15);
4746 w->connsenable[3] = 0;
4747 /* There is only one mic preamplifier, use it effectively. */
4748 w = hdac_widget_get(devinfo, 31);
4750 if ((w->wclass.pin.config &
4751 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
4752 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
4753 w = hdac_widget_get(devinfo, 16);
4755 w->connsenable[2] = 0;
4757 w = hdac_widget_get(devinfo, 15);
4759 w->connsenable[0] = 0;
4762 w = hdac_widget_get(devinfo, 32);
4764 if ((w->wclass.pin.config &
4765 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
4766 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
4767 w = hdac_widget_get(devinfo, 16);
4769 w->connsenable[0] = 0;
4771 w = hdac_widget_get(devinfo, 15);
4773 w->connsenable[1] = 0;
4777 if (subvendor == ASUS_A8X_SUBVENDOR) {
4779 * This is just plain ridiculous.. There
4780 * are several A8 series that share the same
4781 * pci id but works differently (EAPD).
4783 w = hdac_widget_get(devinfo, 26);
4784 if (w != NULL && w->type ==
4785 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4786 (w->wclass.pin.config &
4787 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) !=
4788 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
4789 devinfo->function.audio.quirks &=
4793 case HDA_CODEC_AD1981HD:
4795 * This codec has very unusual design with several
4796 * points inappropriate for the present parser.
4798 /* Disable recording from mono playback mix. */
4799 w = hdac_widget_get(devinfo, 21);
4801 w->connsenable[3] = 0;
4802 /* Disable rear to front mic mixer, use separately. */
4803 w = hdac_widget_get(devinfo, 31);
4806 /* Disable playback mixer, use direct bypass. */
4807 w = hdac_widget_get(devinfo, 14);
4815 * Trace path from DAC to pin.
4818 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid,
4819 int dupseq, int min, int only, int depth)
4821 struct hdac_widget *w;
4825 if (depth > HDA_PARSE_MAXDEPTH)
4827 w = hdac_widget_get(devinfo, nid);
4828 if (w == NULL || w->enable == 0)
4832 device_printf(devinfo->codec->sc->dev,
4833 " %*stracing via nid %d\n",
4834 depth + 1, "", w->nid);
4837 /* Use only unused widgets */
4838 if (w->bindas >= 0 && w->bindas != as) {
4841 device_printf(devinfo->codec->sc->dev,
4842 " %*snid %d busy by association %d\n",
4843 depth + 1, "", w->nid, w->bindas);
4849 if (w->bindseqmask != 0) {
4852 device_printf(devinfo->codec->sc->dev,
4853 " %*snid %d busy by seqmask %x\n",
4854 depth + 1, "", w->nid, w->bindseqmask);
4860 /* If this is headphones - allow duplicate first pin. */
4861 if (w->bindseqmask != 0 &&
4862 (w->bindseqmask & (1 << dupseq)) == 0) {
4864 device_printf(devinfo->codec->sc->dev,
4865 " %*snid %d busy by seqmask %x\n",
4866 depth + 1, "", w->nid, w->bindseqmask);
4873 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4874 /* Do not traverse input. AD1988 has digital monitor
4875 for which we are not ready. */
4877 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4878 /* If we are tracing HP take only dac of first pin. */
4879 if ((only == 0 || only == w->nid) &&
4880 (w->nid >= min) && (dupseq < 0 || w->nid ==
4881 devinfo->function.audio.as[as].dacs[dupseq]))
4884 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4889 /* Find reachable DACs with smallest nid respecting constraints. */
4890 for (i = 0; i < w->nconns; i++) {
4891 if (w->connsenable[i] == 0)
4893 if (w->selconn != -1 && w->selconn != i)
4895 if ((ret = hdac_audio_trace_dac(devinfo, as, seq,
4896 w->conns[i], dupseq, min, only, depth + 1)) != 0) {
4897 if (m == 0 || ret < m) {
4901 if (only || dupseq >= 0)
4905 if (m && only && ((w->nconns > 1 &&
4906 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
4907 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4913 w->bindseqmask |= (1 << seq);
4917 device_printf(devinfo->codec->sc->dev,
4918 " %*snid %d returned %d\n",
4919 depth + 1, "", w->nid, m);
4926 * Trace path from widget to ADC.
4929 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid,
4930 int only, int depth)
4932 struct hdac_widget *w, *wc;
4936 if (depth > HDA_PARSE_MAXDEPTH)
4938 w = hdac_widget_get(devinfo, nid);
4939 if (w == NULL || w->enable == 0)
4942 device_printf(devinfo->codec->sc->dev,
4943 " %*stracing via nid %d\n",
4944 depth + 1, "", w->nid);
4946 /* Use only unused widgets */
4947 if (w->bindas >= 0 && w->bindas != as) {
4949 device_printf(devinfo->codec->sc->dev,
4950 " %*snid %d busy by association %d\n",
4951 depth + 1, "", w->nid, w->bindas);
4957 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4958 /* If we are tracing HP take only dac of first pin. */
4962 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4967 /* Try to find reachable ADCs with specified nid. */
4968 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
4969 wc = hdac_widget_get(devinfo, j);
4970 if (wc == NULL || wc->enable == 0)
4972 for (i = 0; i < wc->nconns; i++) {
4973 if (wc->connsenable[i] == 0)
4975 if (wc->conns[i] != nid)
4977 if (hdac_audio_trace_adc(devinfo, as, seq,
4978 j, only, depth + 1) != 0) {
4980 if (((wc->nconns > 1 &&
4981 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
4982 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) &&
4992 w->bindseqmask |= (1 << seq);
4995 device_printf(devinfo->codec->sc->dev,
4996 " %*snid %d returned %d\n",
4997 depth + 1, "", w->nid, res);
5003 * Erase trace path of the specified association.
5006 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq)
5008 struct hdac_widget *w;
5011 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5012 w = hdac_widget_get(devinfo, i);
5013 if (w == NULL || w->enable == 0)
5015 if (w->bindas == as) {
5017 w->bindseqmask &= ~(1 << seq);
5018 if (w->bindseqmask == 0) {
5032 * Trace association path from DAC to output
5035 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq)
5037 struct hdac_audio_as *ases = devinfo->function.audio.as;
5042 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++)
5044 /* Check if there is no any left. If so - we succeeded. */
5048 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1;
5053 device_printf(devinfo->codec->sc->dev,
5054 " Tracing pin %d with min nid %d",
5055 ases[as].pins[i], min);
5057 printf(" and hpredir %d", hpredir);
5060 /* Trace this pin taking min nid into account. */
5061 res = hdac_audio_trace_dac(devinfo, as, i,
5062 ases[as].pins[i], hpredir, min, 0, 0);
5064 /* If we failed - return to previous and redo it. */
5066 device_printf(devinfo->codec->sc->dev,
5067 " Unable to trace pin %d seq %d with min "
5069 ases[as].pins[i], i, min);
5071 printf(" and hpredir %d", hpredir);
5077 device_printf(devinfo->codec->sc->dev,
5078 " Pin %d traced to DAC %d",
5079 ases[as].pins[i], res);
5081 printf(" and hpredir %d", hpredir);
5082 if (ases[as].fakeredir)
5083 printf(" with fake redirection");
5086 /* Trace again to mark the path */
5087 hdac_audio_trace_dac(devinfo, as, i,
5088 ases[as].pins[i], hpredir, min, res, 0);
5089 ases[as].dacs[i] = res;
5090 /* We succeeded, so call next. */
5091 if (hdac_audio_trace_as_out(devinfo, as, i + 1))
5093 /* If next failed, we should retry with next min */
5094 hdac_audio_undo_trace(devinfo, as, i);
5095 ases[as].dacs[i] = 0;
5101 * Trace association path from input to ADC
5104 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as)
5106 struct hdac_audio_as *ases = devinfo->function.audio.as;
5107 struct hdac_widget *w;
5110 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5111 w = hdac_widget_get(devinfo, j);
5112 if (w == NULL || w->enable == 0)
5114 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
5116 if (w->bindas >= 0 && w->bindas != as)
5120 for (i = 0; i < 16; i++) {
5121 if (ases[as].pins[i] == 0)
5125 device_printf(devinfo->codec->sc->dev,
5126 " Tracing pin %d to ADC %d\n",
5127 ases[as].pins[i], j);
5129 /* Trace this pin taking goal into account. */
5130 if (hdac_audio_trace_adc(devinfo, as, i,
5131 ases[as].pins[i], j, 0) == 0) {
5132 /* If we failed - return to previous and redo it. */
5134 device_printf(devinfo->codec->sc->dev,
5135 " Unable to trace pin %d to ADC %d, undo traces\n",
5136 ases[as].pins[i], j);
5138 hdac_audio_undo_trace(devinfo, as, -1);
5139 for (k = 0; k < 16; k++)
5140 ases[as].dacs[k] = 0;
5144 device_printf(devinfo->codec->sc->dev,
5145 " Pin %d traced to ADC %d\n",
5146 ases[as].pins[i], j);
5148 ases[as].dacs[i] = j;
5157 * Trace input monitor path from mixer to output association.
5160 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5162 struct hdac_audio_as *ases = devinfo->function.audio.as;
5163 struct hdac_widget *w, *wc;
5167 if (depth > HDA_PARSE_MAXDEPTH)
5169 w = hdac_widget_get(devinfo, nid);
5170 if (w == NULL || w->enable == 0)
5173 device_printf(devinfo->codec->sc->dev,
5174 " %*stracing via nid %d\n",
5175 depth + 1, "", w->nid);
5177 /* Use only unused widgets */
5178 if (depth > 0 && w->bindas != -1) {
5179 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) {
5181 device_printf(devinfo->codec->sc->dev,
5182 " %*snid %d found output association %d\n",
5183 depth + 1, "", w->nid, w->bindas);
5188 device_printf(devinfo->codec->sc->dev,
5189 " %*snid %d busy by input association %d\n",
5190 depth + 1, "", w->nid, w->bindas);
5197 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5198 /* Do not traverse input. AD1988 has digital monitor
5199 for which we are not ready. */
5201 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5206 /* Try to find reachable ADCs with specified nid. */
5207 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5208 wc = hdac_widget_get(devinfo, j);
5209 if (wc == NULL || wc->enable == 0)
5211 for (i = 0; i < wc->nconns; i++) {
5212 if (wc->connsenable[i] == 0)
5214 if (wc->conns[i] != nid)
5216 if (hdac_audio_trace_to_out(devinfo,
5217 j, depth + 1) != 0) {
5219 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5231 device_printf(devinfo->codec->sc->dev,
5232 " %*snid %d returned %d\n",
5233 depth + 1, "", w->nid, res);
5239 * Trace extra associations (beeper, monitor)
5242 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo)
5244 struct hdac_audio_as *as = devinfo->function.audio.as;
5245 struct hdac_widget *w;
5249 /* Find mixer associated with input, but supplying signal
5250 for output associations. Hope it will be input monitor. */
5252 device_printf(devinfo->codec->sc->dev,
5253 "Tracing input monitor\n");
5255 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5256 w = hdac_widget_get(devinfo, j);
5257 if (w == NULL || w->enable == 0)
5259 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5261 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN)
5264 device_printf(devinfo->codec->sc->dev,
5265 " Tracing nid %d to out\n",
5268 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5270 device_printf(devinfo->codec->sc->dev,
5271 " nid %d is input monitor\n",
5274 w->pflags |= HDA_ADC_MONITOR;
5275 w->ossdev = SOUND_MIXER_IMIX;
5281 device_printf(devinfo->codec->sc->dev,
5282 "Tracing beeper\n");
5284 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5285 w = hdac_widget_get(devinfo, j);
5286 if (w == NULL || w->enable == 0)
5288 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET)
5291 device_printf(devinfo->codec->sc->dev,
5292 " Tracing nid %d to out\n",
5295 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5297 device_printf(devinfo->codec->sc->dev,
5298 " nid %d traced to out\n",
5307 * Bind assotiations to PCM channels
5310 hdac_audio_bind_as(struct hdac_devinfo *devinfo)
5312 struct hdac_softc *sc = devinfo->codec->sc;
5313 struct hdac_audio_as *as = devinfo->function.audio.as;
5314 int j, cnt = 0, free;
5316 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
5320 if (sc->num_chans == 0) {
5321 sc->chans = (struct hdac_chan *)malloc(
5322 sizeof(struct hdac_chan) * cnt,
5323 M_HDAC, M_ZERO | M_NOWAIT);
5324 if (sc->chans == NULL) {
5325 device_printf(sc->dev,
5326 "Channels memory allocation failed!\n");
5330 sc->chans = (struct hdac_chan *)realloc(sc->chans,
5331 sizeof(struct hdac_chan) * (sc->num_chans + cnt),
5332 M_HDAC, M_ZERO | M_NOWAIT);
5333 if (sc->chans == NULL) {
5335 device_printf(sc->dev,
5336 "Channels memory allocation failed!\n");
5339 /* Fixup relative pointers after realloc */
5340 for (j = 0; j < sc->num_chans; j++)
5341 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist;
5343 free = sc->num_chans;
5344 sc->num_chans += cnt;
5346 for (j = free; j < free + cnt; j++) {
5347 sc->chans[j].devinfo = devinfo;
5348 sc->chans[j].as = -1;
5351 /* Assign associations in order of their numbers, */
5352 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
5353 if (as[j].enable == 0)
5357 sc->chans[free].as = j;
5358 sc->chans[free].dir =
5359 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY;
5360 hdac_pcmchannel_setup(&sc->chans[free]);
5366 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo)
5368 struct hdac_widget *w;
5371 /* Disable power and volume widgets. */
5372 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5373 w = hdac_widget_get(devinfo, i);
5374 if (w == NULL || w->enable == 0)
5376 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET ||
5377 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) {
5380 device_printf(devinfo->codec->sc->dev,
5381 " Disabling nid %d due to it's"
5382 " non-audio type.\n",
5390 hdac_audio_disable_useless(struct hdac_devinfo *devinfo)
5392 struct hdac_widget *w, *cw;
5393 struct hdac_audio_ctl *ctl;
5394 int done, found, i, j, k;
5396 /* Disable useless pins. */
5397 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5398 w = hdac_widget_get(devinfo, i);
5399 if (w == NULL || w->enable == 0)
5401 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5402 if ((w->wclass.pin.config &
5403 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
5404 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) {
5407 device_printf(devinfo->codec->sc->dev,
5408 " Disabling pin nid %d due"
5409 " to None connectivity.\n",
5412 } else if ((w->wclass.pin.config &
5413 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) {
5416 device_printf(devinfo->codec->sc->dev,
5417 " Disabling unassociated"
5426 /* Disable and mute controls for disabled widgets. */
5428 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5429 if (ctl->enable == 0)
5431 if (ctl->widget->enable == 0 ||
5432 (ctl->childwidget != NULL &&
5433 ctl->childwidget->enable == 0)) {
5435 ctl->muted = HDA_AMP_MUTE_ALL;
5439 if (ctl->ndir == HDA_CTL_IN)
5440 ctl->widget->connsenable[ctl->index] = 0;
5443 device_printf(devinfo->codec->sc->dev,
5444 " Disabling ctl %d nid %d cnid %d due"
5445 " to disabled widget.\n", i,
5447 (ctl->childwidget != NULL)?
5448 ctl->childwidget->nid:-1);
5452 /* Disable useless widgets. */
5453 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5454 w = hdac_widget_get(devinfo, i);
5455 if (w == NULL || w->enable == 0)
5457 /* Disable inputs with disabled child widgets. */
5458 for (j = 0; j < w->nconns; j++) {
5459 if (w->connsenable[j]) {
5460 cw = hdac_widget_get(devinfo, w->conns[j]);
5461 if (cw == NULL || cw->enable == 0) {
5462 w->connsenable[j] = 0;
5464 device_printf(devinfo->codec->sc->dev,
5465 " Disabling nid %d connection %d due"
5466 " to disabled child widget.\n",
5472 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5473 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5475 /* Disable mixers and selectors without inputs. */
5477 for (j = 0; j < w->nconns; j++) {
5478 if (w->connsenable[j]) {
5487 device_printf(devinfo->codec->sc->dev,
5488 " Disabling nid %d due to all it's"
5489 " inputs disabled.\n", w->nid);
5492 /* Disable nodes without consumers. */
5493 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5494 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5497 for (k = devinfo->startnode; k < devinfo->endnode; k++) {
5498 cw = hdac_widget_get(devinfo, k);
5499 if (cw == NULL || cw->enable == 0)
5501 for (j = 0; j < cw->nconns; j++) {
5502 if (cw->connsenable[j] && cw->conns[j] == i) {
5512 device_printf(devinfo->codec->sc->dev,
5513 " Disabling nid %d due to all it's"
5514 " consumers disabled.\n", w->nid);
5518 } while (done == 0);
5523 hdac_audio_disable_unas(struct hdac_devinfo *devinfo)
5525 struct hdac_audio_as *as = devinfo->function.audio.as;
5526 struct hdac_widget *w, *cw;
5527 struct hdac_audio_ctl *ctl;
5530 /* Disable unassosiated widgets. */
5531 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5532 w = hdac_widget_get(devinfo, i);
5533 if (w == NULL || w->enable == 0)
5535 if (w->bindas == -1) {
5538 device_printf(devinfo->codec->sc->dev,
5539 " Disabling unassociated nid %d.\n",
5544 /* Disable input connections on input pin and
5545 * output on output. */
5546 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5547 w = hdac_widget_get(devinfo, i);
5548 if (w == NULL || w->enable == 0)
5550 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5554 if (as[w->bindas].dir == HDA_CTL_IN) {
5555 for (j = 0; j < w->nconns; j++) {
5556 if (w->connsenable[j] == 0)
5558 w->connsenable[j] = 0;
5560 device_printf(devinfo->codec->sc->dev,
5561 " Disabling connection to input pin "
5562 "nid %d conn %d.\n",
5566 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5568 if (ctl && ctl->enable) {
5570 ctl->muted = HDA_AMP_MUTE_ALL;
5576 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5577 HDA_CTL_OUT, -1, 1);
5578 if (ctl && ctl->enable) {
5580 ctl->muted = HDA_AMP_MUTE_ALL;
5585 for (k = devinfo->startnode; k < devinfo->endnode; k++) {
5586 cw = hdac_widget_get(devinfo, k);
5587 if (cw == NULL || cw->enable == 0)
5589 for (j = 0; j < cw->nconns; j++) {
5590 if (cw->connsenable[j] && cw->conns[j] == i) {
5591 cw->connsenable[j] = 0;
5593 device_printf(devinfo->codec->sc->dev,
5594 " Disabling connection from output pin "
5595 "nid %d conn %d cnid %d.\n",
5598 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
5601 ctl = hdac_audio_ctl_amp_get(devinfo, k,
5603 if (ctl && ctl->enable) {
5605 ctl->muted = HDA_AMP_MUTE_ALL;
5618 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo)
5620 struct hdac_audio_as *as = devinfo->function.audio.as;
5621 struct hdac_widget *w;
5624 /* On playback path we can safely disable all unseleted inputs. */
5625 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5626 w = hdac_widget_get(devinfo, i);
5627 if (w == NULL || w->enable == 0)
5631 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5633 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN)
5635 for (j = 0; j < w->nconns; j++) {
5636 if (w->connsenable[j] == 0)
5638 if (w->selconn < 0 || w->selconn == j)
5640 w->connsenable[j] = 0;
5642 device_printf(devinfo->codec->sc->dev,
5643 " Disabling unselected connection "
5644 "nid %d conn %d.\n",
5652 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo)
5654 struct hdac_widget *w, *cw;
5655 struct hdac_audio_ctl *ctl;
5658 /* Disable crossassociatement and unwanted crosschannel connections. */
5659 /* ... using selectors */
5660 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5661 w = hdac_widget_get(devinfo, i);
5662 if (w == NULL || w->enable == 0)
5666 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5668 if (w->bindas == -2)
5670 for (j = 0; j < w->nconns; j++) {
5671 if (w->connsenable[j] == 0)
5673 cw = hdac_widget_get(devinfo, w->conns[j]);
5674 if (cw == NULL || w->enable == 0)
5676 if (cw->bindas == -2)
5678 if (w->bindas == cw->bindas &&
5679 (w->bindseqmask & cw->bindseqmask) != 0)
5681 w->connsenable[j] = 0;
5683 device_printf(devinfo->codec->sc->dev,
5684 " Disabling crossassociatement connection "
5685 "nid %d conn %d cnid %d.\n",
5690 /* ... using controls */
5692 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5693 if (ctl->enable == 0 || ctl->childwidget == NULL)
5695 if (ctl->widget->bindas == -2 ||
5696 ctl->childwidget->bindas == -2)
5698 if (ctl->widget->bindas != ctl->childwidget->bindas ||
5699 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) {
5701 ctl->muted = HDA_AMP_MUTE_ALL;
5705 if (ctl->ndir == HDA_CTL_IN)
5706 ctl->widget->connsenable[ctl->index] = 0;
5708 device_printf(devinfo->codec->sc->dev,
5709 " Disabling crossassociatement connection "
5710 "ctl %d nid %d cnid %d.\n", i,
5712 ctl->childwidget->nid);
5719 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0)
5722 * Find controls to control amplification for source.
5725 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index,
5726 int ossdev, int ctlable, int depth, int need)
5728 struct hdac_widget *w, *wc;
5729 struct hdac_audio_ctl *ctl;
5730 int i, j, conns = 0, rneed;
5732 if (depth > HDA_PARSE_MAXDEPTH)
5735 w = hdac_widget_get(devinfo, nid);
5736 if (w == NULL || w->enable == 0)
5739 /* Count number of active inputs. */
5741 for (j = 0; j < w->nconns; j++) {
5742 if (w->connsenable[j])
5747 /* If this is not a first step - use input mixer.
5748 Pins have common input ctl so care must be taken. */
5749 if (depth > 0 && ctlable && (conns == 1 ||
5750 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) {
5751 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN,
5754 if (HDA_CTL_GIVE(ctl) & need)
5755 ctl->ossmask |= (1 << ossdev);
5757 ctl->possmask |= (1 << ossdev);
5758 need &= ~HDA_CTL_GIVE(ctl);
5762 /* If widget has own ossdev - not traverse it.
5763 It will be traversed on it's own. */
5764 if (w->ossdev >= 0 && depth > 0)
5767 /* We must not traverse pin */
5768 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
5769 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5773 /* record that this widget exports such signal, */
5774 w->ossmask |= (1 << ossdev);
5776 /* If signals mixed, we can't assign controls farther.
5777 * Ignore this on depth zero. Caller must knows why.
5778 * Ignore this for static selectors if this input selected.
5784 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1);
5786 if (HDA_CTL_GIVE(ctl) & need)
5787 ctl->ossmask |= (1 << ossdev);
5789 ctl->possmask |= (1 << ossdev);
5790 need &= ~HDA_CTL_GIVE(ctl);
5795 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5796 wc = hdac_widget_get(devinfo, i);
5797 if (wc == NULL || wc->enable == 0)
5799 for (j = 0; j < wc->nconns; j++) {
5800 if (wc->connsenable[j] && wc->conns[j] == nid) {
5801 rneed |= hdac_audio_ctl_source_amp(devinfo,
5802 wc->nid, j, ossdev, ctlable, depth + 1, need);
5812 * Find controls to control amplification for destination.
5815 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid,
5816 int ossdev, int depth, int need)
5818 struct hdac_audio_as *as = devinfo->function.audio.as;
5819 struct hdac_widget *w, *wc;
5820 struct hdac_audio_ctl *ctl;
5821 int i, j, consumers;
5823 if (depth > HDA_PARSE_MAXDEPTH)
5826 w = hdac_widget_get(devinfo, nid);
5827 if (w == NULL || w->enable == 0)
5831 /* If this node produce output for several consumers,
5832 we can't touch it. */
5834 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5835 wc = hdac_widget_get(devinfo, i);
5836 if (wc == NULL || wc->enable == 0)
5838 for (j = 0; j < wc->nconns; j++) {
5839 if (wc->connsenable[j] && wc->conns[j] == nid)
5843 /* The only exception is if real HP redirection is configured
5844 and this is a duplication point.
5845 XXX: Actually exception is not completely correct.
5846 XXX: Duplication point check is not perfect. */
5847 if ((consumers == 2 && (w->bindas < 0 ||
5848 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir ||
5849 (w->bindseqmask & (1 << 15)) == 0)) ||
5853 /* Else use it's output mixer. */
5854 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5855 HDA_CTL_OUT, -1, 1);
5857 if (HDA_CTL_GIVE(ctl) & need)
5858 ctl->ossmask |= (1 << ossdev);
5860 ctl->possmask |= (1 << ossdev);
5861 need &= ~HDA_CTL_GIVE(ctl);
5865 /* We must not traverse pin */
5866 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
5870 for (i = 0; i < w->nconns; i++) {
5872 if (w->connsenable[i] == 0)
5874 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5877 if (HDA_CTL_GIVE(ctl) & tneed)
5878 ctl->ossmask |= (1 << ossdev);
5880 ctl->possmask |= (1 << ossdev);
5881 tneed &= ~HDA_CTL_GIVE(ctl);
5883 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev,
5889 * Assign OSS names to sound sources
5892 hdac_audio_assign_names(struct hdac_devinfo *devinfo)
5894 struct hdac_audio_as *as = devinfo->function.audio.as;
5895 struct hdac_widget *w;
5897 int type = -1, use, used = 0;
5898 static const int types[7][13] = {
5899 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2,
5900 SOUND_MIXER_LINE3, -1 }, /* line */
5901 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */
5902 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */
5903 { SOUND_MIXER_CD, -1 }, /* cd */
5904 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */
5905 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3,
5907 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2,
5908 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT,
5909 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1,
5910 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR,
5914 /* Surely known names */
5915 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5916 w = hdac_widget_get(devinfo, i);
5917 if (w == NULL || w->enable == 0)
5919 if (w->bindas == -1)
5923 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5924 if (as[w->bindas].dir == HDA_CTL_OUT)
5927 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
5928 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
5931 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
5932 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK)
5933 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
5937 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
5940 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
5943 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
5944 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
5951 while (types[type][j] >= 0 &&
5952 (used & (1 << types[type][j])) != 0) {
5955 if (types[type][j] >= 0)
5956 use = types[type][j];
5958 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
5959 use = SOUND_MIXER_PCM;
5961 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
5962 use = SOUND_MIXER_SPEAKER;
5972 /* Semi-known names */
5973 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5974 w = hdac_widget_get(devinfo, i);
5975 if (w == NULL || w->enable == 0)
5979 if (w->bindas == -1)
5981 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5983 if (as[w->bindas].dir == HDA_CTL_OUT)
5986 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
5987 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
5988 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
5989 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
5990 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
5993 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
5996 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
5997 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
6004 while (types[type][j] >= 0 &&
6005 (used & (1 << types[type][j])) != 0) {
6008 if (types[type][j] >= 0) {
6009 w->ossdev = types[type][j];
6010 used |= (1 << types[type][j]);
6014 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6015 w = hdac_widget_get(devinfo, i);
6016 if (w == NULL || w->enable == 0)
6020 if (w->bindas == -1)
6022 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6024 if (as[w->bindas].dir == HDA_CTL_OUT)
6027 while (types[6][j] >= 0 &&
6028 (used & (1 << types[6][j])) != 0) {
6031 if (types[6][j] >= 0) {
6032 w->ossdev = types[6][j];
6033 used |= (1 << types[6][j]);
6039 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
6041 struct hdac_audio_as *as = devinfo->function.audio.as;
6044 /* Trace all associations in order of their numbers, */
6045 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
6046 if (as[j].enable == 0)
6049 device_printf(devinfo->codec->sc->dev,
6050 "Tracing association %d (%d)\n", j, as[j].index);
6052 if (as[j].dir == HDA_CTL_OUT) {
6054 res = hdac_audio_trace_as_out(devinfo, j, 0);
6055 if (res == 0 && as[j].hpredir >= 0 &&
6056 as[j].fakeredir == 0) {
6057 /* If codec can't do analog HP redirection
6058 try to make it using one more DAC. */
6059 as[j].fakeredir = 1;
6063 res = hdac_audio_trace_as_in(devinfo, j);
6067 device_printf(devinfo->codec->sc->dev,
6068 "Association %d (%d) trace succeeded\n",
6073 device_printf(devinfo->codec->sc->dev,
6074 "Association %d (%d) trace failed\n",
6081 /* Trace mixer and beeper pseudo associations. */
6082 hdac_audio_trace_as_extra(devinfo);
6086 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo)
6088 struct hdac_audio_as *as = devinfo->function.audio.as;
6089 struct hdac_audio_ctl *ctl;
6090 struct hdac_widget *w;
6093 /* Assign mixers to the tree. */
6094 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6095 w = hdac_widget_get(devinfo, i);
6096 if (w == NULL || w->enable == 0)
6098 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
6099 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET ||
6100 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6101 as[w->bindas].dir == HDA_CTL_IN)) {
6104 hdac_audio_ctl_source_amp(devinfo, w->nid, -1,
6105 w->ossdev, 1, 0, 1);
6106 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) {
6109 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1,
6110 w->ossdev, 1, 0, 1)) {
6111 /* If we are unable to control input monitor
6112 as source - try to control it as destination. */
6113 hdac_audio_ctl_dest_amp(devinfo, w->nid,
6116 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
6117 hdac_audio_ctl_dest_amp(devinfo, w->nid,
6118 SOUND_MIXER_RECLEV, 0, 1);
6119 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6120 as[w->bindas].dir == HDA_CTL_OUT) {
6121 hdac_audio_ctl_dest_amp(devinfo, w->nid,
6122 SOUND_MIXER_VOLUME, 0, 1);
6125 /* Treat unrequired as possible. */
6127 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6128 if (ctl->ossmask == 0)
6129 ctl->ossmask = ctl->possmask;
6134 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo)
6136 struct hdac_audio_as *as = devinfo->function.audio.as;
6137 struct hdac_widget *w;
6141 for (i = 0; i < devinfo->nodecnt; i++) {
6142 w = &devinfo->widget[i];
6145 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6148 pincap = w->wclass.pin.cap;
6150 /* Disable everything. */
6151 w->wclass.pin.ctrl &= ~(
6152 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
6153 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
6154 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
6155 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
6157 if (w->enable == 0 ||
6158 w->bindas < 0 || as[w->bindas].enable == 0) {
6159 /* Pin is unused so left it disabled. */
6161 } else if (as[w->bindas].dir == HDA_CTL_IN) {
6162 /* Input pin, configure for input. */
6163 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
6164 w->wclass.pin.ctrl |=
6165 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
6167 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
6168 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6169 w->wclass.pin.ctrl |=
6170 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6171 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
6172 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
6173 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6174 w->wclass.pin.ctrl |=
6175 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6176 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
6177 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
6178 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6179 w->wclass.pin.ctrl |=
6180 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6181 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
6183 /* Output pin, configure for output. */
6184 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
6185 w->wclass.pin.ctrl |=
6186 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
6188 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) &&
6189 (w->wclass.pin.config &
6190 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
6191 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
6192 w->wclass.pin.ctrl |=
6193 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
6195 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
6196 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6197 w->wclass.pin.ctrl |=
6198 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6199 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
6200 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
6201 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6202 w->wclass.pin.ctrl |=
6203 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6204 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
6205 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
6206 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6207 w->wclass.pin.ctrl |=
6208 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6209 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
6215 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
6217 struct hdac_audio_ctl *ctl;
6221 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6222 if (ctl->enable == 0 || ctl->ossmask != 0) {
6223 /* Mute disabled and mixer controllable controls.
6224 * Last will be initialized by mixer_init().
6225 * This expected to reduce click on startup. */
6226 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0);
6229 /* Init fixed controls to 0dB amplification. */
6233 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z);
6238 hdac_audio_commit(struct hdac_devinfo *devinfo)
6240 struct hdac_softc *sc = devinfo->codec->sc;
6241 struct hdac_widget *w;
6243 uint32_t gdata, gmask, gdir;
6244 int commitgpio, numgpio;
6247 cad = devinfo->codec->cad;
6249 if (sc->pci_subvendor == APPLE_INTEL_MAC)
6250 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
6253 /* Commit controls. */
6254 hdac_audio_ctl_commit(devinfo);
6256 /* Commit selectors, pins and EAPD. */
6257 for (i = 0; i < devinfo->nodecnt; i++) {
6258 w = &devinfo->widget[i];
6261 if (w->selconn == -1)
6264 hdac_widget_connection_select(w, w->selconn);
6265 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
6267 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
6268 w->wclass.pin.ctrl), cad);
6270 if (w->param.eapdbtl != HDAC_INVALID) {
6273 val = w->param.eapdbtl;
6274 if (devinfo->function.audio.quirks &
6276 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
6278 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
6288 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
6289 devinfo->function.audio.gpio);
6291 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
6292 commitgpio = (numgpio > 0) ? 1 : 0;
6294 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
6295 if (!(devinfo->function.audio.quirks &
6298 if (commitgpio == 0) {
6301 gdata = hdac_command(sc,
6302 HDA_CMD_GET_GPIO_DATA(cad,
6303 devinfo->nid), cad);
6304 gmask = hdac_command(sc,
6305 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
6306 devinfo->nid), cad);
6307 gdir = hdac_command(sc,
6308 HDA_CMD_GET_GPIO_DIRECTION(cad,
6309 devinfo->nid), cad);
6310 device_printf(sc->dev,
6311 "GPIO init: data=0x%08x "
6312 "mask=0x%08x dir=0x%08x\n",
6313 gdata, gmask, gdir);
6325 if (commitgpio != 0) {
6327 device_printf(sc->dev,
6328 "GPIO commit: data=0x%08x mask=0x%08x "
6330 gdata, gmask, gdir);
6333 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
6336 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
6339 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
6345 hdac_powerup(struct hdac_devinfo *devinfo)
6347 struct hdac_softc *sc = devinfo->codec->sc;
6348 nid_t cad = devinfo->codec->cad;
6352 HDA_CMD_SET_POWER_STATE(cad,
6353 devinfo->nid, HDA_CMD_POWER_STATE_D0),
6357 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6359 HDA_CMD_SET_POWER_STATE(cad,
6360 i, HDA_CMD_POWER_STATE_D0),
6367 hdac_pcmchannel_setup(struct hdac_chan *ch)
6369 struct hdac_devinfo *devinfo = ch->devinfo;
6370 struct hdac_audio_as *as = devinfo->function.audio.as;
6371 struct hdac_widget *w;
6372 uint32_t cap, fmtcap, pcmcap;
6375 ch->caps = hdac_caps;
6376 ch->caps.fmtlist = ch->fmtlist;
6379 ch->pcmrates[0] = 48000;
6380 ch->pcmrates[1] = 0;
6383 fmtcap = devinfo->function.audio.supp_stream_formats;
6384 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
6385 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
6387 for (i = 0; i < 16 && ret < max; i++) {
6388 /* Check as is correct */
6391 /* Cound only present DACs */
6392 if (as[ch->as].dacs[i] <= 0)
6394 /* Ignore duplicates */
6395 for (j = 0; j < ret; j++) {
6396 if (ch->io[j] == as[ch->as].dacs[i])
6402 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]);
6403 if (w == NULL || w->enable == 0)
6405 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap))
6407 cap = w->param.supp_stream_formats;
6408 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
6410 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) &&
6411 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
6413 /* Many codec does not declare AC3 support on SPDIF.
6414 I don't beleave that they doesn't support it! */
6415 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6416 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK;
6419 pcmcap = w->param.supp_pcm_size_rate;
6422 pcmcap &= w->param.supp_pcm_size_rate;
6424 ch->io[ret++] = as[ch->as].dacs[i];
6428 ch->supp_stream_formats = fmtcap;
6429 ch->supp_pcm_size_rate = pcmcap;
6440 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) {
6441 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap))
6443 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap))
6445 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap))
6447 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap))
6449 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap))
6451 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
6453 SND_FORMAT(AFMT_S16_LE, 1, 0);
6454 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0);
6455 if (ch->bit32 > 0) {
6456 if (!(devinfo->function.audio.quirks &
6457 HDA_QUIRK_FORCESTEREO))
6459 SND_FORMAT(AFMT_S32_LE, 1, 0);
6461 SND_FORMAT(AFMT_S32_LE, 2, 0);
6464 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) {
6465 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0);
6469 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap))
6470 ch->pcmrates[i++] = 8000;
6471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap))
6472 ch->pcmrates[i++] = 11025;
6473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap))
6474 ch->pcmrates[i++] = 16000;
6475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap))
6476 ch->pcmrates[i++] = 22050;
6477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap))
6478 ch->pcmrates[i++] = 32000;
6479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap))
6480 ch->pcmrates[i++] = 44100;
6481 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */
6482 ch->pcmrates[i++] = 48000;
6483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap))
6484 ch->pcmrates[i++] = 88200;
6485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap))
6486 ch->pcmrates[i++] = 96000;
6487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap))
6488 ch->pcmrates[i++] = 176400;
6489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap))
6490 ch->pcmrates[i++] = 192000;
6491 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */
6492 ch->pcmrates[i] = 0;
6494 ch->caps.minspeed = ch->pcmrates[0];
6495 ch->caps.maxspeed = ch->pcmrates[i - 1];
6503 hdac_create_pcms(struct hdac_devinfo *devinfo)
6505 struct hdac_softc *sc = devinfo->codec->sc;
6506 struct hdac_audio_as *as = devinfo->function.audio.as;
6507 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0;
6509 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
6510 if (as[i].enable == 0)
6512 if (as[i].dir == HDA_CTL_IN) {
6524 devinfo->function.audio.num_devs =
6525 max(ardev, apdev) + max(drdev, dpdev);
6526 devinfo->function.audio.devs =
6527 (struct hdac_pcm_devinfo *)malloc(
6528 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo),
6529 M_HDAC, M_ZERO | M_NOWAIT);
6530 if (devinfo->function.audio.devs == NULL) {
6531 device_printf(sc->dev,
6532 "Unable to allocate memory for devices\n");
6535 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
6536 devinfo->function.audio.devs[i].index = i;
6537 devinfo->function.audio.devs[i].devinfo = devinfo;
6538 devinfo->function.audio.devs[i].play = -1;
6539 devinfo->function.audio.devs[i].rec = -1;
6540 devinfo->function.audio.devs[i].digital = 2;
6542 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
6543 if (as[i].enable == 0)
6545 for (j = 0; j < devinfo->function.audio.num_devs; j++) {
6546 if (devinfo->function.audio.devs[j].digital != 2 &&
6547 devinfo->function.audio.devs[j].digital !=
6550 if (as[i].dir == HDA_CTL_IN) {
6551 if (devinfo->function.audio.devs[j].rec >= 0)
6553 devinfo->function.audio.devs[j].rec
6556 if (devinfo->function.audio.devs[j].play >= 0)
6558 devinfo->function.audio.devs[j].play
6561 sc->chans[as[i].chan].pdevinfo =
6562 &devinfo->function.audio.devs[j];
6563 devinfo->function.audio.devs[j].digital =
6568 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
6569 struct hdac_pcm_devinfo *pdevinfo =
6570 &devinfo->function.audio.devs[i];
6572 device_add_child(sc->dev, "pcm", -1);
6573 device_set_ivars(pdevinfo->dev,
6579 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag)
6581 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
6582 struct hdac_audio_ctl *ctl;
6583 struct hdac_softc *sc = devinfo->codec->sc;
6588 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM |
6589 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
6590 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN |
6591 SOUND_MASK_IMIX | SOUND_MASK_MONITOR);
6594 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) {
6595 if ((flag & (1 << j)) == 0)
6599 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6600 if (ctl->enable == 0 ||
6601 ctl->widget->enable == 0)
6603 if (!((pdevinfo->play >= 0 &&
6604 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
6605 (pdevinfo->rec >= 0 &&
6606 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
6607 (ctl->widget->bindas == -2 && pdevinfo->index == 0)))
6609 if ((ctl->ossmask & (1 << j)) == 0)
6613 device_printf(pdevinfo->dev, "\n");
6614 if (banner != NULL) {
6615 device_printf(pdevinfo->dev, "%s", banner);
6617 device_printf(pdevinfo->dev, "Unknown Ctl");
6619 printf(" (OSS: %s)\n",
6620 hdac_audio_ctl_ossmixer_mask2allname(1 << j,
6622 device_printf(pdevinfo->dev, " |\n");
6625 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i,
6627 (ctl->ndir == HDA_CTL_IN)?"in ":"out");
6628 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir)
6629 printf(" %2d): ", ctl->index);
6632 if (ctl->step > 0) {
6633 printf("%+d/%+ddB (%d steps)%s\n",
6634 (0 - ctl->offset) * (ctl->size + 1) / 4,
6635 (ctl->step - ctl->offset) * (ctl->size + 1) / 4,
6637 ctl->mute?" + mute":"");
6639 printf("%s\n", ctl->mute?"mute":"");
6645 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap)
6651 device_printf(dev, " Stream cap: 0x%08x\n", cap);
6652 device_printf(dev, " ");
6653 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
6655 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
6657 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
6663 device_printf(dev, " PCM cap: 0x%08x\n", cap);
6664 device_printf(dev, " ");
6665 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
6667 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
6669 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
6671 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
6673 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
6678 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
6682 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
6684 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
6686 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
6689 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
6691 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
6693 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
6695 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
6702 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
6706 pincap = w->wclass.pin.cap;
6708 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
6709 device_printf(sc->dev, " ");
6710 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
6712 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
6714 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
6716 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
6718 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
6720 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
6722 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
6724 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
6726 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6728 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6730 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6732 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
6734 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
6738 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
6741 device_printf(sc->dev, " Pin config: 0x%08x\n",
6742 w->wclass.pin.config);
6743 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
6744 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
6746 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
6748 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
6750 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK)
6756 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf)
6758 struct hdac_softc *sc = w->devinfo->codec->sc;
6760 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s "
6761 "jack %2d loc %2d color %7s misc %d%s\n",
6763 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf),
6764 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf),
6765 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)],
6766 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)],
6767 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf),
6768 HDA_CONFIG_DEFAULTCONF_LOCATION(conf),
6769 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)],
6770 HDA_CONFIG_DEFAULTCONF_MISC(conf),
6771 (w->enable == 0)?" [DISABLED]":"");
6775 hdac_dump_pin_configs(struct hdac_devinfo *devinfo)
6777 struct hdac_widget *w;
6780 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6781 w = hdac_widget_get(devinfo, i);
6784 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6786 hdac_dump_pin_config(w, w->wclass.pin.config);
6791 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
6793 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
6794 device_printf(sc->dev, " "
6795 "mute=%d step=%d size=%d offset=%d\n",
6796 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
6797 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
6798 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
6799 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
6803 hdac_dump_nodes(struct hdac_devinfo *devinfo)
6805 struct hdac_softc *sc = devinfo->codec->sc;
6806 static char *ossname[] = SOUND_DEVICE_NAMES;
6807 struct hdac_widget *w, *cw;
6811 device_printf(sc->dev, "\n");
6812 device_printf(sc->dev, "Default Parameter\n");
6813 device_printf(sc->dev, "-----------------\n");
6814 hdac_dump_audio_formats(sc->dev,
6815 devinfo->function.audio.supp_stream_formats,
6816 devinfo->function.audio.supp_pcm_size_rate);
6817 device_printf(sc->dev, " IN amp: 0x%08x\n",
6818 devinfo->function.audio.inamp_cap);
6819 device_printf(sc->dev, " OUT amp: 0x%08x\n",
6820 devinfo->function.audio.outamp_cap);
6821 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6822 w = hdac_widget_get(devinfo, i);
6824 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
6827 device_printf(sc->dev, "\n");
6828 device_printf(sc->dev, " nid: %d%s\n", w->nid,
6829 (w->enable == 0) ? " [DISABLED]" : "");
6830 device_printf(sc->dev, " Name: %s\n", w->name);
6831 device_printf(sc->dev, " Widget cap: 0x%08x\n",
6832 w->param.widget_cap);
6833 if (w->param.widget_cap & 0x0ee1) {
6834 device_printf(sc->dev, " ");
6835 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap))
6837 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap))
6839 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6841 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
6843 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap))
6845 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap))
6847 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap))
6851 if (w->bindas != -1) {
6852 device_printf(sc->dev, " Association: %d (0x%08x)\n",
6853 w->bindas, w->bindseqmask);
6855 if (w->ossmask != 0 || w->ossdev >= 0) {
6856 device_printf(sc->dev, " OSS: %s",
6857 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf)));
6859 printf(" (%s)", ossname[w->ossdev]);
6862 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
6863 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
6864 hdac_dump_audio_formats(sc->dev,
6865 w->param.supp_stream_formats,
6866 w->param.supp_pcm_size_rate);
6867 } else if (w->type ==
6868 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6869 hdac_dump_pin(sc, w);
6870 if (w->param.eapdbtl != HDAC_INVALID)
6871 device_printf(sc->dev, " EAPD: 0x%08x\n",
6873 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
6874 w->param.outamp_cap != 0)
6875 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
6876 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
6877 w->param.inamp_cap != 0)
6878 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
6879 if (w->nconns > 0) {
6880 device_printf(sc->dev, " connections: %d\n", w->nconns);
6881 device_printf(sc->dev, " |\n");
6883 for (j = 0; j < w->nconns; j++) {
6884 cw = hdac_widget_get(devinfo, w->conns[j]);
6885 device_printf(sc->dev, " + %s<- nid=%d [%s]",
6886 (w->connsenable[j] == 0)?"[DISABLED] ":"",
6887 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
6889 printf(" [UNKNOWN]");
6890 else if (cw->enable == 0)
6891 printf(" [DISABLED]");
6892 if (w->nconns > 1 && w->selconn == j && w->type !=
6893 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
6894 printf(" (selected)");
6902 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth)
6904 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
6905 struct hdac_widget *w, *cw;
6909 if (depth > HDA_PARSE_MAXDEPTH)
6912 w = hdac_widget_get(devinfo, nid);
6913 if (w == NULL || w->enable == 0)
6917 device_printf(pdevinfo->dev, "%*s", 4, "");
6919 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, "");
6920 printf("nid=%d [%s]", w->nid, w->name);
6923 if (w->ossmask == 0) {
6927 printf(" [src: %s]",
6928 hdac_audio_ctl_ossmixer_mask2allname(
6929 w->ossmask, buf, sizeof(buf)));
6930 if (w->ossdev >= 0) {
6937 for (i = 0; i < w->nconns; i++) {
6938 if (w->connsenable[i] == 0)
6940 cw = hdac_widget_get(devinfo, w->conns[i]);
6941 if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
6944 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, "");
6947 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1);
6953 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo)
6955 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
6956 struct hdac_softc *sc = devinfo->codec->sc;
6957 struct hdac_widget *w;
6960 if (pdevinfo->play < 0)
6963 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6964 w = hdac_widget_get(devinfo, i);
6965 if (w == NULL || w->enable == 0)
6967 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6969 if (w->bindas != sc->chans[pdevinfo->play].as)
6973 device_printf(pdevinfo->dev, "\n");
6974 device_printf(pdevinfo->dev, "Playback:\n");
6976 device_printf(pdevinfo->dev, "\n");
6977 hdac_dump_dst_nid(pdevinfo, i, 0);
6982 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo)
6984 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
6985 struct hdac_softc *sc = devinfo->codec->sc;
6986 struct hdac_widget *w;
6990 if (pdevinfo->rec < 0)
6993 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6994 w = hdac_widget_get(devinfo, i);
6995 if (w == NULL || w->enable == 0)
6997 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
6999 if (w->bindas != sc->chans[pdevinfo->rec].as)
7003 device_printf(pdevinfo->dev, "\n");
7004 device_printf(pdevinfo->dev, "Record:\n");
7006 device_printf(pdevinfo->dev, "\n");
7007 hdac_dump_dst_nid(pdevinfo, i, 0);
7012 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo)
7014 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7015 struct hdac_widget *w;
7019 if (pdevinfo->index != 0)
7022 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7023 w = hdac_widget_get(devinfo, i);
7024 if (w == NULL || w->enable == 0)
7026 if ((w->pflags & HDA_ADC_MONITOR) == 0)
7030 device_printf(pdevinfo->dev, "\n");
7031 device_printf(pdevinfo->dev, "Input Mix:\n");
7033 device_printf(pdevinfo->dev, "\n");
7034 hdac_dump_dst_nid(pdevinfo, i, 0);
7039 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo)
7041 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc;
7045 if (pdevinfo->play >= 0) {
7047 device_printf(pdevinfo->dev, "\n");
7048 device_printf(pdevinfo->dev, "Playback:\n");
7049 device_printf(pdevinfo->dev, "\n");
7050 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats,
7051 sc->chans[i].supp_pcm_size_rate);
7052 device_printf(pdevinfo->dev, " DAC:");
7053 for (nids = sc->chans[i].io; *nids != -1; nids++)
7054 printf(" %d", *nids);
7057 if (pdevinfo->rec >= 0) {
7059 device_printf(pdevinfo->dev, "\n");
7060 device_printf(pdevinfo->dev, "Record:\n");
7061 device_printf(pdevinfo->dev, "\n");
7062 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats,
7063 sc->chans[i].supp_pcm_size_rate);
7064 device_printf(pdevinfo->dev, " ADC:");
7065 for (nids = sc->chans[i].io; *nids != -1; nids++)
7066 printf(" %d", *nids);
7072 hdac_release_resources(struct hdac_softc *sc)
7082 callout_stop(&sc->poll_hda);
7083 callout_stop(&sc->poll_hdac);
7084 callout_stop(&sc->poll_jack);
7087 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7088 callout_drain(&sc->poll_hda);
7089 callout_drain(&sc->poll_hdac);
7090 callout_drain(&sc->poll_jack);
7094 for (i = 0; i < HDAC_CODEC_MAX; i++) {
7095 if (sc->codecs[i] == NULL)
7097 for (j = 0; j < sc->codecs[i]->num_fgs; j++) {
7098 free(sc->codecs[i]->fgs[j].widget, M_HDAC);
7099 if (sc->codecs[i]->fgs[j].node_type ==
7100 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7101 free(sc->codecs[i]->fgs[j].function.audio.ctl,
7103 free(sc->codecs[i]->fgs[j].function.audio.as,
7105 free(sc->codecs[i]->fgs[j].function.audio.devs,
7109 free(sc->codecs[i]->fgs, M_HDAC);
7110 free(sc->codecs[i], M_HDAC);
7111 sc->codecs[i] = NULL;
7114 hdac_dma_free(sc, &sc->pos_dma);
7115 hdac_dma_free(sc, &sc->rirb_dma);
7116 hdac_dma_free(sc, &sc->corb_dma);
7117 for (i = 0; i < sc->num_chans; i++) {
7118 if (sc->chans[i].blkcnt > 0)
7119 hdac_dma_free(sc, &sc->chans[i].bdl_dma);
7121 free(sc->chans, M_HDAC);
7122 if (sc->chan_dmat != NULL) {
7123 bus_dma_tag_destroy(sc->chan_dmat);
7124 sc->chan_dmat = NULL;
7127 snd_mtxfree(sc->lock);
7130 /* This function surely going to make its way into upper level someday. */
7132 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
7134 const char *res = NULL;
7135 int i = 0, j, k, len, inv;
7143 if (resource_string_value(device_get_name(sc->dev),
7144 device_get_unit(sc->dev), "config", &res) != 0)
7146 if (!(res != NULL && strlen(res) > 0))
7149 device_printf(sc->dev, "HDA Config:");
7152 while (res[i] != '\0' &&
7153 (res[i] == ',' || isspace(res[i]) != 0))
7155 if (res[i] == '\0') {
7162 while (res[j] != '\0' &&
7163 !(res[j] == ',' || isspace(res[j]) != 0))
7166 if (len > 2 && strncmp(res + i, "no", 2) == 0)
7170 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
7171 if (strncmp(res + i + inv,
7172 hdac_quirks_tab[k].key, len - inv) != 0)
7174 if (len - inv != strlen(hdac_quirks_tab[k].key))
7177 printf(" %s%s", (inv != 0) ? "no" : "",
7178 hdac_quirks_tab[k].key);
7180 if (inv == 0 && on != NULL)
7181 *on |= hdac_quirks_tab[k].value;
7182 else if (inv != 0 && off != NULL)
7183 *off |= hdac_quirks_tab[k].value;
7191 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
7193 struct hdac_softc *sc;
7198 dev = oidp->oid_arg1;
7199 sc = device_get_softc(dev);
7205 err = sysctl_handle_int(oidp, &val, 0, req);
7207 if (err != 0 || req->newptr == NULL)
7209 if (val < 0 || val > 1)
7213 if (val != sc->polling) {
7215 callout_stop(&sc->poll_hda);
7216 callout_stop(&sc->poll_hdac);
7218 callout_drain(&sc->poll_hda);
7219 callout_drain(&sc->poll_hdac);
7222 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
7223 ctl |= HDAC_INTCTL_GIE;
7224 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
7226 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
7227 ctl &= ~HDAC_INTCTL_GIE;
7228 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
7230 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7233 hdac_poll_reinit(sc);
7234 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7243 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
7245 struct hdac_softc *sc;
7249 dev = oidp->oid_arg1;
7250 sc = device_get_softc(dev);
7254 val = ((uint64_t)sc->poll_ival * 1000) / hz;
7256 err = sysctl_handle_int(oidp, &val, 0, req);
7258 if (err != 0 || req->newptr == NULL)
7265 val = ((uint64_t)val * hz) / 1000;
7272 sc->poll_ival = val;
7279 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
7281 struct hdac_softc *sc;
7282 struct hdac_codec *codec;
7283 struct hdac_devinfo *devinfo;
7284 struct hdac_widget *w;
7286 uint32_t res, pincap, delay;
7287 int codec_index, fg_index;
7291 dev = oidp->oid_arg1;
7292 sc = device_get_softc(dev);
7296 err = sysctl_handle_int(oidp, &val, 0, req);
7297 if (err != 0 || req->newptr == NULL || val == 0)
7300 /* XXX: Temporary. For debugging. */
7304 } else if (val == 101) {
7310 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7311 codec = sc->codecs[codec_index];
7315 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7316 devinfo = &codec->fgs[fg_index];
7317 if (devinfo->node_type !=
7318 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
7321 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n",
7322 codec_index, devinfo->nid);
7323 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7324 w = hdac_widget_get(devinfo, i);
7325 if (w == NULL || w->type !=
7326 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7328 hdac_dump_pin_config(w, w->wclass.pin.config);
7329 pincap = w->wclass.pin.cap;
7330 device_printf(dev, " Caps: %2s %3s %2s %4s %4s",
7331 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"",
7332 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"",
7333 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"",
7334 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"",
7335 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":"");
7336 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
7337 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) {
7338 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
7341 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
7343 res = hdac_command(sc,
7344 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
7345 if (res != 0x7fffffff && res != 0xffffffff)
7348 } while (++delay < 10000);
7351 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
7354 printf(" Sense: 0x%08x", res);
7356 printf(" delay %dus", delay * 10);
7361 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
7362 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
7363 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
7364 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
7365 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
7366 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
7367 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
7368 device_printf(dev, " GPI:");
7369 res = hdac_command(sc,
7370 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
7371 printf(" data=0x%08x", res);
7372 res = hdac_command(sc,
7373 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
7375 printf(" wake=0x%08x", res);
7376 res = hdac_command(sc,
7377 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
7379 printf(" unsol=0x%08x", res);
7380 res = hdac_command(sc,
7381 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
7382 printf(" sticky=0x%08x\n", res);
7384 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
7385 device_printf(dev, " GPO:");
7386 res = hdac_command(sc,
7387 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
7388 printf(" data=0x%08x\n", res);
7390 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
7391 device_printf(dev, "GPIO:");
7392 res = hdac_command(sc,
7393 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
7394 printf(" data=0x%08x", res);
7395 res = hdac_command(sc,
7396 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
7397 printf(" enable=0x%08x", res);
7398 res = hdac_command(sc,
7399 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
7400 printf(" direction=0x%08x\n", res);
7401 res = hdac_command(sc,
7402 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
7403 device_printf(dev, " wake=0x%08x", res);
7404 res = hdac_command(sc,
7405 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
7407 printf(" unsol=0x%08x", res);
7408 res = hdac_command(sc,
7409 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
7410 printf(" sticky=0x%08x\n", res);
7419 hdac_attach2(void *arg)
7421 struct hdac_codec *codec;
7422 struct hdac_softc *sc;
7423 struct hdac_audio_ctl *ctl;
7424 uint32_t quirks_on, quirks_off;
7425 int codec_index, fg_index;
7426 int i, dmaalloc = 0;
7427 struct hdac_devinfo *devinfo;
7429 sc = (struct hdac_softc *)arg;
7431 hdac_config_fetch(sc, &quirks_on, &quirks_off);
7434 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n",
7435 quirks_on, quirks_off);
7440 /* Remove ourselves from the config hooks */
7441 if (sc->intrhook.ich_func != NULL) {
7442 config_intrhook_disestablish(&sc->intrhook);
7443 sc->intrhook.ich_func = NULL;
7446 /* Start the corb and rirb engines */
7448 device_printf(sc->dev, "Starting CORB Engine...\n");
7450 hdac_corb_start(sc);
7452 device_printf(sc->dev, "Starting RIRB Engine...\n");
7454 hdac_rirb_start(sc);
7457 device_printf(sc->dev,
7458 "Enabling controller interrupt...\n");
7460 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
7462 if (sc->polling == 0) {
7463 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
7464 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
7466 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7471 device_printf(sc->dev,
7472 "Scanning HDA codecs ...\n");
7474 hdac_scan_codecs(sc);
7476 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7477 codec = sc->codecs[codec_index];
7480 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7481 devinfo = &codec->fgs[fg_index];
7483 device_printf(sc->dev, "\n");
7484 device_printf(sc->dev,
7485 "Processing %s FG cad=%d nid=%d...\n",
7486 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio":
7487 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem":
7489 devinfo->codec->cad, devinfo->nid);
7491 if (devinfo->node_type !=
7492 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7494 device_printf(sc->dev,
7495 "Powering down...\n");
7498 HDA_CMD_SET_POWER_STATE(codec->cad,
7499 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7505 device_printf(sc->dev, "Powering up...\n");
7507 hdac_powerup(devinfo);
7509 device_printf(sc->dev, "Parsing audio FG...\n");
7511 hdac_audio_parse(devinfo);
7513 device_printf(sc->dev, "Parsing Ctls...\n");
7515 hdac_audio_ctl_parse(devinfo);
7517 device_printf(sc->dev, "Parsing vendor patch...\n");
7519 hdac_vendor_patch_parse(devinfo);
7520 devinfo->function.audio.quirks |= quirks_on;
7521 devinfo->function.audio.quirks &= ~quirks_off;
7524 device_printf(sc->dev, "Disabling nonaudio...\n");
7526 hdac_audio_disable_nonaudio(devinfo);
7528 device_printf(sc->dev, "Disabling useless...\n");
7530 hdac_audio_disable_useless(devinfo);
7532 device_printf(sc->dev, "Patched pins configuration:\n");
7533 hdac_dump_pin_configs(devinfo);
7536 device_printf(sc->dev, "Parsing pin associations...\n");
7538 hdac_audio_as_parse(devinfo);
7540 device_printf(sc->dev, "Building AFG tree...\n");
7542 hdac_audio_build_tree(devinfo);
7544 device_printf(sc->dev, "Disabling unassociated "
7547 hdac_audio_disable_unas(devinfo);
7549 device_printf(sc->dev, "Disabling nonselected "
7552 hdac_audio_disable_notselected(devinfo);
7554 device_printf(sc->dev, "Disabling useless...\n");
7556 hdac_audio_disable_useless(devinfo);
7558 device_printf(sc->dev, "Disabling "
7559 "crossassociatement connections...\n");
7561 hdac_audio_disable_crossas(devinfo);
7563 device_printf(sc->dev, "Disabling useless...\n");
7565 hdac_audio_disable_useless(devinfo);
7567 device_printf(sc->dev, "Binding associations to channels...\n");
7569 hdac_audio_bind_as(devinfo);
7571 device_printf(sc->dev, "Assigning names to signal sources...\n");
7573 hdac_audio_assign_names(devinfo);
7575 device_printf(sc->dev, "Assigning mixers to the tree...\n");
7577 hdac_audio_assign_mixers(devinfo);
7579 device_printf(sc->dev, "Preparing pin controls...\n");
7581 hdac_audio_prepare_pin_ctrl(devinfo);
7583 device_printf(sc->dev, "AFG commit...\n");
7585 hdac_audio_commit(devinfo);
7587 device_printf(sc->dev, "HP switch init...\n");
7589 hdac_hp_switch_init(devinfo);
7591 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
7593 if (hdac_dma_alloc(sc, &sc->pos_dma,
7594 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
7596 device_printf(sc->dev, "Failed to "
7597 "allocate DMA pos buffer "
7605 device_printf(sc->dev, "Creating PCM devices...\n");
7607 hdac_create_pcms(devinfo);
7610 if (devinfo->function.audio.quirks != 0) {
7611 device_printf(sc->dev, "FG config/quirks:");
7612 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
7613 if ((devinfo->function.audio.quirks &
7614 hdac_quirks_tab[i].value) ==
7615 hdac_quirks_tab[i].value)
7616 printf(" %s", hdac_quirks_tab[i].key);
7621 device_printf(sc->dev, "\n");
7622 device_printf(sc->dev, "+-------------------+\n");
7623 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
7624 device_printf(sc->dev, "+-------------------+\n");
7625 hdac_dump_nodes(devinfo);
7629 device_printf(sc->dev, "\n");
7630 device_printf(sc->dev, "+------------------------+\n");
7631 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
7632 device_printf(sc->dev, "+------------------------+\n");
7633 device_printf(sc->dev, "\n");
7635 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
7636 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i,
7637 (ctl->widget != NULL) ? ctl->widget->nid : -1,
7638 (ctl->ndir == HDA_CTL_IN)?"in ":"out",
7639 (ctl->dir == HDA_CTL_IN)?"in ":"out",
7641 if (ctl->childwidget != NULL)
7642 printf(" cnid %3d", ctl->childwidget->nid);
7645 printf(" ossmask=0x%08x\n",
7647 device_printf(sc->dev,
7648 " mute: %d step: %3d size: %3d off: %3d%s\n",
7649 ctl->mute, ctl->step, ctl->size, ctl->offset,
7650 (ctl->enable == 0) ? " [DISABLED]" :
7651 ((ctl->ossmask == 0) ? " [UNUSED]" : ""));
7659 device_printf(sc->dev, "\n");
7662 bus_generic_attach(sc->dev);
7664 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7665 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7666 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
7667 sysctl_hdac_polling, "I", "Enable polling mode");
7668 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7669 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7670 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
7671 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
7672 "Controller/Jack Sense polling interval (1-1000 ms)");
7673 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7674 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7675 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
7676 sysctl_hdac_pindump, "I", "Dump pin states/data");
7679 /****************************************************************************
7680 * int hdac_suspend(device_t)
7682 * Suspend and power down HDA bus and codecs.
7683 ****************************************************************************/
7685 hdac_suspend(device_t dev)
7687 struct hdac_softc *sc;
7688 struct hdac_codec *codec;
7689 struct hdac_devinfo *devinfo;
7690 int codec_index, fg_index, i;
7693 device_printf(dev, "Suspend...\n");
7696 sc = device_get_softc(dev);
7700 device_printf(dev, "Stop streams...\n");
7702 for (i = 0; i < sc->num_chans; i++) {
7703 if (sc->chans[i].flags & HDAC_CHN_RUNNING) {
7704 sc->chans[i].flags |= HDAC_CHN_SUSPEND;
7705 hdac_channel_stop(sc, &sc->chans[i]);
7709 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7710 codec = sc->codecs[codec_index];
7713 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7714 devinfo = &codec->fgs[fg_index];
7718 " cad=%d nid=%d to the D3 state...\n",
7719 codec->cad, devinfo->nid);
7722 HDA_CMD_SET_POWER_STATE(codec->cad,
7723 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7729 device_printf(dev, "Reset controller...\n");
7731 callout_stop(&sc->poll_hda);
7732 callout_stop(&sc->poll_hdac);
7733 callout_stop(&sc->poll_jack);
7736 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7737 callout_drain(&sc->poll_hda);
7738 callout_drain(&sc->poll_hdac);
7739 callout_drain(&sc->poll_jack);
7742 device_printf(dev, "Suspend done\n");
7748 /****************************************************************************
7749 * int hdac_resume(device_t)
7751 * Powerup and restore HDA bus and codecs state.
7752 ****************************************************************************/
7754 hdac_resume(device_t dev)
7756 struct hdac_softc *sc;
7757 struct hdac_codec *codec;
7758 struct hdac_devinfo *devinfo;
7759 int codec_index, fg_index, i;
7762 device_printf(dev, "Resume...\n");
7765 sc = device_get_softc(dev);
7768 /* Quiesce everything */
7770 device_printf(dev, "Reset controller...\n");
7774 /* Initialize the CORB and RIRB */
7778 /* Start the corb and rirb engines */
7780 device_printf(dev, "Starting CORB Engine...\n");
7782 hdac_corb_start(sc);
7784 device_printf(dev, "Starting RIRB Engine...\n");
7786 hdac_rirb_start(sc);
7790 "Enabling controller interrupt...\n");
7792 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
7794 if (sc->polling == 0) {
7795 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
7796 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
7798 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7802 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7803 codec = sc->codecs[codec_index];
7806 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7807 devinfo = &codec->fgs[fg_index];
7808 if (devinfo->node_type !=
7809 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7812 "Power down unsupported non-audio FG"
7813 " cad=%d nid=%d to the D3 state...\n",
7814 codec->cad, devinfo->nid);
7817 HDA_CMD_SET_POWER_STATE(codec->cad,
7818 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7825 "Power up audio FG cad=%d nid=%d...\n",
7826 devinfo->codec->cad, devinfo->nid);
7828 hdac_powerup(devinfo);
7830 device_printf(dev, "AFG commit...\n");
7832 hdac_audio_commit(devinfo);
7834 device_printf(dev, "HP switch init...\n");
7836 hdac_hp_switch_init(devinfo);
7839 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
7840 struct hdac_pcm_devinfo *pdevinfo =
7841 &devinfo->function.audio.devs[i];
7843 device_printf(pdevinfo->dev,
7844 "OSS mixer reinitialization...\n");
7846 if (mixer_reinit(pdevinfo->dev) == -1)
7847 device_printf(pdevinfo->dev,
7848 "unable to reinitialize the mixer\n");
7855 device_printf(dev, "Start streams...\n");
7857 for (i = 0; i < sc->num_chans; i++) {
7858 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) {
7859 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND;
7860 hdac_channel_start(sc, &sc->chans[i]);
7867 device_printf(dev, "Resume done\n");
7872 /****************************************************************************
7873 * int hdac_detach(device_t)
7875 * Detach and free up resources utilized by the hdac device.
7876 ****************************************************************************/
7878 hdac_detach(device_t dev)
7880 struct hdac_softc *sc;
7882 int i, devcount, error;
7884 if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
7886 for (i = 0; i < devcount; i++) {
7887 if ((error = device_delete_child(dev, devlist[i])) != 0) {
7888 free(devlist, M_TEMP);
7892 free(devlist, M_TEMP);
7894 sc = device_get_softc(dev);
7895 hdac_release_resources(sc);
7901 hdac_print_child(device_t dev, device_t child)
7903 struct hdac_pcm_devinfo *pdevinfo =
7904 (struct hdac_pcm_devinfo *)device_get_ivars(child);
7907 retval = bus_print_child_header(dev, child);
7908 retval += printf(" at cad %d nid %d",
7909 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid);
7910 retval += bus_print_child_footer(dev, child);
7915 static device_method_t hdac_methods[] = {
7916 /* device interface */
7917 DEVMETHOD(device_probe, hdac_probe),
7918 DEVMETHOD(device_attach, hdac_attach),
7919 DEVMETHOD(device_detach, hdac_detach),
7920 DEVMETHOD(device_suspend, hdac_suspend),
7921 DEVMETHOD(device_resume, hdac_resume),
7923 DEVMETHOD(bus_print_child, hdac_print_child),
7927 static driver_t hdac_driver = {
7930 sizeof(struct hdac_softc),
7933 static devclass_t hdac_devclass;
7935 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0);
7936 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
7937 MODULE_VERSION(snd_hda, 1);
7940 hdac_pcm_probe(device_t dev)
7942 struct hdac_pcm_devinfo *pdevinfo =
7943 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
7946 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s",
7947 hdac_codec_name(pdevinfo->devinfo->codec),
7949 pdevinfo->digital?"Digital":"Analog");
7950 device_set_desc_copy(dev, buf);
7955 hdac_pcm_attach(device_t dev)
7957 struct hdac_pcm_devinfo *pdevinfo =
7958 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
7959 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc;
7960 char status[SND_STATUSLEN];
7963 pdevinfo->chan_size = pcm_getbuffersize(dev,
7964 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
7967 device_printf(dev, "+--------------------------------------+\n");
7968 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n");
7969 device_printf(dev, "+--------------------------------------+\n");
7970 hdac_dump_pcmchannels(pdevinfo);
7971 device_printf(dev, "\n");
7972 device_printf(dev, "+-------------------------------+\n");
7973 device_printf(dev, "| DUMPING Playback/Record Paths |\n");
7974 device_printf(dev, "+-------------------------------+\n");
7975 hdac_dump_dac(pdevinfo);
7976 hdac_dump_adc(pdevinfo);
7977 hdac_dump_mix(pdevinfo);
7978 device_printf(dev, "\n");
7979 device_printf(dev, "+-------------------------+\n");
7980 device_printf(dev, "| DUMPING Volume Controls |\n");
7981 device_printf(dev, "+-------------------------+\n");
7982 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME);
7983 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM);
7984 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD);
7985 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC);
7986 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR);
7987 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE);
7988 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER);
7989 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV);
7990 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX);
7991 hdac_dump_ctls(pdevinfo, NULL, 0);
7992 device_printf(dev, "\n");
7995 if (resource_int_value(device_get_name(dev),
7996 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
7998 if (i < HDA_BLK_MIN)
8000 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i;
8002 while (pdevinfo->chan_blkcnt >> i)
8004 pdevinfo->chan_blkcnt = 1 << (i - 1);
8005 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN)
8006 pdevinfo->chan_blkcnt = HDA_BDL_MIN;
8007 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX)
8008 pdevinfo->chan_blkcnt = HDA_BDL_MAX;
8010 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT;
8013 * We don't register interrupt handler with snd_setup_intr
8014 * in pcm device. Mark pcm device as MPSAFE manually.
8016 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
8019 device_printf(dev, "OSS mixer initialization...\n");
8021 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0)
8022 device_printf(dev, "Can't register mixer\n");
8025 device_printf(dev, "Registering PCM channels...\n");
8027 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0,
8028 (pdevinfo->rec >= 0)?1:0) != 0)
8029 device_printf(dev, "Can't register PCM\n");
8031 pdevinfo->registered++;
8033 if (pdevinfo->play >= 0)
8034 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo);
8035 if (pdevinfo->rec >= 0)
8036 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo);
8038 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s",
8039 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid,
8040 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda));
8041 pcm_setstatus(dev, status);
8047 hdac_pcm_detach(device_t dev)
8049 struct hdac_pcm_devinfo *pdevinfo =
8050 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8053 if (pdevinfo->registered > 0) {
8054 err = pcm_unregister(dev);
8062 static device_method_t hdac_pcm_methods[] = {
8063 /* device interface */
8064 DEVMETHOD(device_probe, hdac_pcm_probe),
8065 DEVMETHOD(device_attach, hdac_pcm_attach),
8066 DEVMETHOD(device_detach, hdac_pcm_detach),
8070 static driver_t hdac_pcm_driver = {
8076 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0);