sys/dev/usb/controller/at91dci.c

   1 #include <sys/cdefs.h>
   2 __FBSDID("$FreeBSD$");
   3
   4 /*-
   5  * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the AT91 series USB Device
  31  * Controller
  32  */
  33
  34 /*
  35  * Thanks to "David Brownell" for helping out regarding the hardware
  36  * endpoint profiles.
  37  */
  38
  39 /*
  40  * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is
  41  * reset.
  42  *
  43  * NOTE: When the chip detects BUS-reset it will also reset the
  44  * endpoints, Function-address and more.
  45  */
  46
  47 #include <sys/stdint.h>
  48 #include <sys/stddef.h>
  49 #include <sys/param.h>
  50 #include <sys/queue.h>
  51 #include <sys/types.h>
  52 #include <sys/systm.h>
  53 #include <sys/kernel.h>
  54 #include <sys/bus.h>
  55 #include <sys/linker_set.h>
  56 #include <sys/module.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/condvar.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/sx.h>
  62 #include <sys/unistd.h>
  63 #include <sys/callout.h>
  64 #include <sys/malloc.h>
  65 #include <sys/priv.h>
  66
  67 #include <dev/usb/usb.h>
  68 #include <dev/usb/usbdi.h>
  69
  70 #define USB_DEBUG_VAR at91dcidebug
  71
  72 #include <dev/usb/usb_core.h>
  73 #include <dev/usb/usb_debug.h>
  74 #include <dev/usb/usb_busdma.h>
  75 #include <dev/usb/usb_process.h>
  76 #include <dev/usb/usb_transfer.h>
  77 #include <dev/usb/usb_device.h>
  78 #include <dev/usb/usb_hub.h>
  79 #include <dev/usb/usb_util.h>
  80
  81 #include <dev/usb/usb_controller.h>
  82 #include <dev/usb/usb_bus.h>
  83 #include <dev/usb/controller/at91dci.h>
  84
  85 #define AT9100_DCI_BUS2SC(bus) \
  86    ((struct at91dci_softc *)(((uint8_t *)(bus)) - \
  87     ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus))))
  88
  89 #define AT9100_DCI_PC2SC(pc) \
  90    AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  91
  92 #ifdef USB_DEBUG
  93 static int at91dcidebug = 0;
  94
  95 SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci");
  96 SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW,
  97     &at91dcidebug, 0, "at91dci debug level");
  98 #endif
  99
 100 #define AT9100_DCI_INTR_ENDPT 1
 101
 102 /* prototypes */
 103
 104 struct usb_bus_methods at91dci_bus_methods;
 105 struct usb_pipe_methods at91dci_device_bulk_methods;
 106 struct usb_pipe_methods at91dci_device_ctrl_methods;
 107 struct usb_pipe_methods at91dci_device_intr_methods;
 108 struct usb_pipe_methods at91dci_device_isoc_fs_methods;
 109
 110 static at91dci_cmd_t at91dci_setup_rx;
 111 static at91dci_cmd_t at91dci_data_rx;
 112 static at91dci_cmd_t at91dci_data_tx;
 113 static at91dci_cmd_t at91dci_data_tx_sync;
 114 static void     at91dci_device_done(struct usb_xfer *, usb_error_t);
 115 static void     at91dci_do_poll(struct usb_bus *);
 116 static void     at91dci_standard_done(struct usb_xfer *);
 117 static void     at91dci_root_intr(struct at91dci_softc *sc);
 118
 119 /*
 120  * NOTE: Some of the bits in the CSR register have inverse meaning so
 121  * we need a helper macro when acknowledging events:
 122  */
 123 #define AT91_CSR_ACK(csr, what) do {            \
 124   (csr) &= ~((AT91_UDP_CSR_FORCESTALL|          \
 125               AT91_UDP_CSR_TXPKTRDY|            \
 126               AT91_UDP_CSR_RXBYTECNT) ^ (what));\
 127   (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0|          \
 128              AT91_UDP_CSR_RX_DATA_BK1|          \
 129              AT91_UDP_CSR_TXCOMP|               \
 130              AT91_UDP_CSR_RXSETUP|              \
 131              AT91_UDP_CSR_STALLSENT) ^ (what)); \
 132 } while (0)
 133
 134 /*
 135  * Here is a list of what the chip supports.
 136  * Probably it supports more than listed here!
 137  */
 138 static const struct usb_hw_ep_profile
 139         at91dci_ep_profile[AT91_UDP_EP_MAX] = {
 140
 141         [0] = {
 142                 .max_in_frame_size = 8,
 143                 .max_out_frame_size = 8,
 144                 .is_simplex = 1,
 145                 .support_control = 1,
 146         },
 147         [1] = {
 148                 .max_in_frame_size = 64,
 149                 .max_out_frame_size = 64,
 150                 .is_simplex = 1,
 151                 .support_multi_buffer = 1,
 152                 .support_bulk = 1,
 153                 .support_interrupt = 1,
 154                 .support_isochronous = 1,
 155                 .support_in = 1,
 156                 .support_out = 1,
 157         },
 158         [2] = {
 159                 .max_in_frame_size = 64,
 160                 .max_out_frame_size = 64,
 161                 .is_simplex = 1,
 162                 .support_multi_buffer = 1,
 163                 .support_bulk = 1,
 164                 .support_interrupt = 1,
 165                 .support_isochronous = 1,
 166                 .support_in = 1,
 167                 .support_out = 1,
 168         },
 169         [3] = {
 170                 /* can also do BULK */
 171                 .max_in_frame_size = 8,
 172                 .max_out_frame_size = 8,
 173                 .is_simplex = 1,
 174                 .support_interrupt = 1,
 175                 .support_in = 1,
 176                 .support_out = 1,
 177         },
 178         [4] = {
 179                 .max_in_frame_size = 256,
 180                 .max_out_frame_size = 256,
 181                 .is_simplex = 1,
 182                 .support_multi_buffer = 1,
 183                 .support_bulk = 1,
 184                 .support_interrupt = 1,
 185                 .support_isochronous = 1,
 186                 .support_in = 1,
 187                 .support_out = 1,
 188         },
 189         [5] = {
 190                 .max_in_frame_size = 256,
 191                 .max_out_frame_size = 256,
 192                 .is_simplex = 1,
 193                 .support_multi_buffer = 1,
 194                 .support_bulk = 1,
 195                 .support_interrupt = 1,
 196                 .support_isochronous = 1,
 197                 .support_in = 1,
 198                 .support_out = 1,
 199         },
 200 };
 201
 202 static void
 203 at91dci_get_hw_ep_profile(struct usb_device *udev,
 204     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 205 {
 206         if (ep_addr < AT91_UDP_EP_MAX) {
 207                 *ppf = (at91dci_ep_profile + ep_addr);
 208         } else {
 209                 *ppf = NULL;
 210         }
 211 }
 212
 213 static void
 214 at91dci_clocks_on(struct at91dci_softc *sc)
 215 {
 216         if (sc->sc_flags.clocks_off &&
 217             sc->sc_flags.port_powered) {
 218
 219                 DPRINTFN(5, "\n");
 220
 221                 if (sc->sc_clocks_on) {
 222                         (sc->sc_clocks_on) (sc->sc_clocks_arg);
 223                 }
 224                 sc->sc_flags.clocks_off = 0;
 225
 226                 /* enable Transceiver */
 227                 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0);
 228         }
 229 }
 230
 231 static void
 232 at91dci_clocks_off(struct at91dci_softc *sc)
 233 {
 234         if (!sc->sc_flags.clocks_off) {
 235
 236                 DPRINTFN(5, "\n");
 237
 238                 /* disable Transceiver */
 239                 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS);
 240
 241                 if (sc->sc_clocks_off) {
 242                         (sc->sc_clocks_off) (sc->sc_clocks_arg);
 243                 }
 244                 sc->sc_flags.clocks_off = 1;
 245         }
 246 }
 247
 248 static void
 249 at91dci_pull_up(struct at91dci_softc *sc)
 250 {
 251         /* pullup D+, if possible */
 252
 253         if (!sc->sc_flags.d_pulled_up &&
 254             sc->sc_flags.port_powered) {
 255                 sc->sc_flags.d_pulled_up = 1;
 256                 (sc->sc_pull_up) (sc->sc_pull_arg);
 257         }
 258 }
 259
 260 static void
 261 at91dci_pull_down(struct at91dci_softc *sc)
 262 {
 263         /* pulldown D+, if possible */
 264
 265         if (sc->sc_flags.d_pulled_up) {
 266                 sc->sc_flags.d_pulled_up = 0;
 267                 (sc->sc_pull_down) (sc->sc_pull_arg);
 268         }
 269 }
 270
 271 static void
 272 at91dci_wakeup_peer(struct at91dci_softc *sc)
 273 {
 274         if (!(sc->sc_flags.status_suspend)) {
 275                 return;
 276         }
 277
 278         AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR);
 279
 280         /* wait 8 milliseconds */
 281         /* Wait for reset to complete. */
 282         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 283
 284         AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0);
 285 }
 286
 287 static void
 288 at91dci_set_address(struct at91dci_softc *sc, uint8_t addr)
 289 {
 290         DPRINTFN(5, "addr=%d\n", addr);
 291
 292         AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr |
 293             AT91_UDP_FADDR_EN);
 294 }
 295
 296 static uint8_t
 297 at91dci_setup_rx(struct at91dci_td *td)
 298 {
 299         struct at91dci_softc *sc;
 300         struct usb_device_request req;
 301         uint32_t csr;
 302         uint32_t temp;
 303         uint16_t count;
 304
 305         /* read out FIFO status */
 306         csr = bus_space_read_4(td->io_tag, td->io_hdl,
 307             td->status_reg);
 308
 309         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 310
 311         temp = csr;
 312         temp &= (AT91_UDP_CSR_RX_DATA_BK0 |
 313             AT91_UDP_CSR_RX_DATA_BK1 |
 314             AT91_UDP_CSR_STALLSENT |
 315             AT91_UDP_CSR_RXSETUP |
 316             AT91_UDP_CSR_TXCOMP);
 317
 318         if (!(csr & AT91_UDP_CSR_RXSETUP)) {
 319                 goto not_complete;
 320         }
 321         /* clear did stall */
 322         td->did_stall = 0;
 323
 324         /* get the packet byte count */
 325         count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
 326
 327         /* verify data length */
 328         if (count != td->remainder) {
 329                 DPRINTFN(0, "Invalid SETUP packet "
 330                     "length, %d bytes\n", count);
 331                 goto not_complete;
 332         }
 333         if (count != sizeof(req)) {
 334                 DPRINTFN(0, "Unsupported SETUP packet "
 335                     "length, %d bytes\n", count);
 336                 goto not_complete;
 337         }
 338         /* receive data */
 339         bus_space_read_multi_1(td->io_tag, td->io_hdl,
 340             td->fifo_reg, (void *)&req, sizeof(req));
 341
 342         /* copy data into real buffer */
 343         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 344
 345         td->offset = sizeof(req);
 346         td->remainder = 0;
 347
 348         /* get pointer to softc */
 349         sc = AT9100_DCI_PC2SC(td->pc);
 350
 351         /* sneak peek the set address */
 352         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 353             (req.bRequest == UR_SET_ADDRESS)) {
 354                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 355         } else {
 356                 sc->sc_dv_addr = 0xFF;
 357         }
 358
 359         /* sneak peek the endpoint direction */
 360         if (req.bmRequestType & UE_DIR_IN) {
 361                 csr |= AT91_UDP_CSR_DIR;
 362         } else {
 363                 csr &= ~AT91_UDP_CSR_DIR;
 364         }
 365
 366         /* write the direction of the control transfer */
 367         AT91_CSR_ACK(csr, temp);
 368         bus_space_write_4(td->io_tag, td->io_hdl,
 369             td->status_reg, csr);
 370         return (0);                     /* complete */
 371
 372 not_complete:
 373         /* abort any ongoing transfer */
 374         if (!td->did_stall) {
 375                 DPRINTFN(5, "stalling\n");
 376                 temp |= AT91_UDP_CSR_FORCESTALL;
 377                 td->did_stall = 1;
 378         }
 379
 380         /* clear interrupts, if any */
 381         if (temp) {
 382                 DPRINTFN(5, "clearing 0x%08x\n", temp);
 383                 AT91_CSR_ACK(csr, temp);
 384                 bus_space_write_4(td->io_tag, td->io_hdl,
 385                     td->status_reg, csr);
 386         }
 387         return (1);                     /* not complete */
 388
 389 }
 390
 391 static uint8_t
 392 at91dci_data_rx(struct at91dci_td *td)
 393 {
 394         struct usb_page_search buf_res;
 395         uint32_t csr;
 396         uint32_t temp;
 397         uint16_t count;
 398         uint8_t to;
 399         uint8_t got_short;
 400
 401         to = 2;                         /* don't loop forever! */
 402         got_short = 0;
 403
 404         /* check if any of the FIFO banks have data */
 405 repeat:
 406         /* read out FIFO status */
 407         csr = bus_space_read_4(td->io_tag, td->io_hdl,
 408             td->status_reg);
 409
 410         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 411
 412         if (csr & AT91_UDP_CSR_RXSETUP) {
 413                 if (td->remainder == 0) {
 414                         /*
 415                          * We are actually complete and have
 416                          * received the next SETUP
 417                          */
 418                         DPRINTFN(5, "faking complete\n");
 419                         return (0);     /* complete */
 420                 }
 421                 /*
 422                  * USB Host Aborted the transfer.
 423                  */
 424                 td->error = 1;
 425                 return (0);             /* complete */
 426         }
 427         /* Make sure that "STALLSENT" gets cleared */
 428         temp = csr;
 429         temp &= AT91_UDP_CSR_STALLSENT;
 430
 431         /* check status */
 432         if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 |
 433             AT91_UDP_CSR_RX_DATA_BK1))) {
 434                 if (temp) {
 435                         /* write command */
 436                         AT91_CSR_ACK(csr, temp);
 437                         bus_space_write_4(td->io_tag, td->io_hdl,
 438                             td->status_reg, csr);
 439                 }
 440                 return (1);             /* not complete */
 441         }
 442         /* get the packet byte count */
 443         count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
 444
 445         /* verify the packet byte count */
 446         if (count != td->max_packet_size) {
 447                 if (count < td->max_packet_size) {
 448                         /* we have a short packet */
 449                         td->short_pkt = 1;
 450                         got_short = 1;
 451                 } else {
 452                         /* invalid USB packet */
 453                         td->error = 1;
 454                         return (0);     /* we are complete */
 455                 }
 456         }
 457         /* verify the packet byte count */
 458         if (count > td->remainder) {
 459                 /* invalid USB packet */
 460                 td->error = 1;
 461                 return (0);             /* we are complete */
 462         }
 463         while (count > 0) {
 464                 usbd_get_page(td->pc, td->offset, &buf_res);
 465
 466                 /* get correct length */
 467                 if (buf_res.length > count) {
 468                         buf_res.length = count;
 469                 }
 470                 /* receive data */
 471                 bus_space_read_multi_1(td->io_tag, td->io_hdl,
 472                     td->fifo_reg, buf_res.buffer, buf_res.length);
 473
 474                 /* update counters */
 475                 count -= buf_res.length;
 476                 td->offset += buf_res.length;
 477                 td->remainder -= buf_res.length;
 478         }
 479
 480         /* clear status bits */
 481         if (td->support_multi_buffer) {
 482                 if (td->fifo_bank) {
 483                         td->fifo_bank = 0;
 484                         temp |= AT91_UDP_CSR_RX_DATA_BK1;
 485                 } else {
 486                         td->fifo_bank = 1;
 487                         temp |= AT91_UDP_CSR_RX_DATA_BK0;
 488                 }
 489         } else {
 490                 temp |= (AT91_UDP_CSR_RX_DATA_BK0 |
 491                     AT91_UDP_CSR_RX_DATA_BK1);
 492         }
 493
 494         /* write command */
 495         AT91_CSR_ACK(csr, temp);
 496         bus_space_write_4(td->io_tag, td->io_hdl,
 497             td->status_reg, csr);
 498
 499         /*
 500          * NOTE: We may have to delay a little bit before
 501          * proceeding after clearing the DATA_BK bits.
 502          */
 503
 504         /* check if we are complete */
 505         if ((td->remainder == 0) || got_short) {
 506                 if (td->short_pkt) {
 507                         /* we are complete */
 508                         return (0);
 509                 }
 510                 /* else need to receive a zero length packet */
 511         }
 512         if (--to) {
 513                 goto repeat;
 514         }
 515         return (1);                     /* not complete */
 516 }
 517
 518 static uint8_t
 519 at91dci_data_tx(struct at91dci_td *td)
 520 {
 521         struct usb_page_search buf_res;
 522         uint32_t csr;
 523         uint32_t temp;
 524         uint16_t count;
 525         uint8_t to;
 526
 527         to = 2;                         /* don't loop forever! */
 528
 529 repeat:
 530
 531         /* read out FIFO status */
 532         csr = bus_space_read_4(td->io_tag, td->io_hdl,
 533             td->status_reg);
 534
 535         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 536
 537         if (csr & AT91_UDP_CSR_RXSETUP) {
 538                 /*
 539                  * The current transfer was aborted
 540                  * by the USB Host
 541                  */
 542                 td->error = 1;
 543                 return (0);             /* complete */
 544         }
 545         /* Make sure that "STALLSENT" gets cleared */
 546         temp = csr;
 547         temp &= AT91_UDP_CSR_STALLSENT;
 548
 549         if (csr & AT91_UDP_CSR_TXPKTRDY) {
 550                 if (temp) {
 551                         /* write command */
 552                         AT91_CSR_ACK(csr, temp);
 553                         bus_space_write_4(td->io_tag, td->io_hdl,
 554                             td->status_reg, csr);
 555                 }
 556                 return (1);             /* not complete */
 557         } else {
 558                 /* clear TXCOMP and set TXPKTRDY */
 559                 temp |= (AT91_UDP_CSR_TXCOMP |
 560                     AT91_UDP_CSR_TXPKTRDY);
 561         }
 562
 563         count = td->max_packet_size;
 564         if (td->remainder < count) {
 565                 /* we have a short packet */
 566                 td->short_pkt = 1;
 567                 count = td->remainder;
 568         }
 569         while (count > 0) {
 570
 571                 usbd_get_page(td->pc, td->offset, &buf_res);
 572
 573                 /* get correct length */
 574                 if (buf_res.length > count) {
 575                         buf_res.length = count;
 576                 }
 577                 /* transmit data */
 578                 bus_space_write_multi_1(td->io_tag, td->io_hdl,
 579                     td->fifo_reg, buf_res.buffer, buf_res.length);
 580
 581                 /* update counters */
 582                 count -= buf_res.length;
 583                 td->offset += buf_res.length;
 584                 td->remainder -= buf_res.length;
 585         }
 586
 587         /* write command */
 588         AT91_CSR_ACK(csr, temp);
 589         bus_space_write_4(td->io_tag, td->io_hdl,
 590             td->status_reg, csr);
 591
 592         /* check remainder */
 593         if (td->remainder == 0) {
 594                 if (td->short_pkt) {
 595                         return (0);     /* complete */
 596                 }
 597                 /* else we need to transmit a short packet */
 598         }
 599         if (--to) {
 600                 goto repeat;
 601         }
 602         return (1);                     /* not complete */
 603 }
 604
 605 static uint8_t
 606 at91dci_data_tx_sync(struct at91dci_td *td)
 607 {
 608         struct at91dci_softc *sc;
 609         uint32_t csr;
 610         uint32_t temp;
 611
 612 #if 0
 613 repeat:
 614 #endif
 615
 616         /* read out FIFO status */
 617         csr = bus_space_read_4(td->io_tag, td->io_hdl,
 618             td->status_reg);
 619
 620         DPRINTFN(5, "csr=0x%08x\n", csr);
 621
 622         if (csr & AT91_UDP_CSR_RXSETUP) {
 623                 DPRINTFN(5, "faking complete\n");
 624                 /* Race condition */
 625                 return (0);             /* complete */
 626         }
 627         temp = csr;
 628         temp &= (AT91_UDP_CSR_STALLSENT |
 629             AT91_UDP_CSR_TXCOMP);
 630
 631         /* check status */
 632         if (csr & AT91_UDP_CSR_TXPKTRDY) {
 633                 goto not_complete;
 634         }
 635         if (!(csr & AT91_UDP_CSR_TXCOMP)) {
 636                 goto not_complete;
 637         }
 638         sc = AT9100_DCI_PC2SC(td->pc);
 639         if (sc->sc_dv_addr != 0xFF) {
 640                 /*
 641                  * The AT91 has a special requirement with regard to
 642                  * setting the address and that is to write the new
 643                  * address before clearing TXCOMP:
 644                  */
 645                 at91dci_set_address(sc, sc->sc_dv_addr);
 646         }
 647         /* write command */
 648         AT91_CSR_ACK(csr, temp);
 649         bus_space_write_4(td->io_tag, td->io_hdl,
 650             td->status_reg, csr);
 651
 652         return (0);                     /* complete */
 653
 654 not_complete:
 655         if (temp) {
 656                 /* write command */
 657                 AT91_CSR_ACK(csr, temp);
 658                 bus_space_write_4(td->io_tag, td->io_hdl,
 659                     td->status_reg, csr);
 660         }
 661         return (1);                     /* not complete */
 662 }
 663
 664 static uint8_t
 665 at91dci_xfer_do_fifo(struct usb_xfer *xfer)
 666 {
 667         struct at91dci_softc *sc;
 668         struct at91dci_td *td;
 669         uint8_t temp;
 670
 671         DPRINTFN(9, "\n");
 672
 673         td = xfer->td_transfer_cache;
 674         while (1) {
 675                 if ((td->func) (td)) {
 676                         /* operation in progress */
 677                         break;
 678                 }
 679                 if (((void *)td) == xfer->td_transfer_last) {
 680                         goto done;
 681                 }
 682                 if (td->error) {
 683                         goto done;
 684                 } else if (td->remainder > 0) {
 685                         /*
 686                          * We had a short transfer. If there is no alternate
 687                          * next, stop processing !
 688                          */
 689                         if (!td->alt_next) {
 690                                 goto done;
 691                         }
 692                 }
 693                 /*
 694                  * Fetch the next transfer descriptor and transfer
 695                  * some flags to the next transfer descriptor
 696                  */
 697                 temp = 0;
 698                 if (td->fifo_bank)
 699                         temp |= 1;
 700                 td = td->obj_next;
 701                 xfer->td_transfer_cache = td;
 702                 if (temp & 1)
 703                         td->fifo_bank = 1;
 704         }
 705         return (1);                     /* not complete */
 706
 707 done:
 708         sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
 709         temp = (xfer->endpointno & UE_ADDR);
 710
 711         /* update FIFO bank flag and multi buffer */
 712         if (td->fifo_bank) {
 713                 sc->sc_ep_flags[temp].fifo_bank = 1;
 714         } else {
 715                 sc->sc_ep_flags[temp].fifo_bank = 0;
 716         }
 717
 718         /* compute all actual lengths */
 719
 720         at91dci_standard_done(xfer);
 721
 722         return (0);                     /* complete */
 723 }
 724
 725 static void
 726 at91dci_interrupt_poll(struct at91dci_softc *sc)
 727 {
 728         struct usb_xfer *xfer;
 729
 730 repeat:
 731         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 732                 if (!at91dci_xfer_do_fifo(xfer)) {
 733                         /* queue has been modified */
 734                         goto repeat;
 735                 }
 736         }
 737 }
 738
 739 void
 740 at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on)
 741 {
 742         DPRINTFN(5, "vbus = %u\n", is_on);
 743
 744         USB_BUS_LOCK(&sc->sc_bus);
 745         if (is_on) {
 746                 if (!sc->sc_flags.status_vbus) {
 747                         sc->sc_flags.status_vbus = 1;
 748
 749                         /* complete root HUB interrupt endpoint */
 750                         at91dci_root_intr(sc);
 751                 }
 752         } else {
 753                 if (sc->sc_flags.status_vbus) {
 754                         sc->sc_flags.status_vbus = 0;
 755                         sc->sc_flags.status_bus_reset = 0;
 756                         sc->sc_flags.status_suspend = 0;
 757                         sc->sc_flags.change_suspend = 0;
 758                         sc->sc_flags.change_connect = 1;
 759
 760                         /* complete root HUB interrupt endpoint */
 761                         at91dci_root_intr(sc);
 762                 }
 763         }
 764         USB_BUS_UNLOCK(&sc->sc_bus);
 765 }
 766
 767 void
 768 at91dci_interrupt(struct at91dci_softc *sc)
 769 {
 770         uint32_t status;
 771
 772         USB_BUS_LOCK(&sc->sc_bus);
 773
 774         status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
 775         status &= AT91_UDP_INT_DEFAULT;
 776
 777         if (!status) {
 778                 USB_BUS_UNLOCK(&sc->sc_bus);
 779                 return;
 780         }
 781         /* acknowledge interrupts */
 782
 783         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status);
 784
 785         /* check for any bus state change interrupts */
 786
 787         if (status & AT91_UDP_INT_BUS) {
 788
 789                 DPRINTFN(5, "real bus interrupt 0x%08x\n", status);
 790
 791                 if (status & AT91_UDP_INT_END_BR) {
 792
 793                         /* set correct state */
 794                         sc->sc_flags.status_bus_reset = 1;
 795                         sc->sc_flags.status_suspend = 0;
 796                         sc->sc_flags.change_suspend = 0;
 797                         sc->sc_flags.change_connect = 1;
 798
 799                         /* disable resume interrupt */
 800                         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 801                             AT91_UDP_INT_RXRSM);
 802                         /* enable suspend interrupt */
 803                         AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 804                             AT91_UDP_INT_RXSUSP);
 805                 }
 806                 /*
 807                  * If RXRSM and RXSUSP is set at the same time we interpret
 808                  * that like RESUME. Resume is set when there is at least 3
 809                  * milliseconds of inactivity on the USB BUS.
 810                  */
 811                 if (status & AT91_UDP_INT_RXRSM) {
 812                         if (sc->sc_flags.status_suspend) {
 813                                 sc->sc_flags.status_suspend = 0;
 814                                 sc->sc_flags.change_suspend = 1;
 815
 816                                 /* disable resume interrupt */
 817                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 818                                     AT91_UDP_INT_RXRSM);
 819                                 /* enable suspend interrupt */
 820                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 821                                     AT91_UDP_INT_RXSUSP);
 822                         }
 823                 } else if (status & AT91_UDP_INT_RXSUSP) {
 824                         if (!sc->sc_flags.status_suspend) {
 825                                 sc->sc_flags.status_suspend = 1;
 826                                 sc->sc_flags.change_suspend = 1;
 827
 828                                 /* disable suspend interrupt */
 829                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 830                                     AT91_UDP_INT_RXSUSP);
 831
 832                                 /* enable resume interrupt */
 833                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 834                                     AT91_UDP_INT_RXRSM);
 835                         }
 836                 }
 837                 /* complete root HUB interrupt endpoint */
 838                 at91dci_root_intr(sc);
 839         }
 840         /* check for any endpoint interrupts */
 841
 842         if (status & AT91_UDP_INT_EPS) {
 843
 844                 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status);
 845
 846                 at91dci_interrupt_poll(sc);
 847         }
 848         USB_BUS_UNLOCK(&sc->sc_bus);
 849 }
 850
 851 static void
 852 at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp)
 853 {
 854         struct at91dci_td *td;
 855
 856         /* get current Transfer Descriptor */
 857         td = temp->td_next;
 858         temp->td = td;
 859
 860         /* prepare for next TD */
 861         temp->td_next = td->obj_next;
 862
 863         /* fill out the Transfer Descriptor */
 864         td->func = temp->func;
 865         td->pc = temp->pc;
 866         td->offset = temp->offset;
 867         td->remainder = temp->len;
 868         td->fifo_bank = 0;
 869         td->error = 0;
 870         td->did_stall = temp->did_stall;
 871         td->short_pkt = temp->short_pkt;
 872         td->alt_next = temp->setup_alt_next;
 873 }
 874
 875 static void
 876 at91dci_setup_standard_chain(struct usb_xfer *xfer)
 877 {
 878         struct at91dci_std_temp temp;
 879         struct at91dci_softc *sc;
 880         struct at91dci_td *td;
 881         uint32_t x;
 882         uint8_t ep_no;
 883         uint8_t need_sync;
 884
 885         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 886             xfer->address, UE_GET_ADDR(xfer->endpointno),
 887             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 888
 889         temp.max_frame_size = xfer->max_frame_size;
 890
 891         td = xfer->td_start[0];
 892         xfer->td_transfer_first = td;
 893         xfer->td_transfer_cache = td;
 894
 895         /* setup temp */
 896
 897         temp.td = NULL;
 898         temp.td_next = xfer->td_start[0];
 899         temp.offset = 0;
 900         temp.setup_alt_next = xfer->flags_int.short_frames_ok;
 901         temp.did_stall = !xfer->flags_int.control_stall;
 902
 903         sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
 904         ep_no = (xfer->endpointno & UE_ADDR);
 905
 906         /* check if we should prepend a setup message */
 907
 908         if (xfer->flags_int.control_xfr) {
 909                 if (xfer->flags_int.control_hdr) {
 910
 911                         temp.func = &at91dci_setup_rx;
 912                         temp.len = xfer->frlengths[0];
 913                         temp.pc = xfer->frbuffers + 0;
 914                         temp.short_pkt = temp.len ? 1 : 0;
 915                         /* check for last frame */
 916                         if (xfer->nframes == 1) {
 917                                 /* no STATUS stage yet, SETUP is last */
 918                                 if (xfer->flags_int.control_act)
 919                                         temp.setup_alt_next = 0;
 920                         }
 921
 922                         at91dci_setup_standard_chain_sub(&temp);
 923                 }
 924                 x = 1;
 925         } else {
 926                 x = 0;
 927         }
 928
 929         if (x != xfer->nframes) {
 930                 if (xfer->endpointno & UE_DIR_IN) {
 931                         temp.func = &at91dci_data_tx;
 932                         need_sync = 1;
 933                 } else {
 934                         temp.func = &at91dci_data_rx;
 935                         need_sync = 0;
 936                 }
 937
 938                 /* setup "pc" pointer */
 939                 temp.pc = xfer->frbuffers + x;
 940         } else {
 941                 need_sync = 0;
 942         }
 943         while (x != xfer->nframes) {
 944
 945                 /* DATA0 / DATA1 message */
 946
 947                 temp.len = xfer->frlengths[x];
 948
 949                 x++;
 950
 951                 if (x == xfer->nframes) {
 952                         if (xfer->flags_int.control_xfr) {
 953                                 if (xfer->flags_int.control_act) {
 954                                         temp.setup_alt_next = 0;
 955                                 }
 956                         } else {
 957                                 temp.setup_alt_next = 0;
 958                         }
 959                 }
 960                 if (temp.len == 0) {
 961
 962                         /* make sure that we send an USB packet */
 963
 964                         temp.short_pkt = 0;
 965
 966                 } else {
 967
 968                         /* regular data transfer */
 969
 970                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
 971                 }
 972
 973                 at91dci_setup_standard_chain_sub(&temp);
 974
 975                 if (xfer->flags_int.isochronous_xfr) {
 976                         temp.offset += temp.len;
 977                 } else {
 978                         /* get next Page Cache pointer */
 979                         temp.pc = xfer->frbuffers + x;
 980                 }
 981         }
 982
 983         /* check for control transfer */
 984         if (xfer->flags_int.control_xfr) {
 985
 986                 /* always setup a valid "pc" pointer for status and sync */
 987                 temp.pc = xfer->frbuffers + 0;
 988                 temp.len = 0;
 989                 temp.short_pkt = 0;
 990                 temp.setup_alt_next = 0;
 991
 992                 /* check if we need to sync */
 993                 if (need_sync) {
 994                         /* we need a SYNC point after TX */
 995                         temp.func = &at91dci_data_tx_sync;
 996                         at91dci_setup_standard_chain_sub(&temp);
 997                 }
 998
 999                 /* check if we should append a status stage */
1000                 if (!xfer->flags_int.control_act) {
1001
1002                         /*
1003                          * Send a DATA1 message and invert the current
1004                          * endpoint direction.
1005                          */
1006                         if (xfer->endpointno & UE_DIR_IN) {
1007                                 temp.func = &at91dci_data_rx;
1008                                 need_sync = 0;
1009                         } else {
1010                                 temp.func = &at91dci_data_tx;
1011                                 need_sync = 1;
1012                         }
1013
1014                         at91dci_setup_standard_chain_sub(&temp);
1015                         if (need_sync) {
1016                                 /* we need a SYNC point after TX */
1017                                 temp.func = &at91dci_data_tx_sync;
1018                                 at91dci_setup_standard_chain_sub(&temp);
1019                         }
1020                 }
1021         }
1022
1023         /* must have at least one frame! */
1024         td = temp.td;
1025         xfer->td_transfer_last = td;
1026
1027         /* setup the correct fifo bank */
1028         if (sc->sc_ep_flags[ep_no].fifo_bank) {
1029                 td = xfer->td_transfer_first;
1030                 td->fifo_bank = 1;
1031         }
1032 }
1033
1034 static void
1035 at91dci_timeout(void *arg)
1036 {
1037         struct usb_xfer *xfer = arg;
1038
1039         DPRINTF("xfer=%p\n", xfer);
1040
1041         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1042
1043         /* transfer is transferred */
1044         at91dci_device_done(xfer, USB_ERR_TIMEOUT);
1045 }
1046
1047 static void
1048 at91dci_start_standard_chain(struct usb_xfer *xfer)
1049 {
1050         DPRINTFN(9, "\n");
1051
1052         /* poll one time */
1053         if (at91dci_xfer_do_fifo(xfer)) {
1054
1055                 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1056                 uint8_t ep_no = xfer->endpointno & UE_ADDR;
1057
1058                 /*
1059                  * Only enable the endpoint interrupt when we are actually
1060                  * waiting for data, hence we are dealing with level
1061                  * triggered interrupts !
1062                  */
1063                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no));
1064
1065                 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no);
1066
1067                 /* put transfer on interrupt queue */
1068                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1069
1070                 /* start timeout, if any */
1071                 if (xfer->timeout != 0) {
1072                         usbd_transfer_timeout_ms(xfer,
1073                             &at91dci_timeout, xfer->timeout);
1074                 }
1075         }
1076 }
1077
1078 static void
1079 at91dci_root_intr(struct at91dci_softc *sc)
1080 {
1081         DPRINTFN(9, "\n");
1082
1083         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1084
1085         /* set port bit */
1086         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
1087
1088         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1089             sizeof(sc->sc_hub_idata));
1090 }
1091
1092 static usb_error_t
1093 at91dci_standard_done_sub(struct usb_xfer *xfer)
1094 {
1095         struct at91dci_td *td;
1096         uint32_t len;
1097         uint8_t error;
1098
1099         DPRINTFN(9, "\n");
1100
1101         td = xfer->td_transfer_cache;
1102
1103         do {
1104                 len = td->remainder;
1105
1106                 if (xfer->aframes != xfer->nframes) {
1107                         /*
1108                          * Verify the length and subtract
1109                          * the remainder from "frlengths[]":
1110                          */
1111                         if (len > xfer->frlengths[xfer->aframes]) {
1112                                 td->error = 1;
1113                         } else {
1114                                 xfer->frlengths[xfer->aframes] -= len;
1115                         }
1116                 }
1117                 /* Check for transfer error */
1118                 if (td->error) {
1119                         /* the transfer is finished */
1120                         error = 1;
1121                         td = NULL;
1122                         break;
1123                 }
1124                 /* Check for short transfer */
1125                 if (len > 0) {
1126                         if (xfer->flags_int.short_frames_ok) {
1127                                 /* follow alt next */
1128                                 if (td->alt_next) {
1129                                         td = td->obj_next;
1130                                 } else {
1131                                         td = NULL;
1132                                 }
1133                         } else {
1134                                 /* the transfer is finished */
1135                                 td = NULL;
1136                         }
1137                         error = 0;
1138                         break;
1139                 }
1140                 td = td->obj_next;
1141
1142                 /* this USB frame is complete */
1143                 error = 0;
1144                 break;
1145
1146         } while (0);
1147
1148         /* update transfer cache */
1149
1150         xfer->td_transfer_cache = td;
1151
1152         return (error ?
1153             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1154 }
1155
1156 static void
1157 at91dci_standard_done(struct usb_xfer *xfer)
1158 {
1159         usb_error_t err = 0;
1160
1161         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1162             xfer, xfer->endpoint);
1163
1164         /* reset scanner */
1165
1166         xfer->td_transfer_cache = xfer->td_transfer_first;
1167
1168         if (xfer->flags_int.control_xfr) {
1169
1170                 if (xfer->flags_int.control_hdr) {
1171
1172                         err = at91dci_standard_done_sub(xfer);
1173                 }
1174                 xfer->aframes = 1;
1175
1176                 if (xfer->td_transfer_cache == NULL) {
1177                         goto done;
1178                 }
1179         }
1180         while (xfer->aframes != xfer->nframes) {
1181
1182                 err = at91dci_standard_done_sub(xfer);
1183                 xfer->aframes++;
1184
1185                 if (xfer->td_transfer_cache == NULL) {
1186                         goto done;
1187                 }
1188         }
1189
1190         if (xfer->flags_int.control_xfr &&
1191             !xfer->flags_int.control_act) {
1192
1193                 err = at91dci_standard_done_sub(xfer);
1194         }
1195 done:
1196         at91dci_device_done(xfer, err);
1197 }
1198
1199 /*------------------------------------------------------------------------*
1200  *      at91dci_device_done
1201  *
1202  * NOTE: this function can be called more than one time on the
1203  * same USB transfer!
1204  *------------------------------------------------------------------------*/
1205 static void
1206 at91dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1207 {
1208         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1209         uint8_t ep_no;
1210
1211         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1212
1213         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1214             xfer, xfer->endpoint, error);
1215
1216         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1217                 ep_no = (xfer->endpointno & UE_ADDR);
1218
1219                 /* disable endpoint interrupt */
1220                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no));
1221
1222                 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no);
1223         }
1224         /* dequeue transfer and start next transfer */
1225         usbd_transfer_done(xfer, error);
1226 }
1227
1228 static void
1229 at91dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1230     struct usb_endpoint *ep, uint8_t *did_stall)
1231 {
1232         struct at91dci_softc *sc;
1233         uint32_t csr_val;
1234         uint8_t csr_reg;
1235
1236         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1237
1238         DPRINTFN(5, "endpoint=%p\n", ep);
1239
1240         if (xfer) {
1241                 /* cancel any ongoing transfers */
1242                 at91dci_device_done(xfer, USB_ERR_STALLED);
1243         }
1244         /* set FORCESTALL */
1245         sc = AT9100_DCI_BUS2SC(udev->bus);
1246         csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR);
1247         csr_reg = AT91_UDP_CSR(csr_reg);
1248         csr_val = AT91_UDP_READ_4(sc, csr_reg);
1249         AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL);
1250         AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1251 }
1252
1253 static void
1254 at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no,
1255     uint8_t ep_type, uint8_t ep_dir)
1256 {
1257         const struct usb_hw_ep_profile *pf;
1258         uint32_t csr_val;
1259         uint32_t temp;
1260         uint8_t csr_reg;
1261         uint8_t to;
1262
1263         if (ep_type == UE_CONTROL) {
1264                 /* clearing stall is not needed */
1265                 return;
1266         }
1267         /* compute CSR register offset */
1268         csr_reg = AT91_UDP_CSR(ep_no);
1269
1270         /* compute default CSR value */
1271         csr_val = 0;
1272         AT91_CSR_ACK(csr_val, 0);
1273
1274         /* disable endpoint */
1275         AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1276
1277         /* get endpoint profile */
1278         at91dci_get_hw_ep_profile(NULL, &pf, ep_no);
1279
1280         /* reset FIFO */
1281         AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no));
1282         AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0);
1283
1284         /*
1285          * NOTE: One would assume that a FIFO reset would release the
1286          * FIFO banks aswell, but it doesn't! We have to do this
1287          * manually!
1288          */
1289
1290         /* release FIFO banks, if any */
1291         for (to = 0; to != 2; to++) {
1292
1293                 /* get csr value */
1294                 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1295
1296                 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 |
1297                     AT91_UDP_CSR_RX_DATA_BK1)) {
1298                         /* clear status bits */
1299                         if (pf->support_multi_buffer) {
1300                                 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1301                                         sc->sc_ep_flags[ep_no].fifo_bank = 0;
1302                                         temp = AT91_UDP_CSR_RX_DATA_BK1;
1303                                 } else {
1304                                         sc->sc_ep_flags[ep_no].fifo_bank = 1;
1305                                         temp = AT91_UDP_CSR_RX_DATA_BK0;
1306                                 }
1307                         } else {
1308                                 temp = (AT91_UDP_CSR_RX_DATA_BK0 |
1309                                     AT91_UDP_CSR_RX_DATA_BK1);
1310                         }
1311                 } else {
1312                         temp = 0;
1313                 }
1314
1315                 /* clear FORCESTALL */
1316                 temp |= AT91_UDP_CSR_STALLSENT;
1317
1318                 AT91_CSR_ACK(csr_val, temp);
1319                 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1320         }
1321
1322         /* compute default CSR value */
1323         csr_val = 0;
1324         AT91_CSR_ACK(csr_val, 0);
1325
1326         /* enable endpoint */
1327         csr_val &= ~AT91_UDP_CSR_ET_MASK;
1328         csr_val |= AT91_UDP_CSR_EPEDS;
1329
1330         if (ep_type == UE_CONTROL) {
1331                 csr_val |= AT91_UDP_CSR_ET_CTRL;
1332         } else {
1333                 if (ep_type == UE_BULK) {
1334                         csr_val |= AT91_UDP_CSR_ET_BULK;
1335                 } else if (ep_type == UE_INTERRUPT) {
1336                         csr_val |= AT91_UDP_CSR_ET_INT;
1337                 } else {
1338                         csr_val |= AT91_UDP_CSR_ET_ISO;
1339                 }
1340                 if (ep_dir & UE_DIR_IN) {
1341                         csr_val |= AT91_UDP_CSR_ET_DIR_IN;
1342                 }
1343         }
1344
1345         /* enable endpoint */
1346         AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val);
1347 }
1348
1349 static void
1350 at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1351 {
1352         struct at91dci_softc *sc;
1353         struct usb_endpoint_descriptor *ed;
1354
1355         DPRINTFN(5, "endpoint=%p\n", ep);
1356
1357         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1358
1359         /* check mode */
1360         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1361                 /* not supported */
1362                 return;
1363         }
1364         /* get softc */
1365         sc = AT9100_DCI_BUS2SC(udev->bus);
1366
1367         /* get endpoint descriptor */
1368         ed = ep->edesc;
1369
1370         /* reset endpoint */
1371         at91dci_clear_stall_sub(sc,
1372             (ed->bEndpointAddress & UE_ADDR),
1373             (ed->bmAttributes & UE_XFERTYPE),
1374             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1375 }
1376
1377 usb_error_t
1378 at91dci_init(struct at91dci_softc *sc)
1379 {
1380         uint32_t csr_val;
1381         uint8_t n;
1382
1383         DPRINTF("start\n");
1384
1385         /* set up the bus structure */
1386         sc->sc_bus.usbrev = USB_REV_1_1;
1387         sc->sc_bus.methods = &at91dci_bus_methods;
1388
1389         USB_BUS_LOCK(&sc->sc_bus);
1390
1391         /* turn on clocks */
1392
1393         if (sc->sc_clocks_on) {
1394                 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1395         }
1396         /* wait a little for things to stabilise */
1397         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1398
1399         /* disable and clear all interrupts */
1400
1401         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1402         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1403
1404         /* compute default CSR value */
1405
1406         csr_val = 0;
1407         AT91_CSR_ACK(csr_val, 0);
1408
1409         /* disable all endpoints */
1410
1411         for (n = 0; n != AT91_UDP_EP_MAX; n++) {
1412
1413                 /* disable endpoint */
1414                 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val);
1415         }
1416
1417         /* enable the control endpoint */
1418
1419         AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL |
1420             AT91_UDP_CSR_EPEDS);
1421
1422         /* write to FIFO control register */
1423
1424         AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val);
1425
1426         /* enable the interrupts we want */
1427
1428         AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS);
1429
1430         /* turn off clocks */
1431
1432         at91dci_clocks_off(sc);
1433
1434         USB_BUS_UNLOCK(&sc->sc_bus);
1435
1436         /* catch any lost interrupts */
1437
1438         at91dci_do_poll(&sc->sc_bus);
1439
1440         return (0);                     /* success */
1441 }
1442
1443 void
1444 at91dci_uninit(struct at91dci_softc *sc)
1445 {
1446         USB_BUS_LOCK(&sc->sc_bus);
1447
1448         /* disable and clear all interrupts */
1449         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1450         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1451
1452         sc->sc_flags.port_powered = 0;
1453         sc->sc_flags.status_vbus = 0;
1454         sc->sc_flags.status_bus_reset = 0;
1455         sc->sc_flags.status_suspend = 0;
1456         sc->sc_flags.change_suspend = 0;
1457         sc->sc_flags.change_connect = 1;
1458
1459         at91dci_pull_down(sc);
1460         at91dci_clocks_off(sc);
1461         USB_BUS_UNLOCK(&sc->sc_bus);
1462 }
1463
1464 void
1465 at91dci_suspend(struct at91dci_softc *sc)
1466 {
1467         return;
1468 }
1469
1470 void
1471 at91dci_resume(struct at91dci_softc *sc)
1472 {
1473         return;
1474 }
1475
1476 static void
1477 at91dci_do_poll(struct usb_bus *bus)
1478 {
1479         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
1480
1481         USB_BUS_LOCK(&sc->sc_bus);
1482         at91dci_interrupt_poll(sc);
1483         USB_BUS_UNLOCK(&sc->sc_bus);
1484 }
1485
1486 /*------------------------------------------------------------------------*
1487  * at91dci bulk support
1488  *------------------------------------------------------------------------*/
1489 static void
1490 at91dci_device_bulk_open(struct usb_xfer *xfer)
1491 {
1492         return;
1493 }
1494
1495 static void
1496 at91dci_device_bulk_close(struct usb_xfer *xfer)
1497 {
1498         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1499 }
1500
1501 static void
1502 at91dci_device_bulk_enter(struct usb_xfer *xfer)
1503 {
1504         return;
1505 }
1506
1507 static void
1508 at91dci_device_bulk_start(struct usb_xfer *xfer)
1509 {
1510         /* setup TDs */
1511         at91dci_setup_standard_chain(xfer);
1512         at91dci_start_standard_chain(xfer);
1513 }
1514
1515 struct usb_pipe_methods at91dci_device_bulk_methods =
1516 {
1517         .open = at91dci_device_bulk_open,
1518         .close = at91dci_device_bulk_close,
1519         .enter = at91dci_device_bulk_enter,
1520         .start = at91dci_device_bulk_start,
1521 };
1522
1523 /*------------------------------------------------------------------------*
1524  * at91dci control support
1525  *------------------------------------------------------------------------*/
1526 static void
1527 at91dci_device_ctrl_open(struct usb_xfer *xfer)
1528 {
1529         return;
1530 }
1531
1532 static void
1533 at91dci_device_ctrl_close(struct usb_xfer *xfer)
1534 {
1535         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1536 }
1537
1538 static void
1539 at91dci_device_ctrl_enter(struct usb_xfer *xfer)
1540 {
1541         return;
1542 }
1543
1544 static void
1545 at91dci_device_ctrl_start(struct usb_xfer *xfer)
1546 {
1547         /* setup TDs */
1548         at91dci_setup_standard_chain(xfer);
1549         at91dci_start_standard_chain(xfer);
1550 }
1551
1552 struct usb_pipe_methods at91dci_device_ctrl_methods =
1553 {
1554         .open = at91dci_device_ctrl_open,
1555         .close = at91dci_device_ctrl_close,
1556         .enter = at91dci_device_ctrl_enter,
1557         .start = at91dci_device_ctrl_start,
1558 };
1559
1560 /*------------------------------------------------------------------------*
1561  * at91dci interrupt support
1562  *------------------------------------------------------------------------*/
1563 static void
1564 at91dci_device_intr_open(struct usb_xfer *xfer)
1565 {
1566         return;
1567 }
1568
1569 static void
1570 at91dci_device_intr_close(struct usb_xfer *xfer)
1571 {
1572         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1573 }
1574
1575 static void
1576 at91dci_device_intr_enter(struct usb_xfer *xfer)
1577 {
1578         return;
1579 }
1580
1581 static void
1582 at91dci_device_intr_start(struct usb_xfer *xfer)
1583 {
1584         /* setup TDs */
1585         at91dci_setup_standard_chain(xfer);
1586         at91dci_start_standard_chain(xfer);
1587 }
1588
1589 struct usb_pipe_methods at91dci_device_intr_methods =
1590 {
1591         .open = at91dci_device_intr_open,
1592         .close = at91dci_device_intr_close,
1593         .enter = at91dci_device_intr_enter,
1594         .start = at91dci_device_intr_start,
1595 };
1596
1597 /*------------------------------------------------------------------------*
1598  * at91dci full speed isochronous support
1599  *------------------------------------------------------------------------*/
1600 static void
1601 at91dci_device_isoc_fs_open(struct usb_xfer *xfer)
1602 {
1603         return;
1604 }
1605
1606 static void
1607 at91dci_device_isoc_fs_close(struct usb_xfer *xfer)
1608 {
1609         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1610 }
1611
1612 static void
1613 at91dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1614 {
1615         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1616         uint32_t temp;
1617         uint32_t nframes;
1618
1619         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1620             xfer, xfer->endpoint->isoc_next, xfer->nframes);
1621
1622         /* get the current frame index */
1623
1624         nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM);
1625
1626         /*
1627          * check if the frame index is within the window where the frames
1628          * will be inserted
1629          */
1630         temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK;
1631
1632         if ((xfer->endpoint->is_synced == 0) ||
1633             (temp < xfer->nframes)) {
1634                 /*
1635                  * If there is data underflow or the endpoint queue is
1636                  * empty we schedule the transfer a few frames ahead
1637                  * of the current frame position. Else two isochronous
1638                  * transfers might overlap.
1639                  */
1640                 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK;
1641                 xfer->endpoint->is_synced = 1;
1642                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1643         }
1644         /*
1645          * compute how many milliseconds the insertion is ahead of the
1646          * current frame position:
1647          */
1648         temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK;
1649
1650         /*
1651          * pre-compute when the isochronous transfer will be finished:
1652          */
1653         xfer->isoc_time_complete =
1654             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1655             xfer->nframes;
1656
1657         /* compute frame number for next insertion */
1658         xfer->endpoint->isoc_next += xfer->nframes;
1659
1660         /* setup TDs */
1661         at91dci_setup_standard_chain(xfer);
1662 }
1663
1664 static void
1665 at91dci_device_isoc_fs_start(struct usb_xfer *xfer)
1666 {
1667         /* start TD chain */
1668         at91dci_start_standard_chain(xfer);
1669 }
1670
1671 struct usb_pipe_methods at91dci_device_isoc_fs_methods =
1672 {
1673         .open = at91dci_device_isoc_fs_open,
1674         .close = at91dci_device_isoc_fs_close,
1675         .enter = at91dci_device_isoc_fs_enter,
1676         .start = at91dci_device_isoc_fs_start,
1677 };
1678
1679 /*------------------------------------------------------------------------*
1680  * at91dci root control support
1681  *------------------------------------------------------------------------*
1682  * Simulate a hardware HUB by handling all the necessary requests.
1683  *------------------------------------------------------------------------*/
1684
1685 static const struct usb_device_descriptor at91dci_devd = {
1686         .bLength = sizeof(struct usb_device_descriptor),
1687         .bDescriptorType = UDESC_DEVICE,
1688         .bcdUSB = {0x00, 0x02},
1689         .bDeviceClass = UDCLASS_HUB,
1690         .bDeviceSubClass = UDSUBCLASS_HUB,
1691         .bDeviceProtocol = UDPROTO_HSHUBSTT,
1692         .bMaxPacketSize = 64,
1693         .bcdDevice = {0x00, 0x01},
1694         .iManufacturer = 1,
1695         .iProduct = 2,
1696         .bNumConfigurations = 1,
1697 };
1698
1699 static const struct usb_device_qualifier at91dci_odevd = {
1700         .bLength = sizeof(struct usb_device_qualifier),
1701         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1702         .bcdUSB = {0x00, 0x02},
1703         .bDeviceClass = UDCLASS_HUB,
1704         .bDeviceSubClass = UDSUBCLASS_HUB,
1705         .bDeviceProtocol = UDPROTO_FSHUB,
1706         .bMaxPacketSize0 = 0,
1707         .bNumConfigurations = 0,
1708 };
1709
1710 static const struct at91dci_config_desc at91dci_confd = {
1711         .confd = {
1712                 .bLength = sizeof(struct usb_config_descriptor),
1713                 .bDescriptorType = UDESC_CONFIG,
1714                 .wTotalLength[0] = sizeof(at91dci_confd),
1715                 .bNumInterface = 1,
1716                 .bConfigurationValue = 1,
1717                 .iConfiguration = 0,
1718                 .bmAttributes = UC_SELF_POWERED,
1719                 .bMaxPower = 0,
1720         },
1721         .ifcd = {
1722                 .bLength = sizeof(struct usb_interface_descriptor),
1723                 .bDescriptorType = UDESC_INTERFACE,
1724                 .bNumEndpoints = 1,
1725                 .bInterfaceClass = UICLASS_HUB,
1726                 .bInterfaceSubClass = UISUBCLASS_HUB,
1727                 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
1728         },
1729         .endpd = {
1730                 .bLength = sizeof(struct usb_endpoint_descriptor),
1731                 .bDescriptorType = UDESC_ENDPOINT,
1732                 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT),
1733                 .bmAttributes = UE_INTERRUPT,
1734                 .wMaxPacketSize[0] = 8,
1735                 .bInterval = 255,
1736         },
1737 };
1738
1739 static const struct usb_hub_descriptor_min at91dci_hubd = {
1740         .bDescLength = sizeof(at91dci_hubd),
1741         .bDescriptorType = UDESC_HUB,
1742         .bNbrPorts = 1,
1743         .wHubCharacteristics[0] =
1744         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1745         .wHubCharacteristics[1] =
1746         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1747         .bPwrOn2PwrGood = 50,
1748         .bHubContrCurrent = 0,
1749         .DeviceRemovable = {0},         /* port is removable */
1750 };
1751
1752 #define STRING_LANG \
1753   0x09, 0x04,                           /* American English */
1754
1755 #define STRING_VENDOR \
1756   'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0
1757
1758 #define STRING_PRODUCT \
1759   'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1760   'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1761   'U', 0, 'B', 0,
1762
1763 USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab);
1764 USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor);
1765 USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product);
1766
1767 static usb_error_t
1768 at91dci_roothub_exec(struct usb_device *udev,
1769     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1770 {
1771         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
1772         const void *ptr;
1773         uint16_t len;
1774         uint16_t value;
1775         uint16_t index;
1776         usb_error_t err;
1777
1778         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1779
1780         /* buffer reset */
1781         ptr = (const void *)&sc->sc_hub_temp;
1782         len = 0;
1783         err = 0;
1784
1785         value = UGETW(req->wValue);
1786         index = UGETW(req->wIndex);
1787
1788         /* demultiplex the control request */
1789
1790         switch (req->bmRequestType) {
1791         case UT_READ_DEVICE:
1792                 switch (req->bRequest) {
1793                 case UR_GET_DESCRIPTOR:
1794                         goto tr_handle_get_descriptor;
1795                 case UR_GET_CONFIG:
1796                         goto tr_handle_get_config;
1797                 case UR_GET_STATUS:
1798                         goto tr_handle_get_status;
1799                 default:
1800                         goto tr_stalled;
1801                 }
1802                 break;
1803
1804         case UT_WRITE_DEVICE:
1805                 switch (req->bRequest) {
1806                 case UR_SET_ADDRESS:
1807                         goto tr_handle_set_address;
1808                 case UR_SET_CONFIG:
1809                         goto tr_handle_set_config;
1810                 case UR_CLEAR_FEATURE:
1811                         goto tr_valid;  /* nop */
1812                 case UR_SET_DESCRIPTOR:
1813                         goto tr_valid;  /* nop */
1814                 case UR_SET_FEATURE:
1815                 default:
1816                         goto tr_stalled;
1817                 }
1818                 break;
1819
1820         case UT_WRITE_ENDPOINT:
1821                 switch (req->bRequest) {
1822                 case UR_CLEAR_FEATURE:
1823                         switch (UGETW(req->wValue)) {
1824                         case UF_ENDPOINT_HALT:
1825                                 goto tr_handle_clear_halt;
1826                         case UF_DEVICE_REMOTE_WAKEUP:
1827                                 goto tr_handle_clear_wakeup;
1828                         default:
1829                                 goto tr_stalled;
1830                         }
1831                         break;
1832                 case UR_SET_FEATURE:
1833                         switch (UGETW(req->wValue)) {
1834                         case UF_ENDPOINT_HALT:
1835                                 goto tr_handle_set_halt;
1836                         case UF_DEVICE_REMOTE_WAKEUP:
1837                                 goto tr_handle_set_wakeup;
1838                         default:
1839                                 goto tr_stalled;
1840                         }
1841                         break;
1842                 case UR_SYNCH_FRAME:
1843                         goto tr_valid;  /* nop */
1844                 default:
1845                         goto tr_stalled;
1846                 }
1847                 break;
1848
1849         case UT_READ_ENDPOINT:
1850                 switch (req->bRequest) {
1851                 case UR_GET_STATUS:
1852                         goto tr_handle_get_ep_status;
1853                 default:
1854                         goto tr_stalled;
1855                 }
1856                 break;
1857
1858         case UT_WRITE_INTERFACE:
1859                 switch (req->bRequest) {
1860                 case UR_SET_INTERFACE:
1861                         goto tr_handle_set_interface;
1862                 case UR_CLEAR_FEATURE:
1863                         goto tr_valid;  /* nop */
1864                 case UR_SET_FEATURE:
1865                 default:
1866                         goto tr_stalled;
1867                 }
1868                 break;
1869
1870         case UT_READ_INTERFACE:
1871                 switch (req->bRequest) {
1872                 case UR_GET_INTERFACE:
1873                         goto tr_handle_get_interface;
1874                 case UR_GET_STATUS:
1875                         goto tr_handle_get_iface_status;
1876                 default:
1877                         goto tr_stalled;
1878                 }
1879                 break;
1880
1881         case UT_WRITE_CLASS_INTERFACE:
1882         case UT_WRITE_VENDOR_INTERFACE:
1883                 /* XXX forward */
1884                 break;
1885
1886         case UT_READ_CLASS_INTERFACE:
1887         case UT_READ_VENDOR_INTERFACE:
1888                 /* XXX forward */
1889                 break;
1890
1891         case UT_WRITE_CLASS_DEVICE:
1892                 switch (req->bRequest) {
1893                 case UR_CLEAR_FEATURE:
1894                         goto tr_valid;
1895                 case UR_SET_DESCRIPTOR:
1896                 case UR_SET_FEATURE:
1897                         break;
1898                 default:
1899                         goto tr_stalled;
1900                 }
1901                 break;
1902
1903         case UT_WRITE_CLASS_OTHER:
1904                 switch (req->bRequest) {
1905                 case UR_CLEAR_FEATURE:
1906                         goto tr_handle_clear_port_feature;
1907                 case UR_SET_FEATURE:
1908                         goto tr_handle_set_port_feature;
1909                 case UR_CLEAR_TT_BUFFER:
1910                 case UR_RESET_TT:
1911                 case UR_STOP_TT:
1912                         goto tr_valid;
1913
1914                 default:
1915                         goto tr_stalled;
1916                 }
1917                 break;
1918
1919         case UT_READ_CLASS_OTHER:
1920                 switch (req->bRequest) {
1921                 case UR_GET_TT_STATE:
1922                         goto tr_handle_get_tt_state;
1923                 case UR_GET_STATUS:
1924                         goto tr_handle_get_port_status;
1925                 default:
1926                         goto tr_stalled;
1927                 }
1928                 break;
1929
1930         case UT_READ_CLASS_DEVICE:
1931                 switch (req->bRequest) {
1932                 case UR_GET_DESCRIPTOR:
1933                         goto tr_handle_get_class_descriptor;
1934                 case UR_GET_STATUS:
1935                         goto tr_handle_get_class_status;
1936
1937                 default:
1938                         goto tr_stalled;
1939                 }
1940                 break;
1941         default:
1942                 goto tr_stalled;
1943         }
1944         goto tr_valid;
1945
1946 tr_handle_get_descriptor:
1947         switch (value >> 8) {
1948         case UDESC_DEVICE:
1949                 if (value & 0xff) {
1950                         goto tr_stalled;
1951                 }
1952                 len = sizeof(at91dci_devd);
1953                 ptr = (const void *)&at91dci_devd;
1954                 goto tr_valid;
1955         case UDESC_CONFIG:
1956                 if (value & 0xff) {
1957                         goto tr_stalled;
1958                 }
1959                 len = sizeof(at91dci_confd);
1960                 ptr = (const void *)&at91dci_confd;
1961                 goto tr_valid;
1962         case UDESC_STRING:
1963                 switch (value & 0xff) {
1964                 case 0:         /* Language table */
1965                         len = sizeof(at91dci_langtab);
1966                         ptr = (const void *)&at91dci_langtab;
1967                         goto tr_valid;
1968
1969                 case 1:         /* Vendor */
1970                         len = sizeof(at91dci_vendor);
1971                         ptr = (const void *)&at91dci_vendor;
1972                         goto tr_valid;
1973
1974                 case 2:         /* Product */
1975                         len = sizeof(at91dci_product);
1976                         ptr = (const void *)&at91dci_product;
1977                         goto tr_valid;
1978                 default:
1979                         break;
1980                 }
1981                 break;
1982         default:
1983                 goto tr_stalled;
1984         }
1985         goto tr_stalled;
1986
1987 tr_handle_get_config:
1988         len = 1;
1989         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1990         goto tr_valid;
1991
1992 tr_handle_get_status:
1993         len = 2;
1994         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1995         goto tr_valid;
1996
1997 tr_handle_set_address:
1998         if (value & 0xFF00) {
1999                 goto tr_stalled;
2000         }
2001         sc->sc_rt_addr = value;
2002         goto tr_valid;
2003
2004 tr_handle_set_config:
2005         if (value >= 2) {
2006                 goto tr_stalled;
2007         }
2008         sc->sc_conf = value;
2009         goto tr_valid;
2010
2011 tr_handle_get_interface:
2012         len = 1;
2013         sc->sc_hub_temp.wValue[0] = 0;
2014         goto tr_valid;
2015
2016 tr_handle_get_tt_state:
2017 tr_handle_get_class_status:
2018 tr_handle_get_iface_status:
2019 tr_handle_get_ep_status:
2020         len = 2;
2021         USETW(sc->sc_hub_temp.wValue, 0);
2022         goto tr_valid;
2023
2024 tr_handle_set_halt:
2025 tr_handle_set_interface:
2026 tr_handle_set_wakeup:
2027 tr_handle_clear_wakeup:
2028 tr_handle_clear_halt:
2029         goto tr_valid;
2030
2031 tr_handle_clear_port_feature:
2032         if (index != 1) {
2033                 goto tr_stalled;
2034         }
2035         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2036
2037         switch (value) {
2038         case UHF_PORT_SUSPEND:
2039                 at91dci_wakeup_peer(sc);
2040                 break;
2041
2042         case UHF_PORT_ENABLE:
2043                 sc->sc_flags.port_enabled = 0;
2044                 break;
2045
2046         case UHF_PORT_TEST:
2047         case UHF_PORT_INDICATOR:
2048         case UHF_C_PORT_ENABLE:
2049         case UHF_C_PORT_OVER_CURRENT:
2050         case UHF_C_PORT_RESET:
2051                 /* nops */
2052                 break;
2053         case UHF_PORT_POWER:
2054                 sc->sc_flags.port_powered = 0;
2055                 at91dci_pull_down(sc);
2056                 at91dci_clocks_off(sc);
2057                 break;
2058         case UHF_C_PORT_CONNECTION:
2059                 sc->sc_flags.change_connect = 0;
2060                 break;
2061         case UHF_C_PORT_SUSPEND:
2062                 sc->sc_flags.change_suspend = 0;
2063                 break;
2064         default:
2065                 err = USB_ERR_IOERROR;
2066                 goto done;
2067         }
2068         goto tr_valid;
2069
2070 tr_handle_set_port_feature:
2071         if (index != 1) {
2072                 goto tr_stalled;
2073         }
2074         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2075
2076         switch (value) {
2077         case UHF_PORT_ENABLE:
2078                 sc->sc_flags.port_enabled = 1;
2079                 break;
2080         case UHF_PORT_SUSPEND:
2081         case UHF_PORT_RESET:
2082         case UHF_PORT_TEST:
2083         case UHF_PORT_INDICATOR:
2084                 /* nops */
2085                 break;
2086         case UHF_PORT_POWER:
2087                 sc->sc_flags.port_powered = 1;
2088                 break;
2089         default:
2090                 err = USB_ERR_IOERROR;
2091                 goto done;
2092         }
2093         goto tr_valid;
2094
2095 tr_handle_get_port_status:
2096
2097         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2098
2099         if (index != 1) {
2100                 goto tr_stalled;
2101         }
2102         if (sc->sc_flags.status_vbus) {
2103                 at91dci_clocks_on(sc);
2104                 at91dci_pull_up(sc);
2105         } else {
2106                 at91dci_pull_down(sc);
2107                 at91dci_clocks_off(sc);
2108         }
2109
2110         /* Select FULL-speed and Device Side Mode */
2111
2112         value = UPS_PORT_MODE_DEVICE;
2113
2114         if (sc->sc_flags.port_powered) {
2115                 value |= UPS_PORT_POWER;
2116         }
2117         if (sc->sc_flags.port_enabled) {
2118                 value |= UPS_PORT_ENABLED;
2119         }
2120         if (sc->sc_flags.status_vbus &&
2121             sc->sc_flags.status_bus_reset) {
2122                 value |= UPS_CURRENT_CONNECT_STATUS;
2123         }
2124         if (sc->sc_flags.status_suspend) {
2125                 value |= UPS_SUSPEND;
2126         }
2127         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2128
2129         value = 0;
2130
2131         if (sc->sc_flags.change_connect) {
2132                 value |= UPS_C_CONNECT_STATUS;
2133
2134                 if (sc->sc_flags.status_vbus &&
2135                     sc->sc_flags.status_bus_reset) {
2136                         /* reset endpoint flags */
2137                         bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags));
2138                 }
2139         }
2140         if (sc->sc_flags.change_suspend) {
2141                 value |= UPS_C_SUSPEND;
2142         }
2143         USETW(sc->sc_hub_temp.ps.wPortChange, value);
2144         len = sizeof(sc->sc_hub_temp.ps);
2145         goto tr_valid;
2146
2147 tr_handle_get_class_descriptor:
2148         if (value & 0xFF) {
2149                 goto tr_stalled;
2150         }
2151         ptr = (const void *)&at91dci_hubd;
2152         len = sizeof(at91dci_hubd);
2153         goto tr_valid;
2154
2155 tr_stalled:
2156         err = USB_ERR_STALLED;
2157 tr_valid:
2158 done:
2159         *plength = len;
2160         *pptr = ptr;
2161         return (err);
2162 }
2163
2164 static void
2165 at91dci_xfer_setup(struct usb_setup_params *parm)
2166 {
2167         const struct usb_hw_ep_profile *pf;
2168         struct at91dci_softc *sc;
2169         struct usb_xfer *xfer;
2170         void *last_obj;
2171         uint32_t ntd;
2172         uint32_t n;
2173         uint8_t ep_no;
2174
2175         sc = AT9100_DCI_BUS2SC(parm->udev->bus);
2176         xfer = parm->curr_xfer;
2177
2178         /*
2179          * NOTE: This driver does not use any of the parameters that
2180          * are computed from the following values. Just set some
2181          * reasonable dummies:
2182          */
2183         parm->hc_max_packet_size = 0x500;
2184         parm->hc_max_packet_count = 1;
2185         parm->hc_max_frame_size = 0x500;
2186
2187         usbd_transfer_setup_sub(parm);
2188
2189         /*
2190          * compute maximum number of TDs
2191          */
2192         if (parm->methods == &at91dci_device_ctrl_methods) {
2193
2194                 ntd = xfer->nframes + 1 /* STATUS */ + 1        /* SYNC 1 */
2195                     + 1 /* SYNC 2 */ ;
2196
2197         } else if (parm->methods == &at91dci_device_bulk_methods) {
2198
2199                 ntd = xfer->nframes + 1 /* SYNC */ ;
2200
2201         } else if (parm->methods == &at91dci_device_intr_methods) {
2202
2203                 ntd = xfer->nframes + 1 /* SYNC */ ;
2204
2205         } else if (parm->methods == &at91dci_device_isoc_fs_methods) {
2206
2207                 ntd = xfer->nframes + 1 /* SYNC */ ;
2208
2209         } else {
2210
2211                 ntd = 0;
2212         }
2213
2214         /*
2215          * check if "usbd_transfer_setup_sub" set an error
2216          */
2217         if (parm->err) {
2218                 return;
2219         }
2220         /*
2221          * allocate transfer descriptors
2222          */
2223         last_obj = NULL;
2224
2225         /*
2226          * get profile stuff
2227          */
2228         if (ntd) {
2229
2230                 ep_no = xfer->endpointno & UE_ADDR;
2231                 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2232
2233                 if (pf == NULL) {
2234                         /* should not happen */
2235                         parm->err = USB_ERR_INVAL;
2236                         return;
2237                 }
2238         } else {
2239                 ep_no = 0;
2240                 pf = NULL;
2241         }
2242
2243         /* align data */
2244         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2245
2246         for (n = 0; n != ntd; n++) {
2247
2248                 struct at91dci_td *td;
2249
2250                 if (parm->buf) {
2251
2252                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2253
2254                         /* init TD */
2255                         td->io_tag = sc->sc_io_tag;
2256                         td->io_hdl = sc->sc_io_hdl;
2257                         td->max_packet_size = xfer->max_packet_size;
2258                         td->status_reg = AT91_UDP_CSR(ep_no);
2259                         td->fifo_reg = AT91_UDP_FDR(ep_no);
2260                         if (pf->support_multi_buffer) {
2261                                 td->support_multi_buffer = 1;
2262                         }
2263                         td->obj_next = last_obj;
2264
2265                         last_obj = td;
2266                 }
2267                 parm->size[0] += sizeof(*td);
2268         }
2269
2270         xfer->td_start[0] = last_obj;
2271 }
2272
2273 static void
2274 at91dci_xfer_unsetup(struct usb_xfer *xfer)
2275 {
2276         return;
2277 }
2278
2279 static void
2280 at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2281     struct usb_endpoint *ep)
2282 {
2283         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
2284
2285         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2286             ep, udev->address,
2287             edesc->bEndpointAddress, udev->flags.usb_mode,
2288             sc->sc_rt_addr);
2289
2290         if (udev->device_index != sc->sc_rt_addr) {
2291
2292                 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2293                         /* not supported */
2294                         return;
2295                 }
2296                 if (udev->speed != USB_SPEED_FULL) {
2297                         /* not supported */
2298                         return;
2299                 }
2300                 switch (edesc->bmAttributes & UE_XFERTYPE) {
2301                 case UE_CONTROL:
2302                         ep->methods = &at91dci_device_ctrl_methods;
2303                         break;
2304                 case UE_INTERRUPT:
2305                         ep->methods = &at91dci_device_intr_methods;
2306                         break;
2307                 case UE_ISOCHRONOUS:
2308                         ep->methods = &at91dci_device_isoc_fs_methods;
2309                         break;
2310                 case UE_BULK:
2311                         ep->methods = &at91dci_device_bulk_methods;
2312                         break;
2313                 default:
2314                         /* do nothing */
2315                         break;
2316                 }
2317         }
2318 }
2319
2320 struct usb_bus_methods at91dci_bus_methods =
2321 {
2322         .endpoint_init = &at91dci_ep_init,
2323         .xfer_setup = &at91dci_xfer_setup,
2324         .xfer_unsetup = &at91dci_xfer_unsetup,
2325         .get_hw_ep_profile = &at91dci_get_hw_ep_profile,
2326         .set_stall = &at91dci_set_stall,
2327         .clear_stall = &at91dci_clear_stall,
2328         .roothub_exec = &at91dci_roothub_exec,
2329         .xfer_poll = &at91dci_do_poll,
2330 };