sys/dev/usb/controller/atmegadci.c

   1 #include <sys/cdefs.h>
   2 __FBSDID("$FreeBSD$");
   3
   4 /*-
   5  * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the ATMEGA series USB OTG Controller. This
  31  * driver currently only supports the DCI mode of the USB hardware.
  32  */
  33
  34 /*
  35  * NOTE: When the chip detects BUS-reset it will also reset the
  36  * endpoints, Function-address and more.
  37  */
  38
  39 #include <sys/stdint.h>
  40 #include <sys/stddef.h>
  41 #include <sys/param.h>
  42 #include <sys/queue.h>
  43 #include <sys/types.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/bus.h>
  47 #include <sys/linker_set.h>
  48 #include <sys/module.h>
  49 #include <sys/lock.h>
  50 #include <sys/mutex.h>
  51 #include <sys/condvar.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/sx.h>
  54 #include <sys/unistd.h>
  55 #include <sys/callout.h>
  56 #include <sys/malloc.h>
  57 #include <sys/priv.h>
  58
  59 #include <dev/usb/usb.h>
  60 #include <dev/usb/usbdi.h>
  61
  62 #define USB_DEBUG_VAR atmegadci_debug
  63
  64 #include <dev/usb/usb_core.h>
  65 #include <dev/usb/usb_debug.h>
  66 #include <dev/usb/usb_busdma.h>
  67 #include <dev/usb/usb_process.h>
  68 #include <dev/usb/usb_transfer.h>
  69 #include <dev/usb/usb_device.h>
  70 #include <dev/usb/usb_hub.h>
  71 #include <dev/usb/usb_util.h>
  72
  73 #include <dev/usb/usb_controller.h>
  74 #include <dev/usb/usb_bus.h>
  75 #include <dev/usb/controller/atmegadci.h>
  76
  77 #define ATMEGA_BUS2SC(bus) \
  78    ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
  79     ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
  80
  81 #define ATMEGA_PC2SC(pc) \
  82    ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  83
  84 #ifdef USB_DEBUG
  85 static int atmegadci_debug = 0;
  86
  87 SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI");
  88 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW,
  89     &atmegadci_debug, 0, "ATMEGA DCI debug level");
  90 #endif
  91
  92 #define ATMEGA_INTR_ENDPT 1
  93
  94 /* prototypes */
  95
  96 struct usb_bus_methods atmegadci_bus_methods;
  97 struct usb_pipe_methods atmegadci_device_non_isoc_methods;
  98 struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
  99
 100 static atmegadci_cmd_t atmegadci_setup_rx;
 101 static atmegadci_cmd_t atmegadci_data_rx;
 102 static atmegadci_cmd_t atmegadci_data_tx;
 103 static atmegadci_cmd_t atmegadci_data_tx_sync;
 104 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
 105 static void atmegadci_do_poll(struct usb_bus *);
 106 static void atmegadci_standard_done(struct usb_xfer *);
 107 static void atmegadci_root_intr(struct atmegadci_softc *sc);
 108
 109 /*
 110  * Here is a list of what the chip supports:
 111  */
 112 static const struct usb_hw_ep_profile
 113         atmegadci_ep_profile[2] = {
 114
 115         [0] = {
 116                 .max_in_frame_size = 64,
 117                 .max_out_frame_size = 64,
 118                 .is_simplex = 1,
 119                 .support_control = 1,
 120         },
 121         [1] = {
 122                 .max_in_frame_size = 64,
 123                 .max_out_frame_size = 64,
 124                 .is_simplex = 1,
 125                 .support_bulk = 1,
 126                 .support_interrupt = 1,
 127                 .support_isochronous = 1,
 128                 .support_in = 1,
 129                 .support_out = 1,
 130         },
 131 };
 132
 133 static void
 134 atmegadci_get_hw_ep_profile(struct usb_device *udev,
 135     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 136 {
 137         if (ep_addr == 0)
 138                 *ppf = atmegadci_ep_profile;
 139         else if (ep_addr < ATMEGA_EP_MAX)
 140                 *ppf = atmegadci_ep_profile + 1;
 141         else
 142                 *ppf = NULL;
 143 }
 144
 145 static void
 146 atmegadci_clocks_on(struct atmegadci_softc *sc)
 147 {
 148         if (sc->sc_flags.clocks_off &&
 149             sc->sc_flags.port_powered) {
 150
 151                 DPRINTFN(5, "\n");
 152
 153                 /* turn on clocks */
 154                 (sc->sc_clocks_on) (&sc->sc_bus);
 155
 156                 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
 157                     ATMEGA_USBCON_USBE |
 158                     ATMEGA_USBCON_OTGPADE |
 159                     ATMEGA_USBCON_VBUSTE);
 160
 161                 sc->sc_flags.clocks_off = 0;
 162
 163                 /* enable transceiver ? */
 164         }
 165 }
 166
 167 static void
 168 atmegadci_clocks_off(struct atmegadci_softc *sc)
 169 {
 170         if (!sc->sc_flags.clocks_off) {
 171
 172                 DPRINTFN(5, "\n");
 173
 174                 /* disable Transceiver ? */
 175
 176                 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
 177                     ATMEGA_USBCON_USBE |
 178                     ATMEGA_USBCON_OTGPADE |
 179                     ATMEGA_USBCON_FRZCLK |
 180                     ATMEGA_USBCON_VBUSTE);
 181
 182                 /* turn clocks off */
 183                 (sc->sc_clocks_off) (&sc->sc_bus);
 184
 185                 sc->sc_flags.clocks_off = 1;
 186         }
 187 }
 188
 189 static void
 190 atmegadci_pull_up(struct atmegadci_softc *sc)
 191 {
 192         /* pullup D+, if possible */
 193
 194         if (!sc->sc_flags.d_pulled_up &&
 195             sc->sc_flags.port_powered) {
 196                 sc->sc_flags.d_pulled_up = 1;
 197                 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
 198         }
 199 }
 200
 201 static void
 202 atmegadci_pull_down(struct atmegadci_softc *sc)
 203 {
 204         /* pulldown D+, if possible */
 205
 206         if (sc->sc_flags.d_pulled_up) {
 207                 sc->sc_flags.d_pulled_up = 0;
 208                 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
 209         }
 210 }
 211
 212 static void
 213 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
 214 {
 215         uint8_t temp;
 216
 217         if (!sc->sc_flags.status_suspend) {
 218                 return;
 219         }
 220
 221         temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
 222         ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
 223
 224         /* wait 8 milliseconds */
 225         /* Wait for reset to complete. */
 226         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 227
 228         /* hardware should have cleared RMWKUP bit */
 229 }
 230
 231 static void
 232 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
 233 {
 234         DPRINTFN(5, "addr=%d\n", addr);
 235
 236         addr |= ATMEGA_UDADDR_ADDEN;
 237
 238         ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
 239 }
 240
 241 static uint8_t
 242 atmegadci_setup_rx(struct atmegadci_td *td)
 243 {
 244         struct atmegadci_softc *sc;
 245         struct usb_device_request req;
 246         uint16_t count;
 247         uint8_t temp;
 248
 249         /* get pointer to softc */
 250         sc = ATMEGA_PC2SC(td->pc);
 251
 252         /* select endpoint number */
 253         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 254
 255         /* check endpoint status */
 256         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 257
 258         DPRINTFN(5, "UEINTX=0x%02x\n", temp);
 259
 260         if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
 261                 goto not_complete;
 262         }
 263         /* clear did stall */
 264         td->did_stall = 0;
 265         /* get the packet byte count */
 266         count =
 267             (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
 268             (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
 269
 270         /* mask away undefined bits */
 271         count &= 0x7FF;
 272
 273         /* verify data length */
 274         if (count != td->remainder) {
 275                 DPRINTFN(0, "Invalid SETUP packet "
 276                     "length, %d bytes\n", count);
 277                 goto not_complete;
 278         }
 279         if (count != sizeof(req)) {
 280                 DPRINTFN(0, "Unsupported SETUP packet "
 281                     "length, %d bytes\n", count);
 282                 goto not_complete;
 283         }
 284         /* receive data */
 285         ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
 286             (void *)&req, sizeof(req));
 287
 288         /* copy data into real buffer */
 289         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 290
 291         td->offset = sizeof(req);
 292         td->remainder = 0;
 293
 294         /* sneak peek the set address */
 295         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 296             (req.bRequest == UR_SET_ADDRESS)) {
 297                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 298                 /* must write address before ZLP */
 299                 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
 300         } else {
 301                 sc->sc_dv_addr = 0xFF;
 302         }
 303
 304         /* clear SETUP packet interrupt */
 305         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
 306         return (0);                     /* complete */
 307
 308 not_complete:
 309         /* abort any ongoing transfer */
 310         if (!td->did_stall) {
 311                 DPRINTFN(5, "stalling\n");
 312                 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
 313                     ATMEGA_UECONX_EPEN |
 314                     ATMEGA_UECONX_STALLRQ);
 315                 td->did_stall = 1;
 316         }
 317         if (temp & ATMEGA_UEINTX_RXSTPI) {
 318                 /* clear SETUP packet interrupt */
 319                 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
 320         }
 321         /* we only want to know if there is a SETUP packet */
 322         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
 323         return (1);                     /* not complete */
 324 }
 325
 326 static uint8_t
 327 atmegadci_data_rx(struct atmegadci_td *td)
 328 {
 329         struct atmegadci_softc *sc;
 330         struct usb_page_search buf_res;
 331         uint16_t count;
 332         uint8_t temp;
 333         uint8_t to;
 334         uint8_t got_short;
 335
 336         to = 3;                         /* don't loop forever! */
 337         got_short = 0;
 338
 339         /* get pointer to softc */
 340         sc = ATMEGA_PC2SC(td->pc);
 341
 342         /* select endpoint number */
 343         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 344
 345 repeat:
 346         /* check if any of the FIFO banks have data */
 347         /* check endpoint status */
 348         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 349
 350         DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
 351
 352         if (temp & ATMEGA_UEINTX_RXSTPI) {
 353                 if (td->remainder == 0) {
 354                         /*
 355                          * We are actually complete and have
 356                          * received the next SETUP
 357                          */
 358                         DPRINTFN(5, "faking complete\n");
 359                         return (0);     /* complete */
 360                 }
 361                 /*
 362                  * USB Host Aborted the transfer.
 363                  */
 364                 td->error = 1;
 365                 return (0);             /* complete */
 366         }
 367         /* check status */
 368         if (!(temp & (ATMEGA_UEINTX_FIFOCON |
 369             ATMEGA_UEINTX_RXOUTI))) {
 370                 /* no data */
 371                 goto not_complete;
 372         }
 373         /* get the packet byte count */
 374         count =
 375             (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
 376             (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
 377
 378         /* mask away undefined bits */
 379         count &= 0x7FF;
 380
 381         /* verify the packet byte count */
 382         if (count != td->max_packet_size) {
 383                 if (count < td->max_packet_size) {
 384                         /* we have a short packet */
 385                         td->short_pkt = 1;
 386                         got_short = 1;
 387                 } else {
 388                         /* invalid USB packet */
 389                         td->error = 1;
 390                         return (0);     /* we are complete */
 391                 }
 392         }
 393         /* verify the packet byte count */
 394         if (count > td->remainder) {
 395                 /* invalid USB packet */
 396                 td->error = 1;
 397                 return (0);             /* we are complete */
 398         }
 399         while (count > 0) {
 400                 usbd_get_page(td->pc, td->offset, &buf_res);
 401
 402                 /* get correct length */
 403                 if (buf_res.length > count) {
 404                         buf_res.length = count;
 405                 }
 406                 /* receive data */
 407                 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
 408                     buf_res.buffer, buf_res.length);
 409
 410                 /* update counters */
 411                 count -= buf_res.length;
 412                 td->offset += buf_res.length;
 413                 td->remainder -= buf_res.length;
 414         }
 415
 416         /* clear OUT packet interrupt */
 417         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
 418
 419         /* release FIFO bank */
 420         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
 421
 422         /* check if we are complete */
 423         if ((td->remainder == 0) || got_short) {
 424                 if (td->short_pkt) {
 425                         /* we are complete */
 426                         return (0);
 427                 }
 428                 /* else need to receive a zero length packet */
 429         }
 430         if (--to) {
 431                 goto repeat;
 432         }
 433 not_complete:
 434         /* we only want to know if there is a SETUP packet or OUT packet */
 435         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
 436             ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
 437         return (1);                     /* not complete */
 438 }
 439
 440 static uint8_t
 441 atmegadci_data_tx(struct atmegadci_td *td)
 442 {
 443         struct atmegadci_softc *sc;
 444         struct usb_page_search buf_res;
 445         uint16_t count;
 446         uint8_t to;
 447         uint8_t temp;
 448
 449         to = 3;                         /* don't loop forever! */
 450
 451         /* get pointer to softc */
 452         sc = ATMEGA_PC2SC(td->pc);
 453
 454         /* select endpoint number */
 455         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 456
 457 repeat:
 458
 459         /* check endpoint status */
 460         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 461
 462         DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
 463
 464         if (temp & ATMEGA_UEINTX_RXSTPI) {
 465                 /*
 466                  * The current transfer was aborted
 467                  * by the USB Host
 468                  */
 469                 td->error = 1;
 470                 return (0);             /* complete */
 471         }
 472
 473         temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
 474         if (temp & 3) {
 475                 /* cannot write any data - a bank is busy */
 476                 goto not_complete;
 477         }
 478
 479         count = td->max_packet_size;
 480         if (td->remainder < count) {
 481                 /* we have a short packet */
 482                 td->short_pkt = 1;
 483                 count = td->remainder;
 484         }
 485         while (count > 0) {
 486
 487                 usbd_get_page(td->pc, td->offset, &buf_res);
 488
 489                 /* get correct length */
 490                 if (buf_res.length > count) {
 491                         buf_res.length = count;
 492                 }
 493                 /* transmit data */
 494                 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
 495                     buf_res.buffer, buf_res.length);
 496
 497                 /* update counters */
 498                 count -= buf_res.length;
 499                 td->offset += buf_res.length;
 500                 td->remainder -= buf_res.length;
 501         }
 502
 503         /* clear IN packet interrupt */
 504         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
 505
 506         /* allocate FIFO bank */
 507         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
 508
 509         /* check remainder */
 510         if (td->remainder == 0) {
 511                 if (td->short_pkt) {
 512                         return (0);     /* complete */
 513                 }
 514                 /* else we need to transmit a short packet */
 515         }
 516         if (--to) {
 517                 goto repeat;
 518         }
 519 not_complete:
 520         /* we only want to know if there is a SETUP packet or free IN packet */
 521         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
 522             ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
 523         return (1);                     /* not complete */
 524 }
 525
 526 static uint8_t
 527 atmegadci_data_tx_sync(struct atmegadci_td *td)
 528 {
 529         struct atmegadci_softc *sc;
 530         uint8_t temp;
 531
 532         /* get pointer to softc */
 533         sc = ATMEGA_PC2SC(td->pc);
 534
 535         /* select endpoint number */
 536         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 537
 538         /* check endpoint status */
 539         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 540
 541         DPRINTFN(5, "temp=0x%02x\n", temp);
 542
 543         if (temp & ATMEGA_UEINTX_RXSTPI) {
 544                 DPRINTFN(5, "faking complete\n");
 545                 /* Race condition */
 546                 return (0);             /* complete */
 547         }
 548         /*
 549          * The control endpoint has only got one bank, so if that bank
 550          * is free the packet has been transferred!
 551          */
 552         temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
 553         if (temp & 3) {
 554                 /* cannot write any data - a bank is busy */
 555                 goto not_complete;
 556         }
 557         if (sc->sc_dv_addr != 0xFF) {
 558                 /* set new address */
 559                 atmegadci_set_address(sc, sc->sc_dv_addr);
 560         }
 561         return (0);                     /* complete */
 562
 563 not_complete:
 564         /* we only want to know if there is a SETUP packet or free IN packet */
 565         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
 566             ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
 567         return (1);                     /* not complete */
 568 }
 569
 570 static uint8_t
 571 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
 572 {
 573         struct atmegadci_td *td;
 574
 575         DPRINTFN(9, "\n");
 576
 577         td = xfer->td_transfer_cache;
 578         while (1) {
 579                 if ((td->func) (td)) {
 580                         /* operation in progress */
 581                         break;
 582                 }
 583                 if (((void *)td) == xfer->td_transfer_last) {
 584                         goto done;
 585                 }
 586                 if (td->error) {
 587                         goto done;
 588                 } else if (td->remainder > 0) {
 589                         /*
 590                          * We had a short transfer. If there is no alternate
 591                          * next, stop processing !
 592                          */
 593                         if (!td->alt_next) {
 594                                 goto done;
 595                         }
 596                 }
 597                 /*
 598                  * Fetch the next transfer descriptor and transfer
 599                  * some flags to the next transfer descriptor
 600                  */
 601                 td = td->obj_next;
 602                 xfer->td_transfer_cache = td;
 603         }
 604         return (1);                     /* not complete */
 605
 606 done:
 607         /* compute all actual lengths */
 608
 609         atmegadci_standard_done(xfer);
 610         return (0);                     /* complete */
 611 }
 612
 613 static void
 614 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
 615 {
 616         struct usb_xfer *xfer;
 617
 618 repeat:
 619         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 620                 if (!atmegadci_xfer_do_fifo(xfer)) {
 621                         /* queue has been modified */
 622                         goto repeat;
 623                 }
 624         }
 625 }
 626
 627 static void
 628 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
 629 {
 630         DPRINTFN(5, "vbus = %u\n", is_on);
 631
 632         if (is_on) {
 633                 if (!sc->sc_flags.status_vbus) {
 634                         sc->sc_flags.status_vbus = 1;
 635
 636                         /* complete root HUB interrupt endpoint */
 637
 638                         atmegadci_root_intr(sc);
 639                 }
 640         } else {
 641                 if (sc->sc_flags.status_vbus) {
 642                         sc->sc_flags.status_vbus = 0;
 643                         sc->sc_flags.status_bus_reset = 0;
 644                         sc->sc_flags.status_suspend = 0;
 645                         sc->sc_flags.change_suspend = 0;
 646                         sc->sc_flags.change_connect = 1;
 647
 648                         /* complete root HUB interrupt endpoint */
 649
 650                         atmegadci_root_intr(sc);
 651                 }
 652         }
 653 }
 654
 655 void
 656 atmegadci_interrupt(struct atmegadci_softc *sc)
 657 {
 658         uint8_t status;
 659
 660         USB_BUS_LOCK(&sc->sc_bus);
 661
 662         /* read interrupt status */
 663         status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
 664
 665         /* clear all set interrupts */
 666         ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
 667
 668         DPRINTFN(14, "UDINT=0x%02x\n", status);
 669
 670         /* check for any bus state change interrupts */
 671         if (status & ATMEGA_UDINT_EORSTI) {
 672
 673                 DPRINTFN(5, "end of reset\n");
 674
 675                 /* set correct state */
 676                 sc->sc_flags.status_bus_reset = 1;
 677                 sc->sc_flags.status_suspend = 0;
 678                 sc->sc_flags.change_suspend = 0;
 679                 sc->sc_flags.change_connect = 1;
 680
 681                 /* disable resume interrupt */
 682                 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
 683                     ATMEGA_UDINT_SUSPE |
 684                     ATMEGA_UDINT_EORSTE);
 685
 686                 /* complete root HUB interrupt endpoint */
 687                 atmegadci_root_intr(sc);
 688         }
 689         /*
 690          * If resume and suspend is set at the same time we interpret
 691          * that like RESUME. Resume is set when there is at least 3
 692          * milliseconds of inactivity on the USB BUS.
 693          */
 694         if (status & ATMEGA_UDINT_WAKEUPI) {
 695
 696                 DPRINTFN(5, "resume interrupt\n");
 697
 698                 if (sc->sc_flags.status_suspend) {
 699                         /* update status bits */
 700                         sc->sc_flags.status_suspend = 0;
 701                         sc->sc_flags.change_suspend = 1;
 702
 703                         /* disable resume interrupt */
 704                         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
 705                             ATMEGA_UDINT_SUSPE |
 706                             ATMEGA_UDINT_EORSTE);
 707
 708                         /* complete root HUB interrupt endpoint */
 709                         atmegadci_root_intr(sc);
 710                 }
 711         } else if (status & ATMEGA_UDINT_SUSPI) {
 712
 713                 DPRINTFN(5, "suspend interrupt\n");
 714
 715                 if (!sc->sc_flags.status_suspend) {
 716                         /* update status bits */
 717                         sc->sc_flags.status_suspend = 1;
 718                         sc->sc_flags.change_suspend = 1;
 719
 720                         /* disable suspend interrupt */
 721                         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
 722                             ATMEGA_UDINT_WAKEUPE |
 723                             ATMEGA_UDINT_EORSTE);
 724
 725                         /* complete root HUB interrupt endpoint */
 726                         atmegadci_root_intr(sc);
 727                 }
 728         }
 729         /* check VBUS */
 730         status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
 731
 732         /* clear all set interrupts */
 733         ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
 734
 735         if (status & ATMEGA_USBINT_VBUSTI) {
 736                 uint8_t temp;
 737
 738                 DPRINTFN(5, "USBINT=0x%02x\n", status);
 739
 740                 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
 741                 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
 742         }
 743         /* check for any endpoint interrupts */
 744         status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
 745         /* the hardware will clear the UEINT bits automatically */
 746         if (status) {
 747
 748                 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
 749
 750                 atmegadci_interrupt_poll(sc);
 751         }
 752         USB_BUS_UNLOCK(&sc->sc_bus);
 753 }
 754
 755 static void
 756 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
 757 {
 758         struct atmegadci_td *td;
 759
 760         /* get current Transfer Descriptor */
 761         td = temp->td_next;
 762         temp->td = td;
 763
 764         /* prepare for next TD */
 765         temp->td_next = td->obj_next;
 766
 767         /* fill out the Transfer Descriptor */
 768         td->func = temp->func;
 769         td->pc = temp->pc;
 770         td->offset = temp->offset;
 771         td->remainder = temp->len;
 772         td->error = 0;
 773         td->did_stall = temp->did_stall;
 774         td->short_pkt = temp->short_pkt;
 775         td->alt_next = temp->setup_alt_next;
 776 }
 777
 778 static void
 779 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
 780 {
 781         struct atmegadci_std_temp temp;
 782         struct atmegadci_softc *sc;
 783         struct atmegadci_td *td;
 784         uint32_t x;
 785         uint8_t ep_no;
 786         uint8_t need_sync;
 787
 788         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 789             xfer->address, UE_GET_ADDR(xfer->endpointno),
 790             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 791
 792         temp.max_frame_size = xfer->max_frame_size;
 793
 794         td = xfer->td_start[0];
 795         xfer->td_transfer_first = td;
 796         xfer->td_transfer_cache = td;
 797
 798         /* setup temp */
 799
 800         temp.td = NULL;
 801         temp.td_next = xfer->td_start[0];
 802         temp.offset = 0;
 803         temp.setup_alt_next = xfer->flags_int.short_frames_ok;
 804         temp.did_stall = !xfer->flags_int.control_stall;
 805
 806         sc = ATMEGA_BUS2SC(xfer->xroot->bus);
 807         ep_no = (xfer->endpointno & UE_ADDR);
 808
 809         /* check if we should prepend a setup message */
 810
 811         if (xfer->flags_int.control_xfr) {
 812                 if (xfer->flags_int.control_hdr) {
 813
 814                         temp.func = &atmegadci_setup_rx;
 815                         temp.len = xfer->frlengths[0];
 816                         temp.pc = xfer->frbuffers + 0;
 817                         temp.short_pkt = temp.len ? 1 : 0;
 818                         /* check for last frame */
 819                         if (xfer->nframes == 1) {
 820                                 /* no STATUS stage yet, SETUP is last */
 821                                 if (xfer->flags_int.control_act)
 822                                         temp.setup_alt_next = 0;
 823                         }
 824
 825                         atmegadci_setup_standard_chain_sub(&temp);
 826                 }
 827                 x = 1;
 828         } else {
 829                 x = 0;
 830         }
 831
 832         if (x != xfer->nframes) {
 833                 if (xfer->endpointno & UE_DIR_IN) {
 834                         temp.func = &atmegadci_data_tx;
 835                         need_sync = 1;
 836                 } else {
 837                         temp.func = &atmegadci_data_rx;
 838                         need_sync = 0;
 839                 }
 840
 841                 /* setup "pc" pointer */
 842                 temp.pc = xfer->frbuffers + x;
 843         } else {
 844                 need_sync = 0;
 845         }
 846         while (x != xfer->nframes) {
 847
 848                 /* DATA0 / DATA1 message */
 849
 850                 temp.len = xfer->frlengths[x];
 851
 852                 x++;
 853
 854                 if (x == xfer->nframes) {
 855                         if (xfer->flags_int.control_xfr) {
 856                                 if (xfer->flags_int.control_act) {
 857                                         temp.setup_alt_next = 0;
 858                                 }
 859                         } else {
 860                                 temp.setup_alt_next = 0;
 861                         }
 862                 }
 863                 if (temp.len == 0) {
 864
 865                         /* make sure that we send an USB packet */
 866
 867                         temp.short_pkt = 0;
 868
 869                 } else {
 870
 871                         /* regular data transfer */
 872
 873                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
 874                 }
 875
 876                 atmegadci_setup_standard_chain_sub(&temp);
 877
 878                 if (xfer->flags_int.isochronous_xfr) {
 879                         temp.offset += temp.len;
 880                 } else {
 881                         /* get next Page Cache pointer */
 882                         temp.pc = xfer->frbuffers + x;
 883                 }
 884         }
 885
 886         if (xfer->flags_int.control_xfr) {
 887
 888                 /* always setup a valid "pc" pointer for status and sync */
 889                 temp.pc = xfer->frbuffers + 0;
 890                 temp.len = 0;
 891                 temp.short_pkt = 0;
 892                 temp.setup_alt_next = 0;
 893
 894                 /* check if we need to sync */
 895                 if (need_sync) {
 896                         /* we need a SYNC point after TX */
 897                         temp.func = &atmegadci_data_tx_sync;
 898                         atmegadci_setup_standard_chain_sub(&temp);
 899                 }
 900
 901                 /* check if we should append a status stage */
 902                 if (!xfer->flags_int.control_act) {
 903
 904                         /*
 905                          * Send a DATA1 message and invert the current
 906                          * endpoint direction.
 907                          */
 908                         if (xfer->endpointno & UE_DIR_IN) {
 909                                 temp.func = &atmegadci_data_rx;
 910                                 need_sync = 0;
 911                         } else {
 912                                 temp.func = &atmegadci_data_tx;
 913                                 need_sync = 1;
 914                         }
 915
 916                         atmegadci_setup_standard_chain_sub(&temp);
 917                         if (need_sync) {
 918                                 /* we need a SYNC point after TX */
 919                                 temp.func = &atmegadci_data_tx_sync;
 920                                 atmegadci_setup_standard_chain_sub(&temp);
 921                         }
 922                 }
 923         }
 924         /* must have at least one frame! */
 925         td = temp.td;
 926         xfer->td_transfer_last = td;
 927 }
 928
 929 static void
 930 atmegadci_timeout(void *arg)
 931 {
 932         struct usb_xfer *xfer = arg;
 933
 934         DPRINTF("xfer=%p\n", xfer);
 935
 936         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
 937
 938         /* transfer is transferred */
 939         atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
 940 }
 941
 942 static void
 943 atmegadci_start_standard_chain(struct usb_xfer *xfer)
 944 {
 945         DPRINTFN(9, "\n");
 946
 947         /* poll one time - will turn on interrupts */
 948         if (atmegadci_xfer_do_fifo(xfer)) {
 949
 950                 /* put transfer on interrupt queue */
 951                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
 952
 953                 /* start timeout, if any */
 954                 if (xfer->timeout != 0) {
 955                         usbd_transfer_timeout_ms(xfer,
 956                             &atmegadci_timeout, xfer->timeout);
 957                 }
 958         }
 959 }
 960
 961 static void
 962 atmegadci_root_intr(struct atmegadci_softc *sc)
 963 {
 964         DPRINTFN(9, "\n");
 965
 966         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
 967
 968         /* set port bit */
 969         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
 970
 971         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
 972             sizeof(sc->sc_hub_idata));
 973  }
 974
 975 static usb_error_t
 976 atmegadci_standard_done_sub(struct usb_xfer *xfer)
 977 {
 978         struct atmegadci_td *td;
 979         uint32_t len;
 980         uint8_t error;
 981
 982         DPRINTFN(9, "\n");
 983
 984         td = xfer->td_transfer_cache;
 985
 986         do {
 987                 len = td->remainder;
 988
 989                 if (xfer->aframes != xfer->nframes) {
 990                         /*
 991                          * Verify the length and subtract
 992                          * the remainder from "frlengths[]":
 993                          */
 994                         if (len > xfer->frlengths[xfer->aframes]) {
 995                                 td->error = 1;
 996                         } else {
 997                                 xfer->frlengths[xfer->aframes] -= len;
 998                         }
 999                 }
1000                 /* Check for transfer error */
1001                 if (td->error) {
1002                         /* the transfer is finished */
1003                         error = 1;
1004                         td = NULL;
1005                         break;
1006                 }
1007                 /* Check for short transfer */
1008                 if (len > 0) {
1009                         if (xfer->flags_int.short_frames_ok) {
1010                                 /* follow alt next */
1011                                 if (td->alt_next) {
1012                                         td = td->obj_next;
1013                                 } else {
1014                                         td = NULL;
1015                                 }
1016                         } else {
1017                                 /* the transfer is finished */
1018                                 td = NULL;
1019                         }
1020                         error = 0;
1021                         break;
1022                 }
1023                 td = td->obj_next;
1024
1025                 /* this USB frame is complete */
1026                 error = 0;
1027                 break;
1028
1029         } while (0);
1030
1031         /* update transfer cache */
1032
1033         xfer->td_transfer_cache = td;
1034
1035         return (error ?
1036             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1037 }
1038
1039 static void
1040 atmegadci_standard_done(struct usb_xfer *xfer)
1041 {
1042         usb_error_t err = 0;
1043
1044         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1045             xfer, xfer->endpoint);
1046
1047         /* reset scanner */
1048
1049         xfer->td_transfer_cache = xfer->td_transfer_first;
1050
1051         if (xfer->flags_int.control_xfr) {
1052
1053                 if (xfer->flags_int.control_hdr) {
1054
1055                         err = atmegadci_standard_done_sub(xfer);
1056                 }
1057                 xfer->aframes = 1;
1058
1059                 if (xfer->td_transfer_cache == NULL) {
1060                         goto done;
1061                 }
1062         }
1063         while (xfer->aframes != xfer->nframes) {
1064
1065                 err = atmegadci_standard_done_sub(xfer);
1066                 xfer->aframes++;
1067
1068                 if (xfer->td_transfer_cache == NULL) {
1069                         goto done;
1070                 }
1071         }
1072
1073         if (xfer->flags_int.control_xfr &&
1074             !xfer->flags_int.control_act) {
1075
1076                 err = atmegadci_standard_done_sub(xfer);
1077         }
1078 done:
1079         atmegadci_device_done(xfer, err);
1080 }
1081
1082 /*------------------------------------------------------------------------*
1083  *      atmegadci_device_done
1084  *
1085  * NOTE: this function can be called more than one time on the
1086  * same USB transfer!
1087  *------------------------------------------------------------------------*/
1088 static void
1089 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1090 {
1091         struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1092         uint8_t ep_no;
1093
1094         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1095
1096         DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1097             xfer, xfer->endpoint, error);
1098
1099         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1100                 ep_no = (xfer->endpointno & UE_ADDR);
1101
1102                 /* select endpoint number */
1103                 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1104
1105                 /* disable endpoint interrupt */
1106                 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1107
1108                 DPRINTFN(15, "disabled interrupts!\n");
1109         }
1110         /* dequeue transfer and start next transfer */
1111         usbd_transfer_done(xfer, error);
1112 }
1113
1114 static void
1115 atmegadci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1116     struct usb_endpoint *ep, uint8_t *did_stall)
1117 {
1118         struct atmegadci_softc *sc;
1119         uint8_t ep_no;
1120
1121         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1122
1123         DPRINTFN(5, "endpoint=%p\n", ep);
1124
1125         if (xfer) {
1126                 /* cancel any ongoing transfers */
1127                 atmegadci_device_done(xfer, USB_ERR_STALLED);
1128         }
1129         sc = ATMEGA_BUS2SC(udev->bus);
1130         /* get endpoint number */
1131         ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1132         /* select endpoint number */
1133         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1134         /* set stall */
1135         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1136             ATMEGA_UECONX_EPEN |
1137             ATMEGA_UECONX_STALLRQ);
1138 }
1139
1140 static void
1141 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1142     uint8_t ep_type, uint8_t ep_dir)
1143 {
1144         uint8_t temp;
1145
1146         if (ep_type == UE_CONTROL) {
1147                 /* clearing stall is not needed */
1148                 return;
1149         }
1150         /* select endpoint number */
1151         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1152
1153         /* set endpoint reset */
1154         ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1155
1156         /* clear endpoint reset */
1157         ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1158
1159         /* set stall */
1160         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1161             ATMEGA_UECONX_EPEN |
1162             ATMEGA_UECONX_STALLRQ);
1163
1164         /* reset data toggle */
1165         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1166             ATMEGA_UECONX_EPEN |
1167             ATMEGA_UECONX_RSTDT);
1168
1169         /* clear stall */
1170         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1171             ATMEGA_UECONX_EPEN |
1172             ATMEGA_UECONX_STALLRQC);
1173
1174         do {
1175                 if (ep_type == UE_BULK) {
1176                         temp = ATMEGA_UECFG0X_EPTYPE2;
1177                 } else if (ep_type == UE_INTERRUPT) {
1178                         temp = ATMEGA_UECFG0X_EPTYPE3;
1179                 } else {
1180                         temp = ATMEGA_UECFG0X_EPTYPE1;
1181                 }
1182                 if (ep_dir & UE_DIR_IN) {
1183                         temp |= ATMEGA_UECFG0X_EPDIR;
1184                 }
1185                 /* two banks, 64-bytes wMaxPacket */
1186                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1187                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1188                     ATMEGA_UECFG1X_ALLOC |
1189                     ATMEGA_UECFG1X_EPBK0 |      /* one bank */
1190                     ATMEGA_UECFG1X_EPSIZE(3));
1191
1192                 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1193                 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1194                         DPRINTFN(0, "Chip rejected configuration\n");
1195                 }
1196         } while (0);
1197 }
1198
1199 static void
1200 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1201 {
1202         struct atmegadci_softc *sc;
1203         struct usb_endpoint_descriptor *ed;
1204
1205         DPRINTFN(5, "endpoint=%p\n", ep);
1206
1207         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1208
1209         /* check mode */
1210         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1211                 /* not supported */
1212                 return;
1213         }
1214         /* get softc */
1215         sc = ATMEGA_BUS2SC(udev->bus);
1216
1217         /* get endpoint descriptor */
1218         ed = ep->edesc;
1219
1220         /* reset endpoint */
1221         atmegadci_clear_stall_sub(sc,
1222             (ed->bEndpointAddress & UE_ADDR),
1223             (ed->bmAttributes & UE_XFERTYPE),
1224             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1225 }
1226
1227 usb_error_t
1228 atmegadci_init(struct atmegadci_softc *sc)
1229 {
1230         uint8_t n;
1231
1232         DPRINTF("start\n");
1233
1234         /* set up the bus structure */
1235         sc->sc_bus.usbrev = USB_REV_1_1;
1236         sc->sc_bus.methods = &atmegadci_bus_methods;
1237
1238         USB_BUS_LOCK(&sc->sc_bus);
1239
1240         /* make sure USB is enabled */
1241         ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1242             ATMEGA_USBCON_USBE |
1243             ATMEGA_USBCON_FRZCLK);
1244
1245         /* enable USB PAD regulator */
1246         ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1247             ATMEGA_UHWCON_UVREGE |
1248             ATMEGA_UHWCON_UIMOD);
1249
1250         /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1251         ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1252
1253         /* wait for PLL to lock */
1254         for (n = 0; n != 20; n++) {
1255                 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1256                         break;
1257                 /* wait a little bit for PLL to start */
1258                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1259         }
1260
1261         /* make sure USB is enabled */
1262         ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1263             ATMEGA_USBCON_USBE |
1264             ATMEGA_USBCON_OTGPADE |
1265             ATMEGA_USBCON_VBUSTE);
1266
1267         /* turn on clocks */
1268         (sc->sc_clocks_on) (&sc->sc_bus);
1269
1270         /* make sure device is re-enumerated */
1271         ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1272
1273         /* wait a little for things to stabilise */
1274         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1275
1276         /* enable interrupts */
1277         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1278             ATMEGA_UDINT_SUSPE |
1279             ATMEGA_UDINT_EORSTE);
1280
1281         /* reset all endpoints */
1282         ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1283             (1 << ATMEGA_EP_MAX) - 1);
1284
1285         /* disable reset */
1286         ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1287
1288         /* disable all endpoints */
1289         for (n = 0; n != ATMEGA_EP_MAX; n++) {
1290
1291                 /* select endpoint */
1292                 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1293
1294                 /* disable endpoint interrupt */
1295                 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1296
1297                 /* disable endpoint */
1298                 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1299         }
1300
1301         /* turn off clocks */
1302
1303         atmegadci_clocks_off(sc);
1304
1305         /* read initial VBUS state */
1306
1307         n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1308         atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1309
1310         USB_BUS_UNLOCK(&sc->sc_bus);
1311
1312         /* catch any lost interrupts */
1313
1314         atmegadci_do_poll(&sc->sc_bus);
1315
1316         return (0);                     /* success */
1317 }
1318
1319 void
1320 atmegadci_uninit(struct atmegadci_softc *sc)
1321 {
1322         USB_BUS_LOCK(&sc->sc_bus);
1323
1324         /* turn on clocks */
1325         (sc->sc_clocks_on) (&sc->sc_bus);
1326
1327         /* disable interrupts */
1328         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1329
1330         /* reset all endpoints */
1331         ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1332             (1 << ATMEGA_EP_MAX) - 1);
1333
1334         /* disable reset */
1335         ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1336
1337         sc->sc_flags.port_powered = 0;
1338         sc->sc_flags.status_vbus = 0;
1339         sc->sc_flags.status_bus_reset = 0;
1340         sc->sc_flags.status_suspend = 0;
1341         sc->sc_flags.change_suspend = 0;
1342         sc->sc_flags.change_connect = 1;
1343
1344         atmegadci_pull_down(sc);
1345         atmegadci_clocks_off(sc);
1346
1347         /* disable USB PAD regulator */
1348         ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1349
1350         USB_BUS_UNLOCK(&sc->sc_bus);
1351 }
1352
1353 void
1354 atmegadci_suspend(struct atmegadci_softc *sc)
1355 {
1356         return;
1357 }
1358
1359 void
1360 atmegadci_resume(struct atmegadci_softc *sc)
1361 {
1362         return;
1363 }
1364
1365 static void
1366 atmegadci_do_poll(struct usb_bus *bus)
1367 {
1368         struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1369
1370         USB_BUS_LOCK(&sc->sc_bus);
1371         atmegadci_interrupt_poll(sc);
1372         USB_BUS_UNLOCK(&sc->sc_bus);
1373 }
1374
1375 /*------------------------------------------------------------------------*
1376  * at91dci bulk support
1377  * at91dci control support
1378  * at91dci interrupt support
1379  *------------------------------------------------------------------------*/
1380 static void
1381 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1382 {
1383         return;
1384 }
1385
1386 static void
1387 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1388 {
1389         atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1390 }
1391
1392 static void
1393 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1394 {
1395         return;
1396 }
1397
1398 static void
1399 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1400 {
1401         /* setup TDs */
1402         atmegadci_setup_standard_chain(xfer);
1403         atmegadci_start_standard_chain(xfer);
1404 }
1405
1406 struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1407 {
1408         .open = atmegadci_device_non_isoc_open,
1409         .close = atmegadci_device_non_isoc_close,
1410         .enter = atmegadci_device_non_isoc_enter,
1411         .start = atmegadci_device_non_isoc_start,
1412 };
1413
1414 /*------------------------------------------------------------------------*
1415  * at91dci full speed isochronous support
1416  *------------------------------------------------------------------------*/
1417 static void
1418 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1419 {
1420         return;
1421 }
1422
1423 static void
1424 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1425 {
1426         atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1427 }
1428
1429 static void
1430 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1431 {
1432         struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1433         uint32_t temp;
1434         uint32_t nframes;
1435
1436         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1437             xfer, xfer->endpoint->isoc_next, xfer->nframes);
1438
1439         /* get the current frame index */
1440
1441         nframes =
1442             (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1443             (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1444
1445         nframes &= ATMEGA_FRAME_MASK;
1446
1447         /*
1448          * check if the frame index is within the window where the frames
1449          * will be inserted
1450          */
1451         temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1452
1453         if ((xfer->endpoint->is_synced == 0) ||
1454             (temp < xfer->nframes)) {
1455                 /*
1456                  * If there is data underflow or the pipe queue is
1457                  * empty we schedule the transfer a few frames ahead
1458                  * of the current frame position. Else two isochronous
1459                  * transfers might overlap.
1460                  */
1461                 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1462                 xfer->endpoint->is_synced = 1;
1463                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1464         }
1465         /*
1466          * compute how many milliseconds the insertion is ahead of the
1467          * current frame position:
1468          */
1469         temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1470
1471         /*
1472          * pre-compute when the isochronous transfer will be finished:
1473          */
1474         xfer->isoc_time_complete =
1475             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1476             xfer->nframes;
1477
1478         /* compute frame number for next insertion */
1479         xfer->endpoint->isoc_next += xfer->nframes;
1480
1481         /* setup TDs */
1482         atmegadci_setup_standard_chain(xfer);
1483 }
1484
1485 static void
1486 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1487 {
1488         /* start TD chain */
1489         atmegadci_start_standard_chain(xfer);
1490 }
1491
1492 struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1493 {
1494         .open = atmegadci_device_isoc_fs_open,
1495         .close = atmegadci_device_isoc_fs_close,
1496         .enter = atmegadci_device_isoc_fs_enter,
1497         .start = atmegadci_device_isoc_fs_start,
1498 };
1499
1500 /*------------------------------------------------------------------------*
1501  * at91dci root control support
1502  *------------------------------------------------------------------------*
1503  * Simulate a hardware HUB by handling all the necessary requests.
1504  *------------------------------------------------------------------------*/
1505
1506 static const struct usb_device_descriptor atmegadci_devd = {
1507         .bLength = sizeof(struct usb_device_descriptor),
1508         .bDescriptorType = UDESC_DEVICE,
1509         .bcdUSB = {0x00, 0x02},
1510         .bDeviceClass = UDCLASS_HUB,
1511         .bDeviceSubClass = UDSUBCLASS_HUB,
1512         .bDeviceProtocol = UDPROTO_HSHUBSTT,
1513         .bMaxPacketSize = 64,
1514         .bcdDevice = {0x00, 0x01},
1515         .iManufacturer = 1,
1516         .iProduct = 2,
1517         .bNumConfigurations = 1,
1518 };
1519
1520 static const struct usb_device_qualifier atmegadci_odevd = {
1521         .bLength = sizeof(struct usb_device_qualifier),
1522         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1523         .bcdUSB = {0x00, 0x02},
1524         .bDeviceClass = UDCLASS_HUB,
1525         .bDeviceSubClass = UDSUBCLASS_HUB,
1526         .bDeviceProtocol = UDPROTO_FSHUB,
1527         .bMaxPacketSize0 = 0,
1528         .bNumConfigurations = 0,
1529 };
1530
1531 static const struct atmegadci_config_desc atmegadci_confd = {
1532         .confd = {
1533                 .bLength = sizeof(struct usb_config_descriptor),
1534                 .bDescriptorType = UDESC_CONFIG,
1535                 .wTotalLength[0] = sizeof(atmegadci_confd),
1536                 .bNumInterface = 1,
1537                 .bConfigurationValue = 1,
1538                 .iConfiguration = 0,
1539                 .bmAttributes = UC_SELF_POWERED,
1540                 .bMaxPower = 0,
1541         },
1542         .ifcd = {
1543                 .bLength = sizeof(struct usb_interface_descriptor),
1544                 .bDescriptorType = UDESC_INTERFACE,
1545                 .bNumEndpoints = 1,
1546                 .bInterfaceClass = UICLASS_HUB,
1547                 .bInterfaceSubClass = UISUBCLASS_HUB,
1548                 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
1549         },
1550         .endpd = {
1551                 .bLength = sizeof(struct usb_endpoint_descriptor),
1552                 .bDescriptorType = UDESC_ENDPOINT,
1553                 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1554                 .bmAttributes = UE_INTERRUPT,
1555                 .wMaxPacketSize[0] = 8,
1556                 .bInterval = 255,
1557         },
1558 };
1559
1560 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1561         .bDescLength = sizeof(atmegadci_hubd),
1562         .bDescriptorType = UDESC_HUB,
1563         .bNbrPorts = 1,
1564         .wHubCharacteristics[0] =
1565         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1566         .wHubCharacteristics[1] =
1567         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1568         .bPwrOn2PwrGood = 50,
1569         .bHubContrCurrent = 0,
1570         .DeviceRemovable = {0},         /* port is removable */
1571 };
1572
1573 #define STRING_LANG \
1574   0x09, 0x04,                           /* American English */
1575
1576 #define STRING_VENDOR \
1577   'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0
1578
1579 #define STRING_PRODUCT \
1580   'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1581   'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1582   'U', 0, 'B', 0,
1583
1584 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab);
1585 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1586 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1587
1588 static usb_error_t
1589 atmegadci_roothub_exec(struct usb_device *udev,
1590     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1591 {
1592         struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1593         const void *ptr;
1594         uint16_t len;
1595         uint16_t value;
1596         uint16_t index;
1597         uint8_t temp;
1598         usb_error_t err;
1599
1600         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1601
1602         /* buffer reset */
1603         ptr = (const void *)&sc->sc_hub_temp;
1604         len = 0;
1605         err = 0;
1606
1607         value = UGETW(req->wValue);
1608         index = UGETW(req->wIndex);
1609
1610         /* demultiplex the control request */
1611
1612         switch (req->bmRequestType) {
1613         case UT_READ_DEVICE:
1614                 switch (req->bRequest) {
1615                 case UR_GET_DESCRIPTOR:
1616                         goto tr_handle_get_descriptor;
1617                 case UR_GET_CONFIG:
1618                         goto tr_handle_get_config;
1619                 case UR_GET_STATUS:
1620                         goto tr_handle_get_status;
1621                 default:
1622                         goto tr_stalled;
1623                 }
1624                 break;
1625
1626         case UT_WRITE_DEVICE:
1627                 switch (req->bRequest) {
1628                 case UR_SET_ADDRESS:
1629                         goto tr_handle_set_address;
1630                 case UR_SET_CONFIG:
1631                         goto tr_handle_set_config;
1632                 case UR_CLEAR_FEATURE:
1633                         goto tr_valid;  /* nop */
1634                 case UR_SET_DESCRIPTOR:
1635                         goto tr_valid;  /* nop */
1636                 case UR_SET_FEATURE:
1637                 default:
1638                         goto tr_stalled;
1639                 }
1640                 break;
1641
1642         case UT_WRITE_ENDPOINT:
1643                 switch (req->bRequest) {
1644                 case UR_CLEAR_FEATURE:
1645                         switch (UGETW(req->wValue)) {
1646                         case UF_ENDPOINT_HALT:
1647                                 goto tr_handle_clear_halt;
1648                         case UF_DEVICE_REMOTE_WAKEUP:
1649                                 goto tr_handle_clear_wakeup;
1650                         default:
1651                                 goto tr_stalled;
1652                         }
1653                         break;
1654                 case UR_SET_FEATURE:
1655                         switch (UGETW(req->wValue)) {
1656                         case UF_ENDPOINT_HALT:
1657                                 goto tr_handle_set_halt;
1658                         case UF_DEVICE_REMOTE_WAKEUP:
1659                                 goto tr_handle_set_wakeup;
1660                         default:
1661                                 goto tr_stalled;
1662                         }
1663                         break;
1664                 case UR_SYNCH_FRAME:
1665                         goto tr_valid;  /* nop */
1666                 default:
1667                         goto tr_stalled;
1668                 }
1669                 break;
1670
1671         case UT_READ_ENDPOINT:
1672                 switch (req->bRequest) {
1673                 case UR_GET_STATUS:
1674                         goto tr_handle_get_ep_status;
1675                 default:
1676                         goto tr_stalled;
1677                 }
1678                 break;
1679
1680         case UT_WRITE_INTERFACE:
1681                 switch (req->bRequest) {
1682                 case UR_SET_INTERFACE:
1683                         goto tr_handle_set_interface;
1684                 case UR_CLEAR_FEATURE:
1685                         goto tr_valid;  /* nop */
1686                 case UR_SET_FEATURE:
1687                 default:
1688                         goto tr_stalled;
1689                 }
1690                 break;
1691
1692         case UT_READ_INTERFACE:
1693                 switch (req->bRequest) {
1694                 case UR_GET_INTERFACE:
1695                         goto tr_handle_get_interface;
1696                 case UR_GET_STATUS:
1697                         goto tr_handle_get_iface_status;
1698                 default:
1699                         goto tr_stalled;
1700                 }
1701                 break;
1702
1703         case UT_WRITE_CLASS_INTERFACE:
1704         case UT_WRITE_VENDOR_INTERFACE:
1705                 /* XXX forward */
1706                 break;
1707
1708         case UT_READ_CLASS_INTERFACE:
1709         case UT_READ_VENDOR_INTERFACE:
1710                 /* XXX forward */
1711                 break;
1712
1713         case UT_WRITE_CLASS_DEVICE:
1714                 switch (req->bRequest) {
1715                 case UR_CLEAR_FEATURE:
1716                         goto tr_valid;
1717                 case UR_SET_DESCRIPTOR:
1718                 case UR_SET_FEATURE:
1719                         break;
1720                 default:
1721                         goto tr_stalled;
1722                 }
1723                 break;
1724
1725         case UT_WRITE_CLASS_OTHER:
1726                 switch (req->bRequest) {
1727                 case UR_CLEAR_FEATURE:
1728                         goto tr_handle_clear_port_feature;
1729                 case UR_SET_FEATURE:
1730                         goto tr_handle_set_port_feature;
1731                 case UR_CLEAR_TT_BUFFER:
1732                 case UR_RESET_TT:
1733                 case UR_STOP_TT:
1734                         goto tr_valid;
1735
1736                 default:
1737                         goto tr_stalled;
1738                 }
1739                 break;
1740
1741         case UT_READ_CLASS_OTHER:
1742                 switch (req->bRequest) {
1743                 case UR_GET_TT_STATE:
1744                         goto tr_handle_get_tt_state;
1745                 case UR_GET_STATUS:
1746                         goto tr_handle_get_port_status;
1747                 default:
1748                         goto tr_stalled;
1749                 }
1750                 break;
1751
1752         case UT_READ_CLASS_DEVICE:
1753                 switch (req->bRequest) {
1754                 case UR_GET_DESCRIPTOR:
1755                         goto tr_handle_get_class_descriptor;
1756                 case UR_GET_STATUS:
1757                         goto tr_handle_get_class_status;
1758
1759                 default:
1760                         goto tr_stalled;
1761                 }
1762                 break;
1763         default:
1764                 goto tr_stalled;
1765         }
1766         goto tr_valid;
1767
1768 tr_handle_get_descriptor:
1769         switch (value >> 8) {
1770         case UDESC_DEVICE:
1771                 if (value & 0xff) {
1772                         goto tr_stalled;
1773                 }
1774                 len = sizeof(atmegadci_devd);
1775                 ptr = (const void *)&atmegadci_devd;
1776                 goto tr_valid;
1777         case UDESC_CONFIG:
1778                 if (value & 0xff) {
1779                         goto tr_stalled;
1780                 }
1781                 len = sizeof(atmegadci_confd);
1782                 ptr = (const void *)&atmegadci_confd;
1783                 goto tr_valid;
1784         case UDESC_STRING:
1785                 switch (value & 0xff) {
1786                 case 0:         /* Language table */
1787                         len = sizeof(atmegadci_langtab);
1788                         ptr = (const void *)&atmegadci_langtab;
1789                         goto tr_valid;
1790
1791                 case 1:         /* Vendor */
1792                         len = sizeof(atmegadci_vendor);
1793                         ptr = (const void *)&atmegadci_vendor;
1794                         goto tr_valid;
1795
1796                 case 2:         /* Product */
1797                         len = sizeof(atmegadci_product);
1798                         ptr = (const void *)&atmegadci_product;
1799                         goto tr_valid;
1800                 default:
1801                         break;
1802                 }
1803                 break;
1804         default:
1805                 goto tr_stalled;
1806         }
1807         goto tr_stalled;
1808
1809 tr_handle_get_config:
1810         len = 1;
1811         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1812         goto tr_valid;
1813
1814 tr_handle_get_status:
1815         len = 2;
1816         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1817         goto tr_valid;
1818
1819 tr_handle_set_address:
1820         if (value & 0xFF00) {
1821                 goto tr_stalled;
1822         }
1823         sc->sc_rt_addr = value;
1824         goto tr_valid;
1825
1826 tr_handle_set_config:
1827         if (value >= 2) {
1828                 goto tr_stalled;
1829         }
1830         sc->sc_conf = value;
1831         goto tr_valid;
1832
1833 tr_handle_get_interface:
1834         len = 1;
1835         sc->sc_hub_temp.wValue[0] = 0;
1836         goto tr_valid;
1837
1838 tr_handle_get_tt_state:
1839 tr_handle_get_class_status:
1840 tr_handle_get_iface_status:
1841 tr_handle_get_ep_status:
1842         len = 2;
1843         USETW(sc->sc_hub_temp.wValue, 0);
1844         goto tr_valid;
1845
1846 tr_handle_set_halt:
1847 tr_handle_set_interface:
1848 tr_handle_set_wakeup:
1849 tr_handle_clear_wakeup:
1850 tr_handle_clear_halt:
1851         goto tr_valid;
1852
1853 tr_handle_clear_port_feature:
1854         if (index != 1) {
1855                 goto tr_stalled;
1856         }
1857         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1858
1859         switch (value) {
1860         case UHF_PORT_SUSPEND:
1861                 atmegadci_wakeup_peer(sc);
1862                 break;
1863
1864         case UHF_PORT_ENABLE:
1865                 sc->sc_flags.port_enabled = 0;
1866                 break;
1867
1868         case UHF_PORT_TEST:
1869         case UHF_PORT_INDICATOR:
1870         case UHF_C_PORT_ENABLE:
1871         case UHF_C_PORT_OVER_CURRENT:
1872         case UHF_C_PORT_RESET:
1873                 /* nops */
1874                 break;
1875         case UHF_PORT_POWER:
1876                 sc->sc_flags.port_powered = 0;
1877                 atmegadci_pull_down(sc);
1878                 atmegadci_clocks_off(sc);
1879                 break;
1880         case UHF_C_PORT_CONNECTION:
1881                 /* clear connect change flag */
1882                 sc->sc_flags.change_connect = 0;
1883
1884                 if (!sc->sc_flags.status_bus_reset) {
1885                         /* we are not connected */
1886                         break;
1887                 }
1888
1889                 /* configure the control endpoint */
1890
1891                 /* select endpoint number */
1892                 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1893
1894                 /* set endpoint reset */
1895                 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1896
1897                 /* clear endpoint reset */
1898                 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1899
1900                 /* enable and stall endpoint */
1901                 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1902                     ATMEGA_UECONX_EPEN |
1903                     ATMEGA_UECONX_STALLRQ);
1904
1905                 /* one bank, 64-bytes wMaxPacket */
1906                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1907                     ATMEGA_UECFG0X_EPTYPE0);
1908                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1909                     ATMEGA_UECFG1X_ALLOC |
1910                     ATMEGA_UECFG1X_EPBK0 |
1911                     ATMEGA_UECFG1X_EPSIZE(3));
1912
1913                 /* check valid config */
1914                 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1915                 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1916                         DPRINTFN(0, "Chip rejected EP0 configuration\n");
1917                 }
1918                 break;
1919         case UHF_C_PORT_SUSPEND:
1920                 sc->sc_flags.change_suspend = 0;
1921                 break;
1922         default:
1923                 err = USB_ERR_IOERROR;
1924                 goto done;
1925         }
1926         goto tr_valid;
1927
1928 tr_handle_set_port_feature:
1929         if (index != 1) {
1930                 goto tr_stalled;
1931         }
1932         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1933
1934         switch (value) {
1935         case UHF_PORT_ENABLE:
1936                 sc->sc_flags.port_enabled = 1;
1937                 break;
1938         case UHF_PORT_SUSPEND:
1939         case UHF_PORT_RESET:
1940         case UHF_PORT_TEST:
1941         case UHF_PORT_INDICATOR:
1942                 /* nops */
1943                 break;
1944         case UHF_PORT_POWER:
1945                 sc->sc_flags.port_powered = 1;
1946                 break;
1947         default:
1948                 err = USB_ERR_IOERROR;
1949                 goto done;
1950         }
1951         goto tr_valid;
1952
1953 tr_handle_get_port_status:
1954
1955         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1956
1957         if (index != 1) {
1958                 goto tr_stalled;
1959         }
1960         if (sc->sc_flags.status_vbus) {
1961                 atmegadci_clocks_on(sc);
1962                 atmegadci_pull_up(sc);
1963         } else {
1964                 atmegadci_pull_down(sc);
1965                 atmegadci_clocks_off(sc);
1966         }
1967
1968         /* Select FULL-speed and Device Side Mode */
1969
1970         value = UPS_PORT_MODE_DEVICE;
1971
1972         if (sc->sc_flags.port_powered) {
1973                 value |= UPS_PORT_POWER;
1974         }
1975         if (sc->sc_flags.port_enabled) {
1976                 value |= UPS_PORT_ENABLED;
1977         }
1978         if (sc->sc_flags.status_vbus &&
1979             sc->sc_flags.status_bus_reset) {
1980                 value |= UPS_CURRENT_CONNECT_STATUS;
1981         }
1982         if (sc->sc_flags.status_suspend) {
1983                 value |= UPS_SUSPEND;
1984         }
1985         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1986
1987         value = 0;
1988
1989         if (sc->sc_flags.change_connect) {
1990                 value |= UPS_C_CONNECT_STATUS;
1991         }
1992         if (sc->sc_flags.change_suspend) {
1993                 value |= UPS_C_SUSPEND;
1994         }
1995         USETW(sc->sc_hub_temp.ps.wPortChange, value);
1996         len = sizeof(sc->sc_hub_temp.ps);
1997         goto tr_valid;
1998
1999 tr_handle_get_class_descriptor:
2000         if (value & 0xFF) {
2001                 goto tr_stalled;
2002         }
2003         ptr = (const void *)&atmegadci_hubd;
2004         len = sizeof(atmegadci_hubd);
2005         goto tr_valid;
2006
2007 tr_stalled:
2008         err = USB_ERR_STALLED;
2009 tr_valid:
2010 done:
2011         *plength = len;
2012         *pptr = ptr;
2013         return (err);
2014 }
2015
2016 static void
2017 atmegadci_xfer_setup(struct usb_setup_params *parm)
2018 {
2019         const struct usb_hw_ep_profile *pf;
2020         struct atmegadci_softc *sc;
2021         struct usb_xfer *xfer;
2022         void *last_obj;
2023         uint32_t ntd;
2024         uint32_t n;
2025         uint8_t ep_no;
2026
2027         sc = ATMEGA_BUS2SC(parm->udev->bus);
2028         xfer = parm->curr_xfer;
2029
2030         /*
2031          * NOTE: This driver does not use any of the parameters that
2032          * are computed from the following values. Just set some
2033          * reasonable dummies:
2034          */
2035         parm->hc_max_packet_size = 0x500;
2036         parm->hc_max_packet_count = 1;
2037         parm->hc_max_frame_size = 0x500;
2038
2039         usbd_transfer_setup_sub(parm);
2040
2041         /*
2042          * compute maximum number of TDs
2043          */
2044         if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2045
2046                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2047                     + 1 /* SYNC 2 */ ;
2048         } else {
2049
2050                 ntd = xfer->nframes + 1 /* SYNC */ ;
2051         }
2052
2053         /*
2054          * check if "usbd_transfer_setup_sub" set an error
2055          */
2056         if (parm->err)
2057                 return;
2058
2059         /*
2060          * allocate transfer descriptors
2061          */
2062         last_obj = NULL;
2063
2064         /*
2065          * get profile stuff
2066          */
2067         ep_no = xfer->endpointno & UE_ADDR;
2068         atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2069
2070         if (pf == NULL) {
2071                 /* should not happen */
2072                 parm->err = USB_ERR_INVAL;
2073                 return;
2074         }
2075
2076         /* align data */
2077         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2078
2079         for (n = 0; n != ntd; n++) {
2080
2081                 struct atmegadci_td *td;
2082
2083                 if (parm->buf) {
2084
2085                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2086
2087                         /* init TD */
2088                         td->max_packet_size = xfer->max_packet_size;
2089                         td->ep_no = ep_no;
2090                         if (pf->support_multi_buffer) {
2091                                 td->support_multi_buffer = 1;
2092                         }
2093                         td->obj_next = last_obj;
2094
2095                         last_obj = td;
2096                 }
2097                 parm->size[0] += sizeof(*td);
2098         }
2099
2100         xfer->td_start[0] = last_obj;
2101 }
2102
2103 static void
2104 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2105 {
2106         return;
2107 }
2108
2109 static void
2110 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2111     struct usb_endpoint *ep)
2112 {
2113         struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2114
2115         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2116             ep, udev->address,
2117             edesc->bEndpointAddress, udev->flags.usb_mode,
2118             sc->sc_rt_addr, udev->device_index);
2119
2120         if (udev->device_index != sc->sc_rt_addr) {
2121
2122                 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2123                         /* not supported */
2124                         return;
2125                 }
2126                 if (udev->speed != USB_SPEED_FULL) {
2127                         /* not supported */
2128                         return;
2129                 }
2130                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2131                         ep->methods = &atmegadci_device_isoc_fs_methods;
2132                 else
2133                         ep->methods = &atmegadci_device_non_isoc_methods;
2134         }
2135 }
2136
2137 struct usb_bus_methods atmegadci_bus_methods =
2138 {
2139         .endpoint_init = &atmegadci_ep_init,
2140         .xfer_setup = &atmegadci_xfer_setup,
2141         .xfer_unsetup = &atmegadci_xfer_unsetup,
2142         .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2143         .set_stall = &atmegadci_set_stall,
2144         .clear_stall = &atmegadci_clear_stall,
2145         .roothub_exec = &atmegadci_roothub_exec,
2146         .xfer_poll = &atmegadci_do_poll,
2147 };