sys/dev/usb/controller/avr32dci.c

   1 #include <sys/cdefs.h>
   2 __FBSDID("$FreeBSD$");
   3
   4 /*-
   5  * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the AVR32 series USB Device
  31  * Controller
  32  */
  33
  34 /*
  35  * NOTE: When the chip detects BUS-reset it will also reset the
  36  * endpoints, Function-address and more.
  37  */
  38
  39 #include <sys/stdint.h>
  40 #include <sys/stddef.h>
  41 #include <sys/param.h>
  42 #include <sys/queue.h>
  43 #include <sys/types.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/bus.h>
  47 #include <sys/linker_set.h>
  48 #include <sys/module.h>
  49 #include <sys/lock.h>
  50 #include <sys/mutex.h>
  51 #include <sys/condvar.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/sx.h>
  54 #include <sys/unistd.h>
  55 #include <sys/callout.h>
  56 #include <sys/malloc.h>
  57 #include <sys/priv.h>
  58
  59 #include <dev/usb/usb.h>
  60 #include <dev/usb/usbdi.h>
  61
  62 #define USB_DEBUG_VAR avr32dci_debug
  63
  64 #include <dev/usb/usb_core.h>
  65 #include <dev/usb/usb_debug.h>
  66 #include <dev/usb/usb_busdma.h>
  67 #include <dev/usb/usb_process.h>
  68 #include <dev/usb/usb_transfer.h>
  69 #include <dev/usb/usb_device.h>
  70 #include <dev/usb/usb_hub.h>
  71 #include <dev/usb/usb_util.h>
  72
  73 #include <dev/usb/usb_controller.h>
  74 #include <dev/usb/usb_bus.h>
  75 #include <dev/usb/controller/avr32dci.h>
  76
  77 #define AVR32_BUS2SC(bus) \
  78    ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \
  79     ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus))))
  80
  81 #define AVR32_PC2SC(pc) \
  82    AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  83
  84 #ifdef USB_DEBUG
  85 static int avr32dci_debug = 0;
  86
  87 SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI");
  88 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RW,
  89     &avr32dci_debug, 0, "AVR32 DCI debug level");
  90 #endif
  91
  92 #define AVR32_INTR_ENDPT 1
  93
  94 /* prototypes */
  95
  96 struct usb_bus_methods avr32dci_bus_methods;
  97 struct usb_pipe_methods avr32dci_device_non_isoc_methods;
  98 struct usb_pipe_methods avr32dci_device_isoc_fs_methods;
  99
 100 static avr32dci_cmd_t avr32dci_setup_rx;
 101 static avr32dci_cmd_t avr32dci_data_rx;
 102 static avr32dci_cmd_t avr32dci_data_tx;
 103 static avr32dci_cmd_t avr32dci_data_tx_sync;
 104 static void avr32dci_device_done(struct usb_xfer *, usb_error_t);
 105 static void avr32dci_do_poll(struct usb_bus *);
 106 static void avr32dci_standard_done(struct usb_xfer *);
 107 static void avr32dci_root_intr(struct avr32dci_softc *sc);
 108
 109 /*
 110  * Here is a list of what the chip supports:
 111  */
 112 static const struct usb_hw_ep_profile
 113         avr32dci_ep_profile[4] = {
 114
 115         [0] = {
 116                 .max_in_frame_size = 64,
 117                 .max_out_frame_size = 64,
 118                 .is_simplex = 1,
 119                 .support_control = 1,
 120         },
 121
 122         [1] = {
 123                 .max_in_frame_size = 512,
 124                 .max_out_frame_size = 512,
 125                 .is_simplex = 1,
 126                 .support_bulk = 1,
 127                 .support_interrupt = 1,
 128                 .support_isochronous = 1,
 129                 .support_in = 1,
 130                 .support_out = 1,
 131         },
 132
 133         [2] = {
 134                 .max_in_frame_size = 64,
 135                 .max_out_frame_size = 64,
 136                 .is_simplex = 1,
 137                 .support_bulk = 1,
 138                 .support_interrupt = 1,
 139                 .support_in = 1,
 140                 .support_out = 1,
 141         },
 142
 143         [3] = {
 144                 .max_in_frame_size = 1024,
 145                 .max_out_frame_size = 1024,
 146                 .is_simplex = 1,
 147                 .support_bulk = 1,
 148                 .support_interrupt = 1,
 149                 .support_isochronous = 1,
 150                 .support_in = 1,
 151                 .support_out = 1,
 152         },
 153 };
 154
 155 static void
 156 avr32dci_get_hw_ep_profile(struct usb_device *udev,
 157     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 158 {
 159         if (ep_addr == 0)
 160                 *ppf = avr32dci_ep_profile;
 161         else if (ep_addr < 3)
 162                 *ppf = avr32dci_ep_profile + 1;
 163         else if (ep_addr < 5)
 164                 *ppf = avr32dci_ep_profile + 2;
 165         else if (ep_addr < 7)
 166                 *ppf = avr32dci_ep_profile + 3;
 167         else
 168                 *ppf = NULL;
 169 }
 170
 171 static void
 172 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
 173 {
 174         uint32_t temp;
 175
 176         temp = AVR32_READ_4(sc, AVR32_CTRL);
 177         temp |= set;
 178         temp &= ~clear;
 179         AVR32_WRITE_4(sc, AVR32_CTRL, temp);
 180 }
 181
 182 static void
 183 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
 184 {
 185         uint32_t temp;
 186
 187         temp = AVR32_READ_4(sc, AVR32_IEN);
 188         temp |= set;
 189         temp &= ~clear;
 190         AVR32_WRITE_4(sc, AVR32_IEN, temp);
 191 }
 192
 193 static void
 194 avr32dci_clocks_on(struct avr32dci_softc *sc)
 195 {
 196         if (sc->sc_flags.clocks_off &&
 197             sc->sc_flags.port_powered) {
 198
 199                 DPRINTFN(5, "\n");
 200
 201                 /* turn on clocks */
 202                 (sc->sc_clocks_on) (&sc->sc_bus);
 203
 204                 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
 205
 206                 sc->sc_flags.clocks_off = 0;
 207         }
 208 }
 209
 210 static void
 211 avr32dci_clocks_off(struct avr32dci_softc *sc)
 212 {
 213         if (!sc->sc_flags.clocks_off) {
 214
 215                 DPRINTFN(5, "\n");
 216
 217                 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA);
 218
 219                 /* turn clocks off */
 220                 (sc->sc_clocks_off) (&sc->sc_bus);
 221
 222                 sc->sc_flags.clocks_off = 1;
 223         }
 224 }
 225
 226 static void
 227 avr32dci_pull_up(struct avr32dci_softc *sc)
 228 {
 229         /* pullup D+, if possible */
 230
 231         if (!sc->sc_flags.d_pulled_up &&
 232             sc->sc_flags.port_powered) {
 233                 sc->sc_flags.d_pulled_up = 1;
 234                 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH);
 235         }
 236 }
 237
 238 static void
 239 avr32dci_pull_down(struct avr32dci_softc *sc)
 240 {
 241         /* pulldown D+, if possible */
 242
 243         if (sc->sc_flags.d_pulled_up) {
 244                 sc->sc_flags.d_pulled_up = 0;
 245                 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
 246         }
 247 }
 248
 249 static void
 250 avr32dci_wakeup_peer(struct avr32dci_softc *sc)
 251 {
 252         if (!sc->sc_flags.status_suspend) {
 253                 return;
 254         }
 255         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0);
 256
 257         /* wait 8 milliseconds */
 258         /* Wait for reset to complete. */
 259         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 260
 261         /* hardware should have cleared RMWKUP bit */
 262 }
 263
 264 static void
 265 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr)
 266 {
 267         DPRINTFN(5, "addr=%d\n", addr);
 268
 269         avr32dci_mod_ctrl(sc, AVR32_UDADDR_ADDEN | addr, 0);
 270 }
 271
 272 static uint8_t
 273 avr32dci_setup_rx(struct avr32dci_td *td)
 274 {
 275         struct avr32dci_softc *sc;
 276         struct usb_device_request req;
 277         uint16_t count;
 278         uint32_t temp;
 279
 280         /* get pointer to softc */
 281         sc = AVR32_PC2SC(td->pc);
 282
 283         /* check endpoint status */
 284         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 285
 286         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 287
 288         if (!(temp & AVR32_EPTSTA_RX_SETUP)) {
 289                 goto not_complete;
 290         }
 291         /* clear did stall */
 292         td->did_stall = 0;
 293         /* get the packet byte count */
 294         count = AVR32_EPTSTA_BYTE_COUNT(temp);
 295
 296         /* verify data length */
 297         if (count != td->remainder) {
 298                 DPRINTFN(0, "Invalid SETUP packet "
 299                     "length, %d bytes\n", count);
 300                 goto not_complete;
 301         }
 302         if (count != sizeof(req)) {
 303                 DPRINTFN(0, "Unsupported SETUP packet "
 304                     "length, %d bytes\n", count);
 305                 goto not_complete;
 306         }
 307         /* receive data */
 308         memcpy(&req, sc->physdata, sizeof(req));
 309
 310         /* copy data into real buffer */
 311         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 312
 313         td->offset = sizeof(req);
 314         td->remainder = 0;
 315
 316         /* sneak peek the set address */
 317         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 318             (req.bRequest == UR_SET_ADDRESS)) {
 319                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 320                 /* must write address before ZLP */
 321                 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN |
 322                     AVR32_CTRL_DEV_ADDR);
 323                 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0);
 324         } else {
 325                 sc->sc_dv_addr = 0xFF;
 326         }
 327
 328         /* clear SETUP packet interrupt */
 329         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
 330         return (0);                     /* complete */
 331
 332 not_complete:
 333         if (temp & AVR32_EPTSTA_RX_SETUP) {
 334                 /* clear SETUP packet interrupt */
 335                 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
 336         }
 337         /* abort any ongoing transfer */
 338         if (!td->did_stall) {
 339                 DPRINTFN(5, "stalling\n");
 340                 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no),
 341                     AVR32_EPTSTA_FRCESTALL);
 342                 td->did_stall = 1;
 343         }
 344         return (1);                     /* not complete */
 345 }
 346
 347 static uint8_t
 348 avr32dci_data_rx(struct avr32dci_td *td)
 349 {
 350         struct avr32dci_softc *sc;
 351         struct usb_page_search buf_res;
 352         uint16_t count;
 353         uint32_t temp;
 354         uint8_t to;
 355         uint8_t got_short;
 356
 357         to = 4;                         /* don't loop forever! */
 358         got_short = 0;
 359
 360         /* get pointer to softc */
 361         sc = AVR32_PC2SC(td->pc);
 362
 363 repeat:
 364         /* check if any of the FIFO banks have data */
 365         /* check endpoint status */
 366         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 367
 368         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 369
 370         if (temp & AVR32_EPTSTA_RX_SETUP) {
 371                 if (td->remainder == 0) {
 372                         /*
 373                          * We are actually complete and have
 374                          * received the next SETUP
 375                          */
 376                         DPRINTFN(5, "faking complete\n");
 377                         return (0);     /* complete */
 378                 }
 379                 /*
 380                  * USB Host Aborted the transfer.
 381                  */
 382                 td->error = 1;
 383                 return (0);             /* complete */
 384         }
 385         /* check status */
 386         if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) {
 387                 /* no data */
 388                 goto not_complete;
 389         }
 390         /* get the packet byte count */
 391         count = AVR32_EPTSTA_BYTE_COUNT(temp);
 392
 393         /* verify the packet byte count */
 394         if (count != td->max_packet_size) {
 395                 if (count < td->max_packet_size) {
 396                         /* we have a short packet */
 397                         td->short_pkt = 1;
 398                         got_short = 1;
 399                 } else {
 400                         /* invalid USB packet */
 401                         td->error = 1;
 402                         return (0);     /* we are complete */
 403                 }
 404         }
 405         /* verify the packet byte count */
 406         if (count > td->remainder) {
 407                 /* invalid USB packet */
 408                 td->error = 1;
 409                 return (0);             /* we are complete */
 410         }
 411         while (count > 0) {
 412                 usbd_get_page(td->pc, td->offset, &buf_res);
 413
 414                 /* get correct length */
 415                 if (buf_res.length > count) {
 416                         buf_res.length = count;
 417                 }
 418                 /* receive data */
 419                 bcopy(sc->physdata +
 420                     (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
 421                     (td->ep_no << 16) + (td->offset % td->max_packet_size),
 422                     buf_res.buffer, buf_res.length)
 423                 /* update counters */
 424                     count -= buf_res.length;
 425                 td->offset += buf_res.length;
 426                 td->remainder -= buf_res.length;
 427         }
 428
 429         /* clear OUT packet interrupt */
 430         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY);
 431
 432         /* check if we are complete */
 433         if ((td->remainder == 0) || got_short) {
 434                 if (td->short_pkt) {
 435                         /* we are complete */
 436                         return (0);
 437                 }
 438                 /* else need to receive a zero length packet */
 439         }
 440         if (--to) {
 441                 goto repeat;
 442         }
 443 not_complete:
 444         return (1);                     /* not complete */
 445 }
 446
 447 static uint8_t
 448 avr32dci_data_tx(struct avr32dci_td *td)
 449 {
 450         struct avr32dci_softc *sc;
 451         struct usb_page_search buf_res;
 452         uint16_t count;
 453         uint8_t to;
 454         uint32_t temp;
 455
 456         to = 4;                         /* don't loop forever! */
 457
 458         /* get pointer to softc */
 459         sc = AVR32_PC2SC(td->pc);
 460
 461 repeat:
 462
 463         /* check endpoint status */
 464         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 465
 466         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 467
 468         if (temp & AVR32_EPTSTA_RX_SETUP) {
 469                 /*
 470                  * The current transfer was aborted
 471                  * by the USB Host
 472                  */
 473                 td->error = 1;
 474                 return (0);             /* complete */
 475         }
 476         if (temp & AVR32_EPTSTA_TX_PK_RDY) {
 477                 /* cannot write any data - all banks are busy */
 478                 goto not_complete;
 479         }
 480         count = td->max_packet_size;
 481         if (td->remainder < count) {
 482                 /* we have a short packet */
 483                 td->short_pkt = 1;
 484                 count = td->remainder;
 485         }
 486         while (count > 0) {
 487
 488                 usbd_get_page(td->pc, td->offset, &buf_res);
 489
 490                 /* get correct length */
 491                 if (buf_res.length > count) {
 492                         buf_res.length = count;
 493                 }
 494                 /* transmit data */
 495                 bcopy(buf_res.buffer, sc->physdata +
 496                     (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
 497                     (td->ep_no << 16) + (td->offset % td->max_packet_size),
 498                     buf_res.length)
 499                 /* update counters */
 500                     count -= buf_res.length;
 501                 td->offset += buf_res.length;
 502                 td->remainder -= buf_res.length;
 503         }
 504
 505         /* allocate FIFO bank */
 506         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_TX_BK_RDY);
 507
 508         /* check remainder */
 509         if (td->remainder == 0) {
 510                 if (td->short_pkt) {
 511                         return (0);     /* complete */
 512                 }
 513                 /* else we need to transmit a short packet */
 514         }
 515         if (--to) {
 516                 goto repeat;
 517         }
 518 not_complete:
 519         return (1);                     /* not complete */
 520 }
 521
 522 static uint8_t
 523 avr32dci_data_tx_sync(struct avr32dci_td *td)
 524 {
 525         struct avr32dci_softc *sc;
 526         uint32_t temp;
 527
 528         /* get pointer to softc */
 529         sc = AVR32_PC2SC(td->pc);
 530
 531         /* check endpoint status */
 532         temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
 533
 534         DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
 535
 536         if (temp & AVR32_EPTSTA_RX_SETUP) {
 537                 DPRINTFN(5, "faking complete\n");
 538                 /* Race condition */
 539                 return (0);             /* complete */
 540         }
 541         /*
 542          * The control endpoint has only got one bank, so if that bank
 543          * is free the packet has been transferred!
 544          */
 545         if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) {
 546                 /* cannot write any data - a bank is busy */
 547                 goto not_complete;
 548         }
 549         if (sc->sc_dv_addr != 0xFF) {
 550                 /* set new address */
 551                 avr32dci_set_address(sc, sc->sc_dv_addr);
 552         }
 553         return (0);                     /* complete */
 554
 555 not_complete:
 556         return (1);                     /* not complete */
 557 }
 558
 559 static uint8_t
 560 avr32dci_xfer_do_fifo(struct usb_xfer *xfer)
 561 {
 562         struct avr32dci_td *td;
 563
 564         DPRINTFN(9, "\n");
 565
 566         td = xfer->td_transfer_cache;
 567         while (1) {
 568                 if ((td->func) (td)) {
 569                         /* operation in progress */
 570                         break;
 571                 }
 572                 if (((void *)td) == xfer->td_transfer_last) {
 573                         goto done;
 574                 }
 575                 if (td->error) {
 576                         goto done;
 577                 } else if (td->remainder > 0) {
 578                         /*
 579                          * We had a short transfer. If there is no alternate
 580                          * next, stop processing !
 581                          */
 582                         if (!td->alt_next) {
 583                                 goto done;
 584                         }
 585                 }
 586                 /*
 587                  * Fetch the next transfer descriptor and transfer
 588                  * some flags to the next transfer descriptor
 589                  */
 590                 td = td->obj_next;
 591                 xfer->td_transfer_cache = td;
 592         }
 593         return (1);                     /* not complete */
 594
 595 done:
 596         /* compute all actual lengths */
 597
 598         avr32dci_standard_done(xfer);
 599         return (0);                     /* complete */
 600 }
 601
 602 static void
 603 avr32dci_interrupt_poll(struct avr32dci_softc *sc)
 604 {
 605         struct usb_xfer *xfer;
 606
 607 repeat:
 608         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 609                 if (!avr32dci_xfer_do_fifo(xfer)) {
 610                         /* queue has been modified */
 611                         goto repeat;
 612                 }
 613         }
 614 }
 615
 616 void
 617 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on)
 618 {
 619         DPRINTFN(5, "vbus = %u\n", is_on);
 620
 621         if (is_on) {
 622                 if (!sc->sc_flags.status_vbus) {
 623                         sc->sc_flags.status_vbus = 1;
 624
 625                         /* complete root HUB interrupt endpoint */
 626
 627                         avr32dci_root_intr(sc);
 628                 }
 629         } else {
 630                 if (sc->sc_flags.status_vbus) {
 631                         sc->sc_flags.status_vbus = 0;
 632                         sc->sc_flags.status_bus_reset = 0;
 633                         sc->sc_flags.status_suspend = 0;
 634                         sc->sc_flags.change_suspend = 0;
 635                         sc->sc_flags.change_connect = 1;
 636
 637                         /* complete root HUB interrupt endpoint */
 638
 639                         avr32dci_root_intr(sc);
 640                 }
 641         }
 642 }
 643
 644 void
 645 avr32dci_interrupt(struct avr32dci_softc *sc)
 646 {
 647         uint32_t status;
 648
 649         USB_BUS_LOCK(&sc->sc_bus);
 650
 651         /* read interrupt status */
 652         status = AVR32_READ_4(sc, AVR32_INTSTA);
 653
 654         /* clear all set interrupts */
 655         AVR32_WRITE_4(sc, AVR32_CLRINT, status);
 656
 657         DPRINTFN(14, "INTSTA=0x%08x\n", status);
 658
 659         /* check for any bus state change interrupts */
 660         if (status & AVR32_INT_ENDRESET) {
 661
 662                 DPRINTFN(5, "end of reset\n");
 663
 664                 /* set correct state */
 665                 sc->sc_flags.status_bus_reset = 1;
 666                 sc->sc_flags.status_suspend = 0;
 667                 sc->sc_flags.change_suspend = 0;
 668                 sc->sc_flags.change_connect = 1;
 669
 670                 /* disable resume interrupt */
 671                 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
 672                     AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
 673
 674                 /* complete root HUB interrupt endpoint */
 675                 avr32dci_root_intr(sc);
 676         }
 677         /*
 678          * If resume and suspend is set at the same time we interpret
 679          * that like RESUME. Resume is set when there is at least 3
 680          * milliseconds of inactivity on the USB BUS.
 681          */
 682         if (status & AVR32_INT_WAKE_UP) {
 683
 684                 DPRINTFN(5, "resume interrupt\n");
 685
 686                 if (sc->sc_flags.status_suspend) {
 687                         /* update status bits */
 688                         sc->sc_flags.status_suspend = 0;
 689                         sc->sc_flags.change_suspend = 1;
 690
 691                         /* disable resume interrupt */
 692                         avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
 693                             AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
 694
 695                         /* complete root HUB interrupt endpoint */
 696                         avr32dci_root_intr(sc);
 697                 }
 698         } else if (status & AVR32_INT_DET_SUSPD) {
 699
 700                 DPRINTFN(5, "suspend interrupt\n");
 701
 702                 if (!sc->sc_flags.status_suspend) {
 703                         /* update status bits */
 704                         sc->sc_flags.status_suspend = 1;
 705                         sc->sc_flags.change_suspend = 1;
 706
 707                         /* disable suspend interrupt */
 708                         avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP |
 709                             AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD);
 710
 711                         /* complete root HUB interrupt endpoint */
 712                         avr32dci_root_intr(sc);
 713                 }
 714         }
 715         /* check for any endpoint interrupts */
 716         if (status & -AVR32_INT_EPT_INT(0)) {
 717
 718                 DPRINTFN(5, "real endpoint interrupt\n");
 719
 720                 avr32dci_interrupt_poll(sc);
 721         }
 722         USB_BUS_UNLOCK(&sc->sc_bus);
 723 }
 724
 725 static void
 726 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp)
 727 {
 728         struct avr32dci_td *td;
 729
 730         /* get current Transfer Descriptor */
 731         td = temp->td_next;
 732         temp->td = td;
 733
 734         /* prepare for next TD */
 735         temp->td_next = td->obj_next;
 736
 737         /* fill out the Transfer Descriptor */
 738         td->func = temp->func;
 739         td->pc = temp->pc;
 740         td->offset = temp->offset;
 741         td->remainder = temp->len;
 742         td->error = 0;
 743         td->did_stall = temp->did_stall;
 744         td->short_pkt = temp->short_pkt;
 745         td->alt_next = temp->setup_alt_next;
 746 }
 747
 748 static void
 749 avr32dci_setup_standard_chain(struct usb_xfer *xfer)
 750 {
 751         struct avr32dci_std_temp temp;
 752         struct avr32dci_softc *sc;
 753         struct avr32dci_td *td;
 754         uint32_t x;
 755         uint8_t ep_no;
 756         uint8_t need_sync;
 757
 758         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 759             xfer->address, UE_GET_ADDR(xfer->endpoint),
 760             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 761
 762         temp.max_frame_size = xfer->max_frame_size;
 763
 764         td = xfer->td_start[0];
 765         xfer->td_transfer_first = td;
 766         xfer->td_transfer_cache = td;
 767
 768         /* setup temp */
 769
 770         temp.td = NULL;
 771         temp.td_next = xfer->td_start[0];
 772         temp.offset = 0;
 773         temp.setup_alt_next = xfer->flags_int.short_frames_ok;
 774         temp.did_stall = !xfer->flags_int.control_stall;
 775
 776         sc = AVR32_BUS2SC(xfer->xroot->bus);
 777         ep_no = (xfer->endpoint & UE_ADDR);
 778
 779         /* check if we should prepend a setup message */
 780
 781         if (xfer->flags_int.control_xfr) {
 782                 if (xfer->flags_int.control_hdr) {
 783
 784                         temp.func = &avr32dci_setup_rx;
 785                         temp.len = xfer->frlengths[0];
 786                         temp.pc = xfer->frbuffers + 0;
 787                         temp.short_pkt = temp.len ? 1 : 0;
 788                         /* check for last frame */
 789                         if (xfer->nframes == 1) {
 790                                 /* no STATUS stage yet, SETUP is last */
 791                                 if (xfer->flags_int.control_act)
 792                                         temp.setup_alt_next = 0;
 793                         }
 794                         avr32dci_setup_standard_chain_sub(&temp);
 795                 }
 796                 x = 1;
 797         } else {
 798                 x = 0;
 799         }
 800
 801         if (x != xfer->nframes) {
 802                 if (xfer->endpoint & UE_DIR_IN) {
 803                         temp.func = &avr32dci_data_tx;
 804                         need_sync = 1;
 805                 } else {
 806                         temp.func = &avr32dci_data_rx;
 807                         need_sync = 0;
 808                 }
 809
 810                 /* setup "pc" pointer */
 811                 temp.pc = xfer->frbuffers + x;
 812         } else {
 813                 need_sync = 0;
 814         }
 815         while (x != xfer->nframes) {
 816
 817                 /* DATA0 / DATA1 message */
 818
 819                 temp.len = xfer->frlengths[x];
 820
 821                 x++;
 822
 823                 if (x == xfer->nframes) {
 824                         if (xfer->flags_int.control_xfr) {
 825                                 if (xfer->flags_int.control_act) {
 826                                         temp.setup_alt_next = 0;
 827                                 }
 828                         } else {
 829                                 temp.setup_alt_next = 0;
 830                         }
 831                 }
 832                 if (temp.len == 0) {
 833
 834                         /* make sure that we send an USB packet */
 835
 836                         temp.short_pkt = 0;
 837
 838                 } else {
 839
 840                         /* regular data transfer */
 841
 842                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
 843                 }
 844
 845                 avr32dci_setup_standard_chain_sub(&temp);
 846
 847                 if (xfer->flags_int.isochronous_xfr) {
 848                         temp.offset += temp.len;
 849                 } else {
 850                         /* get next Page Cache pointer */
 851                         temp.pc = xfer->frbuffers + x;
 852                 }
 853         }
 854
 855         if (xfer->flags_int.control_xfr) {
 856
 857                 /* always setup a valid "pc" pointer for status and sync */
 858                 temp.pc = xfer->frbuffers + 0;
 859                 temp.len = 0;
 860                 temp.short_pkt = 0;
 861                 temp.setup_alt_next = 0;
 862
 863                 /* check if we need to sync */
 864                 if (need_sync) {
 865                         /* we need a SYNC point after TX */
 866                         temp.func = &avr32dci_data_tx_sync;
 867                         avr32dci_setup_standard_chain_sub(&temp);
 868                 }
 869                 /* check if we should append a status stage */
 870                 if (!xfer->flags_int.control_act) {
 871
 872                         /*
 873                          * Send a DATA1 message and invert the current
 874                          * endpoint direction.
 875                          */
 876                         if (xfer->endpoint & UE_DIR_IN) {
 877                                 temp.func = &avr32dci_data_rx;
 878                                 need_sync = 0;
 879                         } else {
 880                                 temp.func = &avr32dci_data_tx;
 881                                 need_sync = 1;
 882                         }
 883
 884                         avr32dci_setup_standard_chain_sub(&temp);
 885                         if (need_sync) {
 886                                 /* we need a SYNC point after TX */
 887                                 temp.func = &avr32dci_data_tx_sync;
 888                                 avr32dci_setup_standard_chain_sub(&temp);
 889                         }
 890                 }
 891         }
 892         /* must have at least one frame! */
 893         td = temp.td;
 894         xfer->td_transfer_last = td;
 895 }
 896
 897 static void
 898 avr32dci_timeout(void *arg)
 899 {
 900         struct usb_xfer *xfer = arg;
 901
 902         DPRINTF("xfer=%p\n", xfer);
 903
 904         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
 905
 906         /* transfer is transferred */
 907         avr32dci_device_done(xfer, USB_ERR_TIMEOUT);
 908 }
 909
 910 static void
 911 avr32dci_start_standard_chain(struct usb_xfer *xfer)
 912 {
 913         DPRINTFN(9, "\n");
 914
 915         /* poll one time - will turn on interrupts */
 916         if (avr32dci_xfer_do_fifo(xfer)) {
 917                 uint8_t ep_no = xfer->endpoint & UE_ADDR_MASK;
 918
 919                 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0);
 920
 921                 /* put transfer on interrupt queue */
 922                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
 923
 924                 /* start timeout, if any */
 925                 if (xfer->timeout != 0) {
 926                         usbd_transfer_timeout_ms(xfer,
 927                             &avr32dci_timeout, xfer->timeout);
 928                 }
 929         }
 930 }
 931
 932 static void
 933 avr32dci_root_intr(struct avr32dci_softc *sc)
 934 {
 935         DPRINTFN(9, "\n");
 936
 937         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
 938
 939         /* set port bit */
 940         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
 941
 942         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
 943             sizeof(sc->sc_hub_idata));
 944 }
 945
 946 static usb_error_t
 947 avr32dci_standard_done_sub(struct usb_xfer *xfer)
 948 {
 949         struct avr32dci_td *td;
 950         uint32_t len;
 951         uint8_t error;
 952
 953         DPRINTFN(9, "\n");
 954
 955         td = xfer->td_transfer_cache;
 956
 957         do {
 958                 len = td->remainder;
 959
 960                 if (xfer->aframes != xfer->nframes) {
 961                         /*
 962                          * Verify the length and subtract
 963                          * the remainder from "frlengths[]":
 964                          */
 965                         if (len > xfer->frlengths[xfer->aframes]) {
 966                                 td->error = 1;
 967                         } else {
 968                                 xfer->frlengths[xfer->aframes] -= len;
 969                         }
 970                 }
 971                 /* Check for transfer error */
 972                 if (td->error) {
 973                         /* the transfer is finished */
 974                         error = 1;
 975                         td = NULL;
 976                         break;
 977                 }
 978                 /* Check for short transfer */
 979                 if (len > 0) {
 980                         if (xfer->flags_int.short_frames_ok) {
 981                                 /* follow alt next */
 982                                 if (td->alt_next) {
 983                                         td = td->obj_next;
 984                                 } else {
 985                                         td = NULL;
 986                                 }
 987                         } else {
 988                                 /* the transfer is finished */
 989                                 td = NULL;
 990                         }
 991                         error = 0;
 992                         break;
 993                 }
 994                 td = td->obj_next;
 995
 996                 /* this USB frame is complete */
 997                 error = 0;
 998                 break;
 999
1000         } while (0);
1001
1002         /* update transfer cache */
1003
1004         xfer->td_transfer_cache = td;
1005
1006         return (error ?
1007             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1008 }
1009
1010 static void
1011 avr32dci_standard_done(struct usb_xfer *xfer)
1012 {
1013         usb_error_t err = 0;
1014
1015         DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
1016             xfer, xfer->pipe);
1017
1018         /* reset scanner */
1019
1020         xfer->td_transfer_cache = xfer->td_transfer_first;
1021
1022         if (xfer->flags_int.control_xfr) {
1023
1024                 if (xfer->flags_int.control_hdr) {
1025
1026                         err = avr32dci_standard_done_sub(xfer);
1027                 }
1028                 xfer->aframes = 1;
1029
1030                 if (xfer->td_transfer_cache == NULL) {
1031                         goto done;
1032                 }
1033         }
1034         while (xfer->aframes != xfer->nframes) {
1035
1036                 err = avr32dci_standard_done_sub(xfer);
1037                 xfer->aframes++;
1038
1039                 if (xfer->td_transfer_cache == NULL) {
1040                         goto done;
1041                 }
1042         }
1043
1044         if (xfer->flags_int.control_xfr &&
1045             !xfer->flags_int.control_act) {
1046
1047                 err = avr32dci_standard_done_sub(xfer);
1048         }
1049 done:
1050         avr32dci_device_done(xfer, err);
1051 }
1052
1053 /*------------------------------------------------------------------------*
1054  *      avr32dci_device_done
1055  *
1056  * NOTE: this function can be called more than one time on the
1057  * same USB transfer!
1058  *------------------------------------------------------------------------*/
1059 static void
1060 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1061 {
1062         struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1063         uint8_t ep_no;
1064
1065         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1066
1067         DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n",
1068             xfer, xfer->pipe, error);
1069
1070         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1071                 ep_no = (xfer->endpoint & UE_ADDR);
1072
1073                 /* disable endpoint interrupt */
1074                 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no));
1075
1076                 DPRINTFN(15, "disabled interrupts!\n");
1077         }
1078         /* dequeue transfer and start next transfer */
1079         usbd_transfer_done(xfer, error);
1080 }
1081
1082 static void
1083 avr32dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1084     struct usb_endpoint *ep, uint8_t *did_stall)
1085 {
1086         struct avr32dci_softc *sc;
1087         uint8_t ep_no;
1088
1089         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1090
1091         DPRINTFN(5, "pipe=%p\n", pipe);
1092
1093         if (xfer) {
1094                 /* cancel any ongoing transfers */
1095                 avr32dci_device_done(xfer, USB_ERR_STALLED);
1096         }
1097         sc = AVR32_BUS2SC(udev->bus);
1098         /* get endpoint number */
1099         ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1100         /* set stall */
1101         AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1102 }
1103
1104 static void
1105 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no,
1106     uint8_t ep_type, uint8_t ep_dir)
1107 {
1108         const struct usb_hw_ep_profile *pf;
1109         uint32_t temp;
1110         uint32_t epsize;
1111         uint8_t n;
1112
1113         if (ep_type == UE_CONTROL) {
1114                 /* clearing stall is not needed */
1115                 return;
1116         }
1117         /* set endpoint reset */
1118         AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no));
1119
1120         /* set stall */
1121         AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1122
1123         /* reset data toggle */
1124         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ);
1125
1126         /* clear stall */
1127         AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1128
1129         if (ep_type == UE_BULK) {
1130                 temp = AVR32_EPTCFG_TYPE_BULK;
1131         } else if (ep_type == UE_INTERRUPT) {
1132                 temp = AVR32_EPTCFG_TYPE_INTR;
1133         } else {
1134                 temp = AVR32_EPTCFG_TYPE_ISOC |
1135                     AVR32_EPTCFG_NB_TRANS(1);
1136         }
1137         if (ep_dir & UE_DIR_IN) {
1138                 temp |= AVR32_EPTCFG_EPDIR_IN;
1139         }
1140         avr32dci_get_hw_ep_profile(NULL, &pf, ep_no);
1141
1142         /* compute endpoint size (use maximum) */
1143         epsize = pf->max_in_frame_size | pf->max_out_frame_size;
1144         n = 0;
1145         while ((epsize /= 2))
1146                 n++;
1147         temp |= AVR32_EPTCFG_EPSIZE(n);
1148
1149         /* use the maximum number of banks supported */
1150         if (ep_no < 1)
1151                 temp |= AVR32_EPTCFG_NBANK(1);
1152         else if (ep_no < 3)
1153                 temp |= AVR32_EPTCFG_NBANK(2);
1154         else
1155                 temp |= AVR32_EPTCFG_NBANK(3);
1156
1157         AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp);
1158
1159         temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no));
1160
1161         if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1162                 DPRINTFN(0, "Chip rejected configuration\n");
1163         } else {
1164                 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no),
1165                     AVR32_EPTCTL_EPT_ENABL);
1166         }
1167 }
1168
1169 static void
1170 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1171 {
1172         struct avr32dci_softc *sc;
1173         struct usb_endpoint_descriptor *ed;
1174
1175         DPRINTFN(5, "pipe=%p\n", pipe);
1176
1177         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1178
1179         /* check mode */
1180         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1181                 /* not supported */
1182                 return;
1183         }
1184         /* get softc */
1185         sc = AVR32_BUS2SC(udev->bus);
1186
1187         /* get endpoint descriptor */
1188         ed = pipe->edesc;
1189
1190         /* reset endpoint */
1191         avr32dci_clear_stall_sub(sc,
1192             (ed->bEndpointAddress & UE_ADDR),
1193             (ed->bmAttributes & UE_XFERTYPE),
1194             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1195 }
1196
1197 usb_error_t
1198 avr32dci_init(struct avr32dci_softc *sc)
1199 {
1200         uint8_t n;
1201
1202         DPRINTF("start\n");
1203
1204         /* set up the bus structure */
1205         sc->sc_bus.usbrev = USB_REV_1_1;
1206         sc->sc_bus.methods = &avr32dci_bus_methods;
1207
1208         USB_BUS_LOCK(&sc->sc_bus);
1209
1210         /* make sure USB is enabled */
1211         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
1212
1213         /* turn on clocks */
1214         (sc->sc_clocks_on) (&sc->sc_bus);
1215
1216         /* make sure device is re-enumerated */
1217         avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
1218
1219         /* wait a little for things to stabilise */
1220         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1221
1222         /* disable interrupts */
1223         avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1224
1225         /* enable interrupts */
1226         avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
1227             AVR32_INT_ENDRESET, 0);
1228
1229         /* reset all endpoints */
1230 /**INDENT** Warning@1207: Extra ) */
1231         AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
1232
1233         /* disable all endpoints */
1234         for (n = 0; n != AVR32_EP_MAX; n++) {
1235                 /* disable endpoint */
1236                 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1237         }
1238
1239         /* turn off clocks */
1240
1241         avr32dci_clocks_off(sc);
1242
1243         USB_BUS_UNLOCK(&sc->sc_bus);
1244
1245         /* catch any lost interrupts */
1246
1247         avr32dci_do_poll(&sc->sc_bus);
1248
1249         return (0);                     /* success */
1250 }
1251
1252 void
1253 avr32dci_uninit(struct avr32dci_softc *sc)
1254 {
1255         uint8_t n;
1256
1257         USB_BUS_LOCK(&sc->sc_bus);
1258
1259         /* turn on clocks */
1260         (sc->sc_clocks_on) (&sc->sc_bus);
1261
1262         /* disable interrupts */
1263         avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1264
1265         /* reset all endpoints */
1266 /**INDENT** Warning@1242: Extra ) */
1267         AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
1268
1269         /* disable all endpoints */
1270         for (n = 0; n != AVR32_EP_MAX; n++) {
1271                 /* disable endpoint */
1272                 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1273         }
1274
1275         sc->sc_flags.port_powered = 0;
1276         sc->sc_flags.status_vbus = 0;
1277         sc->sc_flags.status_bus_reset = 0;
1278         sc->sc_flags.status_suspend = 0;
1279         sc->sc_flags.change_suspend = 0;
1280         sc->sc_flags.change_connect = 1;
1281
1282         avr32dci_pull_down(sc);
1283         avr32dci_clocks_off(sc);
1284
1285         USB_BUS_UNLOCK(&sc->sc_bus);
1286 }
1287
1288 void
1289 avr32dci_suspend(struct avr32dci_softc *sc)
1290 {
1291         return;
1292 }
1293
1294 void
1295 avr32dci_resume(struct avr32dci_softc *sc)
1296 {
1297         return;
1298 }
1299
1300 static void
1301 avr32dci_do_poll(struct usb_bus *bus)
1302 {
1303         struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
1304
1305         USB_BUS_LOCK(&sc->sc_bus);
1306         avr32dci_interrupt_poll(sc);
1307         USB_BUS_UNLOCK(&sc->sc_bus);
1308 }
1309
1310 /*------------------------------------------------------------------------*
1311  * at91dci bulk support
1312  * at91dci control support
1313  * at91dci interrupt support
1314  *------------------------------------------------------------------------*/
1315 static void
1316 avr32dci_device_non_isoc_open(struct usb_xfer *xfer)
1317 {
1318         return;
1319 }
1320
1321 static void
1322 avr32dci_device_non_isoc_close(struct usb_xfer *xfer)
1323 {
1324         avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1325 }
1326
1327 static void
1328 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer)
1329 {
1330         return;
1331 }
1332
1333 static void
1334 avr32dci_device_non_isoc_start(struct usb_xfer *xfer)
1335 {
1336         /* setup TDs */
1337         avr32dci_setup_standard_chain(xfer);
1338         avr32dci_start_standard_chain(xfer);
1339 }
1340
1341 struct usb_pipe_methods avr32dci_device_non_isoc_methods =
1342 {
1343         .open = avr32dci_device_non_isoc_open,
1344         .close = avr32dci_device_non_isoc_close,
1345         .enter = avr32dci_device_non_isoc_enter,
1346         .start = avr32dci_device_non_isoc_start,
1347 };
1348
1349 /*------------------------------------------------------------------------*
1350  * at91dci full speed isochronous support
1351  *------------------------------------------------------------------------*/
1352 static void
1353 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer)
1354 {
1355         return;
1356 }
1357
1358 static void
1359 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer)
1360 {
1361         avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1362 }
1363
1364 static void
1365 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1366 {
1367         struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1368         uint32_t temp;
1369         uint32_t nframes;
1370         uint8_t ep_no;
1371
1372         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1373             xfer, xfer->pipe->isoc_next, xfer->nframes);
1374
1375         /* get the current frame index */
1376         ep_no = xfer->endpoint & UE_ADDR_MASK;
1377         nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8);
1378
1379         nframes &= AVR32_FRAME_MASK;
1380
1381         /*
1382          * check if the frame index is within the window where the frames
1383          * will be inserted
1384          */
1385         temp = (nframes - xfer->pipe->isoc_next) & AVR32_FRAME_MASK;
1386
1387         if ((xfer->pipe->is_synced == 0) ||
1388             (temp < xfer->nframes)) {
1389                 /*
1390                  * If there is data underflow or the pipe queue is
1391                  * empty we schedule the transfer a few frames ahead
1392                  * of the current frame position. Else two isochronous
1393                  * transfers might overlap.
1394                  */
1395                 xfer->pipe->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
1396                 xfer->pipe->is_synced = 1;
1397                 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next);
1398         }
1399         /*
1400          * compute how many milliseconds the insertion is ahead of the
1401          * current frame position:
1402          */
1403         temp = (xfer->pipe->isoc_next - nframes) & AVR32_FRAME_MASK;
1404
1405         /*
1406          * pre-compute when the isochronous transfer will be finished:
1407          */
1408         xfer->isoc_time_complete =
1409             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1410             xfer->nframes;
1411
1412         /* compute frame number for next insertion */
1413         xfer->pipe->isoc_next += xfer->nframes;
1414
1415         /* setup TDs */
1416         avr32dci_setup_standard_chain(xfer);
1417 }
1418
1419 static void
1420 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer)
1421 {
1422         /* start TD chain */
1423         avr32dci_start_standard_chain(xfer);
1424 }
1425
1426 struct usb_pipe_methods avr32dci_device_isoc_fs_methods =
1427 {
1428         .open = avr32dci_device_isoc_fs_open,
1429         .close = avr32dci_device_isoc_fs_close,
1430         .enter = avr32dci_device_isoc_fs_enter,
1431         .start = avr32dci_device_isoc_fs_start,
1432 };
1433
1434 /*------------------------------------------------------------------------*
1435  * at91dci root control support
1436  *------------------------------------------------------------------------*
1437  * Simulate a hardware HUB by handling all the necessary requests.
1438  *------------------------------------------------------------------------*/
1439
1440 static const struct usb_device_descriptor avr32dci_devd = {
1441         .bLength = sizeof(struct usb_device_descriptor),
1442         .bDescriptorType = UDESC_DEVICE,
1443         .bcdUSB = {0x00, 0x02},
1444         .bDeviceClass = UDCLASS_HUB,
1445         .bDeviceSubClass = UDSUBCLASS_HUB,
1446         .bDeviceProtocol = UDPROTO_HSHUBSTT,
1447         .bMaxPacketSize = 64,
1448         .bcdDevice = {0x00, 0x01},
1449         .iManufacturer = 1,
1450         .iProduct = 2,
1451         .bNumConfigurations = 1,
1452 };
1453
1454 static const struct usb_device_qualifier avr32dci_odevd = {
1455         .bLength = sizeof(struct usb_device_qualifier),
1456         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1457         .bcdUSB = {0x00, 0x02},
1458         .bDeviceClass = UDCLASS_HUB,
1459         .bDeviceSubClass = UDSUBCLASS_HUB,
1460         .bDeviceProtocol = UDPROTO_FSHUB,
1461         .bMaxPacketSize0 = 0,
1462         .bNumConfigurations = 0,
1463 };
1464
1465 static const struct avr32dci_config_desc avr32dci_confd = {
1466         .confd = {
1467                 .bLength = sizeof(struct usb_config_descriptor),
1468                 .bDescriptorType = UDESC_CONFIG,
1469                 .wTotalLength[0] = sizeof(avr32dci_confd),
1470                 .bNumInterface = 1,
1471                 .bConfigurationValue = 1,
1472                 .iConfiguration = 0,
1473                 .bmAttributes = UC_SELF_POWERED,
1474                 .bMaxPower = 0,
1475         },
1476         .ifcd = {
1477                 .bLength = sizeof(struct usb_interface_descriptor),
1478                 .bDescriptorType = UDESC_INTERFACE,
1479                 .bNumEndpoints = 1,
1480                 .bInterfaceClass = UICLASS_HUB,
1481                 .bInterfaceSubClass = UISUBCLASS_HUB,
1482                 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
1483         },
1484         .endpd = {
1485                 .bLength = sizeof(struct usb_endpoint_descriptor),
1486                 .bDescriptorType = UDESC_ENDPOINT,
1487                 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT),
1488                 .bmAttributes = UE_INTERRUPT,
1489                 .wMaxPacketSize[0] = 8,
1490                 .bInterval = 255,
1491         },
1492 };
1493
1494 static const struct usb_hub_descriptor_min avr32dci_hubd = {
1495         .bDescLength = sizeof(avr32dci_hubd),
1496         .bDescriptorType = UDESC_HUB,
1497         .bNbrPorts = 1,
1498         .wHubCharacteristics[0] =
1499         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1500         .wHubCharacteristics[1] =
1501         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1502         .bPwrOn2PwrGood = 50,
1503         .bHubContrCurrent = 0,
1504         .DeviceRemovable = {0},         /* port is removable */
1505 };
1506
1507 #define STRING_LANG \
1508   0x09, 0x04,                           /* American English */
1509
1510 #define STRING_VENDOR \
1511   'A', 0, 'V', 0, 'R', 0, '3', 0, '2', 0
1512
1513 #define STRING_PRODUCT \
1514   'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1515   'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1516   'U', 0, 'B', 0,
1517
1518 USB_MAKE_STRING_DESC(STRING_LANG, avr32dci_langtab);
1519 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor);
1520 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product);
1521
1522 static usb_error_t
1523 avr32dci_roothub_exec(struct usb_device *udev,
1524     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1525 {
1526         struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
1527         const void *ptr;
1528         uint16_t len;
1529         uint16_t value;
1530         uint16_t index;
1531         uint32_t temp;
1532         usb_error_t err;
1533
1534         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1535
1536         /* buffer reset */
1537         ptr = (const void *)&sc->sc_hub_temp;
1538         len = 0;
1539         err = 0;
1540
1541         value = UGETW(req->wValue);
1542         index = UGETW(req->wIndex);
1543
1544         /* demultiplex the control request */
1545
1546         switch (req->bmRequestType) {
1547         case UT_READ_DEVICE:
1548                 switch (req->bRequest) {
1549                 case UR_GET_DESCRIPTOR:
1550                         goto tr_handle_get_descriptor;
1551                 case UR_GET_CONFIG:
1552                         goto tr_handle_get_config;
1553                 case UR_GET_STATUS:
1554                         goto tr_handle_get_status;
1555                 default:
1556                         goto tr_stalled;
1557                 }
1558                 break;
1559
1560         case UT_WRITE_DEVICE:
1561                 switch (req->bRequest) {
1562                 case UR_SET_ADDRESS:
1563                         goto tr_handle_set_address;
1564                 case UR_SET_CONFIG:
1565                         goto tr_handle_set_config;
1566                 case UR_CLEAR_FEATURE:
1567                         goto tr_valid;  /* nop */
1568                 case UR_SET_DESCRIPTOR:
1569                         goto tr_valid;  /* nop */
1570                 case UR_SET_FEATURE:
1571                 default:
1572                         goto tr_stalled;
1573                 }
1574                 break;
1575
1576         case UT_WRITE_ENDPOINT:
1577                 switch (req->bRequest) {
1578                 case UR_CLEAR_FEATURE:
1579                         switch (UGETW(req->wValue)) {
1580                         case UF_ENDPOINT_HALT:
1581                                 goto tr_handle_clear_halt;
1582                         case UF_DEVICE_REMOTE_WAKEUP:
1583                                 goto tr_handle_clear_wakeup;
1584                         default:
1585                                 goto tr_stalled;
1586                         }
1587                         break;
1588                 case UR_SET_FEATURE:
1589                         switch (UGETW(req->wValue)) {
1590                         case UF_ENDPOINT_HALT:
1591                                 goto tr_handle_set_halt;
1592                         case UF_DEVICE_REMOTE_WAKEUP:
1593                                 goto tr_handle_set_wakeup;
1594                         default:
1595                                 goto tr_stalled;
1596                         }
1597                         break;
1598                 case UR_SYNCH_FRAME:
1599                         goto tr_valid;  /* nop */
1600                 default:
1601                         goto tr_stalled;
1602                 }
1603                 break;
1604
1605         case UT_READ_ENDPOINT:
1606                 switch (req->bRequest) {
1607                 case UR_GET_STATUS:
1608                         goto tr_handle_get_ep_status;
1609                 default:
1610                         goto tr_stalled;
1611                 }
1612                 break;
1613
1614         case UT_WRITE_INTERFACE:
1615                 switch (req->bRequest) {
1616                 case UR_SET_INTERFACE:
1617                         goto tr_handle_set_interface;
1618                 case UR_CLEAR_FEATURE:
1619                         goto tr_valid;  /* nop */
1620                 case UR_SET_FEATURE:
1621                 default:
1622                         goto tr_stalled;
1623                 }
1624                 break;
1625
1626         case UT_READ_INTERFACE:
1627                 switch (req->bRequest) {
1628                 case UR_GET_INTERFACE:
1629                         goto tr_handle_get_interface;
1630                 case UR_GET_STATUS:
1631                         goto tr_handle_get_iface_status;
1632                 default:
1633                         goto tr_stalled;
1634                 }
1635                 break;
1636
1637         case UT_WRITE_CLASS_INTERFACE:
1638         case UT_WRITE_VENDOR_INTERFACE:
1639                 /* XXX forward */
1640                 break;
1641
1642         case UT_READ_CLASS_INTERFACE:
1643         case UT_READ_VENDOR_INTERFACE:
1644                 /* XXX forward */
1645                 break;
1646
1647         case UT_WRITE_CLASS_DEVICE:
1648                 switch (req->bRequest) {
1649                 case UR_CLEAR_FEATURE:
1650                         goto tr_valid;
1651                 case UR_SET_DESCRIPTOR:
1652                 case UR_SET_FEATURE:
1653                         break;
1654                 default:
1655                         goto tr_stalled;
1656                 }
1657                 break;
1658
1659         case UT_WRITE_CLASS_OTHER:
1660                 switch (req->bRequest) {
1661                 case UR_CLEAR_FEATURE:
1662                         goto tr_handle_clear_port_feature;
1663                 case UR_SET_FEATURE:
1664                         goto tr_handle_set_port_feature;
1665                 case UR_CLEAR_TT_BUFFER:
1666                 case UR_RESET_TT:
1667                 case UR_STOP_TT:
1668                         goto tr_valid;
1669
1670                 default:
1671                         goto tr_stalled;
1672                 }
1673                 break;
1674
1675         case UT_READ_CLASS_OTHER:
1676                 switch (req->bRequest) {
1677                 case UR_GET_TT_STATE:
1678                         goto tr_handle_get_tt_state;
1679                 case UR_GET_STATUS:
1680                         goto tr_handle_get_port_status;
1681                 default:
1682                         goto tr_stalled;
1683                 }
1684                 break;
1685
1686         case UT_READ_CLASS_DEVICE:
1687                 switch (req->bRequest) {
1688                 case UR_GET_DESCRIPTOR:
1689                         goto tr_handle_get_class_descriptor;
1690                 case UR_GET_STATUS:
1691                         goto tr_handle_get_class_status;
1692
1693                 default:
1694                         goto tr_stalled;
1695                 }
1696                 break;
1697         default:
1698                 goto tr_stalled;
1699         }
1700         goto tr_valid;
1701
1702 tr_handle_get_descriptor:
1703         switch (value >> 8) {
1704         case UDESC_DEVICE:
1705                 if (value & 0xff) {
1706                         goto tr_stalled;
1707                 }
1708                 len = sizeof(avr32dci_devd);
1709                 ptr = (const void *)&avr32dci_devd;
1710                 goto tr_valid;
1711         case UDESC_CONFIG:
1712                 if (value & 0xff) {
1713                         goto tr_stalled;
1714                 }
1715                 len = sizeof(avr32dci_confd);
1716                 ptr = (const void *)&avr32dci_confd;
1717                 goto tr_valid;
1718         case UDESC_STRING:
1719                 switch (value & 0xff) {
1720                 case 0:         /* Language table */
1721                         len = sizeof(avr32dci_langtab);
1722                         ptr = (const void *)&avr32dci_langtab;
1723                         goto tr_valid;
1724
1725                 case 1:         /* Vendor */
1726                         len = sizeof(avr32dci_vendor);
1727                         ptr = (const void *)&avr32dci_vendor;
1728                         goto tr_valid;
1729
1730                 case 2:         /* Product */
1731                         len = sizeof(avr32dci_product);
1732                         ptr = (const void *)&avr32dci_product;
1733                         goto tr_valid;
1734                 default:
1735                         break;
1736                 }
1737                 break;
1738         default:
1739                 goto tr_stalled;
1740         }
1741         goto tr_stalled;
1742
1743 tr_handle_get_config:
1744         len = 1;
1745         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1746         goto tr_valid;
1747
1748 tr_handle_get_status:
1749         len = 2;
1750         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1751         goto tr_valid;
1752
1753 tr_handle_set_address:
1754         if (value & 0xFF00) {
1755                 goto tr_stalled;
1756         }
1757         sc->sc_rt_addr = value;
1758         goto tr_valid;
1759
1760 tr_handle_set_config:
1761         if (value >= 2) {
1762                 goto tr_stalled;
1763         }
1764         sc->sc_conf = value;
1765         goto tr_valid;
1766
1767 tr_handle_get_interface:
1768         len = 1;
1769         sc->sc_hub_temp.wValue[0] = 0;
1770         goto tr_valid;
1771
1772 tr_handle_get_tt_state:
1773 tr_handle_get_class_status:
1774 tr_handle_get_iface_status:
1775 tr_handle_get_ep_status:
1776         len = 2;
1777         USETW(sc->sc_hub_temp.wValue, 0);
1778         goto tr_valid;
1779
1780 tr_handle_set_halt:
1781 tr_handle_set_interface:
1782 tr_handle_set_wakeup:
1783 tr_handle_clear_wakeup:
1784 tr_handle_clear_halt:
1785         goto tr_valid;
1786
1787 tr_handle_clear_port_feature:
1788         if (index != 1) {
1789                 goto tr_stalled;
1790         }
1791         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1792
1793         switch (value) {
1794         case UHF_PORT_SUSPEND:
1795                 avr32dci_wakeup_peer(sc);
1796                 break;
1797
1798         case UHF_PORT_ENABLE:
1799                 sc->sc_flags.port_enabled = 0;
1800                 break;
1801
1802         case UHF_PORT_TEST:
1803         case UHF_PORT_INDICATOR:
1804         case UHF_C_PORT_ENABLE:
1805         case UHF_C_PORT_OVER_CURRENT:
1806         case UHF_C_PORT_RESET:
1807                 /* nops */
1808                 break;
1809         case UHF_PORT_POWER:
1810                 sc->sc_flags.port_powered = 0;
1811                 avr32dci_pull_down(sc);
1812                 avr32dci_clocks_off(sc);
1813                 break;
1814         case UHF_C_PORT_CONNECTION:
1815                 /* clear connect change flag */
1816                 sc->sc_flags.change_connect = 0;
1817
1818                 if (!sc->sc_flags.status_bus_reset) {
1819                         /* we are not connected */
1820                         break;
1821                 }
1822                 /* configure the control endpoint */
1823                 /* set endpoint reset */
1824                 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0));
1825
1826                 /* set stall */
1827                 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL);
1828
1829                 /* reset data toggle */
1830                 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ);
1831
1832                 /* clear stall */
1833                 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL);
1834
1835                 /* configure */
1836                 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CONTROL |
1837                     AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6));
1838
1839                 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0));
1840
1841                 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1842                         DPRINTFN(0, "Chip rejected configuration\n");
1843                 } else {
1844                         AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0),
1845                             AVR32_EPTCTL_EPT_ENABL);
1846                 }
1847                 break;
1848         case UHF_C_PORT_SUSPEND:
1849                 sc->sc_flags.change_suspend = 0;
1850                 break;
1851         default:
1852                 err = USB_ERR_IOERROR;
1853                 goto done;
1854         }
1855         goto tr_valid;
1856
1857 tr_handle_set_port_feature:
1858         if (index != 1) {
1859                 goto tr_stalled;
1860         }
1861         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1862
1863         switch (value) {
1864         case UHF_PORT_ENABLE:
1865                 sc->sc_flags.port_enabled = 1;
1866                 break;
1867         case UHF_PORT_SUSPEND:
1868         case UHF_PORT_RESET:
1869         case UHF_PORT_TEST:
1870         case UHF_PORT_INDICATOR:
1871                 /* nops */
1872                 break;
1873         case UHF_PORT_POWER:
1874                 sc->sc_flags.port_powered = 1;
1875                 break;
1876         default:
1877                 err = USB_ERR_IOERROR;
1878                 goto done;
1879         }
1880         goto tr_valid;
1881
1882 tr_handle_get_port_status:
1883
1884         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1885
1886         if (index != 1) {
1887                 goto tr_stalled;
1888         }
1889         if (sc->sc_flags.status_vbus) {
1890                 avr32dci_clocks_on(sc);
1891                 avr32dci_pull_up(sc);
1892         } else {
1893                 avr32dci_pull_down(sc);
1894                 avr32dci_clocks_off(sc);
1895         }
1896
1897         /* Select Device Side Mode */
1898
1899         value = UPS_PORT_MODE_DEVICE;
1900
1901         /* Check for High Speed */
1902         if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED)
1903                 value |= UPS_HIGH_SPEED;
1904
1905         if (sc->sc_flags.port_powered) {
1906                 value |= UPS_PORT_POWER;
1907         }
1908         if (sc->sc_flags.port_enabled) {
1909                 value |= UPS_PORT_ENABLED;
1910         }
1911         if (sc->sc_flags.status_vbus &&
1912             sc->sc_flags.status_bus_reset) {
1913                 value |= UPS_CURRENT_CONNECT_STATUS;
1914         }
1915         if (sc->sc_flags.status_suspend) {
1916                 value |= UPS_SUSPEND;
1917         }
1918         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1919
1920         value = 0;
1921
1922         if (sc->sc_flags.change_connect) {
1923                 value |= UPS_C_CONNECT_STATUS;
1924         }
1925         if (sc->sc_flags.change_suspend) {
1926                 value |= UPS_C_SUSPEND;
1927         }
1928         USETW(sc->sc_hub_temp.ps.wPortChange, value);
1929         len = sizeof(sc->sc_hub_temp.ps);
1930         goto tr_valid;
1931
1932 tr_handle_get_class_descriptor:
1933         if (value & 0xFF) {
1934                 goto tr_stalled;
1935         }
1936         ptr = (const void *)&avr32dci_hubd;
1937         len = sizeof(avr32dci_hubd);
1938         goto tr_valid;
1939
1940 tr_stalled:
1941         err = USB_ERR_STALLED;
1942 tr_valid:
1943 done:
1944         *plength = len;
1945         *pptr = ptr;
1946         return (err);
1947 }
1948
1949 static void
1950 avr32dci_xfer_setup(struct usb_setup_params *parm)
1951 {
1952         const struct usb_hw_ep_profile *pf;
1953         struct avr32dci_softc *sc;
1954         struct usb_xfer *xfer;
1955         void *last_obj;
1956         uint32_t ntd;
1957         uint32_t n;
1958         uint8_t ep_no;
1959
1960         sc = AVR32_BUS2SC(parm->udev->bus);
1961         xfer = parm->curr_xfer;
1962
1963         /*
1964          * NOTE: This driver does not use any of the parameters that
1965          * are computed from the following values. Just set some
1966          * reasonable dummies:
1967          */
1968         parm->hc_max_packet_size = 0x400;
1969         parm->hc_max_packet_count = 1;
1970         parm->hc_max_frame_size = 0x400;
1971
1972         usbd_transfer_setup_sub(parm);
1973
1974         /*
1975          * compute maximum number of TDs
1976          */
1977         if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
1978
1979                 ntd = xfer->nframes + 1 /* STATUS */ + 1        /* SYNC 1 */
1980                     + 1 /* SYNC 2 */ ;
1981         } else {
1982
1983                 ntd = xfer->nframes + 1 /* SYNC */ ;
1984         }
1985
1986         /*
1987          * check if "usbd_transfer_setup_sub" set an error
1988          */
1989         if (parm->err)
1990                 return;
1991
1992         /*
1993          * allocate transfer descriptors
1994          */
1995         last_obj = NULL;
1996
1997         /*
1998          * get profile stuff
1999          */
2000         ep_no = xfer->endpoint & UE_ADDR;
2001         avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2002
2003         if (pf == NULL) {
2004                 /* should not happen */
2005                 parm->err = USB_ERR_INVAL;
2006                 return;
2007         }
2008         /* align data */
2009         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2010
2011         for (n = 0; n != ntd; n++) {
2012
2013                 struct avr32dci_td *td;
2014
2015                 if (parm->buf) {
2016                         uint32_t temp;
2017
2018                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2019
2020                         /* init TD */
2021                         td->max_packet_size = xfer->max_packet_size;
2022                         td->ep_no = ep_no;
2023                         temp = pf->max_in_frame_size | pf->max_out_frame_size;
2024                         td->bank_shift = 0;
2025                         while ((temp /= 2))
2026                                 td->bank_shift++;
2027                         if (pf->support_multi_buffer) {
2028                                 td->support_multi_buffer = 1;
2029                         }
2030                         td->obj_next = last_obj;
2031
2032                         last_obj = td;
2033                 }
2034                 parm->size[0] += sizeof(*td);
2035         }
2036
2037         xfer->td_start[0] = last_obj;
2038 }
2039
2040 static void
2041 avr32dci_xfer_unsetup(struct usb_xfer *xfer)
2042 {
2043         return;
2044 }
2045
2046 static void
2047 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2048     struct usb_endpoint *ep)
2049 {
2050         struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
2051
2052         DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2053             pipe, udev->address,
2054             edesc->bEndpointAddress, udev->flags.usb_mode,
2055             sc->sc_rt_addr, udev->device_index);
2056
2057         if (udev->device_index != sc->sc_rt_addr) {
2058
2059                 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2060                         /* not supported */
2061                         return;
2062                 }
2063                 if ((udev->speed != USB_SPEED_FULL) &&
2064                     (udev->speed != USB_SPEED_HIGH)) {
2065                         /* not supported */
2066                         return;
2067                 }
2068                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2069                         pipe->methods = &avr32dci_device_isoc_fs_methods;
2070                 else
2071                         pipe->methods = &avr32dci_device_non_isoc_methods;
2072         }
2073 }
2074
2075 struct usb_bus_methods avr32dci_bus_methods =
2076 {
2077         .endpoint_init = &avr32dci_ep_init,
2078         .xfer_setup = &avr32dci_xfer_setup,
2079         .xfer_unsetup = &avr32dci_xfer_unsetup,
2080         .get_hw_ep_profile = &avr32dci_get_hw_ep_profile,
2081         .set_stall = &avr32dci_set_stall,
2082         .clear_stall = &avr32dci_clear_stall,
2083         .roothub_exec = &avr32dci_roothub_exec,
2084         .xfer_poll = &avr32dci_do_poll,
2085 };