2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/mutex.h>
50 #include <sys/sched.h>
56 #include <machine/apicreg.h>
57 #include <machine/cpu.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/apicvar.h>
62 #include <machine/md_var.h>
63 #include <machine/smp.h>
64 #include <machine/specialreg.h>
67 #include <sys/interrupt.h>
72 #include <sys/dtrace_bsd.h>
73 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU];
76 /* Sanity checks on IDT vectors. */
77 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
78 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
79 CTASSERT(APIC_LOCAL_INTS == 240);
80 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
82 /* Magic IRQ values for the timer and syscalls. */
83 #define IRQ_TIMER (NUM_IO_INTS + 1)
84 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
87 * Support for local APICs. Local APICs manage interrupts on each
88 * individual processor as opposed to I/O APICs which receive interrupts
89 * from I/O devices and then forward them on to the local APICs.
91 * Local APICs can also send interrupts to each other thus providing the
96 u_int lvt_edgetrigger:1;
105 struct lvt la_lvts[LVT_MAX + 1];
108 u_int la_cluster_id:2;
110 u_long *la_timer_count;
111 u_long la_hard_ticks;
112 u_long la_stat_ticks;
113 u_long la_prof_ticks;
114 /* Include IDT_SYSCALL to make indexing easier. */
115 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
116 } static lapics[MAX_APIC_ID + 1];
118 /* XXX: should thermal be an NMI? */
120 /* Global defaults for local APIC LVT entries. */
121 static struct lvt lvts[LVT_MAX + 1] = {
122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
126 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
130 static inthand_t *ioint_handlers[] = {
132 IDTVEC(apic_isr1), /* 32 - 63 */
133 IDTVEC(apic_isr2), /* 64 - 95 */
134 IDTVEC(apic_isr3), /* 96 - 127 */
135 IDTVEC(apic_isr4), /* 128 - 159 */
136 IDTVEC(apic_isr5), /* 160 - 191 */
137 IDTVEC(apic_isr6), /* 192 - 223 */
138 IDTVEC(apic_isr7), /* 224 - 255 */
142 static u_int32_t lapic_timer_divisors[] = {
143 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
144 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
147 extern inthand_t IDTVEC(rsvd);
149 volatile lapic_t *lapic;
150 vm_paddr_t lapic_paddr;
151 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
153 static void lapic_enable(void);
154 static void lapic_resume(struct pic *pic);
155 static void lapic_timer_enable_intr(void);
156 static void lapic_timer_oneshot(u_int count);
157 static void lapic_timer_periodic(u_int count);
158 static void lapic_timer_set_divisor(u_int divisor);
159 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
161 struct pic lapic_pic = { .pic_resume = lapic_resume };
164 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
168 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
169 if (la->la_lvts[pin].lvt_active)
170 lvt = &la->la_lvts[pin];
174 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
176 if (lvt->lvt_edgetrigger == 0)
177 value |= APIC_LVT_TM;
178 if (lvt->lvt_activehi == 0)
179 value |= APIC_LVT_IIPP_INTALO;
182 value |= lvt->lvt_mode;
183 switch (lvt->lvt_mode) {
184 case APIC_LVT_DM_NMI:
185 case APIC_LVT_DM_SMI:
186 case APIC_LVT_DM_INIT:
187 case APIC_LVT_DM_EXTINT:
188 if (!lvt->lvt_edgetrigger) {
189 printf("lapic%u: Forcing LINT%u to edge trigger\n",
191 value |= APIC_LVT_TM;
193 /* Use a vector of 0. */
195 case APIC_LVT_DM_FIXED:
196 value |= lvt->lvt_vector;
199 panic("bad APIC LVT delivery mode: %#x\n", value);
205 * Map the local APIC and setup necessary interrupt vectors.
208 lapic_init(vm_paddr_t addr)
211 /* Map the local APIC and setup the spurious interrupt handler. */
212 KASSERT(trunc_page(addr) == addr,
213 ("local APIC not aligned on a page boundary"));
214 lapic = pmap_mapdev(addr, sizeof(lapic_t));
216 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
217 GSEL(GCODE_SEL, SEL_KPL));
219 /* Perform basic initialization of the BSP's local APIC. */
222 /* Set BSP's per-CPU local APIC ID. */
223 PCPU_SET(apic_id, lapic_id());
225 /* Local APIC timer interrupt. */
226 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
227 GSEL(GCODE_SEL, SEL_KPL));
229 /* XXX: error/thermal interrupts */
233 * Create a local APIC instance.
236 lapic_create(u_int apic_id, int boot_cpu)
240 if (apic_id > MAX_APIC_ID) {
241 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
243 panic("Can't ignore BSP");
246 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
250 * Assume no local LVT overrides and a cluster of 0 and
251 * intra-cluster ID of 0.
253 lapics[apic_id].la_present = 1;
254 lapics[apic_id].la_id = apic_id;
255 for (i = 0; i < LVT_MAX; i++) {
256 lapics[apic_id].la_lvts[i] = lvts[i];
257 lapics[apic_id].la_lvts[i].lvt_active = 0;
259 for (i = 0; i <= APIC_NUM_IOINTS; i++)
260 lapics[apic_id].la_ioint_irqs[i] = -1;
261 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
262 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
266 cpu_add(apic_id, boot_cpu);
271 * Dump contents of local APIC registers
274 lapic_dump(const char* str)
277 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
278 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
279 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
280 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
281 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
282 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
283 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
288 lapic_setup(int boot)
293 char buf[MAXCOMLEN + 1];
295 la = &lapics[lapic_id()];
296 KASSERT(la->la_present, ("missing APIC structure"));
297 eflags = intr_disable();
298 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
300 /* Initialize the TPR to allow all interrupts. */
303 /* Setup spurious vector and enable the local APIC. */
306 /* Program LINT[01] LVT entries. */
307 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
308 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
310 /* Program the PMC LVT entry if present. */
311 if (maxlvt >= LVT_PMC)
312 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
314 /* Program timer LVT and setup handler. */
315 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
317 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
318 intrcnt_add(buf, &la->la_timer_count);
321 /* We don't setup the timer during boot on the BSP until later. */
322 if (!(boot && PCPU_GET(cpuid) == 0) && lapic_timer_hz != 0) {
323 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
325 lapic_timer_set_divisor(lapic_timer_divisor);
326 lapic_timer_periodic(lapic_timer_period);
327 lapic_timer_enable_intr();
330 /* XXX: Error and thermal LVTs */
332 intr_restore(eflags);
336 lapic_reenable_pmc(void)
341 value = lapic->lvt_pcint;
342 value &= ~APIC_LVT_M;
343 lapic->lvt_pcint = value;
349 lapic_update_pmc(void *dummy)
353 la = &lapics[lapic_id()];
354 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
359 lapic_enable_pmc(void)
364 /* Fail if the local APIC is not present. */
368 /* Fail if the PMC LVT is not present. */
369 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
370 if (maxlvt < LVT_PMC)
373 lvts[LVT_PMC].lvt_masked = 0;
377 * If hwpmc was loaded at boot time then the APs may not be
378 * started yet. In that case, don't forward the request to
379 * them as they will program the lvt when they start.
382 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
385 lapic_update_pmc(NULL);
393 lapic_disable_pmc(void)
398 /* Fail if the local APIC is not present. */
402 /* Fail if the PMC LVT is not present. */
403 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
404 if (maxlvt < LVT_PMC)
407 lvts[LVT_PMC].lvt_masked = 1;
410 /* The APs should always be started when hwpmc is unloaded. */
411 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
413 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
418 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
419 * that it can drive hardclock, statclock, and profclock. This function
420 * returns true if it is able to use the local APIC timer to drive the
421 * clocks and false if it is not able.
424 lapic_setup_clock(void)
429 /* Can't drive the timer without a local APIC. */
433 if (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)
436 /* Start off with a divisor of 2 (power on reset default). */
437 lapic_timer_divisor = 2;
439 /* Try to calibrate the local APIC timer. */
441 lapic_timer_set_divisor(lapic_timer_divisor);
442 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
444 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
445 if (value != APIC_TIMER_MAX_COUNT)
447 lapic_timer_divisor <<= 1;
448 } while (lapic_timer_divisor <= 128);
449 if (lapic_timer_divisor > 128)
450 panic("lapic: Divisor too big");
453 printf("lapic: Divisor %lu, Frequency %lu hz\n",
454 lapic_timer_divisor, value);
457 * We want to run stathz in the neighborhood of 128hz. We would
458 * like profhz to run as often as possible, so we let it run on
459 * each clock tick. We try to honor the requested 'hz' value as
462 * If 'hz' is above 1500, then we just let the lapic timer
463 * (and profhz) run at hz. If 'hz' is below 1500 but above
464 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
465 * is below 750 then we let the lapic timer run at 4 * 'hz'.
470 lapic_timer_hz = hz * 2;
472 lapic_timer_hz = hz * 4;
473 if (lapic_timer_hz < 128)
474 stathz = lapic_timer_hz;
476 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
477 profhz = lapic_timer_hz;
478 lapic_timer_period = value / lapic_timer_hz;
481 * Start up the timer on the BSP. The APs will kick off their
482 * timer during lapic_setup().
484 lapic_timer_periodic(lapic_timer_period);
485 lapic_timer_enable_intr();
494 /* Software disable the local APIC. */
496 value &= ~APIC_SVR_SWEN;
505 /* Program the spurious vector to enable the local APIC. */
507 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
508 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
512 /* Reset the local APIC on the BSP during resume. */
514 lapic_resume(struct pic *pic)
524 KASSERT(lapic != NULL, ("local APIC is not mapped"));
525 return (lapic->id >> APIC_ID_SHIFT);
529 lapic_intr_pending(u_int vector)
531 volatile u_int32_t *irr;
534 * The IRR registers are an array of 128-bit registers each of
535 * which only describes 32 interrupts in the low 32 bits.. Thus,
536 * we divide the vector by 32 to get the 128-bit index. We then
537 * multiply that index by 4 to get the equivalent index from
538 * treating the IRR as an array of 32-bit registers. Finally, we
539 * modulus the vector by 32 to determine the individual bit to
543 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
547 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
551 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
553 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
555 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
556 ("%s: intra cluster id %u too big", __func__, cluster_id));
557 la = &lapics[apic_id];
558 la->la_cluster = cluster;
559 la->la_cluster_id = cluster_id;
563 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
568 if (apic_id == APIC_ID_ALL) {
569 lvts[pin].lvt_masked = masked;
573 KASSERT(lapics[apic_id].la_present,
574 ("%s: missing APIC %u", __func__, apic_id));
575 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
576 lapics[apic_id].la_lvts[pin].lvt_active = 1;
578 printf("lapic%u:", apic_id);
581 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
586 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
592 if (apic_id == APIC_ID_ALL) {
597 KASSERT(lapics[apic_id].la_present,
598 ("%s: missing APIC %u", __func__, apic_id));
599 lvt = &lapics[apic_id].la_lvts[pin];
602 printf("lapic%u:", apic_id);
604 lvt->lvt_mode = mode;
606 case APIC_LVT_DM_NMI:
607 case APIC_LVT_DM_SMI:
608 case APIC_LVT_DM_INIT:
609 case APIC_LVT_DM_EXTINT:
610 lvt->lvt_edgetrigger = 1;
611 lvt->lvt_activehi = 1;
612 if (mode == APIC_LVT_DM_EXTINT)
618 panic("Unsupported delivery mode: 0x%x\n", mode);
623 case APIC_LVT_DM_NMI:
626 case APIC_LVT_DM_SMI:
629 case APIC_LVT_DM_INIT:
632 case APIC_LVT_DM_EXTINT:
636 printf(" -> LINT%u\n", pin);
642 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
645 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
647 if (apic_id == APIC_ID_ALL) {
648 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
652 KASSERT(lapics[apic_id].la_present,
653 ("%s: missing APIC %u", __func__, apic_id));
654 lapics[apic_id].la_lvts[pin].lvt_active = 1;
655 lapics[apic_id].la_lvts[pin].lvt_activehi =
656 (pol == INTR_POLARITY_HIGH);
658 printf("lapic%u:", apic_id);
661 printf(" LINT%u polarity: %s\n", pin,
662 pol == INTR_POLARITY_HIGH ? "high" : "low");
667 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
670 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
672 if (apic_id == APIC_ID_ALL) {
673 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
677 KASSERT(lapics[apic_id].la_present,
678 ("%s: missing APIC %u", __func__, apic_id));
679 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
680 (trigger == INTR_TRIGGER_EDGE);
681 lapics[apic_id].la_lvts[pin].lvt_active = 1;
683 printf("lapic%u:", apic_id);
686 printf(" LINT%u trigger: %s\n", pin,
687 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
692 * Adjust the TPR of the current CPU so that it blocks all interrupts below
693 * the passed in vector.
696 lapic_set_tpr(u_int vector)
703 tpr = lapic->tpr & ~APIC_TPR_PRIO;
717 * Read the contents of the error status register. We have to write
718 * to the register first before reading from it.
729 lapic_handle_intr(int vector, struct trapframe *frame)
734 panic("Couldn't get vector from ISR!");
735 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
737 intr_execute_handlers(isrc, frame);
741 lapic_handle_timer(struct trapframe *frame)
745 /* Send EOI first thing. */
748 #if defined(SMP) && !defined(SCHED_ULE)
750 * Don't do any accounting for the disabled HTT cores, since it
751 * will provide misleading numbers for the userland.
753 * No locking is necessary here, since even if we loose the race
754 * when hlt_cpus_mask changes it is not a big deal, really.
756 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
757 * and unlike other schedulers it actually schedules threads to
760 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
764 /* Look up our local APIC structure for the tick counters. */
765 la = &lapics[PCPU_GET(apic_id)];
766 (*la->la_timer_count)++;
771 * If the DTrace hooks are configured and a callback function
772 * has been registered, then call it to process the high speed
775 int cpu = PCPU_GET(cpuid);
776 if (lapic_cyclic_clock_func[cpu] != NULL)
777 (*lapic_cyclic_clock_func[cpu])(frame);
780 /* Fire hardclock at hz. */
781 la->la_hard_ticks += hz;
782 if (la->la_hard_ticks >= lapic_timer_hz) {
783 la->la_hard_ticks -= lapic_timer_hz;
784 if (PCPU_GET(cpuid) == 0)
785 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
787 hardclock_cpu(TRAPF_USERMODE(frame));
790 /* Fire statclock at stathz. */
791 la->la_stat_ticks += stathz;
792 if (la->la_stat_ticks >= lapic_timer_hz) {
793 la->la_stat_ticks -= lapic_timer_hz;
794 statclock(TRAPF_USERMODE(frame));
797 /* Fire profclock at profhz, but only when needed. */
798 la->la_prof_ticks += profhz;
799 if (la->la_prof_ticks >= lapic_timer_hz) {
800 la->la_prof_ticks -= lapic_timer_hz;
802 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
808 lapic_timer_set_divisor(u_int divisor)
811 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
812 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
813 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
814 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
818 lapic_timer_oneshot(u_int count)
822 value = lapic->lvt_timer;
823 value &= ~APIC_LVTT_TM;
824 value |= APIC_LVTT_TM_ONE_SHOT;
825 lapic->lvt_timer = value;
826 lapic->icr_timer = count;
830 lapic_timer_periodic(u_int count)
834 value = lapic->lvt_timer;
835 value &= ~APIC_LVTT_TM;
836 value |= APIC_LVTT_TM_PERIODIC;
837 lapic->lvt_timer = value;
838 lapic->icr_timer = count;
842 lapic_timer_enable_intr(void)
846 value = lapic->lvt_timer;
847 value &= ~APIC_LVT_M;
848 lapic->lvt_timer = value;
852 apic_cpuid(u_int apic_id)
855 return apic_cpuids[apic_id];
861 /* Request a free IDT vector to be used by the specified IRQ. */
863 apic_alloc_vector(u_int apic_id, u_int irq)
867 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
870 * Search for a free vector. Currently we just use a very simple
871 * algorithm to find the first free vector.
873 mtx_lock_spin(&icu_lock);
874 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
875 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
877 lapics[apic_id].la_ioint_irqs[vector] = irq;
878 mtx_unlock_spin(&icu_lock);
879 return (vector + APIC_IO_INTS);
881 mtx_unlock_spin(&icu_lock);
886 * Request 'count' free contiguous IDT vectors to be used by 'count'
887 * IRQs. 'count' must be a power of two and the vectors will be
888 * aligned on a boundary of 'align'. If the request cannot be
889 * satisfied, 0 is returned.
892 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
894 u_int first, run, vector;
896 KASSERT(powerof2(count), ("bad count"));
897 KASSERT(powerof2(align), ("bad align"));
898 KASSERT(align >= count, ("align < count"));
900 for (run = 0; run < count; run++)
901 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
906 * Search for 'count' free vectors. As with apic_alloc_vector(),
907 * this just uses a simple first fit algorithm.
911 mtx_lock_spin(&icu_lock);
912 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
914 /* Vector is in use, end run. */
915 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
921 /* Start a new run if run == 0 and vector is aligned. */
923 if ((vector & (align - 1)) != 0)
929 /* Keep looping if the run isn't long enough yet. */
933 /* Found a run, assign IRQs and return the first vector. */
934 for (vector = 0; vector < count; vector++)
935 lapics[apic_id].la_ioint_irqs[first + vector] =
937 mtx_unlock_spin(&icu_lock);
938 return (first + APIC_IO_INTS);
940 mtx_unlock_spin(&icu_lock);
941 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
946 * Enable a vector for a particular apic_id. Since all lapics share idt
947 * entries and ioint_handlers this enables the vector on all lapics. lapics
948 * which do not have the vector configured would report spurious interrupts
952 apic_enable_vector(u_int apic_id, u_int vector)
955 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
956 KASSERT(ioint_handlers[vector / 32] != NULL,
957 ("No ISR handler for vector %u", vector));
958 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
959 GSEL(GCODE_SEL, SEL_KPL));
963 apic_disable_vector(u_int apic_id, u_int vector)
966 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
967 KASSERT(ioint_handlers[vector / 32] != NULL,
968 ("No ISR handler for vector %u", vector));
971 * We can not currently clear the idt entry because other cpus
972 * may have a valid vector at this offset.
974 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL,
975 GSEL(GCODE_SEL, SEL_KPL));
979 /* Release an APIC vector when it's no longer in use. */
981 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
985 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
986 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
987 ("Vector %u does not map to an IRQ line", vector));
988 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
989 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
990 irq, ("IRQ mismatch"));
993 * Bind us to the cpu that owned the vector before freeing it so
994 * we don't lose an interrupt delivery race.
999 if (sched_is_bound(td))
1000 panic("apic_free_vector: Thread already bound.\n");
1001 sched_bind(td, apic_cpuid(apic_id));
1004 mtx_lock_spin(&icu_lock);
1005 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1006 mtx_unlock_spin(&icu_lock);
1014 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1016 apic_idt_to_irq(u_int apic_id, u_int vector)
1020 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1021 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1022 ("Vector %u does not map to an IRQ line", vector));
1023 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1031 * Dump data about APIC IDT vector mappings.
1033 DB_SHOW_COMMAND(apic, db_show_apic)
1035 struct intsrc *isrc;
1040 if (strcmp(modif, "vv") == 0)
1042 else if (strcmp(modif, "v") == 0)
1046 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1047 if (lapics[apic_id].la_present == 0)
1049 db_printf("Interrupts bound to lapic %u\n", apic_id);
1050 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1051 irq = lapics[apic_id].la_ioint_irqs[i];
1052 if (irq == -1 || irq == IRQ_SYSCALL)
1054 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1055 if (irq == IRQ_TIMER)
1056 db_printf("lapic timer\n");
1057 else if (irq < NUM_IO_INTS) {
1058 isrc = intr_lookup_source(irq);
1059 if (isrc == NULL || verbose == 0)
1060 db_printf("IRQ %u\n", irq);
1062 db_dump_intr_event(isrc->is_event,
1065 db_printf("IRQ %u ???\n", irq);
1071 dump_mask(const char *prefix, uint32_t v, int base)
1076 for (i = 0; i < 32; i++)
1079 db_printf("%s:", prefix);
1082 db_printf(" %02x", base + i);
1088 /* Show info from the lapic regs for this CPU. */
1089 DB_SHOW_COMMAND(lapic, db_show_lapic)
1093 db_printf("lapic ID = %d\n", lapic_id());
1095 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1097 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1099 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1100 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1101 db_printf("TPR = %02x\n", lapic->tpr);
1103 #define dump_field(prefix, index) \
1104 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1107 db_printf("In-service Interrupts:\n");
1117 db_printf("TMR Interrupts:\n");
1127 db_printf("IRR Interrupts:\n");
1142 * APIC probing support code. This includes code to manage enumerators.
1145 static SLIST_HEAD(, apic_enumerator) enumerators =
1146 SLIST_HEAD_INITIALIZER(enumerators);
1147 static struct apic_enumerator *best_enum;
1150 apic_register_enumerator(struct apic_enumerator *enumerator)
1153 struct apic_enumerator *apic_enum;
1155 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1156 if (apic_enum == enumerator)
1157 panic("%s: Duplicate register of %s", __func__,
1158 enumerator->apic_name);
1161 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1165 * Probe the APIC enumerators, enumerate CPUs, and initialize the
1169 apic_init(void *dummy __unused)
1171 struct apic_enumerator *enumerator;
1175 /* We only support built in local APICs. */
1176 if (!(cpu_feature & CPUID_APIC))
1179 /* Don't probe if APIC mode is disabled. */
1180 if (resource_disabled("apic", 0))
1183 /* First, probe all the enumerators to find the best match. */
1186 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1187 retval = enumerator->apic_probe();
1190 if (best_enum == NULL || best < retval) {
1191 best_enum = enumerator;
1195 if (best_enum == NULL) {
1197 printf("APIC: Could not find any APICs.\n");
1202 printf("APIC: Using the %s enumerator.\n",
1203 best_enum->apic_name);
1206 * To work around an errata, we disable the local APIC on some
1207 * CPUs during early startup. We need to turn the local APIC back
1208 * on on such CPUs now.
1210 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL &&
1211 (cpu_id & 0xff0) == 0x610) {
1212 apic_base = rdmsr(MSR_APICBASE);
1213 apic_base |= APICBASE_ENABLED;
1214 wrmsr(MSR_APICBASE, apic_base);
1217 /* Second, probe the CPU's in the system. */
1218 retval = best_enum->apic_probe_cpus();
1220 printf("%s: Failed to probe CPUs: returned %d\n",
1221 best_enum->apic_name, retval);
1223 /* Third, initialize the local APIC. */
1224 retval = best_enum->apic_setup_local();
1226 printf("%s: Failed to setup the local APIC: returned %d\n",
1227 best_enum->apic_name, retval);
1229 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL);
1232 * Setup the I/O APICs.
1235 apic_setup_io(void *dummy __unused)
1239 if (best_enum == NULL)
1241 retval = best_enum->apic_setup_io();
1243 printf("%s: Failed to setup I/O APICs: returned %d\n",
1244 best_enum->apic_name, retval);
1250 * Finish setting up the local APIC on the BSP once we know how to
1251 * properly program the LINT pins.
1254 intr_register_pic(&lapic_pic);
1258 /* Enable the MSI "pic". */
1261 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1265 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1266 * private to the sys/i386 code. The public interface for the rest of the
1267 * kernel is defined in mp_machdep.c.
1270 lapic_ipi_wait(int delay)
1275 * Wait delay loops for IPI to be sent. This is highly bogus
1276 * since this is sensitive to CPU clock speed. If delay is
1277 * -1, we wait forever.
1284 for (x = 0; x < delay; x += incr) {
1285 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1293 lapic_ipi_raw(register_t icrlo, u_int dest)
1295 register_t value, eflags;
1297 /* XXX: Need more sanity checking of icrlo? */
1298 KASSERT(lapic != NULL, ("%s called too early", __func__));
1299 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1300 ("%s: invalid dest field", __func__));
1301 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1302 ("%s: reserved bits set in ICR LO register", __func__));
1304 /* Set destination in ICR HI register if it is being used. */
1305 eflags = intr_disable();
1306 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1307 value = lapic->icr_hi;
1308 value &= ~APIC_ID_MASK;
1309 value |= dest << APIC_ID_SHIFT;
1310 lapic->icr_hi = value;
1313 /* Program the contents of the IPI and dispatch it. */
1314 value = lapic->icr_lo;
1315 value &= APIC_ICRLO_RESV_MASK;
1317 lapic->icr_lo = value;
1318 intr_restore(eflags);
1321 #define BEFORE_SPIN 1000000
1322 #ifdef DETECT_DEADLOCK
1323 #define AFTER_SPIN 1000
1327 lapic_ipi_vectored(u_int vector, int dest)
1329 register_t icrlo, destfield;
1331 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1332 ("%s: invalid vector %d", __func__, vector));
1334 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE;
1337 * IPI_STOP_HARD is just a "fake" vector used to send a NMI.
1338 * Use special rules regard NMI if passed, otherwise specify
1341 if (vector == IPI_STOP_HARD)
1342 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT;
1344 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT;
1347 case APIC_IPI_DEST_SELF:
1348 icrlo |= APIC_DEST_SELF;
1350 case APIC_IPI_DEST_ALL:
1351 icrlo |= APIC_DEST_ALLISELF;
1353 case APIC_IPI_DEST_OTHERS:
1354 icrlo |= APIC_DEST_ALLESELF;
1357 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1358 ("%s: invalid destination 0x%x", __func__, dest));
1362 /* Wait for an earlier IPI to finish. */
1363 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1364 if (panicstr != NULL)
1367 panic("APIC: Previous IPI is stuck");
1370 lapic_ipi_raw(icrlo, destfield);
1372 #ifdef DETECT_DEADLOCK
1373 /* Wait for IPI to be delivered. */
1374 if (!lapic_ipi_wait(AFTER_SPIN)) {
1375 #ifdef needsattention
1379 * The above function waits for the message to actually be
1380 * delivered. It breaks out after an arbitrary timeout
1381 * since the message should eventually be delivered (at
1382 * least in theory) and that if it wasn't we would catch
1383 * the failure with the check above when the next IPI is
1386 * We could skip this wait entirely, EXCEPT it probably
1387 * protects us from other routines that assume that the
1388 * message was delivered and acted upon when this function
1391 printf("APIC: IPI might be stuck\n");
1392 #else /* !needsattention */
1393 /* Wait until mesage is sent without a timeout. */
1394 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1396 #endif /* needsattention */
1398 #endif /* DETECT_DEADLOCK */