2 * Copyright 2006-2007 by Juniper Networks.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/sockio.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/socket.h>
41 #include <sys/queue.h>
44 #include <sys/endian.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
55 #include <machine/resource.h>
56 #include <machine/bus.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/ocpbus.h>
59 #include <machine/spr.h>
61 #include <powerpc/mpc85xx/ocpbus.h>
63 #define REG_CFG_ADDR 0x0000
64 #define CONFIG_ACCESS_ENABLE 0x80000000
66 #define REG_CFG_DATA 0x0004
67 #define REG_INT_ACK 0x0008
69 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
70 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
71 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
72 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
74 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
75 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
76 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
77 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
79 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
81 struct pci_ocp_softc {
85 bus_addr_t sc_iomem_va; /* Virtual mapping. */
86 bus_addr_t sc_iomem_alloc; /* Next allocation. */
87 struct rman sc_ioport;
88 bus_addr_t sc_ioport_va; /* Virtual mapping. */
89 bus_addr_t sc_ioport_alloc; /* Next allocation. */
91 struct resource *sc_res;
92 bus_space_handle_t sc_bsh;
93 bus_space_tag_t sc_bst;
99 /* Devices that need special attention. */
101 int sc_devfn_via_ide;
104 static int pci_ocp_attach(device_t);
105 static int pci_ocp_probe(device_t);
107 static struct resource *pci_ocp_alloc_resource(device_t, device_t, int, int *,
108 u_long, u_long, u_long, u_int);
109 static int pci_ocp_read_ivar(device_t, device_t, int, uintptr_t *);
110 static int pci_ocp_release_resource(device_t, device_t, int, int,
112 static int pci_ocp_write_ivar(device_t, device_t, int, uintptr_t);
114 static int pci_ocp_maxslots(device_t);
115 static uint32_t pci_ocp_read_config(device_t, u_int, u_int, u_int, u_int, int);
116 static void pci_ocp_write_config(device_t, u_int, u_int, u_int, u_int,
120 * Bus interface definitions.
122 static device_method_t pci_ocp_methods[] = {
123 /* Device interface */
124 DEVMETHOD(device_probe, pci_ocp_probe),
125 DEVMETHOD(device_attach, pci_ocp_attach),
128 DEVMETHOD(bus_print_child, bus_generic_print_child),
129 DEVMETHOD(bus_read_ivar, pci_ocp_read_ivar),
130 DEVMETHOD(bus_write_ivar, pci_ocp_write_ivar),
131 DEVMETHOD(bus_alloc_resource, pci_ocp_alloc_resource),
132 DEVMETHOD(bus_release_resource, pci_ocp_release_resource),
133 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
135 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
136 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
139 DEVMETHOD(pcib_maxslots, pci_ocp_maxslots),
140 DEVMETHOD(pcib_read_config, pci_ocp_read_config),
141 DEVMETHOD(pcib_write_config, pci_ocp_write_config),
142 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
147 static driver_t pci_ocp_driver = {
150 sizeof(struct pci_ocp_softc),
153 devclass_t pcib_devclass;
155 DRIVER_MODULE(pcib, ocpbus, pci_ocp_driver, pcib_devclass, 0, 0);
158 pci_ocp_cfgread(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
159 u_int reg, int bytes)
163 if (bus == sc->sc_busnr)
166 addr = CONFIG_ACCESS_ENABLE;
167 addr |= (bus & 0xff) << 16;
168 addr |= (slot & 0x1f) << 11;
169 addr |= (func & 0x7) << 8;
172 addr |= (reg & 0xf00) << 16;
173 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
177 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
178 REG_CFG_DATA + (reg & 3));
181 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
182 REG_CFG_DATA + (reg & 2)));
185 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
196 pci_ocp_cfgwrite(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
197 u_int reg, uint32_t data, int bytes)
201 if (bus == sc->sc_busnr)
204 addr = CONFIG_ACCESS_ENABLE;
205 addr |= (bus & 0xff) << 16;
206 addr |= (slot & 0x1f) << 11;
207 addr |= (func & 0x7) << 8;
210 addr |= (reg & 0xf00) << 16;
211 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
215 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
216 REG_CFG_DATA + (reg & 3), data);
219 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
220 REG_CFG_DATA + (reg & 2), htole16(data));
223 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
224 REG_CFG_DATA, htole32(data));
231 dump(struct pci_ocp_softc *sc)
235 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
236 for (i = 0; i < 5; i++) {
237 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
238 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
239 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
240 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
243 for (i = 1; i < 4; i++) {
244 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
245 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
246 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
247 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
252 for (i = 0; i < 0x48; i += 4) {
253 printf("cfg%02x=0x%08x\n", i, pci_ocp_cfgread(sc, 0, 0, 0,
260 pci_ocp_maxslots(device_t dev)
262 struct pci_ocp_softc *sc = device_get_softc(dev);
264 return ((sc->sc_pcie) ? 0 : 30);
268 pci_ocp_read_config(device_t dev, u_int bus, u_int slot, u_int func,
269 u_int reg, int bytes)
271 struct pci_ocp_softc *sc = device_get_softc(dev);
274 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
276 devfn = DEVFN(bus, slot, func);
277 if (devfn == sc->sc_devfn_tundra)
279 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
281 return (pci_ocp_cfgread(sc, bus, slot, func, reg, bytes));
285 pci_ocp_write_config(device_t dev, u_int bus, u_int slot, u_int func,
286 u_int reg, uint32_t val, int bytes)
288 struct pci_ocp_softc *sc = device_get_softc(dev);
290 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
292 pci_ocp_cfgwrite(sc, bus, slot, func, reg, val, bytes);
296 pci_ocp_probe(device_t dev)
299 struct pci_ocp_softc *sc;
300 const char *mpcid, *type;
307 parent = device_get_parent(dev);
308 error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype);
311 if (devtype != OCPBUS_DEVTYPE_PCIB)
314 sc = device_get_softc(dev);
317 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
319 if (sc->sc_res == NULL)
322 sc->sc_bst = rman_get_bustag(sc->sc_res);
323 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
327 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
328 if (cfgreg != 0x1057 && cfgreg != 0x1957)
330 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_DEVICE, 2);
342 * Documentation from Freescale is incorrect.
343 * Use right values after documentation is corrected.
359 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
360 while (cfgreg != 0) {
361 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, cfgreg, 2);
362 switch (cfgreg & 0xff) {
363 case PCIY_PCIX: /* PCI-X */
366 case PCIY_EXPRESS: /* PCI Express */
367 type = "PCI Express";
371 cfgreg = (cfgreg >> 8) & 0xff;
374 error = bus_get_resource(dev, SYS_RES_MEMORY, 1, &start, &size);
375 if (error || start == 0 || size == 0)
378 snprintf(buf, sizeof(buf),
379 "Freescale MPC%s %s host controller", mpcid, type);
380 device_set_desc_copy(dev, buf);
381 error = BUS_PROBE_DEFAULT;
384 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
389 pci_ocp_init_via(struct pci_ocp_softc *sc, uint16_t device, int bus,
393 if (device == 0x0686) {
394 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
395 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
396 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
397 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
398 } else if (device == 0x0571) {
399 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
400 pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
405 pci_ocp_init_bar(struct pci_ocp_softc *sc, int bus, int slot, int func,
409 uint32_t addr, mask, size;
412 reg = PCIR_BAR(barno);
414 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
416 case 0: addr = 0x1f0; break;
417 case 1: addr = 0x3f4; break;
418 case 2: addr = 0x170; break;
419 case 3: addr = 0x374; break;
420 case 4: addr = 0xcc0; break;
423 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
427 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
428 size = pci_ocp_read_config(sc->sc_dev, bus, slot, func, reg, 4);
431 width = ((size & 7) == 4) ? 2 : 1;
433 if (size & 1) { /* I/O port */
434 allocp = &sc->sc_ioport_alloc;
436 if ((size & 0xffff0000) == 0)
438 } else { /* memory */
439 allocp = &sc->sc_iomem_alloc;
444 /* Sanity check (must be a power of 2). */
448 addr = (*allocp + mask) & ~mask;
449 *allocp = addr + size;
452 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
453 device_get_unit(sc->sc_dev), bus, slot, func, reg,
456 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
458 pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg + 4,
464 pci_ocp_route_int(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
467 u_int devfn, intline;
469 devfn = DEVFN(bus, slot, func);
470 if (devfn == sc->sc_devfn_via_ide)
472 else if (devfn == sc->sc_devfn_via_ide + 1)
474 else if (devfn == sc->sc_devfn_via_ide + 2)
478 intline = intpin - 1;
479 intline += (bus != sc->sc_busnr) ? slot : 0;
480 intline = PIC_IRQ_EXT(intline & 3);
486 printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n",
487 device_get_unit(sc->sc_dev), bus, slot, func,
494 pci_ocp_init(struct pci_ocp_softc *sc, int bus, int maxslot)
499 uint16_t vendor, device;
500 uint8_t command, hdrtype, class, subclass;
501 uint8_t intline, intpin;
504 for (slot = 0; slot < maxslot; slot++) {
506 for (func = 0; func <= maxfunc; func++) {
507 hdrtype = pci_ocp_read_config(sc->sc_dev, bus, slot,
508 func, PCIR_HDRTYPE, 1);
509 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
512 if (func == 0 && (hdrtype & PCIM_MFDEV))
513 maxfunc = PCI_FUNCMAX;
515 vendor = pci_ocp_read_config(sc->sc_dev, bus, slot,
516 func, PCIR_VENDOR, 2);
517 device = pci_ocp_read_config(sc->sc_dev, bus, slot,
518 func, PCIR_DEVICE, 2);
520 if (vendor == 0x1957 && device == 0x3fff) {
521 sc->sc_devfn_tundra = DEVFN(bus, slot, func);
525 command = pci_ocp_read_config(sc->sc_dev, bus, slot,
526 func, PCIR_COMMAND, 1);
527 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
528 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
529 PCIR_COMMAND, command, 1);
531 if (vendor == 0x1106)
532 pci_ocp_init_via(sc, device, bus, slot, func);
534 /* Program the base address registers. */
535 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
538 bar += pci_ocp_init_bar(sc, bus, slot, func,
541 /* Perform interrupt routing. */
542 intpin = pci_ocp_read_config(sc->sc_dev, bus, slot,
543 func, PCIR_INTPIN, 1);
544 intline = pci_ocp_route_int(sc, bus, slot, func,
546 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
547 PCIR_INTLINE, intline, 1);
549 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
550 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
551 PCIR_COMMAND, command, 1);
554 * Handle PCI-PCI bridges
556 class = pci_ocp_read_config(sc->sc_dev, bus, slot,
557 func, PCIR_CLASS, 1);
558 if (class != PCIC_BRIDGE)
560 subclass = pci_ocp_read_config(sc->sc_dev, bus, slot,
561 func, PCIR_SUBCLASS, 1);
562 if (subclass != PCIS_BRIDGE_PCI)
567 /* Program I/O decoder. */
568 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
569 PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
570 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
571 PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
572 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
573 PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
574 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
575 PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
577 /* Program (non-prefetchable) memory decoder. */
578 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
579 PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
580 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
581 PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
583 /* Program prefetchable memory decoder. */
584 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
585 PCIR_PMBASEL_1, 0x0010, 2);
586 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
587 PCIR_PMLIMITL_1, 0x000f, 2);
588 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
589 PCIR_PMBASEH_1, 0x00000000, 4);
590 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
591 PCIR_PMLIMITH_1, 0x00000000, 4);
593 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
594 PCIR_PRIBUS_1, bus, 1);
595 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
596 PCIR_SECBUS_1, secbus, 1);
597 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
598 PCIR_SUBBUS_1, 0xff, 1);
600 secbus = pci_ocp_init(sc, secbus,
601 (subclass == PCIS_BRIDGE_PCI) ? 31 : 1);
603 pci_ocp_write_config(sc->sc_dev, bus, slot, func,
604 PCIR_SUBBUS_1, secbus, 1);
612 pci_ocp_inbound(struct pci_ocp_softc *sc, int wnd, int tgt, u_long start,
613 u_long size, u_long pci_start)
615 uint32_t attr, bar, tar;
617 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
620 case OCP85XX_TGTIF_RAM1:
621 attr = 0xa0f55000 | (ffsl(size) - 2);
628 bar = pci_start >> 12;
630 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
631 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
632 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
633 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
637 pci_ocp_outbound(struct pci_ocp_softc *sc, int wnd, int res, u_long start,
638 u_long size, u_long pci_start)
640 uint32_t attr, bar, tar;
644 attr = 0x80044000 | (ffsl(size) - 2);
647 attr = 0x80088000 | (ffsl(size) - 2);
654 tar = pci_start >> 12;
656 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
657 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
658 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
659 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
663 pci_ocp_iorange(struct pci_ocp_softc *sc, int type, int wnd)
666 u_long start, end, size, alloc;
667 bus_addr_t pci_start, pci_end;
668 bus_addr_t *vap, *allocp;
671 error = bus_get_resource(sc->sc_dev, type, 1, &start, &size);
675 end = start + size - 1;
683 vap = &sc->sc_ioport_va;
684 allocp = &sc->sc_ioport_alloc;
691 vap = &sc->sc_iomem_va;
692 allocp = &sc->sc_iomem_alloc;
698 rm->rm_type = RMAN_ARRAY;
699 rm->rm_start = pci_start;
700 rm->rm_end = pci_end;
701 error = rman_init(rm);
705 error = rman_manage_region(rm, pci_start, pci_end);
711 *allocp = pci_start + alloc;
712 *vap = (uintptr_t)pmap_mapdev(start, size);
714 pci_ocp_outbound(sc, wnd, type, start, size, pci_start);
719 pci_ocp_attach(device_t dev)
721 struct pci_ocp_softc *sc;
725 sc = device_get_softc(dev);
729 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
731 if (sc->sc_res == NULL) {
732 device_printf(dev, "could not map I/O memory\n");
735 sc->sc_bst = rman_get_bustag(sc->sc_res);
736 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
738 cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
739 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
741 pci_ocp_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
743 pci_ocp_outbound(sc, 0, -1, 0, 0, 0);
744 error = pci_ocp_iorange(sc, SYS_RES_MEMORY, 1);
745 error = pci_ocp_iorange(sc, SYS_RES_IOPORT, 2);
746 pci_ocp_outbound(sc, 3, -1, 0, 0, 0);
747 pci_ocp_outbound(sc, 4, -1, 0, 0, 0);
749 pci_ocp_inbound(sc, 1, -1, 0, 0, 0);
750 pci_ocp_inbound(sc, 2, -1, 0, 0, 0);
751 pci_ocp_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 2U*1024U*1024U*1024U, 0);
753 sc->sc_devfn_tundra = -1;
754 sc->sc_devfn_via_ide = -1;
756 maxslot = (sc->sc_pcie) ? 1 : 31;
757 pci_ocp_init(sc, sc->sc_busnr, maxslot);
759 device_add_child(dev, "pci", -1);
760 return (bus_generic_attach(dev));
763 static struct resource *
764 pci_ocp_alloc_resource(device_t dev, device_t child, int type, int *rid,
765 u_long start, u_long end, u_long count, u_int flags)
767 struct pci_ocp_softc *sc = device_get_softc(dev);
769 struct resource *res;
775 va = sc->sc_ioport_va;
779 va = sc->sc_iomem_va;
782 if (start < PIC_IRQ_START) {
783 device_printf(dev, "%s requested ISA interrupt %lu\n",
784 device_get_nameunit(child), start);
786 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
787 type, rid, start, end, count, flags));
792 res = rman_reserve_resource(rm, start, end, count, flags, child);
796 rman_set_bustag(res, &bs_le_tag);
797 rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start);
802 pci_ocp_release_resource(device_t dev, device_t child, int type, int rid,
803 struct resource *res)
806 return (rman_release_resource(res));
810 pci_ocp_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
812 struct pci_ocp_softc *sc = device_get_softc(dev);
816 *result = sc->sc_busnr;
818 case PCIB_IVAR_DOMAIN:
819 *result = device_get_unit(dev);
826 pci_ocp_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
828 struct pci_ocp_softc *sc = device_get_softc(dev);
832 sc->sc_busnr = value;